[Hexagon] Split double registers
[oota-llvm.git] / test / CodeGen / Hexagon / sdr-shr32.ll
1 ; RUN: llc -march=hexagon < %s | FileCheck %s
2 ; CHECK-NOT: lsr{{.*}}#31
3
4 target datalayout = "e-m:e-p:32:32-i64:64-a:0-v32:32-n16:32"
5 target triple = "hexagon-unknown--elf"
6
7 ; Function Attrs: nounwind readnone
8 define i64 @foo(i64 %x) #0 {
9 entry:
10   %0 = tail call i64 @llvm.hexagon.S2.asr.i.p(i64 %x, i32 32)
11   ret i64 %0
12 }
13
14 ; Function Attrs: nounwind readnone
15 declare i64 @llvm.hexagon.S2.asr.i.p(i64, i32) #1
16
17 attributes #0 = { nounwind readnone "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
18 attributes #1 = { nounwind readnone }
19
20 !llvm.ident = !{!0}
21
22 !0 = !{!"Clang $LLVM_VERSION_MAJOR.$LLVM_VERSION_MINOR (based on LLVM 3.7.0)"}