test/CodeGen/AArch64/fp16-v16-instructions.ll

   1 ; RUN: llc < %s -mtriple=aarch64-none-eabi | FileCheck %s
   2
   3
   4 define <16 x half> @sitofp_i32(<16 x i32> %a) #0 {
   5 ; CHECK-LABEL: sitofp_i32:
   6 ; CHECK-DAG: scvtf [[S0:v[0-9]+\.4s]], v0.4s
   7 ; CHECK-DAG: scvtf [[S1:v[0-9]+\.4s]], v1.4s
   8 ; CHECK-DAG: scvtf [[S2:v[0-9]+\.4s]], v2.4s
   9 ; CHECK-DAG: scvtf [[S3:v[0-9]+\.4s]], v3.4s
  10 ; CHECK-DAG: fcvtn v0.4h, [[S0]]
  11 ; CHECK-DAG: fcvtn v1.4h, [[S2]]
  12 ; CHECK-DAG: v[[R1:[0-9]+]].4h, [[S1]]
  13 ; CHECK-DAG: v[[R3:[0-9]+]].4h, [[S3]]
  14 ; CHECK-DAg: ins v0.d[1], v[[R1]].d[0]
  15 ; CHECK-DAG: ins v1.d[1], v[[R3]].d[0]
  16
  17   %1 = sitofp <16 x i32> %a to <16 x half>
  18   ret <16 x half> %1
  19 }
  20
  21
  22 define <16 x half> @sitofp_i64(<16 x i64> %a) #0 {
  23 ; CHECK-LABEL: sitofp_i64:
  24 ; CHECK-DAG: scvtf [[D0:v[0-9]+\.2d]], v0.2d
  25 ; CHECK-DAG: scvtf [[D1:v[0-9]+\.2d]], v1.2d
  26 ; CHECK-DAG: scvtf [[D2:v[0-9]+\.2d]], v2.2d
  27 ; CHECK-DAG: scvtf [[D3:v[0-9]+\.2d]], v3.2d
  28 ; CHECK-DAG: scvtf [[D4:v[0-9]+\.2d]], v4.2d
  29 ; CHECK-DAG: scvtf [[D5:v[0-9]+\.2d]], v5.2d
  30 ; CHECK-DAG: scvtf [[D6:v[0-9]+\.2d]], v6.2d
  31 ; CHECK-DAG: scvtf [[D7:v[0-9]+\.2d]], v7.2d
  32
  33 ; CHECK-DAG: fcvtn [[S0:v[0-9]+]].2s, [[D0]]
  34 ; CHECK-DAG: fcvtn [[S1:v[0-9]+]].2s, [[D2]]
  35 ; CHECK-DAG: fcvtn [[S2:v[0-9]+]].2s, [[D4]]
  36 ; CHECK-DAG: fcvtn [[S3:v[0-9]+]].2s, [[D6]]
  37
  38 ; CHECK-DAG: fcvtn2 [[S0]].4s, [[D1]]
  39 ; CHECK-DAG: fcvtn2 [[S1]].4s, [[D3]]
  40 ; CHECK-DAG: fcvtn2 [[S2]].4s, [[D5]]
  41 ; CHECK-DAG: fcvtn2 [[S3]].4s, [[D7]]
  42
  43 ; CHECK-DAG: fcvtn v0.4h, [[S0]].4s
  44 ; CHECK-DAG: fcvtn v1.4h, [[S2]].4s
  45 ; CHECK-DAG: fcvtn v[[R1:[0-9]+]].4h, [[S1]].4s
  46 ; CHECK-DAG: fcvtn v[[R3:[0-9]+]].4h, [[S3]].4s
  47 ; CHECK-DAG: ins v0.d[1], v[[R1]].d[0]
  48 ; CHECK-DAG: ins v1.d[1], v[[R3]].d[0]
  49
  50   %1 = sitofp <16 x i64> %a to <16 x half>
  51   ret <16 x half> %1
  52 }
  53
  54
  55 define <16 x half> @uitofp_i32(<16 x i32> %a) #0 {
  56 ; CHECK-LABEL: uitofp_i32:
  57 ; CHECK-DAG: ucvtf [[S0:v[0-9]+\.4s]], v0.4s
  58 ; CHECK-DAG: ucvtf [[S1:v[0-9]+\.4s]], v1.4s
  59 ; CHECK-DAG: ucvtf [[S2:v[0-9]+\.4s]], v2.4s
  60 ; CHECK-DAG: ucvtf [[S3:v[0-9]+\.4s]], v3.4s
  61 ; CHECK-DAG: fcvtn v0.4h, [[S0]]
  62 ; CHECK-DAG: fcvtn v1.4h, [[S2]]
  63 ; CHECK-DAG: v[[R1:[0-9]+]].4h, [[S1]]
  64 ; CHECK-DAG: v[[R3:[0-9]+]].4h, [[S3]]
  65 ; CHECK-DAg: ins v0.d[1], v[[R1]].d[0]
  66 ; CHECK-DAG: ins v1.d[1], v[[R3]].d[0]
  67
  68   %1 = uitofp <16 x i32> %a to <16 x half>
  69   ret <16 x half> %1
  70 }
  71
  72
  73 define <16 x half> @uitofp_i64(<16 x i64> %a) #0 {
  74 ; CHECK-LABEL: uitofp_i64:
  75 ; CHECK-DAG: ucvtf [[D0:v[0-9]+\.2d]], v0.2d
  76 ; CHECK-DAG: ucvtf [[D1:v[0-9]+\.2d]], v1.2d
  77 ; CHECK-DAG: ucvtf [[D2:v[0-9]+\.2d]], v2.2d
  78 ; CHECK-DAG: ucvtf [[D3:v[0-9]+\.2d]], v3.2d
  79 ; CHECK-DAG: ucvtf [[D4:v[0-9]+\.2d]], v4.2d
  80 ; CHECK-DAG: ucvtf [[D5:v[0-9]+\.2d]], v5.2d
  81 ; CHECK-DAG: ucvtf [[D6:v[0-9]+\.2d]], v6.2d
  82 ; CHECK-DAG: ucvtf [[D7:v[0-9]+\.2d]], v7.2d
  83
  84 ; CHECK-DAG: fcvtn [[S0:v[0-9]+]].2s, [[D0]]
  85 ; CHECK-DAG: fcvtn [[S1:v[0-9]+]].2s, [[D2]]
  86 ; CHECK-DAG: fcvtn [[S2:v[0-9]+]].2s, [[D4]]
  87 ; CHECK-DAG: fcvtn [[S3:v[0-9]+]].2s, [[D6]]
  88
  89 ; CHECK-DAG: fcvtn2 [[S0]].4s, [[D1]]
  90 ; CHECK-DAG: fcvtn2 [[S1]].4s, [[D3]]
  91 ; CHECK-DAG: fcvtn2 [[S2]].4s, [[D5]]
  92 ; CHECK-DAG: fcvtn2 [[S3]].4s, [[D7]]
  93
  94 ; CHECK-DAG: fcvtn v0.4h, [[S0]].4s
  95 ; CHECK-DAG: fcvtn v1.4h, [[S2]].4s
  96 ; CHECK-DAG: fcvtn v[[R1:[0-9]+]].4h, [[S1]].4s
  97 ; CHECK-DAG: fcvtn v[[R3:[0-9]+]].4h, [[S3]].4s
  98 ; CHECK-DAG: ins v0.d[1], v[[R1]].d[0]
  99 ; CHECK-DAG: ins v1.d[1], v[[R3]].d[0]
 100
 101   %1 = uitofp <16 x i64> %a to <16 x half>
 102   ret <16 x half> %1
 103 }
 104
 105 attributes #0 = { nounwind }