1 ; RUN: llc < %s -march=arm64 -asm-verbose=false -verify-machineinstrs -mcpu=cyclone | FileCheck %s
3 define i32 @val_compare_and_swap(i32* %p, i32 %cmp, i32 %new) #0 {
4 ; CHECK-LABEL: val_compare_and_swap:
5 ; CHECK-NEXT: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
6 ; CHECK-NEXT: ldaxr [[RESULT:w[0-9]+]], [x0]
7 ; CHECK-NEXT: cmp [[RESULT]], w1
8 ; CHECK-NEXT: b.ne [[LABEL2:.?LBB[0-9]+_[0-9]+]]
9 ; CHECK-NEXT: stxr [[SCRATCH_REG:w[0-9]+]], w2, [x0]
10 ; CHECK-NEXT: cbnz [[SCRATCH_REG]], [[LABEL]]
11 ; CHECK-NEXT: [[LABEL2]]:
12 %pair = cmpxchg i32* %p, i32 %cmp, i32 %new acquire acquire
13 %val = extractvalue { i32, i1 } %pair, 0
17 define i32 @val_compare_and_swap_from_load(i32* %p, i32 %cmp, i32* %pnew) #0 {
18 ; CHECK-LABEL: val_compare_and_swap_from_load:
19 ; CHECK-NEXT: ldr [[NEW:w[0-9]+]], [x2]
20 ; CHECK-NEXT: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
21 ; CHECK-NEXT: ldaxr [[RESULT:w[0-9]+]], [x0]
22 ; CHECK-NEXT: cmp [[RESULT]], w1
23 ; CHECK-NEXT: b.ne [[LABEL2:.?LBB[0-9]+_[0-9]+]]
24 ; CHECK-NEXT: stxr [[SCRATCH_REG:w[0-9]+]], [[NEW]], [x0]
25 ; CHECK-NEXT: cbnz [[SCRATCH_REG]], [[LABEL]]
26 ; CHECK-NEXT: [[LABEL2]]:
27 %new = load i32, i32* %pnew
28 %pair = cmpxchg i32* %p, i32 %cmp, i32 %new acquire acquire
29 %val = extractvalue { i32, i1 } %pair, 0
33 define i32 @val_compare_and_swap_rel(i32* %p, i32 %cmp, i32 %new) #0 {
34 ; CHECK-LABEL: val_compare_and_swap_rel:
35 ; CHECK-NEXT: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
36 ; CHECK-NEXT: ldaxr [[RESULT:w[0-9]+]], [x0]
37 ; CHECK-NEXT: cmp [[RESULT]], w1
38 ; CHECK-NEXT: b.ne [[LABEL2:.?LBB[0-9]+_[0-9]+]]
39 ; CHECK-NEXT: stlxr [[SCRATCH_REG:w[0-9]+]], w2, [x0]
40 ; CHECK-NEXT: cbnz [[SCRATCH_REG]], [[LABEL]]
41 ; CHECK-NEXT: [[LABEL2]]:
42 %pair = cmpxchg i32* %p, i32 %cmp, i32 %new acq_rel monotonic
43 %val = extractvalue { i32, i1 } %pair, 0
47 define i64 @val_compare_and_swap_64(i64* %p, i64 %cmp, i64 %new) #0 {
48 ; CHECK-LABEL: val_compare_and_swap_64:
49 ; CHECK-NEXT: mov x[[ADDR:[0-9]+]], x0
50 ; CHECK-NEXT: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
51 ; CHECK-NEXT: ldxr [[RESULT:x[0-9]+]], [x[[ADDR]]]
52 ; CHECK-NEXT: cmp [[RESULT]], x1
53 ; CHECK-NEXT: b.ne [[LABEL2:.?LBB[0-9]+_[0-9]+]]
54 ; CHECK-NEXT: stxr [[SCRATCH_REG:w[0-9]+]], x2, [x[[ADDR]]]
55 ; CHECK-NEXT: cbnz [[SCRATCH_REG]], [[LABEL]]
56 ; CHECK-NEXT: [[LABEL2]]:
57 %pair = cmpxchg i64* %p, i64 %cmp, i64 %new monotonic monotonic
58 %val = extractvalue { i64, i1 } %pair, 0
62 define i32 @fetch_and_nand(i32* %p) #0 {
63 ; CHECK-LABEL: fetch_and_nand:
64 ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
65 ; CHECK: ldxr w[[DEST_REG:[0-9]+]], [x0]
66 ; CHECK: mvn [[TMP_REG:w[0-9]+]], w[[DEST_REG]]
67 ; CHECK: orr [[SCRATCH2_REG:w[0-9]+]], [[TMP_REG]], #0xfffffff8
68 ; CHECK-NOT: stlxr [[SCRATCH2_REG]], [[SCRATCH2_REG]]
69 ; CHECK: stlxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x0]
70 ; CHECK: cbnz [[SCRATCH_REG]], [[LABEL]]
71 ; CHECK: mov x0, x[[DEST_REG]]
72 %val = atomicrmw nand i32* %p, i32 7 release
76 define i64 @fetch_and_nand_64(i64* %p) #0 {
77 ; CHECK-LABEL: fetch_and_nand_64:
78 ; CHECK: mov x[[ADDR:[0-9]+]], x0
79 ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
80 ; CHECK: ldaxr x[[DEST_REG:[0-9]+]], [x[[ADDR]]]
81 ; CHECK: mvn w[[TMP_REG:[0-9]+]], w[[DEST_REG]]
82 ; CHECK: orr [[SCRATCH2_REG:x[0-9]+]], x[[TMP_REG]], #0xfffffffffffffff8
83 ; CHECK: stlxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x[[ADDR]]]
84 ; CHECK: cbnz [[SCRATCH_REG]], [[LABEL]]
86 %val = atomicrmw nand i64* %p, i64 7 acq_rel
90 define i32 @fetch_and_or(i32* %p) #0 {
91 ; CHECK-LABEL: fetch_and_or:
92 ; CHECK: movz [[OLDVAL_REG:w[0-9]+]], #0x5
93 ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
94 ; CHECK: ldaxr w[[DEST_REG:[0-9]+]], [x0]
95 ; CHECK: orr [[SCRATCH2_REG:w[0-9]+]], w[[DEST_REG]], [[OLDVAL_REG]]
96 ; CHECK-NOT: stlxr [[SCRATCH2_REG]], [[SCRATCH2_REG]]
97 ; CHECK: stlxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x0]
98 ; CHECK: cbnz [[SCRATCH_REG]], [[LABEL]]
99 ; CHECK: mov x0, x[[DEST_REG]]
100 %val = atomicrmw or i32* %p, i32 5 seq_cst
104 define i64 @fetch_and_or_64(i64* %p) #0 {
105 ; CHECK: fetch_and_or_64:
106 ; CHECK: mov x[[ADDR:[0-9]+]], x0
107 ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
108 ; CHECK: ldxr [[DEST_REG:x[0-9]+]], [x[[ADDR]]]
109 ; CHECK: orr [[SCRATCH2_REG:x[0-9]+]], [[DEST_REG]], #0x7
110 ; CHECK: stxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x[[ADDR]]]
111 ; CHECK: cbnz [[SCRATCH_REG]], [[LABEL]]
112 %val = atomicrmw or i64* %p, i64 7 monotonic
116 define void @acquire_fence() #0 {
119 ; CHECK-LABEL: acquire_fence:
123 define void @release_fence() #0 {
126 ; CHECK-LABEL: release_fence:
127 ; CHECK: dmb ish{{$}}
130 define void @seq_cst_fence() #0 {
133 ; CHECK-LABEL: seq_cst_fence:
134 ; CHECK: dmb ish{{$}}
137 define i32 @atomic_load(i32* %p) #0 {
138 %r = load atomic i32, i32* %p seq_cst, align 4
140 ; CHECK-LABEL: atomic_load:
144 define i8 @atomic_load_relaxed_8(i8* %p, i32 %off32) #0 {
145 ; CHECK-LABEL: atomic_load_relaxed_8:
146 %ptr_unsigned = getelementptr i8, i8* %p, i32 4095
147 %val_unsigned = load atomic i8, i8* %ptr_unsigned monotonic, align 1
148 ; CHECK: ldrb {{w[0-9]+}}, [x0, #4095]
150 %ptr_regoff = getelementptr i8, i8* %p, i32 %off32
151 %val_regoff = load atomic i8, i8* %ptr_regoff unordered, align 1
152 %tot1 = add i8 %val_unsigned, %val_regoff
153 ; CHECK: ldrb {{w[0-9]+}}, [x0, w1, sxtw]
155 %ptr_unscaled = getelementptr i8, i8* %p, i32 -256
156 %val_unscaled = load atomic i8, i8* %ptr_unscaled monotonic, align 1
157 %tot2 = add i8 %tot1, %val_unscaled
158 ; CHECK: ldurb {{w[0-9]+}}, [x0, #-256]
160 %ptr_random = getelementptr i8, i8* %p, i32 1191936 ; 0x123000 (i.e. ADD imm)
161 %val_random = load atomic i8, i8* %ptr_random unordered, align 1
162 %tot3 = add i8 %tot2, %val_random
163 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
164 ; CHECK: ldrb {{w[0-9]+}}, [x[[ADDR]]]
169 define i16 @atomic_load_relaxed_16(i16* %p, i32 %off32) #0 {
170 ; CHECK-LABEL: atomic_load_relaxed_16:
171 %ptr_unsigned = getelementptr i16, i16* %p, i32 4095
172 %val_unsigned = load atomic i16, i16* %ptr_unsigned monotonic, align 2
173 ; CHECK: ldrh {{w[0-9]+}}, [x0, #8190]
175 %ptr_regoff = getelementptr i16, i16* %p, i32 %off32
176 %val_regoff = load atomic i16, i16* %ptr_regoff unordered, align 2
177 %tot1 = add i16 %val_unsigned, %val_regoff
178 ; CHECK: ldrh {{w[0-9]+}}, [x0, w1, sxtw #1]
180 %ptr_unscaled = getelementptr i16, i16* %p, i32 -128
181 %val_unscaled = load atomic i16, i16* %ptr_unscaled monotonic, align 2
182 %tot2 = add i16 %tot1, %val_unscaled
183 ; CHECK: ldurh {{w[0-9]+}}, [x0, #-256]
185 %ptr_random = getelementptr i16, i16* %p, i32 595968 ; 0x123000/2 (i.e. ADD imm)
186 %val_random = load atomic i16, i16* %ptr_random unordered, align 2
187 %tot3 = add i16 %tot2, %val_random
188 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
189 ; CHECK: ldrh {{w[0-9]+}}, [x[[ADDR]]]
194 define i32 @atomic_load_relaxed_32(i32* %p, i32 %off32) #0 {
195 ; CHECK-LABEL: atomic_load_relaxed_32:
196 %ptr_unsigned = getelementptr i32, i32* %p, i32 4095
197 %val_unsigned = load atomic i32, i32* %ptr_unsigned monotonic, align 4
198 ; CHECK: ldr {{w[0-9]+}}, [x0, #16380]
200 %ptr_regoff = getelementptr i32, i32* %p, i32 %off32
201 %val_regoff = load atomic i32, i32* %ptr_regoff unordered, align 4
202 %tot1 = add i32 %val_unsigned, %val_regoff
203 ; CHECK: ldr {{w[0-9]+}}, [x0, w1, sxtw #2]
205 %ptr_unscaled = getelementptr i32, i32* %p, i32 -64
206 %val_unscaled = load atomic i32, i32* %ptr_unscaled monotonic, align 4
207 %tot2 = add i32 %tot1, %val_unscaled
208 ; CHECK: ldur {{w[0-9]+}}, [x0, #-256]
210 %ptr_random = getelementptr i32, i32* %p, i32 297984 ; 0x123000/4 (i.e. ADD imm)
211 %val_random = load atomic i32, i32* %ptr_random unordered, align 4
212 %tot3 = add i32 %tot2, %val_random
213 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
214 ; CHECK: ldr {{w[0-9]+}}, [x[[ADDR]]]
219 define i64 @atomic_load_relaxed_64(i64* %p, i32 %off32) #0 {
220 ; CHECK-LABEL: atomic_load_relaxed_64:
221 %ptr_unsigned = getelementptr i64, i64* %p, i32 4095
222 %val_unsigned = load atomic i64, i64* %ptr_unsigned monotonic, align 8
223 ; CHECK: ldr {{x[0-9]+}}, [x0, #32760]
225 %ptr_regoff = getelementptr i64, i64* %p, i32 %off32
226 %val_regoff = load atomic i64, i64* %ptr_regoff unordered, align 8
227 %tot1 = add i64 %val_unsigned, %val_regoff
228 ; CHECK: ldr {{x[0-9]+}}, [x0, w1, sxtw #3]
230 %ptr_unscaled = getelementptr i64, i64* %p, i32 -32
231 %val_unscaled = load atomic i64, i64* %ptr_unscaled monotonic, align 8
232 %tot2 = add i64 %tot1, %val_unscaled
233 ; CHECK: ldur {{x[0-9]+}}, [x0, #-256]
235 %ptr_random = getelementptr i64, i64* %p, i32 148992 ; 0x123000/8 (i.e. ADD imm)
236 %val_random = load atomic i64, i64* %ptr_random unordered, align 8
237 %tot3 = add i64 %tot2, %val_random
238 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
239 ; CHECK: ldr {{x[0-9]+}}, [x[[ADDR]]]
245 define void @atomc_store(i32* %p) #0 {
246 store atomic i32 4, i32* %p seq_cst, align 4
248 ; CHECK-LABEL: atomc_store:
252 define void @atomic_store_relaxed_8(i8* %p, i32 %off32, i8 %val) #0 {
253 ; CHECK-LABEL: atomic_store_relaxed_8:
254 %ptr_unsigned = getelementptr i8, i8* %p, i32 4095
255 store atomic i8 %val, i8* %ptr_unsigned monotonic, align 1
256 ; CHECK: strb {{w[0-9]+}}, [x0, #4095]
258 %ptr_regoff = getelementptr i8, i8* %p, i32 %off32
259 store atomic i8 %val, i8* %ptr_regoff unordered, align 1
260 ; CHECK: strb {{w[0-9]+}}, [x0, w1, sxtw]
262 %ptr_unscaled = getelementptr i8, i8* %p, i32 -256
263 store atomic i8 %val, i8* %ptr_unscaled monotonic, align 1
264 ; CHECK: sturb {{w[0-9]+}}, [x0, #-256]
266 %ptr_random = getelementptr i8, i8* %p, i32 1191936 ; 0x123000 (i.e. ADD imm)
267 store atomic i8 %val, i8* %ptr_random unordered, align 1
268 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
269 ; CHECK: strb {{w[0-9]+}}, [x[[ADDR]]]
274 define void @atomic_store_relaxed_16(i16* %p, i32 %off32, i16 %val) #0 {
275 ; CHECK-LABEL: atomic_store_relaxed_16:
276 %ptr_unsigned = getelementptr i16, i16* %p, i32 4095
277 store atomic i16 %val, i16* %ptr_unsigned monotonic, align 2
278 ; CHECK: strh {{w[0-9]+}}, [x0, #8190]
280 %ptr_regoff = getelementptr i16, i16* %p, i32 %off32
281 store atomic i16 %val, i16* %ptr_regoff unordered, align 2
282 ; CHECK: strh {{w[0-9]+}}, [x0, w1, sxtw #1]
284 %ptr_unscaled = getelementptr i16, i16* %p, i32 -128
285 store atomic i16 %val, i16* %ptr_unscaled monotonic, align 2
286 ; CHECK: sturh {{w[0-9]+}}, [x0, #-256]
288 %ptr_random = getelementptr i16, i16* %p, i32 595968 ; 0x123000/2 (i.e. ADD imm)
289 store atomic i16 %val, i16* %ptr_random unordered, align 2
290 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
291 ; CHECK: strh {{w[0-9]+}}, [x[[ADDR]]]
296 define void @atomic_store_relaxed_32(i32* %p, i32 %off32, i32 %val) #0 {
297 ; CHECK-LABEL: atomic_store_relaxed_32:
298 %ptr_unsigned = getelementptr i32, i32* %p, i32 4095
299 store atomic i32 %val, i32* %ptr_unsigned monotonic, align 4
300 ; CHECK: str {{w[0-9]+}}, [x0, #16380]
302 %ptr_regoff = getelementptr i32, i32* %p, i32 %off32
303 store atomic i32 %val, i32* %ptr_regoff unordered, align 4
304 ; CHECK: str {{w[0-9]+}}, [x0, w1, sxtw #2]
306 %ptr_unscaled = getelementptr i32, i32* %p, i32 -64
307 store atomic i32 %val, i32* %ptr_unscaled monotonic, align 4
308 ; CHECK: stur {{w[0-9]+}}, [x0, #-256]
310 %ptr_random = getelementptr i32, i32* %p, i32 297984 ; 0x123000/4 (i.e. ADD imm)
311 store atomic i32 %val, i32* %ptr_random unordered, align 4
312 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
313 ; CHECK: str {{w[0-9]+}}, [x[[ADDR]]]
318 define void @atomic_store_relaxed_64(i64* %p, i32 %off32, i64 %val) #0 {
319 ; CHECK-LABEL: atomic_store_relaxed_64:
320 %ptr_unsigned = getelementptr i64, i64* %p, i32 4095
321 store atomic i64 %val, i64* %ptr_unsigned monotonic, align 8
322 ; CHECK: str {{x[0-9]+}}, [x0, #32760]
324 %ptr_regoff = getelementptr i64, i64* %p, i32 %off32
325 store atomic i64 %val, i64* %ptr_regoff unordered, align 8
326 ; CHECK: str {{x[0-9]+}}, [x0, w1, sxtw #3]
328 %ptr_unscaled = getelementptr i64, i64* %p, i32 -32
329 store atomic i64 %val, i64* %ptr_unscaled monotonic, align 8
330 ; CHECK: stur {{x[0-9]+}}, [x0, #-256]
332 %ptr_random = getelementptr i64, i64* %p, i32 148992 ; 0x123000/8 (i.e. ADD imm)
333 store atomic i64 %val, i64* %ptr_random unordered, align 8
334 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
335 ; CHECK: str {{x[0-9]+}}, [x[[ADDR]]]
343 %"class.X::Atomic" = type { %struct.x_atomic_t }
344 %struct.x_atomic_t = type { i32 }
346 @counter = external hidden global %"class.X::Atomic", align 4
348 define i32 @next_id() nounwind optsize ssp align 2 {
350 %0 = atomicrmw add i32* getelementptr inbounds (%"class.X::Atomic", %"class.X::Atomic"* @counter, i64 0, i32 0, i32 0), i32 1 seq_cst
351 %add.i = add i32 %0, 1
352 %tobool = icmp eq i32 %add.i, 0
353 br i1 %tobool, label %if.else, label %return
355 if.else: ; preds = %entry
356 %1 = atomicrmw add i32* getelementptr inbounds (%"class.X::Atomic", %"class.X::Atomic"* @counter, i64 0, i32 0, i32 0), i32 1 seq_cst
357 %add.i2 = add i32 %1, 1
360 return: ; preds = %if.else, %entry
361 %retval.0 = phi i32 [ %add.i2, %if.else ], [ %add.i, %entry ]
365 attributes #0 = { nounwind }