1 //===- XCoreRegisterInfo.cpp - XCore Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the XCore implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "XCoreRegisterInfo.h"
15 #include "XCoreMachineFunctionInfo.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineLocation.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/RegisterScavenging.h"
24 #include "llvm/Target/TargetFrameInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Type.h"
29 #include "llvm/Function.h"
30 #include "llvm/ADT/BitVector.h"
31 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/Support/Debug.h"
36 XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii)
37 : XCoreGenRegisterInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
42 static inline bool isImmUs(unsigned val) {
46 static inline bool isImmU6(unsigned val) {
47 return val < (1 << 6);
50 static inline bool isImmU16(unsigned val) {
51 return val < (1 << 16);
54 static const unsigned XCore_ArgRegs[] = {
55 XCore::R0, XCore::R1, XCore::R2, XCore::R3
58 const unsigned * XCoreRegisterInfo::getArgRegs(const MachineFunction *MF)
63 unsigned XCoreRegisterInfo::getNumArgRegs(const MachineFunction *MF)
65 return array_lengthof(XCore_ArgRegs);
68 bool XCoreRegisterInfo::needsFrameMoves(const MachineFunction &MF)
70 const MachineFrameInfo *MFI = MF.getFrameInfo();
71 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
72 return (MMI && MMI->hasDebugInfo()) ||
73 !MF.getFunction()->doesNotThrow() ||
74 UnwindTablesMandatory;
77 const unsigned* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
79 static const unsigned CalleeSavedRegs[] = {
80 XCore::R4, XCore::R5, XCore::R6, XCore::R7,
81 XCore::R8, XCore::R9, XCore::R10, XCore::LR,
84 return CalleeSavedRegs;
87 const TargetRegisterClass* const*
88 XCoreRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
89 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
90 XCore::GRRegsRegisterClass, XCore::GRRegsRegisterClass,
91 XCore::GRRegsRegisterClass, XCore::GRRegsRegisterClass,
92 XCore::GRRegsRegisterClass, XCore::GRRegsRegisterClass,
93 XCore::GRRegsRegisterClass, XCore::RRegsRegisterClass,
96 return CalleeSavedRegClasses;
99 BitVector XCoreRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
100 BitVector Reserved(getNumRegs());
101 Reserved.set(XCore::CP);
102 Reserved.set(XCore::DP);
103 Reserved.set(XCore::SP);
104 Reserved.set(XCore::LR);
106 Reserved.set(XCore::R10);
112 XCoreRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
113 // TODO can we estimate stack size?
117 bool XCoreRegisterInfo::hasFP(const MachineFunction &MF) const {
118 return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
121 // This function eliminates ADJCALLSTACKDOWN,
122 // ADJCALLSTACKUP pseudo instructions
123 void XCoreRegisterInfo::
124 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
125 MachineBasicBlock::iterator I) const {
126 if (!hasReservedCallFrame(MF)) {
127 // Turn the adjcallstackdown instruction into 'extsp <amt>' and the
128 // adjcallstackup instruction into 'ldaw sp, sp[<amt>]'
129 MachineInstr *Old = I;
130 uint64_t Amount = Old->getOperand(0).getImm();
132 // We need to keep the stack aligned properly. To do this, we round the
133 // amount of space needed for the outgoing arguments up to the next
134 // alignment boundary.
135 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
136 Amount = (Amount+Align-1)/Align*Align;
138 assert(Amount%4 == 0);
141 bool isU6 = isImmU6(Amount);
143 if (!isU6 && !isImmU16(Amount)) {
144 // FIX could emit multiple instructions in this case.
145 cerr << "eliminateCallFramePseudoInstr size too big: "
151 if (Old->getOpcode() == XCore::ADJCALLSTACKDOWN) {
152 int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
153 New=BuildMI(MF, TII.get(Opcode))
156 assert(Old->getOpcode() == XCore::ADJCALLSTACKUP);
157 int Opcode = isU6 ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs;
158 New=BuildMI(MF, TII.get(Opcode), XCore::SP)
162 // Replace the pseudo instruction with a new instruction...
170 void XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
171 int SPAdj, RegScavenger *RS) const {
172 assert(SPAdj == 0 && "Unexpected");
173 MachineInstr &MI = *II;
176 while (!MI.getOperand(i).isFI()) {
178 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
181 MachineOperand &FrameOp = MI.getOperand(i);
182 int FrameIndex = FrameOp.getIndex();
184 MachineFunction &MF = *MI.getParent()->getParent();
185 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
186 int StackSize = MF.getFrameInfo()->getStackSize();
189 DOUT << "\nFunction : " << MF.getFunction()->getName() << "\n";
190 DOUT << "<--------->\n";
192 DOUT << "FrameIndex : " << FrameIndex << "\n";
193 DOUT << "FrameOffset : " << Offset << "\n";
194 DOUT << "StackSize : " << StackSize << "\n";
199 // fold constant into offset.
200 Offset += MI.getOperand(i + 1).getImm();
201 MI.getOperand(i + 1).ChangeToImmediate(0);
203 assert(Offset%4 == 0 && "Misaligned stack offset");
206 DOUT << "Offset : " << Offset << "\n";
207 DOUT << "<--------->\n";
214 unsigned Reg = MI.getOperand(0).getReg();
215 bool isKill = MI.getOpcode() == XCore::STWFI && MI.getOperand(0).isKill();
217 assert(XCore::GRRegsRegisterClass->contains(Reg) &&
218 "Unexpected register operand");
220 MachineBasicBlock &MBB = *MI.getParent();
223 bool isUs = isImmUs(Offset);
224 unsigned FramePtr = XCore::R10;
226 MachineInstr *New = 0;
229 cerr << "eliminateFrameIndex Frame size too big: " << Offset << "\n";
232 unsigned ScratchReg = RS->scavengeRegister(XCore::GRRegsRegisterClass, II,
234 loadConstant(MBB, II, ScratchReg, Offset);
235 switch (MI.getOpcode()) {
237 New = BuildMI(MBB, II, TII.get(XCore::LDW_3r), Reg)
239 .addReg(ScratchReg, false, false, true);
242 New = BuildMI(MBB, II, TII.get(XCore::STW_3r))
243 .addReg(Reg, false, false, isKill)
245 .addReg(ScratchReg, false, false, true);
248 New = BuildMI(MBB, II, TII.get(XCore::LDAWF_l3r), Reg)
250 .addReg(ScratchReg, false, false, true);
253 assert(0 && "Unexpected Opcode\n");
256 switch (MI.getOpcode()) {
258 New = BuildMI(MBB, II, TII.get(XCore::LDW_2rus), Reg)
263 New = BuildMI(MBB, II, TII.get(XCore::STW_2rus))
264 .addReg(Reg, false, false, isKill)
269 New = BuildMI(MBB, II, TII.get(XCore::LDAWF_l2rus), Reg)
274 assert(0 && "Unexpected Opcode\n");
278 bool isU6 = isImmU6(Offset);
279 if (!isU6 && !isImmU16(Offset)) {
280 // FIXME could make this work for LDWSP, LDAWSP.
281 cerr << "eliminateFrameIndex Frame size too big: " << Offset << "\n";
285 switch (MI.getOpcode()) {
288 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
289 BuildMI(MBB, II, TII.get(NewOpcode), Reg)
293 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
294 BuildMI(MBB, II, TII.get(NewOpcode))
295 .addReg(Reg, false, false, isKill)
299 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
300 BuildMI(MBB, II, TII.get(NewOpcode), Reg)
304 assert(0 && "Unexpected Opcode\n");
307 // Erase old instruction.
312 XCoreRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
313 RegScavenger *RS) const {
314 MachineFrameInfo *MFI = MF.getFrameInfo();
315 bool LRUsed = MF.getRegInfo().isPhysRegUsed(XCore::LR);
316 const TargetRegisterClass *RC = XCore::GRRegsRegisterClass;
317 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
319 MF.getRegInfo().setPhysRegUnused(XCore::LR);
321 bool isVarArg = MF.getFunction()->isVarArg();
324 // A fixed offset of 0 allows us to save / restore LR using entsp / retsp.
325 FrameIdx = MFI->CreateFixedObject(RC->getSize(), 0);
327 FrameIdx = MFI->CreateStackObject(RC->getSize(), RC->getAlignment());
329 XFI->setUsesLR(FrameIdx);
330 XFI->setLRSpillSlot(FrameIdx);
332 if (requiresRegisterScavenging(MF)) {
333 // Reserve a slot close to SP or frame pointer.
334 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
335 RC->getAlignment()));
338 // A callee save register is used to hold the FP.
339 // This needs saving / restoring in the epilogue / prologue.
340 XFI->setFPSpillSlot(MFI->CreateStackObject(RC->getSize(),
341 RC->getAlignment()));
345 void XCoreRegisterInfo::
346 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
350 void XCoreRegisterInfo::
351 loadConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
352 unsigned DstReg, int64_t Value) const {
353 // TODO use mkmsk if possible.
354 if (!isImmU16(Value)) {
355 // TODO use constant pool.
356 cerr << "loadConstant value too big " << Value << "\n";
359 int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
360 BuildMI(MBB, I, TII.get(Opcode), DstReg).addImm(Value);
363 void XCoreRegisterInfo::
364 storeToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
365 unsigned SrcReg, int Offset) const {
366 assert(Offset%4 == 0 && "Misaligned stack offset");
368 bool isU6 = isImmU6(Offset);
369 if (!isU6 && !isImmU16(Offset)) {
370 cerr << "storeToStack offset too big " << Offset << "\n";
373 int Opcode = isU6 ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
374 BuildMI(MBB, I, TII.get(Opcode))
379 void XCoreRegisterInfo::
380 loadFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
381 unsigned DstReg, int Offset) const {
382 assert(Offset%4 == 0 && "Misaligned stack offset");
384 bool isU6 = isImmU6(Offset);
385 if (!isU6 && !isImmU16(Offset)) {
386 cerr << "storeToStack offset too big " << Offset << "\n";
389 int Opcode = isU6 ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
390 BuildMI(MBB, I, TII.get(Opcode), DstReg)
394 void XCoreRegisterInfo::emitPrologue(MachineFunction &MF) const {
395 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
396 MachineBasicBlock::iterator MBBI = MBB.begin();
397 MachineFrameInfo *MFI = MF.getFrameInfo();
398 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
399 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
403 // Work out frame sizes.
404 int FrameSize = MFI->getStackSize();
406 assert(FrameSize%4 == 0 && "Misaligned frame size");
410 bool isU6 = isImmU6(FrameSize);
412 if (!isU6 && !isImmU16(FrameSize)) {
413 // FIXME could emit multiple instructions.
414 cerr << "emitPrologue Frame size too big: " << FrameSize << "\n";
417 bool emitFrameMoves = needsFrameMoves(MF);
419 // Do we need to allocate space on the stack?
421 bool saveLR = XFI->getUsesLR();
422 bool LRSavedOnEntry = false;
424 if (saveLR && (MFI->getObjectOffset(XFI->getLRSpillSlot()) == 0)) {
425 Opcode = (isU6) ? XCore::ENTSP_u6 : XCore::ENTSP_lu6;
426 MBB.addLiveIn(XCore::LR);
428 LRSavedOnEntry = true;
430 Opcode = (isU6) ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
432 BuildMI(MBB, MBBI, TII.get(Opcode)).addImm(FrameSize);
434 if (emitFrameMoves) {
435 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
437 // Show update of SP.
438 unsigned FrameLabelId = MMI->NextLabelID();
439 BuildMI(MBB, MBBI, TII.get(XCore::DBG_LABEL)).addImm(FrameLabelId);
441 MachineLocation SPDst(MachineLocation::VirtualFP);
442 MachineLocation SPSrc(MachineLocation::VirtualFP, -FrameSize * 4);
443 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
445 if (LRSavedOnEntry) {
446 MachineLocation CSDst(MachineLocation::VirtualFP, 0);
447 MachineLocation CSSrc(XCore::LR);
448 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
452 int LRSpillOffset = MFI->getObjectOffset(XFI->getLRSpillSlot());
453 storeToStack(MBB, MBBI, XCore::LR, LRSpillOffset + FrameSize*4);
454 MBB.addLiveIn(XCore::LR);
456 if (emitFrameMoves) {
457 unsigned SaveLRLabelId = MMI->NextLabelID();
458 BuildMI(MBB, MBBI, TII.get(XCore::DBG_LABEL)).addImm(SaveLRLabelId);
459 MachineLocation CSDst(MachineLocation::VirtualFP, LRSpillOffset);
460 MachineLocation CSSrc(XCore::LR);
461 MMI->getFrameMoves().push_back(MachineMove(SaveLRLabelId,
468 // Save R10 to the stack.
469 int FPSpillOffset = MFI->getObjectOffset(XFI->getFPSpillSlot());
470 storeToStack(MBB, MBBI, XCore::R10, FPSpillOffset + FrameSize*4);
471 // R10 is live-in. It is killed at the spill.
472 MBB.addLiveIn(XCore::R10);
473 if (emitFrameMoves) {
474 unsigned SaveR10LabelId = MMI->NextLabelID();
475 BuildMI(MBB, MBBI, TII.get(XCore::DBG_LABEL)).addImm(SaveR10LabelId);
476 MachineLocation CSDst(MachineLocation::VirtualFP, FPSpillOffset);
477 MachineLocation CSSrc(XCore::R10);
478 MMI->getFrameMoves().push_back(MachineMove(SaveR10LabelId,
481 // Set the FP from the SP.
482 unsigned FramePtr = XCore::R10;
483 BuildMI(MBB, MBBI, TII.get(XCore::LDAWSP_ru6), FramePtr)
485 if (emitFrameMoves) {
486 // Show FP is now valid.
487 unsigned FrameLabelId = MMI->NextLabelID();
488 BuildMI(MBB, MBBI, TII.get(XCore::DBG_LABEL)).addImm(FrameLabelId);
489 MachineLocation SPDst(FramePtr);
490 MachineLocation SPSrc(MachineLocation::VirtualFP);
491 MMI->getFrameMoves().push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
495 if (emitFrameMoves) {
496 // Frame moves for callee saved.
497 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
498 std::vector<std::pair<unsigned, CalleeSavedInfo> >&SpillLabels =
499 XFI->getSpillLabels();
500 for (unsigned I = 0, E = SpillLabels.size(); I != E; ++I) {
501 unsigned SpillLabel = SpillLabels[I].first;
502 CalleeSavedInfo &CSI = SpillLabels[I].second;
503 int Offset = MFI->getObjectOffset(CSI.getFrameIdx());
504 unsigned Reg = CSI.getReg();
505 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
506 MachineLocation CSSrc(Reg);
507 Moves.push_back(MachineMove(SpillLabel, CSDst, CSSrc));
512 void XCoreRegisterInfo::emitEpilogue(MachineFunction &MF,
513 MachineBasicBlock &MBB) const {
514 MachineFrameInfo *MFI = MF.getFrameInfo();
515 MachineBasicBlock::iterator MBBI = prior(MBB.end());
520 // Restore the stack pointer.
521 unsigned FramePtr = XCore::R10;
522 BuildMI(MBB, MBBI, TII.get(XCore::SETSP_1r))
526 // Work out frame sizes.
527 int FrameSize = MFI->getStackSize();
529 assert(FrameSize%4 == 0 && "Misaligned frame size");
533 bool isU6 = isImmU6(FrameSize);
535 if (!isU6 && !isImmU16(FrameSize)) {
536 // FIXME could emit multiple instructions.
537 cerr << "emitEpilogue Frame size too big: " << FrameSize << "\n";
542 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
546 int FPSpillOffset = MFI->getObjectOffset(XFI->getFPSpillSlot());
547 FPSpillOffset += FrameSize*4;
548 loadFromStack(MBB, MBBI, XCore::R10, FPSpillOffset);
550 bool restoreLR = XFI->getUsesLR();
551 if (restoreLR && MFI->getObjectOffset(XFI->getLRSpillSlot()) != 0) {
552 int LRSpillOffset = MFI->getObjectOffset(XFI->getLRSpillSlot());
553 LRSpillOffset += FrameSize*4;
554 loadFromStack(MBB, MBBI, XCore::LR, LRSpillOffset);
558 // Fold prologue into return instruction
559 assert(MBBI->getOpcode() == XCore::RETSP_u6
560 || MBBI->getOpcode() == XCore::RETSP_lu6);
561 int Opcode = (isU6) ? XCore::RETSP_u6 : XCore::RETSP_lu6;
562 BuildMI(MBB, MBBI, TII.get(Opcode)).addImm(FrameSize);
565 int Opcode = (isU6) ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs;
566 BuildMI(MBB, MBBI, TII.get(Opcode), XCore::SP).addImm(FrameSize);
571 int XCoreRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
572 return XCoreGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
575 unsigned XCoreRegisterInfo::getFrameRegister(MachineFunction &MF) const {
578 return FP ? XCore::R10 : XCore::SP;
581 unsigned XCoreRegisterInfo::getRARegister() const {
585 void XCoreRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
587 // Initial state of the frame pointer is SP.
588 MachineLocation Dst(MachineLocation::VirtualFP);
589 MachineLocation Src(XCore::SP, 0);
590 Moves.push_back(MachineMove(0, Dst, Src));
593 #include "XCoreGenRegisterInfo.inc"