1 //===-- XCoreRegisterInfo.cpp - XCore Register Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the XCore implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "XCoreRegisterInfo.h"
16 #include "XCoreMachineFunctionInfo.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineModuleInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/IR/Type.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/raw_ostream.h"
30 #include "llvm/Target/TargetFrameLowering.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetOptions.h"
35 #define GET_REGINFO_TARGET_DESC
36 #include "XCoreGenRegisterInfo.inc"
40 XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii)
41 : XCoreGenRegisterInfo(XCore::LR), TII(tii) {
45 static inline bool isImmUs(unsigned val) {
49 static inline bool isImmU6(unsigned val) {
50 return val < (1 << 6);
53 static inline bool isImmU16(unsigned val) {
54 return val < (1 << 16);
57 bool XCoreRegisterInfo::needsFrameMoves(const MachineFunction &MF) {
58 return MF.getMMI().hasDebugInfo() ||
59 MF.getFunction()->needsUnwindTableEntry();
62 const uint16_t* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
64 static const uint16_t CalleeSavedRegs[] = {
65 XCore::R4, XCore::R5, XCore::R6, XCore::R7,
66 XCore::R8, XCore::R9, XCore::R10, XCore::LR,
69 return CalleeSavedRegs;
72 BitVector XCoreRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
73 BitVector Reserved(getNumRegs());
74 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
76 Reserved.set(XCore::CP);
77 Reserved.set(XCore::DP);
78 Reserved.set(XCore::SP);
79 Reserved.set(XCore::LR);
81 Reserved.set(XCore::R10);
87 XCoreRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
88 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
90 // TODO can we estimate stack size?
91 return TFI->hasFP(MF);
95 XCoreRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
96 return requiresRegisterScavenging(MF);
100 XCoreRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
104 // This function eliminates ADJCALLSTACKDOWN,
105 // ADJCALLSTACKUP pseudo instructions
106 void XCoreRegisterInfo::
107 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
108 MachineBasicBlock::iterator I) const {
109 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
111 if (!TFI->hasReservedCallFrame(MF)) {
112 // Turn the adjcallstackdown instruction into 'extsp <amt>' and the
113 // adjcallstackup instruction into 'ldaw sp, sp[<amt>]'
114 MachineInstr *Old = I;
115 uint64_t Amount = Old->getOperand(0).getImm();
117 // We need to keep the stack aligned properly. To do this, we round the
118 // amount of space needed for the outgoing arguments up to the next
119 // alignment boundary.
120 unsigned Align = TFI->getStackAlignment();
121 Amount = (Amount+Align-1)/Align*Align;
123 assert(Amount%4 == 0);
126 bool isU6 = isImmU6(Amount);
127 if (!isU6 && !isImmU16(Amount)) {
128 // FIX could emit multiple instructions in this case.
130 errs() << "eliminateCallFramePseudoInstr size too big: "
137 if (Old->getOpcode() == XCore::ADJCALLSTACKDOWN) {
138 int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
139 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode))
142 assert(Old->getOpcode() == XCore::ADJCALLSTACKUP);
143 int Opcode = isU6 ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs;
144 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP)
148 // Replace the pseudo instruction with a new instruction...
157 XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
158 int SPAdj, unsigned FIOperandNum,
159 RegScavenger *RS) const {
160 assert(SPAdj == 0 && "Unexpected");
161 MachineInstr &MI = *II;
162 DebugLoc dl = MI.getDebugLoc();
163 MachineOperand &FrameOp = MI.getOperand(FIOperandNum);
164 int FrameIndex = FrameOp.getIndex();
166 MachineFunction &MF = *MI.getParent()->getParent();
167 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
168 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
169 int StackSize = MF.getFrameInfo()->getStackSize();
172 DEBUG(errs() << "\nFunction : "
173 << MF.getName() << "\n");
174 DEBUG(errs() << "<--------->\n");
175 DEBUG(MI.print(errs()));
176 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n");
177 DEBUG(errs() << "FrameOffset : " << Offset << "\n");
178 DEBUG(errs() << "StackSize : " << StackSize << "\n");
183 unsigned FrameReg = getFrameRegister(MF);
185 // Special handling of DBG_VALUE instructions.
186 if (MI.isDebugValue()) {
187 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
188 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
192 // fold constant into offset.
193 Offset += MI.getOperand(FIOperandNum + 1).getImm();
194 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
196 assert(Offset%4 == 0 && "Misaligned stack offset");
198 DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
202 bool FP = TFI->hasFP(MF);
204 unsigned Reg = MI.getOperand(0).getReg();
205 bool isKill = MI.getOpcode() == XCore::STWFI && MI.getOperand(0).isKill();
207 assert(XCore::GRRegsRegClass.contains(Reg) && "Unexpected register operand");
209 MachineBasicBlock &MBB = *MI.getParent();
212 bool isUs = isImmUs(Offset);
216 report_fatal_error("eliminateFrameIndex Frame size too big: " +
218 unsigned ScratchReg = RS->scavengeRegister(&XCore::GRRegsRegClass, II,
220 loadConstant(MBB, II, ScratchReg, Offset, dl);
221 switch (MI.getOpcode()) {
223 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
225 .addReg(ScratchReg, RegState::Kill);
228 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r))
229 .addReg(Reg, getKillRegState(isKill))
231 .addReg(ScratchReg, RegState::Kill);
234 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
236 .addReg(ScratchReg, RegState::Kill);
239 llvm_unreachable("Unexpected Opcode");
242 switch (MI.getOpcode()) {
244 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
249 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
250 .addReg(Reg, getKillRegState(isKill))
255 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
260 llvm_unreachable("Unexpected Opcode");
264 bool isU6 = isImmU6(Offset);
265 if (!isU6 && !isImmU16(Offset))
266 report_fatal_error("eliminateFrameIndex Frame size too big: " +
269 switch (MI.getOpcode()) {
272 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
273 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
277 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
278 BuildMI(MBB, II, dl, TII.get(NewOpcode))
279 .addReg(Reg, getKillRegState(isKill))
283 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
284 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
288 llvm_unreachable("Unexpected Opcode");
291 // Erase old instruction.
295 void XCoreRegisterInfo::
296 loadConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
297 unsigned DstReg, int64_t Value, DebugLoc dl) const {
298 // TODO use mkmsk if possible.
299 if (!isImmU16(Value)) {
300 // TODO use constant pool.
301 report_fatal_error("loadConstant value too big " + Twine(Value));
303 int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
304 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value);
307 unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
308 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
310 return TFI->hasFP(MF) ? XCore::R10 : XCore::SP;