lib/Target/XCore/Disassembler/XCoreDisassembler.cpp

   1 //===- XCoreDisassembler.cpp - Disassembler for XCore -----------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 ///
  10 /// \file
  11 /// \brief This file is part of the XCore Disassembler.
  12 ///
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "XCore.h"
  16 #include "XCoreRegisterInfo.h"
  17 #include "llvm/MC/MCContext.h"
  18 #include "llvm/MC/MCDisassembler.h"
  19 #include "llvm/MC/MCFixedLenDisassembler.h"
  20 #include "llvm/MC/MCInst.h"
  21 #include "llvm/MC/MCSubtargetInfo.h"
  22 #include "llvm/Support/MemoryObject.h"
  23 #include "llvm/Support/TargetRegistry.h"
  24
  25 using namespace llvm;
  26
  27 #define DEBUG_TYPE "xcore-disassembler"
  28
  29 typedef MCDisassembler::DecodeStatus DecodeStatus;
  30
  31 namespace {
  32
  33 /// \brief A disassembler class for XCore.
  34 class XCoreDisassembler : public MCDisassembler {
  35 public:
  36   XCoreDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
  37     MCDisassembler(STI, Ctx) {}
  38
  39   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
  40                               const MemoryObject &Region, uint64_t Address,
  41                               raw_ostream &VStream,
  42                               raw_ostream &CStream) const override;
  43 };
  44 }
  45
  46 static bool readInstruction16(const MemoryObject &Region, uint64_t Address,
  47                               uint64_t &Size, uint16_t &Insn) {
  48   uint8_t Bytes[4];
  49
  50   // We want to read exactly 2 Bytes of data.
  51   if (Region.readBytes(Address, 2, Bytes) == -1) {
  52     Size = 0;
  53     return false;
  54   }
  55   // Encoded as a little-endian 16-bit word in the stream.
  56   Insn = (Bytes[0] << 0) | (Bytes[1] << 8);
  57   return true;
  58 }
  59
  60 static bool readInstruction32(const MemoryObject &Region, uint64_t Address,
  61                               uint64_t &Size, uint32_t &Insn) {
  62   uint8_t Bytes[4];
  63
  64   // We want to read exactly 4 Bytes of data.
  65   if (Region.readBytes(Address, 4, Bytes) == -1) {
  66     Size = 0;
  67     return false;
  68   }
  69   // Encoded as a little-endian 32-bit word in the stream.
  70   Insn =
  71       (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | (Bytes[3] << 24);
  72   return true;
  73 }
  74
  75 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
  76   const XCoreDisassembler *Dis = static_cast<const XCoreDisassembler*>(D);
  77   const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
  78   return *(RegInfo->getRegClass(RC).begin() + RegNo);
  79 }
  80
  81 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
  82                                               unsigned RegNo,
  83                                               uint64_t Address,
  84                                               const void *Decoder);
  85
  86 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst,
  87                                              unsigned RegNo,
  88                                              uint64_t Address,
  89                                              const void *Decoder);
  90
  91 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
  92                                       uint64_t Address, const void *Decoder);
  93
  94 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
  95                                         uint64_t Address, const void *Decoder);
  96
  97 static DecodeStatus Decode2RInstruction(MCInst &Inst,
  98                                         unsigned Insn,
  99                                         uint64_t Address,
 100                                         const void *Decoder);
 101
 102 static DecodeStatus Decode2RImmInstruction(MCInst &Inst,
 103                                            unsigned Insn,
 104                                            uint64_t Address,
 105                                            const void *Decoder);
 106
 107 static DecodeStatus DecodeR2RInstruction(MCInst &Inst,
 108                                          unsigned Insn,
 109                                          uint64_t Address,
 110                                          const void *Decoder);
 111
 112 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst,
 113                                               unsigned Insn,
 114                                               uint64_t Address,
 115                                               const void *Decoder);
 116
 117 static DecodeStatus DecodeRUSInstruction(MCInst &Inst,
 118                                          unsigned Insn,
 119                                          uint64_t Address,
 120                                          const void *Decoder);
 121
 122 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst,
 123                                              unsigned Insn,
 124                                              uint64_t Address,
 125                                              const void *Decoder);
 126
 127 static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst &Inst,
 128                                                    unsigned Insn,
 129                                                    uint64_t Address,
 130                                                    const void *Decoder);
 131
 132 static DecodeStatus DecodeL2RInstruction(MCInst &Inst,
 133                                          unsigned Insn,
 134                                          uint64_t Address,
 135                                          const void *Decoder);
 136
 137 static DecodeStatus DecodeLR2RInstruction(MCInst &Inst,
 138                                           unsigned Insn,
 139                                           uint64_t Address,
 140                                           const void *Decoder);
 141
 142 static DecodeStatus Decode3RInstruction(MCInst &Inst,
 143                                         unsigned Insn,
 144                                         uint64_t Address,
 145                                         const void *Decoder);
 146
 147 static DecodeStatus Decode3RImmInstruction(MCInst &Inst,
 148                                            unsigned Insn,
 149                                            uint64_t Address,
 150                                            const void *Decoder);
 151
 152 static DecodeStatus Decode2RUSInstruction(MCInst &Inst,
 153                                           unsigned Insn,
 154                                           uint64_t Address,
 155                                           const void *Decoder);
 156
 157 static DecodeStatus Decode2RUSBitpInstruction(MCInst &Inst,
 158                                               unsigned Insn,
 159                                               uint64_t Address,
 160                                               const void *Decoder);
 161
 162 static DecodeStatus DecodeL3RInstruction(MCInst &Inst,
 163                                          unsigned Insn,
 164                                          uint64_t Address,
 165                                          const void *Decoder);
 166
 167 static DecodeStatus DecodeL3RSrcDstInstruction(MCInst &Inst,
 168                                                unsigned Insn,
 169                                                uint64_t Address,
 170                                                const void *Decoder);
 171
 172 static DecodeStatus DecodeL2RUSInstruction(MCInst &Inst,
 173                                            unsigned Insn,
 174                                            uint64_t Address,
 175                                            const void *Decoder);
 176
 177 static DecodeStatus DecodeL2RUSBitpInstruction(MCInst &Inst,
 178                                                unsigned Insn,
 179                                                uint64_t Address,
 180                                                const void *Decoder);
 181
 182 static DecodeStatus DecodeL6RInstruction(MCInst &Inst,
 183                                          unsigned Insn,
 184                                          uint64_t Address,
 185                                          const void *Decoder);
 186
 187 static DecodeStatus DecodeL5RInstruction(MCInst &Inst,
 188                                          unsigned Insn,
 189                                          uint64_t Address,
 190                                          const void *Decoder);
 191
 192 static DecodeStatus DecodeL4RSrcDstInstruction(MCInst &Inst,
 193                                                unsigned Insn,
 194                                                uint64_t Address,
 195                                                const void *Decoder);
 196
 197 static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst,
 198                                                      unsigned Insn,
 199                                                      uint64_t Address,
 200                                                      const void *Decoder);
 201
 202 #include "XCoreGenDisassemblerTables.inc"
 203
 204 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
 205                                               unsigned RegNo,
 206                                               uint64_t Address,
 207                                               const void *Decoder)
 208 {
 209   if (RegNo > 11)
 210     return MCDisassembler::Fail;
 211   unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo);
 212   Inst.addOperand(MCOperand::CreateReg(Reg));
 213   return MCDisassembler::Success;
 214 }
 215
 216 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst,
 217                                              unsigned RegNo,
 218                                              uint64_t Address,
 219                                              const void *Decoder)
 220 {
 221   if (RegNo > 15)
 222     return MCDisassembler::Fail;
 223   unsigned Reg = getReg(Decoder, XCore::RRegsRegClassID, RegNo);
 224   Inst.addOperand(MCOperand::CreateReg(Reg));
 225   return MCDisassembler::Success;
 226 }
 227
 228 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
 229                                       uint64_t Address, const void *Decoder) {
 230   if (Val > 11)
 231     return MCDisassembler::Fail;
 232   static unsigned Values[] = {
 233     32 /*bpw*/, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32
 234   };
 235   Inst.addOperand(MCOperand::CreateImm(Values[Val]));
 236   return MCDisassembler::Success;
 237 }
 238
 239 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
 240                                         uint64_t Address, const void *Decoder) {
 241   Inst.addOperand(MCOperand::CreateImm(-(int64_t)Val));
 242   return MCDisassembler::Success;
 243 }
 244
 245 static DecodeStatus
 246 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
 247   unsigned Combined = fieldFromInstruction(Insn, 6, 5);
 248   if (Combined < 27)
 249     return MCDisassembler::Fail;
 250   if (fieldFromInstruction(Insn, 5, 1)) {
 251     if (Combined == 31)
 252       return MCDisassembler::Fail;
 253     Combined += 5;
 254   }
 255   Combined -= 27;
 256   unsigned Op1High = Combined % 3;
 257   unsigned Op2High = Combined / 3;
 258   Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2);
 259   Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2);
 260   return MCDisassembler::Success;
 261 }
 262
 263 static DecodeStatus
 264 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2,
 265                      unsigned &Op3) {
 266   unsigned Combined = fieldFromInstruction(Insn, 6, 5);
 267   if (Combined >= 27)
 268     return MCDisassembler::Fail;
 269
 270   unsigned Op1High = Combined % 3;
 271   unsigned Op2High = (Combined / 3) % 3;
 272   unsigned Op3High = Combined / 9;
 273   Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2);
 274   Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2);
 275   Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2);
 276   return MCDisassembler::Success;
 277 }
 278
 279 static DecodeStatus
 280 Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
 281                          const void *Decoder) {
 282   // Try and decode as a 3R instruction.
 283   unsigned Opcode = fieldFromInstruction(Insn, 11, 5);
 284   switch (Opcode) {
 285   case 0x0:
 286     Inst.setOpcode(XCore::STW_2rus);
 287     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
 288   case 0x1:
 289     Inst.setOpcode(XCore::LDW_2rus);
 290     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
 291   case 0x2:
 292     Inst.setOpcode(XCore::ADD_3r);
 293     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 294   case 0x3:
 295     Inst.setOpcode(XCore::SUB_3r);
 296     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 297   case 0x4:
 298     Inst.setOpcode(XCore::SHL_3r);
 299     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 300   case 0x5:
 301     Inst.setOpcode(XCore::SHR_3r);
 302     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 303   case 0x6:
 304     Inst.setOpcode(XCore::EQ_3r);
 305     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 306   case 0x7:
 307     Inst.setOpcode(XCore::AND_3r);
 308     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 309   case 0x8:
 310     Inst.setOpcode(XCore::OR_3r);
 311     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 312   case 0x9:
 313     Inst.setOpcode(XCore::LDW_3r);
 314     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 315   case 0x10:
 316     Inst.setOpcode(XCore::LD16S_3r);
 317     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 318   case 0x11:
 319     Inst.setOpcode(XCore::LD8U_3r);
 320     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 321   case 0x12:
 322     Inst.setOpcode(XCore::ADD_2rus);
 323     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
 324   case 0x13:
 325     Inst.setOpcode(XCore::SUB_2rus);
 326     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
 327   case 0x14:
 328     Inst.setOpcode(XCore::SHL_2rus);
 329     return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
 330   case 0x15:
 331     Inst.setOpcode(XCore::SHR_2rus);
 332     return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
 333   case 0x16:
 334     Inst.setOpcode(XCore::EQ_2rus);
 335     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
 336   case 0x17:
 337     Inst.setOpcode(XCore::TSETR_3r);
 338     return Decode3RImmInstruction(Inst, Insn, Address, Decoder);
 339   case 0x18:
 340     Inst.setOpcode(XCore::LSS_3r);
 341     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 342   case 0x19:
 343     Inst.setOpcode(XCore::LSU_3r);
 344     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 345   }
 346   return MCDisassembler::Fail;
 347 }
 348
 349 static DecodeStatus
 350 Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 351                     const void *Decoder) {
 352   unsigned Op1, Op2;
 353   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 354   if (S != MCDisassembler::Success)
 355     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 356
 357   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 358   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 359   return S;
 360 }
 361
 362 static DecodeStatus
 363 Decode2RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 364                        const void *Decoder) {
 365   unsigned Op1, Op2;
 366   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 367   if (S != MCDisassembler::Success)
 368     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 369
 370   Inst.addOperand(MCOperand::CreateImm(Op1));
 371   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 372   return S;
 373 }
 374
 375 static DecodeStatus
 376 DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 377                      const void *Decoder) {
 378   unsigned Op1, Op2;
 379   DecodeStatus S = Decode2OpInstruction(Insn, Op2, Op1);
 380   if (S != MCDisassembler::Success)
 381     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 382
 383   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 384   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 385   return S;
 386 }
 387
 388 static DecodeStatus
 389 Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 390                           const void *Decoder) {
 391   unsigned Op1, Op2;
 392   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 393   if (S != MCDisassembler::Success)
 394     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 395
 396   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 397   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 398   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 399   return S;
 400 }
 401
 402 static DecodeStatus
 403 DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 404                      const void *Decoder) {
 405   unsigned Op1, Op2;
 406   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 407   if (S != MCDisassembler::Success)
 408     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 409
 410   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 411   Inst.addOperand(MCOperand::CreateImm(Op2));
 412   return S;
 413 }
 414
 415 static DecodeStatus
 416 DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 417                          const void *Decoder) {
 418   unsigned Op1, Op2;
 419   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 420   if (S != MCDisassembler::Success)
 421     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 422
 423   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 424   DecodeBitpOperand(Inst, Op2, Address, Decoder);
 425   return S;
 426 }
 427
 428 static DecodeStatus
 429 DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 430                                const void *Decoder) {
 431   unsigned Op1, Op2;
 432   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 433   if (S != MCDisassembler::Success)
 434     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 435
 436   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 437   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 438   DecodeBitpOperand(Inst, Op2, Address, Decoder);
 439   return S;
 440 }
 441
 442 static DecodeStatus
 443 DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
 444                           const void *Decoder) {
 445   // Try and decode as a L3R / L2RUS instruction.
 446   unsigned Opcode = fieldFromInstruction(Insn, 16, 4) |
 447                     fieldFromInstruction(Insn, 27, 5) << 4;
 448   switch (Opcode) {
 449   case 0x0c:
 450     Inst.setOpcode(XCore::STW_l3r);
 451     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 452   case 0x1c:
 453     Inst.setOpcode(XCore::XOR_l3r);
 454     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 455   case 0x2c:
 456     Inst.setOpcode(XCore::ASHR_l3r);
 457     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 458   case 0x3c:
 459     Inst.setOpcode(XCore::LDAWF_l3r);
 460     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 461   case 0x4c:
 462     Inst.setOpcode(XCore::LDAWB_l3r);
 463     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 464   case 0x5c:
 465     Inst.setOpcode(XCore::LDA16F_l3r);
 466     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 467   case 0x6c:
 468     Inst.setOpcode(XCore::LDA16B_l3r);
 469     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 470   case 0x7c:
 471     Inst.setOpcode(XCore::MUL_l3r);
 472     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 473   case 0x8c:
 474     Inst.setOpcode(XCore::DIVS_l3r);
 475     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 476   case 0x9c:
 477     Inst.setOpcode(XCore::DIVU_l3r);
 478     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 479   case 0x10c:
 480     Inst.setOpcode(XCore::ST16_l3r);
 481     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 482   case 0x11c:
 483     Inst.setOpcode(XCore::ST8_l3r);
 484     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 485   case 0x12c:
 486     Inst.setOpcode(XCore::ASHR_l2rus);
 487     return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
 488   case 0x12d:
 489     Inst.setOpcode(XCore::OUTPW_l2rus);
 490     return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
 491   case 0x12e:
 492     Inst.setOpcode(XCore::INPW_l2rus);
 493     return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
 494   case 0x13c:
 495     Inst.setOpcode(XCore::LDAWF_l2rus);
 496     return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
 497   case 0x14c:
 498     Inst.setOpcode(XCore::LDAWB_l2rus);
 499     return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
 500   case 0x15c:
 501     Inst.setOpcode(XCore::CRC_l3r);
 502     return DecodeL3RSrcDstInstruction(Inst, Insn, Address, Decoder);
 503   case 0x18c:
 504     Inst.setOpcode(XCore::REMS_l3r);
 505     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 506   case 0x19c:
 507     Inst.setOpcode(XCore::REMU_l3r);
 508     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 509   }
 510   return MCDisassembler::Fail;
 511 }
 512
 513 static DecodeStatus
 514 DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 515                                const void *Decoder) {
 516   unsigned Op1, Op2;
 517   DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
 518                                         Op1, Op2);
 519   if (S != MCDisassembler::Success)
 520     return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
 521
 522   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 523   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 524   return S;
 525 }
 526
 527 static DecodeStatus
 528 DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 529                                const void *Decoder) {
 530   unsigned Op1, Op2;
 531   DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
 532                                         Op1, Op2);
 533   if (S != MCDisassembler::Success)
 534     return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
 535
 536   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 537   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 538   return S;
 539 }
 540
 541 static DecodeStatus
 542 Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 543                     const void *Decoder) {
 544   unsigned Op1, Op2, Op3;
 545   DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
 546   if (S == MCDisassembler::Success) {
 547     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 548     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 549     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 550   }
 551   return S;
 552 }
 553
 554 static DecodeStatus
 555 Decode3RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 556                        const void *Decoder) {
 557   unsigned Op1, Op2, Op3;
 558   DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
 559   if (S == MCDisassembler::Success) {
 560     Inst.addOperand(MCOperand::CreateImm(Op1));
 561     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 562     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 563   }
 564   return S;
 565 }
 566
 567 static DecodeStatus
 568 Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 569                       const void *Decoder) {
 570   unsigned Op1, Op2, Op3;
 571   DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
 572   if (S == MCDisassembler::Success) {
 573     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 574     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 575     Inst.addOperand(MCOperand::CreateImm(Op3));
 576   }
 577   return S;
 578 }
 579
 580 static DecodeStatus
 581 Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 582                       const void *Decoder) {
 583   unsigned Op1, Op2, Op3;
 584   DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
 585   if (S == MCDisassembler::Success) {
 586     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 587     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 588     DecodeBitpOperand(Inst, Op3, Address, Decoder);
 589   }
 590   return S;
 591 }
 592
 593 static DecodeStatus
 594 DecodeL3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 595                      const void *Decoder) {
 596   unsigned Op1, Op2, Op3;
 597   DecodeStatus S =
 598     Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 599   if (S == MCDisassembler::Success) {
 600     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 601     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 602     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 603   }
 604   return S;
 605 }
 606
 607 static DecodeStatus
 608 DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 609                            const void *Decoder) {
 610   unsigned Op1, Op2, Op3;
 611   DecodeStatus S =
 612   Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 613   if (S == MCDisassembler::Success) {
 614     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 615     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 616     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 617     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 618   }
 619   return S;
 620 }
 621
 622 static DecodeStatus
 623 DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 624                        const void *Decoder) {
 625   unsigned Op1, Op2, Op3;
 626   DecodeStatus S =
 627   Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 628   if (S == MCDisassembler::Success) {
 629     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 630     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 631     Inst.addOperand(MCOperand::CreateImm(Op3));
 632   }
 633   return S;
 634 }
 635
 636 static DecodeStatus
 637 DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 638                            const void *Decoder) {
 639   unsigned Op1, Op2, Op3;
 640   DecodeStatus S =
 641   Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 642   if (S == MCDisassembler::Success) {
 643     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 644     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 645     DecodeBitpOperand(Inst, Op3, Address, Decoder);
 646   }
 647   return S;
 648 }
 649
 650 static DecodeStatus
 651 DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 652                      const void *Decoder) {
 653   unsigned Op1, Op2, Op3, Op4, Op5, Op6;
 654   DecodeStatus S =
 655     Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 656   if (S != MCDisassembler::Success)
 657     return S;
 658   S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6);
 659   if (S != MCDisassembler::Success)
 660     return S;
 661   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 662   DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
 663   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 664   DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 665   DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
 666   DecodeGRRegsRegisterClass(Inst, Op6, Address, Decoder);
 667   return S;
 668 }
 669
 670 static DecodeStatus
 671 DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
 672                      const void *Decoder) {
 673   // Try and decode as a L6R instruction.
 674   Inst.clear();
 675   unsigned Opcode = fieldFromInstruction(Insn, 27, 5);
 676   switch (Opcode) {
 677   case 0x00:
 678     Inst.setOpcode(XCore::LMUL_l6r);
 679     return DecodeL6RInstruction(Inst, Insn, Address, Decoder);
 680   }
 681   return MCDisassembler::Fail;
 682 }
 683
 684 static DecodeStatus
 685 DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 686                      const void *Decoder) {
 687   unsigned Op1, Op2, Op3, Op4, Op5;
 688   DecodeStatus S =
 689     Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 690   if (S != MCDisassembler::Success)
 691     return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
 692   S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5);
 693   if (S != MCDisassembler::Success)
 694     return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
 695
 696   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 697   DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
 698   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 699   DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 700   DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
 701   return S;
 702 }
 703
 704 static DecodeStatus
 705 DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 706                            const void *Decoder) {
 707   unsigned Op1, Op2, Op3;
 708   unsigned Op4 = fieldFromInstruction(Insn, 16, 4);
 709   DecodeStatus S =
 710     Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 711   if (S == MCDisassembler::Success) {
 712     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 713     S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
 714   }
 715   if (S == MCDisassembler::Success) {
 716     DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
 717     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 718     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 719   }
 720   return S;
 721 }
 722
 723 static DecodeStatus
 724 DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 725                                  const void *Decoder) {
 726   unsigned Op1, Op2, Op3;
 727   unsigned Op4 = fieldFromInstruction(Insn, 16, 4);
 728   DecodeStatus S =
 729   Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 730   if (S == MCDisassembler::Success) {
 731     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 732     S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
 733   }
 734   if (S == MCDisassembler::Success) {
 735     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 736     DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
 737     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 738     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 739   }
 740   return S;
 741 }
 742
 743 MCDisassembler::DecodeStatus XCoreDisassembler::getInstruction(
 744     MCInst &instr, uint64_t &Size, const MemoryObject &Region, uint64_t Address,
 745     raw_ostream &vStream, raw_ostream &cStream) const {
 746   uint16_t insn16;
 747
 748   if (!readInstruction16(Region, Address, Size, insn16)) {
 749     return Fail;
 750   }
 751
 752   // Calling the auto-generated decoder function.
 753   DecodeStatus Result = decodeInstruction(DecoderTable16, instr, insn16,
 754                                           Address, this, STI);
 755   if (Result != Fail) {
 756     Size = 2;
 757     return Result;
 758   }
 759
 760   uint32_t insn32;
 761
 762   if (!readInstruction32(Region, Address, Size, insn32)) {
 763     return Fail;
 764   }
 765
 766   // Calling the auto-generated decoder function.
 767   Result = decodeInstruction(DecoderTable32, instr, insn32, Address, this, STI);
 768   if (Result != Fail) {
 769     Size = 4;
 770     return Result;
 771   }
 772
 773   return Fail;
 774 }
 775
 776 namespace llvm {
 777   extern Target TheXCoreTarget;
 778 }
 779
 780 static MCDisassembler *createXCoreDisassembler(const Target &T,
 781                                                const MCSubtargetInfo &STI,
 782                                                MCContext &Ctx) {
 783   return new XCoreDisassembler(STI, Ctx);
 784 }
 785
 786 extern "C" void LLVMInitializeXCoreDisassembler() {
 787   // Register the disassembler.
 788   TargetRegistry::RegisterMCDisassembler(TheXCoreTarget,
 789                                          createXCoreDisassembler);
 790 }