1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file implements a TargetTransformInfo analysis pass specific to the
11 /// X86 target machine. It uses the target's detailed information to provide
12 /// more precise answers to certain TTI queries, while letting the target
13 /// independent and default TTI implementations handle the rest.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "x86tti"
19 #include "X86TargetMachine.h"
20 #include "llvm/Analysis/TargetTransformInfo.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Target/TargetLowering.h"
23 #include "llvm/Target/CostTable.h"
26 // Declare the pass initialization routine locally as target-specific passes
27 // don't havve a target-wide initialization entry point, and so we rely on the
28 // pass constructor initialization.
30 void initializeX86TTIPass(PassRegistry &);
35 class X86TTI : public ImmutablePass, public TargetTransformInfo {
36 const X86TargetMachine *TM;
37 const X86Subtarget *ST;
38 const X86TargetLowering *TLI;
40 /// Estimate the overhead of scalarizing an instruction. Insert and Extract
41 /// are set if the result needs to be inserted and/or extracted from vectors.
42 unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const;
45 X86TTI() : ImmutablePass(ID), TM(0), ST(0), TLI(0) {
46 llvm_unreachable("This pass cannot be directly constructed");
49 X86TTI(const X86TargetMachine *TM)
50 : ImmutablePass(ID), TM(TM), ST(TM->getSubtargetImpl()),
51 TLI(TM->getTargetLowering()) {
52 initializeX86TTIPass(*PassRegistry::getPassRegistry());
55 virtual void initializePass() {
59 virtual void finalizePass() {
63 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
64 TargetTransformInfo::getAnalysisUsage(AU);
67 /// Pass identification.
70 /// Provide necessary pointer adjustments for the two base classes.
71 virtual void *getAdjustedAnalysisPointer(const void *ID) {
72 if (ID == &TargetTransformInfo::ID)
73 return (TargetTransformInfo*)this;
77 /// \name Scalar TTI Implementations
79 virtual PopcntSupportKind getPopcntSupport(unsigned TyWidth) const;
83 /// \name Vector TTI Implementations
86 virtual unsigned getNumberOfRegisters(bool Vector) const;
87 virtual unsigned getRegisterBitWidth(bool Vector) const;
88 virtual unsigned getMaximumUnrollFactor() const;
89 virtual unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty) const;
90 virtual unsigned getShuffleCost(ShuffleKind Kind, Type *Tp,
91 int Index, Type *SubTp) const;
92 virtual unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
94 virtual unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
96 virtual unsigned getVectorInstrCost(unsigned Opcode, Type *Val,
97 unsigned Index) const;
98 virtual unsigned getMemoryOpCost(unsigned Opcode, Type *Src,
100 unsigned AddressSpace) const;
105 } // end anonymous namespace
107 INITIALIZE_AG_PASS(X86TTI, TargetTransformInfo, "x86tti",
108 "X86 Target Transform Info", true, true, false)
112 llvm::createX86TargetTransformInfoPass(const X86TargetMachine *TM) {
113 return new X86TTI(TM);
117 //===----------------------------------------------------------------------===//
121 //===----------------------------------------------------------------------===//
123 X86TTI::PopcntSupportKind X86TTI::getPopcntSupport(unsigned TyWidth) const {
124 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
125 // TODO: Currently the __builtin_popcount() implementation using SSE3
126 // instructions is inefficient. Once the problem is fixed, we should
127 // call ST->hasSSE3() instead of ST->hasSSE4().
128 return ST->hasSSE41() ? PSK_FastHardware : PSK_Software;
131 unsigned X86TTI::getNumberOfRegisters(bool Vector) const {
132 if (Vector && !ST->hasSSE1())
140 unsigned X86TTI::getRegisterBitWidth(bool Vector) const {
142 if (ST->hasAVX()) return 256;
143 if (ST->hasSSE1()) return 128;
153 unsigned X86TTI::getMaximumUnrollFactor() const {
157 // Sandybridge and Haswell have multiple execution ports and pipelined
165 unsigned X86TTI::getArithmeticInstrCost(unsigned Opcode, Type *Ty) const {
166 // Legalize the type.
167 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Ty);
169 int ISD = TLI->InstructionOpcodeToISD(Opcode);
170 assert(ISD && "Invalid opcode");
172 static const CostTblEntry<MVT> AVX2CostTable[] = {
173 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to
174 // customize them to detect the cases where shift amount is a scalar one.
175 { ISD::SHL, MVT::v4i32, 1 },
176 { ISD::SRL, MVT::v4i32, 1 },
177 { ISD::SRA, MVT::v4i32, 1 },
178 { ISD::SHL, MVT::v8i32, 1 },
179 { ISD::SRL, MVT::v8i32, 1 },
180 { ISD::SRA, MVT::v8i32, 1 },
181 { ISD::SHL, MVT::v2i64, 1 },
182 { ISD::SRL, MVT::v2i64, 1 },
183 { ISD::SHL, MVT::v4i64, 1 },
184 { ISD::SRL, MVT::v4i64, 1 },
186 { ISD::SHL, MVT::v32i8, 42 }, // cmpeqb sequence.
187 { ISD::SHL, MVT::v16i16, 16*10 }, // Scalarized.
189 { ISD::SRL, MVT::v32i8, 32*10 }, // Scalarized.
190 { ISD::SRL, MVT::v16i16, 8*10 }, // Scalarized.
192 { ISD::SRA, MVT::v32i8, 32*10 }, // Scalarized.
193 { ISD::SRA, MVT::v16i16, 16*10 }, // Scalarized.
194 { ISD::SRA, MVT::v4i64, 4*10 }, // Scalarized.
197 // Look for AVX2 lowering tricks.
199 int Idx = CostTableLookup<MVT>(AVX2CostTable, array_lengthof(AVX2CostTable),
202 return LT.first * AVX2CostTable[Idx].Cost;
205 static const CostTblEntry<MVT> SSE2CostTable[] = {
206 // We don't correctly identify costs of casts because they are marked as
208 // For some cases, where the shift amount is a scalar we would be able
209 // to generate better code. Unfortunately, when this is the case the value
210 // (the splat) will get hoisted out of the loop, thereby making it invisible
211 // to ISel. The cost model must return worst case assumptions because it is
212 // used for vectorization and we don't want to make vectorized code worse
214 { ISD::SHL, MVT::v16i8, 30 }, // cmpeqb sequence.
215 { ISD::SHL, MVT::v8i16, 8*10 }, // Scalarized.
216 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul.
217 { ISD::SHL, MVT::v2i64, 2*10 }, // Scalarized.
219 { ISD::SRL, MVT::v16i8, 16*10 }, // Scalarized.
220 { ISD::SRL, MVT::v8i16, 8*10 }, // Scalarized.
221 { ISD::SRL, MVT::v4i32, 4*10 }, // Scalarized.
222 { ISD::SRL, MVT::v2i64, 2*10 }, // Scalarized.
224 { ISD::SRA, MVT::v16i8, 16*10 }, // Scalarized.
225 { ISD::SRA, MVT::v8i16, 8*10 }, // Scalarized.
226 { ISD::SRA, MVT::v4i32, 4*10 }, // Scalarized.
227 { ISD::SRA, MVT::v2i64, 2*10 }, // Scalarized.
231 int Idx = CostTableLookup<MVT>(SSE2CostTable, array_lengthof(SSE2CostTable),
234 return LT.first * SSE2CostTable[Idx].Cost;
237 static const CostTblEntry<MVT> AVX1CostTable[] = {
238 // We don't have to scalarize unsupported ops. We can issue two half-sized
239 // operations and we only need to extract the upper YMM half.
240 // Two ops + 1 extract + 1 insert = 4.
241 { ISD::MUL, MVT::v8i32, 4 },
242 { ISD::SUB, MVT::v8i32, 4 },
243 { ISD::ADD, MVT::v8i32, 4 },
244 { ISD::SUB, MVT::v4i64, 4 },
245 { ISD::ADD, MVT::v4i64, 4 },
246 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then
247 // are lowered as a series of long multiplies(3), shifts(4) and adds(2)
248 // Because we believe v4i64 to be a legal type, we must also include the
249 // split factor of two in the cost table. Therefore, the cost here is 18
251 { ISD::MUL, MVT::v4i64, 18 },
254 // Look for AVX1 lowering tricks.
255 if (ST->hasAVX() && !ST->hasAVX2()) {
256 int Idx = CostTableLookup<MVT>(AVX1CostTable, array_lengthof(AVX1CostTable),
259 return LT.first * AVX1CostTable[Idx].Cost;
262 // Custom lowering of vectors.
263 static const CostTblEntry<MVT> CustomLowered[] = {
264 // A v2i64/v4i64 and multiply is custom lowered as a series of long
265 // multiplies(3), shifts(4) and adds(2).
266 { ISD::MUL, MVT::v2i64, 9 },
267 { ISD::MUL, MVT::v4i64, 9 },
269 int Idx = CostTableLookup<MVT>(CustomLowered, array_lengthof(CustomLowered),
272 return LT.first * CustomLowered[Idx].Cost;
274 // Special lowering of v4i32 mul on sse2, sse3: Lower v4i32 mul as 2x shuffle,
275 // 2x pmuludq, 2x shuffle.
276 if (ISD == ISD::MUL && LT.second == MVT::v4i32 && ST->hasSSE2() &&
280 // Fallback to the default implementation.
281 return TargetTransformInfo::getArithmeticInstrCost(Opcode, Ty);
284 unsigned X86TTI::getShuffleCost(ShuffleKind Kind, Type *Tp, int Index,
286 // We only estimate the cost of reverse shuffles.
287 if (Kind != SK_Reverse)
288 return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
290 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Tp);
292 if (LT.second.getSizeInBits() > 128)
293 Cost = 3; // Extract + insert + copy.
295 // Multiple by the number of parts.
296 return Cost * LT.first;
299 unsigned X86TTI::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) const {
300 int ISD = TLI->InstructionOpcodeToISD(Opcode);
301 assert(ISD && "Invalid opcode");
303 EVT SrcTy = TLI->getValueType(Src);
304 EVT DstTy = TLI->getValueType(Dst);
306 if (!SrcTy.isSimple() || !DstTy.isSimple())
307 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
309 static const TypeConversionCostTblEntry<MVT> AVXConversionTbl[] = {
310 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
311 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
312 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
313 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
314 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 },
315 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 1 },
317 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 },
318 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 },
319 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 },
320 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 },
321 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
322 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
323 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 },
324 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
325 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 },
326 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 },
327 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 },
328 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 },
330 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 },
331 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 },
332 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 },
333 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 },
334 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 },
335 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 },
336 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
337 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 },
338 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 },
339 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 },
340 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 },
341 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 },
343 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 1 },
344 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 },
345 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 6 },
346 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 9 },
347 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 8 },
348 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 6 },
349 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 6 },
350 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 3 },
354 int Idx = ConvertCostTableLookup<MVT>(AVXConversionTbl,
355 array_lengthof(AVXConversionTbl),
356 ISD, DstTy.getSimpleVT(), SrcTy.getSimpleVT());
358 return AVXConversionTbl[Idx].Cost;
361 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
364 unsigned X86TTI::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
365 Type *CondTy) const {
366 // Legalize the type.
367 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(ValTy);
371 int ISD = TLI->InstructionOpcodeToISD(Opcode);
372 assert(ISD && "Invalid opcode");
374 static const CostTblEntry<MVT> SSE42CostTbl[] = {
375 { ISD::SETCC, MVT::v2f64, 1 },
376 { ISD::SETCC, MVT::v4f32, 1 },
377 { ISD::SETCC, MVT::v2i64, 1 },
378 { ISD::SETCC, MVT::v4i32, 1 },
379 { ISD::SETCC, MVT::v8i16, 1 },
380 { ISD::SETCC, MVT::v16i8, 1 },
383 static const CostTblEntry<MVT> AVX1CostTbl[] = {
384 { ISD::SETCC, MVT::v4f64, 1 },
385 { ISD::SETCC, MVT::v8f32, 1 },
386 // AVX1 does not support 8-wide integer compare.
387 { ISD::SETCC, MVT::v4i64, 4 },
388 { ISD::SETCC, MVT::v8i32, 4 },
389 { ISD::SETCC, MVT::v16i16, 4 },
390 { ISD::SETCC, MVT::v32i8, 4 },
393 static const CostTblEntry<MVT> AVX2CostTbl[] = {
394 { ISD::SETCC, MVT::v4i64, 1 },
395 { ISD::SETCC, MVT::v8i32, 1 },
396 { ISD::SETCC, MVT::v16i16, 1 },
397 { ISD::SETCC, MVT::v32i8, 1 },
401 int Idx = CostTableLookup<MVT>(AVX2CostTbl, array_lengthof(AVX2CostTbl), ISD, MTy);
403 return LT.first * AVX2CostTbl[Idx].Cost;
407 int Idx = CostTableLookup<MVT>(AVX1CostTbl, array_lengthof(AVX1CostTbl), ISD, MTy);
409 return LT.first * AVX1CostTbl[Idx].Cost;
412 if (ST->hasSSE42()) {
413 int Idx = CostTableLookup<MVT>(SSE42CostTbl, array_lengthof(SSE42CostTbl), ISD, MTy);
415 return LT.first * SSE42CostTbl[Idx].Cost;
418 return TargetTransformInfo::getCmpSelInstrCost(Opcode, ValTy, CondTy);
421 unsigned X86TTI::getVectorInstrCost(unsigned Opcode, Type *Val,
422 unsigned Index) const {
423 assert(Val->isVectorTy() && "This must be a vector type");
426 // Legalize the type.
427 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Val);
429 // This type is legalized to a scalar type.
430 if (!LT.second.isVector())
433 // The type may be split. Normalize the index to the new type.
434 unsigned Width = LT.second.getVectorNumElements();
435 Index = Index % Width;
437 // Floating point scalars are already located in index #0.
438 if (Val->getScalarType()->isFloatingPointTy() && Index == 0)
442 return TargetTransformInfo::getVectorInstrCost(Opcode, Val, Index);
445 unsigned X86TTI::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
446 unsigned AddressSpace) const {
447 // Legalize the type.
448 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Src);
449 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) &&
452 // Each load/store unit costs 1.
453 unsigned Cost = LT.first * 1;
455 // On Sandybridge 256bit load/stores are double pumped
456 // (but not on Haswell).
457 if (LT.second.getSizeInBits() > 128 && !ST->hasAVX2())