Rename createAsmInfo to createMCAsmInfo and move registration code to MCTargetDesc...
[oota-llvm.git] / lib / Target / X86 / X86TargetMachine.cpp
1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the X86 specific subclass of TargetMachine.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "X86TargetMachine.h"
15 #include "X86.h"
16 #include "llvm/PassManager.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/MC/MCCodeEmitter.h"
20 #include "llvm/MC/MCStreamer.h"
21 #include "llvm/Support/FormattedStream.h"
22 #include "llvm/Target/TargetOptions.h"
23 #include "llvm/Target/TargetRegistry.h"
24 using namespace llvm;
25
26 static MCStreamer *createMCStreamer(const Target &T, const std::string &TT,
27                                     MCContext &Ctx, TargetAsmBackend &TAB,
28                                     raw_ostream &_OS,
29                                     MCCodeEmitter *_Emitter,
30                                     bool RelaxAll,
31                                     bool NoExecStack) {
32   Triple TheTriple(TT);
33
34   if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
35     return createMachOStreamer(Ctx, TAB, _OS, _Emitter, RelaxAll);
36
37   if (TheTriple.isOSWindows())
38     return createWinCOFFStreamer(Ctx, TAB, *_Emitter, _OS, RelaxAll);
39
40   return createELFStreamer(Ctx, TAB, _OS, _Emitter, RelaxAll, NoExecStack);
41 }
42
43 extern "C" void LLVMInitializeX86Target() {
44   // Register the target.
45   RegisterTargetMachine<X86_32TargetMachine> X(TheX86_32Target);
46   RegisterTargetMachine<X86_64TargetMachine> Y(TheX86_64Target);
47
48   // Register the code emitter.
49   TargetRegistry::RegisterCodeEmitter(TheX86_32Target,
50                                       createX86MCCodeEmitter);
51   TargetRegistry::RegisterCodeEmitter(TheX86_64Target,
52                                       createX86MCCodeEmitter);
53
54   // Register the asm backend.
55   TargetRegistry::RegisterAsmBackend(TheX86_32Target,
56                                      createX86_32AsmBackend);
57   TargetRegistry::RegisterAsmBackend(TheX86_64Target,
58                                      createX86_64AsmBackend);
59
60   // Register the object streamer.
61   TargetRegistry::RegisterObjectStreamer(TheX86_32Target,
62                                          createMCStreamer);
63   TargetRegistry::RegisterObjectStreamer(TheX86_64Target,
64                                          createMCStreamer);
65 }
66
67
68 X86_32TargetMachine::X86_32TargetMachine(const Target &T, const std::string &TT,
69                                          const std::string &CPU,
70                                          const std::string &FS)
71   : X86TargetMachine(T, TT, CPU, FS, false),
72     DataLayout(getSubtargetImpl()->isTargetDarwin() ?
73                "e-p:32:32-f64:32:64-i64:32:64-f80:128:128-f128:128:128-n8:16:32" :
74                (getSubtargetImpl()->isTargetCygMing() ||
75                 getSubtargetImpl()->isTargetWindows()) ?
76                "e-p:32:32-f64:64:64-i64:64:64-f80:32:32-f128:128:128-n8:16:32" :
77                "e-p:32:32-f64:32:64-i64:32:64-f80:32:32-f128:128:128-n8:16:32"),
78     InstrInfo(*this),
79     TSInfo(*this),
80     TLInfo(*this),
81     JITInfo(*this) {
82 }
83
84
85 X86_64TargetMachine::X86_64TargetMachine(const Target &T, const std::string &TT,
86                                          const std::string &CPU, 
87                                          const std::string &FS)
88   : X86TargetMachine(T, TT, CPU, FS, true),
89     DataLayout("e-p:64:64-s:64-f64:64:64-i64:64:64-f80:128:128-f128:128:128-n8:16:32:64"),
90     InstrInfo(*this),
91     TSInfo(*this),
92     TLInfo(*this),
93     JITInfo(*this) {
94 }
95
96 /// X86TargetMachine ctor - Create an X86 target.
97 ///
98 X86TargetMachine::X86TargetMachine(const Target &T, const std::string &TT,
99                                    const std::string &CPU,
100                                    const std::string &FS, bool is64Bit)
101   : LLVMTargetMachine(T, TT, CPU, FS),
102     Subtarget(TT, CPU, FS, StackAlignmentOverride, is64Bit),
103     FrameLowering(*this, Subtarget),
104     ELFWriterInfo(is64Bit, true) {
105   DefRelocModel = getRelocationModel();
106
107   // If no relocation model was picked, default as appropriate for the target.
108   if (getRelocationModel() == Reloc::Default) {
109     // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
110     // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
111     // use static relocation model by default.
112     if (Subtarget.isTargetDarwin()) {
113       if (Subtarget.is64Bit())
114         setRelocationModel(Reloc::PIC_);
115       else
116         setRelocationModel(Reloc::DynamicNoPIC);
117     } else if (Subtarget.isTargetWin64())
118       setRelocationModel(Reloc::PIC_);
119     else
120       setRelocationModel(Reloc::Static);
121   }
122
123   assert(getRelocationModel() != Reloc::Default &&
124          "Relocation mode not picked");
125
126   // ELF and X86-64 don't have a distinct DynamicNoPIC model.  DynamicNoPIC
127   // is defined as a model for code which may be used in static or dynamic
128   // executables but not necessarily a shared library. On X86-32 we just
129   // compile in -static mode, in x86-64 we use PIC.
130   if (getRelocationModel() == Reloc::DynamicNoPIC) {
131     if (is64Bit)
132       setRelocationModel(Reloc::PIC_);
133     else if (!Subtarget.isTargetDarwin())
134       setRelocationModel(Reloc::Static);
135   }
136
137   // If we are on Darwin, disallow static relocation model in X86-64 mode, since
138   // the Mach-O file format doesn't support it.
139   if (getRelocationModel() == Reloc::Static &&
140       Subtarget.isTargetDarwin() &&
141       is64Bit)
142     setRelocationModel(Reloc::PIC_);
143
144   // Determine the PICStyle based on the target selected.
145   if (getRelocationModel() == Reloc::Static) {
146     // Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None.
147     Subtarget.setPICStyle(PICStyles::None);
148   } else if (Subtarget.is64Bit()) {
149     // PIC in 64 bit mode is always rip-rel.
150     Subtarget.setPICStyle(PICStyles::RIPRel);
151   } else if (Subtarget.isTargetCygMing()) {
152     Subtarget.setPICStyle(PICStyles::None);
153   } else if (Subtarget.isTargetDarwin()) {
154     if (getRelocationModel() == Reloc::PIC_)
155       Subtarget.setPICStyle(PICStyles::StubPIC);
156     else {
157       assert(getRelocationModel() == Reloc::DynamicNoPIC);
158       Subtarget.setPICStyle(PICStyles::StubDynamicNoPIC);
159     }
160   } else if (Subtarget.isTargetELF()) {
161     Subtarget.setPICStyle(PICStyles::GOT);
162   }
163
164   // Finally, if we have "none" as our PIC style, force to static mode.
165   if (Subtarget.getPICStyle() == PICStyles::None)
166     setRelocationModel(Reloc::Static);
167
168   // default to hard float ABI
169   if (FloatABIType == FloatABI::Default)
170     FloatABIType = FloatABI::Hard;    
171 }
172
173 //===----------------------------------------------------------------------===//
174 // Pass Pipeline Configuration
175 //===----------------------------------------------------------------------===//
176
177 bool X86TargetMachine::addInstSelector(PassManagerBase &PM,
178                                        CodeGenOpt::Level OptLevel) {
179   // Install an instruction selector.
180   PM.add(createX86ISelDag(*this, OptLevel));
181
182   // For 32-bit, prepend instructions to set the "global base reg" for PIC.
183   if (!Subtarget.is64Bit())
184     PM.add(createGlobalBaseRegPass());
185
186   return false;
187 }
188
189 bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM,
190                                       CodeGenOpt::Level OptLevel) {
191   PM.add(createX86MaxStackAlignmentHeuristicPass());
192   return false;  // -print-machineinstr shouldn't print after this.
193 }
194
195 bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM,
196                                        CodeGenOpt::Level OptLevel) {
197   PM.add(createX86FloatingPointStackifierPass());
198   return true;  // -print-machineinstr should print after this.
199 }
200
201 bool X86TargetMachine::addPreEmitPass(PassManagerBase &PM,
202                                       CodeGenOpt::Level OptLevel) {
203   if (OptLevel != CodeGenOpt::None && Subtarget.hasSSE2()) {
204     PM.add(createSSEDomainFixPass());
205     return true;
206   }
207   return false;
208 }
209
210 bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
211                                       CodeGenOpt::Level OptLevel,
212                                       JITCodeEmitter &JCE) {
213   // FIXME: Move this to TargetJITInfo!
214   // On Darwin, do not override 64-bit setting made in X86TargetMachine().
215   if (DefRelocModel == Reloc::Default &&
216       (!Subtarget.isTargetDarwin() || !Subtarget.is64Bit())) {
217     setRelocationModel(Reloc::Static);
218     Subtarget.setPICStyle(PICStyles::None);
219   }
220
221
222   PM.add(createX86JITCodeEmitterPass(*this, JCE));
223
224   return false;
225 }
226
227 void X86TargetMachine::setCodeModelForStatic() {
228
229     if (getCodeModel() != CodeModel::Default) return;
230
231     // For static codegen, if we're not already set, use Small codegen.
232     setCodeModel(CodeModel::Small);
233 }
234
235
236 void X86TargetMachine::setCodeModelForJIT() {
237
238   if (getCodeModel() != CodeModel::Default) return;
239
240   // 64-bit JIT places everything in the same buffer except external functions.
241   if (Subtarget.is64Bit())
242     setCodeModel(CodeModel::Large);
243   else
244     setCodeModel(CodeModel::Small);
245 }