1 //===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the X86 specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_X86_X86SUBTARGET_H
15 #define LLVM_LIB_TARGET_X86_X86SUBTARGET_H
17 #include "X86FrameLowering.h"
18 #include "X86ISelLowering.h"
19 #include "X86InstrInfo.h"
20 #include "X86SelectionDAGInfo.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/Target/TargetSubtargetInfo.h"
26 #define GET_SUBTARGETINFO_HEADER
27 #include "X86GenSubtargetInfo.inc"
34 /// PICStyles - The X86 backend supports a number of different styles of PIC.
38 StubPIC, // Used on i386-darwin in -fPIC mode.
39 StubDynamicNoPIC, // Used on i386-darwin in -mdynamic-no-pic mode.
40 GOT, // Used on many 32-bit unices in -fPIC mode.
41 RIPRel, // Used on X86-64 when not in -static mode.
42 None // Set when in -static mode (not PIC or DynamicNoPIC mode).
46 class X86Subtarget final : public X86GenSubtargetInfo {
50 NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
54 NoThreeDNow, ThreeDNow, ThreeDNowA
57 enum X86ProcFamilyEnum {
58 Others, IntelAtom, IntelSLM
61 /// X86ProcFamily - X86 processor family: Intel Atom, and others
62 X86ProcFamilyEnum X86ProcFamily;
64 /// PICStyle - Which PIC style to use
66 PICStyles::Style PICStyle;
68 /// X86SSELevel - MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or
70 X86SSEEnum X86SSELevel;
72 /// X863DNowLevel - 3DNow or 3DNow Athlon, or none supported.
74 X863DNowEnum X863DNowLevel;
76 /// HasCMov - True if this processor has conditional move instructions
77 /// (generally pentium pro+).
80 /// HasX86_64 - True if the processor supports X86-64 instructions.
84 /// HasPOPCNT - True if the processor supports POPCNT.
87 /// HasSSE4A - True if the processor supports SSE4A instructions.
90 /// HasAES - Target has AES instructions
93 /// HasPCLMUL - Target has carry-less multiplication
96 /// HasFMA - Target has 3-operand fused multiply-add
99 /// HasFMA4 - Target has 4-operand fused multiply-add
102 /// HasXOP - Target has XOP instructions
105 /// HasTBM - Target has TBM instructions.
108 /// HasMOVBE - True if the processor has the MOVBE instruction.
111 /// HasRDRAND - True if the processor has the RDRAND instruction.
114 /// HasF16C - Processor has 16-bit floating point conversion instructions.
117 /// HasFSGSBase - Processor has FS/GS base insturctions.
120 /// HasLZCNT - Processor has LZCNT instruction.
123 /// HasBMI - Processor has BMI1 instructions.
126 /// HasBMI2 - Processor has BMI2 instructions.
129 /// HasRTM - Processor has RTM instructions.
132 /// HasHLE - Processor has HLE.
135 /// HasADX - Processor has ADX instructions.
138 /// HasSHA - Processor has SHA instructions.
141 /// HasSGX - Processor has SGX instructions.
144 /// HasPRFCHW - Processor has PRFCHW instructions.
147 /// HasRDSEED - Processor has RDSEED instructions.
150 /// HasSMAP - Processor has SMAP instructions.
153 /// IsBTMemSlow - True if BT (bit test) of memory instructions are slow.
156 /// IsSHLDSlow - True if SHLD instructions are slow.
159 /// IsUAMemFast - True if unaligned memory access is fast.
162 /// HasVectorUAMem - True if SIMD operations can have unaligned memory
163 /// operands. This may require setting a feature bit in the processor.
166 /// HasCmpxchg16b - True if this processor has the CMPXCHG16B instruction;
167 /// this is true for most x86-64 chips, but not the first AMD chips.
170 /// UseLeaForSP - True if the LEA instruction should be used for adjusting
171 /// the stack pointer. This is an optimization for Intel Atom processors.
174 /// HasSlowDivide32 - True if 8-bit divisions are significantly faster than
175 /// 32-bit divisions and should be used when possible.
176 bool HasSlowDivide32;
178 /// HasSlowDivide64 - True if 16-bit divides are significantly faster than
179 /// 64-bit divisions and should be used when possible.
180 bool HasSlowDivide64;
182 /// PadShortFunctions - True if the short functions should be padded to prevent
183 /// a stall when returning too early.
184 bool PadShortFunctions;
186 /// CallRegIndirect - True if the Calls with memory reference should be converted
187 /// to a register-based indirect call.
188 bool CallRegIndirect;
189 /// LEAUsesAG - True if the LEA instruction inputs have to be ready at
190 /// address generation (AG) time.
193 /// SlowLEA - True if the LEA instruction with certain arguments is slow
196 /// SlowIncDec - True if INC and DEC instructions are slow when writing to flags
199 /// Use the RSQRT* instructions to optimize square root calculations.
200 /// For this to be profitable, the cost of FSQRT and FDIV must be
201 /// substantially higher than normal FP ops like FADD and FMUL.
204 /// Use the RCP* instructions to optimize FP division calculations.
205 /// For this to be profitable, the cost of FDIV must be
206 /// substantially higher than normal FP ops like FADD and FMUL.
207 bool UseReciprocalEst;
209 /// Processor has AVX-512 PreFetch Instructions
212 /// Processor has AVX-512 Exponential and Reciprocal Instructions
215 /// Processor has AVX-512 Conflict Detection Instructions
218 /// Processor has AVX-512 Doubleword and Quadword instructions
221 /// Processor has AVX-512 Byte and Word instructions
224 /// Processor has AVX-512 Vector Length eXtenstions
227 /// stackAlignment - The minimum alignment known to hold of the stack frame on
228 /// entry to the function and which must be maintained by every function.
229 unsigned stackAlignment;
231 /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
233 unsigned MaxInlineSizeThreshold;
235 /// TargetTriple - What processor and OS we're targeting.
238 /// Instruction itineraries for scheduling
239 InstrItineraryData InstrItins;
242 // Calculates type size & alignment
245 /// StackAlignOverride - Override the stack alignment.
246 unsigned StackAlignOverride;
248 /// In64BitMode - True if compiling for 64-bit, false for 16-bit or 32-bit.
251 /// In32BitMode - True if compiling for 32-bit, false for 16-bit or 64-bit.
254 /// In16BitMode - True if compiling for 16-bit, false for 32-bit or 64-bit.
257 X86SelectionDAGInfo TSInfo;
258 // Ordering here is important. X86InstrInfo initializes X86RegisterInfo which
259 // X86TargetLowering needs.
260 X86InstrInfo InstrInfo;
261 X86TargetLowering TLInfo;
262 X86FrameLowering FrameLowering;
265 /// This constructor initializes the data members to match that
266 /// of the specified triple.
268 X86Subtarget(const std::string &TT, const std::string &CPU,
269 const std::string &FS, const X86TargetMachine &TM,
270 unsigned StackAlignOverride);
272 const X86TargetLowering *getTargetLowering() const override {
275 const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; }
276 const DataLayout *getDataLayout() const override { return &DL; }
277 const X86FrameLowering *getFrameLowering() const override {
278 return &FrameLowering;
280 const X86SelectionDAGInfo *getSelectionDAGInfo() const override {
283 const X86RegisterInfo *getRegisterInfo() const override {
284 return &getInstrInfo()->getRegisterInfo();
287 /// getStackAlignment - Returns the minimum alignment known to hold of the
288 /// stack frame on entry to the function and which must be maintained by every
289 /// function for this subtarget.
290 unsigned getStackAlignment() const { return stackAlignment; }
292 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
293 /// that still makes it profitable to inline the call.
294 unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
296 /// ParseSubtargetFeatures - Parses features string setting specified
297 /// subtarget options. Definition of function is auto generated by tblgen.
298 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
301 /// \brief Initialize the full set of dependencies so we can use an initializer
302 /// list for X86Subtarget.
303 X86Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
304 void initializeEnvironment();
305 void initSubtargetFeatures(StringRef CPU, StringRef FS);
307 /// Is this x86_64? (disregarding specific ABI / programming model)
308 bool is64Bit() const {
312 bool is32Bit() const {
316 bool is16Bit() const {
320 /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
321 bool isTarget64BitILP32() const {
322 return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32 ||
323 TargetTriple.getOS() == Triple::NaCl);
326 /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
327 bool isTarget64BitLP64() const {
328 return In64BitMode && (TargetTriple.getEnvironment() != Triple::GNUX32 &&
329 TargetTriple.getOS() != Triple::NaCl);
332 PICStyles::Style getPICStyle() const { return PICStyle; }
333 void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
335 bool hasCMov() const { return HasCMov; }
336 bool hasMMX() const { return X86SSELevel >= MMX; }
337 bool hasSSE1() const { return X86SSELevel >= SSE1; }
338 bool hasSSE2() const { return X86SSELevel >= SSE2; }
339 bool hasSSE3() const { return X86SSELevel >= SSE3; }
340 bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
341 bool hasSSE41() const { return X86SSELevel >= SSE41; }
342 bool hasSSE42() const { return X86SSELevel >= SSE42; }
343 bool hasAVX() const { return X86SSELevel >= AVX; }
344 bool hasAVX2() const { return X86SSELevel >= AVX2; }
345 bool hasAVX512() const { return X86SSELevel >= AVX512F; }
346 bool hasFp256() const { return hasAVX(); }
347 bool hasInt256() const { return hasAVX2(); }
348 bool hasSSE4A() const { return HasSSE4A; }
349 bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
350 bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
351 bool hasPOPCNT() const { return HasPOPCNT; }
352 bool hasAES() const { return HasAES; }
353 bool hasPCLMUL() const { return HasPCLMUL; }
354 bool hasFMA() const { return HasFMA; }
355 // FIXME: Favor FMA when both are enabled. Is this the right thing to do?
356 bool hasFMA4() const { return HasFMA4 && !HasFMA; }
357 bool hasXOP() const { return HasXOP; }
358 bool hasTBM() const { return HasTBM; }
359 bool hasMOVBE() const { return HasMOVBE; }
360 bool hasRDRAND() const { return HasRDRAND; }
361 bool hasF16C() const { return HasF16C; }
362 bool hasFSGSBase() const { return HasFSGSBase; }
363 bool hasLZCNT() const { return HasLZCNT; }
364 bool hasBMI() const { return HasBMI; }
365 bool hasBMI2() const { return HasBMI2; }
366 bool hasRTM() const { return HasRTM; }
367 bool hasHLE() const { return HasHLE; }
368 bool hasADX() const { return HasADX; }
369 bool hasSHA() const { return HasSHA; }
370 bool hasSGX() const { return HasSGX; }
371 bool hasPRFCHW() const { return HasPRFCHW; }
372 bool hasRDSEED() const { return HasRDSEED; }
373 bool hasSMAP() const { return HasSMAP; }
374 bool isBTMemSlow() const { return IsBTMemSlow; }
375 bool isSHLDSlow() const { return IsSHLDSlow; }
376 bool isUnalignedMemAccessFast() const { return IsUAMemFast; }
377 bool hasVectorUAMem() const { return HasVectorUAMem; }
378 bool hasCmpxchg16b() const { return HasCmpxchg16b; }
379 bool useLeaForSP() const { return UseLeaForSP; }
380 bool hasSlowDivide32() const { return HasSlowDivide32; }
381 bool hasSlowDivide64() const { return HasSlowDivide64; }
382 bool padShortFunctions() const { return PadShortFunctions; }
383 bool callRegIndirect() const { return CallRegIndirect; }
384 bool LEAusesAG() const { return LEAUsesAG; }
385 bool slowLEA() const { return SlowLEA; }
386 bool slowIncDec() const { return SlowIncDec; }
387 bool useSqrtEst() const { return UseSqrtEst; }
388 bool useReciprocalEst() const { return UseReciprocalEst; }
389 bool hasCDI() const { return HasCDI; }
390 bool hasPFI() const { return HasPFI; }
391 bool hasERI() const { return HasERI; }
392 bool hasDQI() const { return HasDQI; }
393 bool hasBWI() const { return HasBWI; }
394 bool hasVLX() const { return HasVLX; }
396 bool isAtom() const { return X86ProcFamily == IntelAtom; }
397 bool isSLM() const { return X86ProcFamily == IntelSLM; }
399 const Triple &getTargetTriple() const { return TargetTriple; }
401 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
402 bool isTargetFreeBSD() const {
403 return TargetTriple.getOS() == Triple::FreeBSD;
405 bool isTargetSolaris() const {
406 return TargetTriple.getOS() == Triple::Solaris;
409 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
410 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
411 bool isTargetMacho() const { return TargetTriple.isOSBinFormatMachO(); }
413 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
414 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
415 bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
416 bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
418 bool isTargetWindowsMSVC() const {
419 return TargetTriple.isWindowsMSVCEnvironment();
422 bool isTargetKnownWindowsMSVC() const {
423 return TargetTriple.isKnownWindowsMSVCEnvironment();
426 bool isTargetWindowsCygwin() const {
427 return TargetTriple.isWindowsCygwinEnvironment();
430 bool isTargetWindowsGNU() const {
431 return TargetTriple.isWindowsGNUEnvironment();
434 bool isTargetWindowsItanium() const {
435 return TargetTriple.isWindowsItaniumEnvironment();
438 bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
440 bool isOSWindows() const { return TargetTriple.isOSWindows(); }
442 bool isTargetWin64() const {
443 return In64BitMode && TargetTriple.isOSWindows();
446 bool isTargetWin32() const {
447 return !In64BitMode && (isTargetCygMing() || isTargetKnownWindowsMSVC());
450 bool isPICStyleSet() const { return PICStyle != PICStyles::None; }
451 bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
452 bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
454 bool isPICStyleStubPIC() const {
455 return PICStyle == PICStyles::StubPIC;
458 bool isPICStyleStubNoDynamic() const {
459 return PICStyle == PICStyles::StubDynamicNoPIC;
461 bool isPICStyleStubAny() const {
462 return PICStyle == PICStyles::StubDynamicNoPIC ||
463 PICStyle == PICStyles::StubPIC;
466 bool isCallingConvWin64(CallingConv::ID CC) const {
467 return (isTargetWin64() && CC != CallingConv::X86_64_SysV) ||
468 CC == CallingConv::X86_64_Win64;
471 /// ClassifyGlobalReference - Classify a global variable reference for the
472 /// current subtarget according to how we should reference it in a non-pcrel
474 unsigned char ClassifyGlobalReference(const GlobalValue *GV,
475 const TargetMachine &TM)const;
477 /// ClassifyBlockAddressReference - Classify a blockaddress reference for the
478 /// current subtarget according to how we should reference it in a non-pcrel
480 unsigned char ClassifyBlockAddressReference() const;
482 /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
483 /// to immediate address.
484 bool IsLegalToCallImmediateAddr(const TargetMachine &TM) const;
486 /// This function returns the name of a function which has an interface
487 /// like the non-standard bzero function, if such a function exists on
488 /// the current subtarget and it is considered prefereable over
489 /// memset with zero passed as the second argument. Otherwise it
491 const char *getBZeroEntry() const;
493 /// This function returns true if the target has sincos() routine in its
494 /// compiler runtime or math libraries.
495 bool hasSinCos() const;
497 /// Enable the MachineScheduler pass for all X86 subtargets.
498 bool enableMachineScheduler() const override { return true; }
500 bool enableEarlyIfConversion() const override;
502 /// getInstrItins = Return the instruction itineraries based on the
503 /// subtarget selection.
504 const InstrItineraryData *getInstrItineraryData() const override {
508 AntiDepBreakMode getAntiDepBreakMode() const override {
509 return TargetSubtargetInfo::ANTIDEP_CRITICAL;
513 } // End llvm namespace