1 //===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 Register file, defining the registers themselves,
11 // aliases between the registers, and the register classes built out of the
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Register definitions...
19 let Namespace = "X86" in {
21 // In the register alias definitions below, we define which registers alias
22 // which others. We only specify which registers the small registers alias,
23 // because the register file generator is smart enough to figure out that
24 // AL aliases AX if we tell it that AX aliased AL (for example).
26 // Dwarf numbering is different for 32-bit and 64-bit, and there are
27 // variations by target as well. The numbers here are for 64-bit.
28 // They are altered by X86RegisterInfo::getDwarfRegNum at runtime. Note
29 // that we can't assign the same number here to different registers, as
30 // getDwarfRegNum has only the number here to work with.
34 def AL : Register<"AL">, DwarfRegNum<0>;
35 def DL : Register<"DL">, DwarfRegNum<1>;
36 def CL : Register<"CL">, DwarfRegNum<2>;
37 def BL : Register<"BL">, DwarfRegNum<3>;
40 def SIL : Register<"SIL">, DwarfRegNum<4>;
41 def DIL : Register<"DIL">, DwarfRegNum<5>;
42 def BPL : Register<"BPL">, DwarfRegNum<6>;
43 def SPL : Register<"SPL">, DwarfRegNum<7>;
44 def R8B : Register<"R8B">, DwarfRegNum<8>;
45 def R9B : Register<"R9B">, DwarfRegNum<9>;
46 def R10B : Register<"R10B">, DwarfRegNum<10>;
47 def R11B : Register<"R11B">, DwarfRegNum<11>;
48 def R12B : Register<"R12B">, DwarfRegNum<12>;
49 def R13B : Register<"R13B">, DwarfRegNum<13>;
50 def R14B : Register<"R14B">, DwarfRegNum<14>;
51 def R15B : Register<"R15B">, DwarfRegNum<15>;
53 // High registers X86-32 only
54 def AH : Register<"AH">, DwarfRegNum<0>;
55 def DH : Register<"DH">, DwarfRegNum<1>;
56 def CH : Register<"CH">, DwarfRegNum<2>;
57 def BH : Register<"BH">, DwarfRegNum<3>;
60 def AX : RegisterWithSubRegs<"AX", [AH,AL]>, DwarfRegNum<0>;
61 def DX : RegisterWithSubRegs<"DX", [DH,DL]>, DwarfRegNum<1>;
62 def CX : RegisterWithSubRegs<"CX", [CH,CL]>, DwarfRegNum<2>;
63 def BX : RegisterWithSubRegs<"BX", [BH,BL]>, DwarfRegNum<3>;
64 def SI : RegisterWithSubRegs<"SI", [SIL]>, DwarfRegNum<4>;
65 def DI : RegisterWithSubRegs<"DI", [DIL]>, DwarfRegNum<5>;
66 def BP : RegisterWithSubRegs<"BP", [BPL]>, DwarfRegNum<6>;
67 def SP : RegisterWithSubRegs<"SP", [SPL]>, DwarfRegNum<7>;
68 def IP : Register<"IP">, DwarfRegNum<16>;
71 def R8W : RegisterWithSubRegs<"R8W", [R8B]>, DwarfRegNum<8>;
72 def R9W : RegisterWithSubRegs<"R9W", [R9B]>, DwarfRegNum<9>;
73 def R10W : RegisterWithSubRegs<"R10W", [R10B]>, DwarfRegNum<10>;
74 def R11W : RegisterWithSubRegs<"R11W", [R11B]>, DwarfRegNum<11>;
75 def R12W : RegisterWithSubRegs<"R12W", [R12B]>, DwarfRegNum<12>;
76 def R13W : RegisterWithSubRegs<"R13W", [R13B]>, DwarfRegNum<13>;
77 def R14W : RegisterWithSubRegs<"R14W", [R14B]>, DwarfRegNum<14>;
78 def R15W : RegisterWithSubRegs<"R15W", [R15B]>, DwarfRegNum<15>;
81 def EAX : RegisterWithSubRegs<"EAX", [AX]>, DwarfRegNum<0>;
82 def EDX : RegisterWithSubRegs<"EDX", [DX]>, DwarfRegNum<1>;
83 def ECX : RegisterWithSubRegs<"ECX", [CX]>, DwarfRegNum<2>;
84 def EBX : RegisterWithSubRegs<"EBX", [BX]>, DwarfRegNum<3>;
85 def ESI : RegisterWithSubRegs<"ESI", [SI]>, DwarfRegNum<4>;
86 def EDI : RegisterWithSubRegs<"EDI", [DI]>, DwarfRegNum<5>;
87 def EBP : RegisterWithSubRegs<"EBP", [BP]>, DwarfRegNum<6>;
88 def ESP : RegisterWithSubRegs<"ESP", [SP]>, DwarfRegNum<7>;
89 def EIP : RegisterWithSubRegs<"EIP", [IP]>, DwarfRegNum<16>;
92 def R8D : RegisterWithSubRegs<"R8D", [R8W]>, DwarfRegNum<8>;
93 def R9D : RegisterWithSubRegs<"R9D", [R9W]>, DwarfRegNum<9>;
94 def R10D : RegisterWithSubRegs<"R10D", [R10W]>, DwarfRegNum<10>;
95 def R11D : RegisterWithSubRegs<"R11D", [R11W]>, DwarfRegNum<11>;
96 def R12D : RegisterWithSubRegs<"R12D", [R12W]>, DwarfRegNum<12>;
97 def R13D : RegisterWithSubRegs<"R13D", [R13W]>, DwarfRegNum<13>;
98 def R14D : RegisterWithSubRegs<"R14D", [R14W]>, DwarfRegNum<14>;
99 def R15D : RegisterWithSubRegs<"R15D", [R15W]>, DwarfRegNum<15>;
101 // 64-bit registers, X86-64 only
102 def RAX : RegisterWithSubRegs<"RAX", [EAX]>, DwarfRegNum<0>;
103 def RDX : RegisterWithSubRegs<"RDX", [EDX]>, DwarfRegNum<1>;
104 def RCX : RegisterWithSubRegs<"RCX", [ECX]>, DwarfRegNum<2>;
105 def RBX : RegisterWithSubRegs<"RBX", [EBX]>, DwarfRegNum<3>;
106 def RSI : RegisterWithSubRegs<"RSI", [ESI]>, DwarfRegNum<4>;
107 def RDI : RegisterWithSubRegs<"RDI", [EDI]>, DwarfRegNum<5>;
108 def RBP : RegisterWithSubRegs<"RBP", [EBP]>, DwarfRegNum<6>;
109 def RSP : RegisterWithSubRegs<"RSP", [ESP]>, DwarfRegNum<7>;
111 def R8 : RegisterWithSubRegs<"R8", [R8D]>, DwarfRegNum<8>;
112 def R9 : RegisterWithSubRegs<"R9", [R9D]>, DwarfRegNum<9>;
113 def R10 : RegisterWithSubRegs<"R10", [R10D]>, DwarfRegNum<10>;
114 def R11 : RegisterWithSubRegs<"R11", [R11D]>, DwarfRegNum<11>;
115 def R12 : RegisterWithSubRegs<"R12", [R12D]>, DwarfRegNum<12>;
116 def R13 : RegisterWithSubRegs<"R13", [R13D]>, DwarfRegNum<13>;
117 def R14 : RegisterWithSubRegs<"R14", [R14D]>, DwarfRegNum<14>;
118 def R15 : RegisterWithSubRegs<"R15", [R15D]>, DwarfRegNum<15>;
119 def RIP : RegisterWithSubRegs<"RIP", [EIP]>, DwarfRegNum<16>;
121 // MMX Registers. These are actually aliased to ST0 .. ST7
122 def MM0 : Register<"MM0">, DwarfRegNum<41>;
123 def MM1 : Register<"MM1">, DwarfRegNum<42>;
124 def MM2 : Register<"MM2">, DwarfRegNum<43>;
125 def MM3 : Register<"MM3">, DwarfRegNum<44>;
126 def MM4 : Register<"MM4">, DwarfRegNum<45>;
127 def MM5 : Register<"MM5">, DwarfRegNum<46>;
128 def MM6 : Register<"MM6">, DwarfRegNum<47>;
129 def MM7 : Register<"MM7">, DwarfRegNum<48>;
131 // Pseudo Floating Point registers
132 def FP0 : Register<"FP0">, DwarfRegNum<-1>;
133 def FP1 : Register<"FP1">, DwarfRegNum<-1>;
134 def FP2 : Register<"FP2">, DwarfRegNum<-1>;
135 def FP3 : Register<"FP3">, DwarfRegNum<-1>;
136 def FP4 : Register<"FP4">, DwarfRegNum<-1>;
137 def FP5 : Register<"FP5">, DwarfRegNum<-1>;
138 def FP6 : Register<"FP6">, DwarfRegNum<-1>;
140 // XMM Registers, used by the various SSE instruction set extensions
141 def XMM0: Register<"XMM0">, DwarfRegNum<17>;
142 def XMM1: Register<"XMM1">, DwarfRegNum<18>;
143 def XMM2: Register<"XMM2">, DwarfRegNum<19>;
144 def XMM3: Register<"XMM3">, DwarfRegNum<20>;
145 def XMM4: Register<"XMM4">, DwarfRegNum<21>;
146 def XMM5: Register<"XMM5">, DwarfRegNum<22>;
147 def XMM6: Register<"XMM6">, DwarfRegNum<23>;
148 def XMM7: Register<"XMM7">, DwarfRegNum<24>;
151 def XMM8: Register<"XMM8">, DwarfRegNum<25>;
152 def XMM9: Register<"XMM9">, DwarfRegNum<26>;
153 def XMM10: Register<"XMM10">, DwarfRegNum<27>;
154 def XMM11: Register<"XMM11">, DwarfRegNum<28>;
155 def XMM12: Register<"XMM12">, DwarfRegNum<29>;
156 def XMM13: Register<"XMM13">, DwarfRegNum<30>;
157 def XMM14: Register<"XMM14">, DwarfRegNum<31>;
158 def XMM15: Register<"XMM15">, DwarfRegNum<32>;
160 // Floating point stack registers
161 def ST0 : Register<"ST(0)">, DwarfRegNum<33>;
162 def ST1 : Register<"ST(1)">, DwarfRegNum<34>;
163 def ST2 : Register<"ST(2)">, DwarfRegNum<35>;
164 def ST3 : Register<"ST(3)">, DwarfRegNum<36>;
165 def ST4 : Register<"ST(4)">, DwarfRegNum<37>;
166 def ST5 : Register<"ST(5)">, DwarfRegNum<38>;
167 def ST6 : Register<"ST(6)">, DwarfRegNum<39>;
168 def ST7 : Register<"ST(7)">, DwarfRegNum<40>;
170 // Status flags register
171 def EFLAGS : Register<"EFLAGS">;
175 //===----------------------------------------------------------------------===//
176 // Subregister Set Definitions... now that we have all of the pieces, define the
177 // sub registers for each register.
180 def : SubRegSet<1, [AX, CX, DX, BX, SP, BP, SI, DI,
181 R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
182 [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
183 R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
185 // It's unclear if this subreg set is safe, given that not all registers
186 // in the class have an 'H' subreg.
187 // def : SubRegSet<2, [AX, CX, DX, BX],
188 // [AH, CH, DH, BH]>;
190 def : SubRegSet<1, [EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI,
191 R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D],
192 [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
193 R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
195 def : SubRegSet<2, [EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI,
196 R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D],
197 [AX, CX, DX, BX, SP, BP, SI, DI,
198 R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>;
201 def : SubRegSet<1, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI,
202 R8, R9, R10, R11, R12, R13, R14, R15],
203 [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
204 R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
206 def : SubRegSet<2, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI,
207 R8, R9, R10, R11, R12, R13, R14, R15],
208 [AX, CX, DX, BX, SP, BP, SI, DI,
209 R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>;
211 def : SubRegSet<3, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI,
212 R8, R9, R10, R11, R12, R13, R14, R15],
213 [EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI,
214 R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D]>;
216 //===----------------------------------------------------------------------===//
217 // Register Class Definitions... now that we have all of the pieces, define the
218 // top-level register classes. The order specified in the register list is
219 // implicitly defined to be the register allocation order.
222 // List call-clobbered registers before callee-save registers. RBX, RBP, (and
223 // R12, R13, R14, and R15 for X86-64) are callee-save registers.
224 // In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and
226 // FIXME: Allow AH, CH, DH, BH in 64-mode for non-REX instructions,
227 def GR8 : RegisterClass<"X86", [i8], 8,
228 [AL, CL, DL, BL, AH, CH, DH, BH, SIL, DIL, BPL, SPL,
229 R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]> {
230 let MethodProtos = [{
231 iterator allocation_order_begin(const MachineFunction &MF) const;
232 iterator allocation_order_end(const MachineFunction &MF) const;
234 let MethodBodies = [{
235 // Does the function dedicate RBP / EBP to being a frame ptr?
236 // If so, don't allocate SPL or BPL.
237 static const unsigned X86_GR8_AO_64_fp[] =
238 {X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL,
239 X86::R8B, X86::R9B, X86::R10B, X86::R11B,
240 X86::BL, X86::R14B, X86::R15B, X86::R12B, X86::R13B};
241 // If not, just don't allocate SPL.
242 static const unsigned X86_GR8_AO_64[] =
243 {X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL,
244 X86::R8B, X86::R9B, X86::R10B, X86::R11B,
245 X86::BL, X86::R14B, X86::R15B, X86::R12B, X86::R13B, X86::BPL};
246 // In 32-mode, none of the 8-bit registers aliases EBP or ESP.
247 static const unsigned X86_GR8_AO_32[] =
248 {X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH};
251 GR8Class::allocation_order_begin(const MachineFunction &MF) const {
252 const TargetMachine &TM = MF.getTarget();
253 const MRegisterInfo *RI = TM.getRegisterInfo();
254 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
255 if (!Subtarget.is64Bit())
256 return X86_GR8_AO_32;
257 else if (RI->hasFP(MF))
258 return X86_GR8_AO_64_fp;
260 return X86_GR8_AO_64;
264 GR8Class::allocation_order_end(const MachineFunction &MF) const {
265 const TargetMachine &TM = MF.getTarget();
266 const MRegisterInfo *RI = TM.getRegisterInfo();
267 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
268 if (!Subtarget.is64Bit())
269 return X86_GR8_AO_32 + (sizeof(X86_GR8_AO_32) / sizeof(unsigned));
270 else if (RI->hasFP(MF))
271 return X86_GR8_AO_64_fp + (sizeof(X86_GR8_AO_64_fp) / sizeof(unsigned));
273 return X86_GR8_AO_64 + (sizeof(X86_GR8_AO_64) / sizeof(unsigned));
279 def GR16 : RegisterClass<"X86", [i16], 16,
280 [AX, CX, DX, SI, DI, BX, BP, SP,
281 R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]> {
282 let SubRegClassList = [GR8];
283 let MethodProtos = [{
284 iterator allocation_order_begin(const MachineFunction &MF) const;
285 iterator allocation_order_end(const MachineFunction &MF) const;
287 let MethodBodies = [{
288 // Does the function dedicate RBP / EBP to being a frame ptr?
289 // If so, don't allocate SP or BP.
290 static const unsigned X86_GR16_AO_64_fp[] =
291 {X86::AX, X86::CX, X86::DX, X86::SI, X86::DI,
292 X86::R8W, X86::R9W, X86::R10W, X86::R11W,
293 X86::BX, X86::R14W, X86::R15W, X86::R12W, X86::R13W};
294 static const unsigned X86_GR16_AO_32_fp[] =
295 {X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX};
296 // If not, just don't allocate SPL.
297 static const unsigned X86_GR16_AO_64[] =
298 {X86::AX, X86::CX, X86::DX, X86::SI, X86::DI,
299 X86::R8W, X86::R9W, X86::R10W, X86::R11W,
300 X86::BX, X86::R14W, X86::R15W, X86::R12W, X86::R13W, X86::BP};
301 static const unsigned X86_GR16_AO_32[] =
302 {X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP};
305 GR16Class::allocation_order_begin(const MachineFunction &MF) const {
306 const TargetMachine &TM = MF.getTarget();
307 const MRegisterInfo *RI = TM.getRegisterInfo();
308 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
309 if (Subtarget.is64Bit()) {
311 return X86_GR16_AO_64_fp;
313 return X86_GR16_AO_64;
316 return X86_GR16_AO_32_fp;
318 return X86_GR16_AO_32;
323 GR16Class::allocation_order_end(const MachineFunction &MF) const {
324 const TargetMachine &TM = MF.getTarget();
325 const MRegisterInfo *RI = TM.getRegisterInfo();
326 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
327 if (Subtarget.is64Bit()) {
329 return X86_GR16_AO_64_fp+(sizeof(X86_GR16_AO_64_fp)/sizeof(unsigned));
331 return X86_GR16_AO_64 + (sizeof(X86_GR16_AO_64) / sizeof(unsigned));
334 return X86_GR16_AO_32_fp+(sizeof(X86_GR16_AO_32_fp)/sizeof(unsigned));
336 return X86_GR16_AO_32 + (sizeof(X86_GR16_AO_32) / sizeof(unsigned));
343 def GR32 : RegisterClass<"X86", [i32], 32,
344 [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP,
345 R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D]> {
346 let SubRegClassList = [GR8, GR16];
347 let MethodProtos = [{
348 iterator allocation_order_begin(const MachineFunction &MF) const;
349 iterator allocation_order_end(const MachineFunction &MF) const;
351 let MethodBodies = [{
352 // Does the function dedicate RBP / EBP to being a frame ptr?
353 // If so, don't allocate ESP or EBP.
354 static const unsigned X86_GR32_AO_64_fp[] =
355 {X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI,
356 X86::R8D, X86::R9D, X86::R10D, X86::R11D,
357 X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D};
358 static const unsigned X86_GR32_AO_32_fp[] =
359 {X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX};
360 // If not, just don't allocate SPL.
361 static const unsigned X86_GR32_AO_64[] =
362 {X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI,
363 X86::R8D, X86::R9D, X86::R10D, X86::R11D,
364 X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::EBP};
365 static const unsigned X86_GR32_AO_32[] =
366 {X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP};
369 GR32Class::allocation_order_begin(const MachineFunction &MF) const {
370 const TargetMachine &TM = MF.getTarget();
371 const MRegisterInfo *RI = TM.getRegisterInfo();
372 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
373 if (Subtarget.is64Bit()) {
375 return X86_GR32_AO_64_fp;
377 return X86_GR32_AO_64;
380 return X86_GR32_AO_32_fp;
382 return X86_GR32_AO_32;
387 GR32Class::allocation_order_end(const MachineFunction &MF) const {
388 const TargetMachine &TM = MF.getTarget();
389 const MRegisterInfo *RI = TM.getRegisterInfo();
390 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
391 if (Subtarget.is64Bit()) {
393 return X86_GR32_AO_64_fp+(sizeof(X86_GR32_AO_64_fp)/sizeof(unsigned));
395 return X86_GR32_AO_64 + (sizeof(X86_GR32_AO_64) / sizeof(unsigned));
398 return X86_GR32_AO_32_fp+(sizeof(X86_GR32_AO_32_fp)/sizeof(unsigned));
400 return X86_GR32_AO_32 + (sizeof(X86_GR32_AO_32) / sizeof(unsigned));
407 def GR64 : RegisterClass<"X86", [i64], 64,
408 [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
409 RBX, R14, R15, R12, R13, RBP, RSP]> {
410 let SubRegClassList = [GR8, GR16, GR32];
411 let MethodProtos = [{
412 iterator allocation_order_end(const MachineFunction &MF) const;
414 let MethodBodies = [{
416 GR64Class::allocation_order_end(const MachineFunction &MF) const {
417 const TargetMachine &TM = MF.getTarget();
418 const MRegisterInfo *RI = TM.getRegisterInfo();
419 if (RI->hasFP(MF)) // Does the function dedicate RBP to being a frame ptr?
420 return end()-2; // If so, don't allocate RSP or RBP
422 return end()-1; // If not, just don't allocate RSP
428 // GR16, GR32 subclasses which contain registers that have GR8 sub-registers.
429 // These should only be used for 32-bit mode.
430 def GR16_ : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]> {
431 let SubRegClassList = [GR8];
433 def GR32_ : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]> {
434 let SubRegClassList = [GR8, GR16];
437 // Scalar SSE2 floating point registers.
438 def FR32 : RegisterClass<"X86", [f32], 32,
439 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
440 XMM8, XMM9, XMM10, XMM11,
441 XMM12, XMM13, XMM14, XMM15]> {
442 let MethodProtos = [{
443 iterator allocation_order_end(const MachineFunction &MF) const;
445 let MethodBodies = [{
447 FR32Class::allocation_order_end(const MachineFunction &MF) const {
448 const TargetMachine &TM = MF.getTarget();
449 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
450 if (!Subtarget.is64Bit())
451 return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
458 def FR64 : RegisterClass<"X86", [f64], 64,
459 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
460 XMM8, XMM9, XMM10, XMM11,
461 XMM12, XMM13, XMM14, XMM15]> {
462 let MethodProtos = [{
463 iterator allocation_order_end(const MachineFunction &MF) const;
465 let MethodBodies = [{
467 FR64Class::allocation_order_end(const MachineFunction &MF) const {
468 const TargetMachine &TM = MF.getTarget();
469 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
470 if (!Subtarget.is64Bit())
471 return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
479 // FIXME: This sets up the floating point register files as though they are f64
480 // values, though they really are f80 values. This will cause us to spill
481 // values as 64-bit quantities instead of 80-bit quantities, which is much much
482 // faster on common hardware. In reality, this should be controlled by a
483 // command line option or something.
485 def RFP32 : RegisterClass<"X86", [f32], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
486 def RFP64 : RegisterClass<"X86", [f64], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
487 def RFP80 : RegisterClass<"X86", [f80], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
489 // Floating point stack registers (these are not allocatable by the
490 // register allocator - the floating point stackifier is responsible
491 // for transforming FPn allocations to STn registers)
492 def RST : RegisterClass<"X86", [f64], 32,
493 [ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> {
494 let MethodProtos = [{
495 iterator allocation_order_end(const MachineFunction &MF) const;
497 let MethodBodies = [{
499 RSTClass::allocation_order_end(const MachineFunction &MF) const {
505 // Generic vector registers: VR64 and VR128.
506 def VR64 : RegisterClass<"X86", [v8i8, v4i16, v2i32, v1i64], 64,
507 [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>;
508 def VR128 : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],128,
509 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
510 XMM8, XMM9, XMM10, XMM11,
511 XMM12, XMM13, XMM14, XMM15]> {
512 let MethodProtos = [{
513 iterator allocation_order_end(const MachineFunction &MF) const;
515 let MethodBodies = [{
517 VR128Class::allocation_order_end(const MachineFunction &MF) const {
518 const TargetMachine &TM = MF.getTarget();
519 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
520 if (!Subtarget.is64Bit())
521 return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
528 // Status flags registers.
529 def CCR : RegisterClass<"X86", [i32], 32, [EFLAGS]> {
530 let CopyCost = -1; // Don't allow copying of status registers.