1 //===- X86RegisterInfo.h - X86 Register Information Impl --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef X86REGISTERINFO_H
15 #define X86REGISTERINFO_H
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/Target/MRegisterInfo.h"
20 #include "X86GenRegisterInfo.h.inc"
24 class TargetInstrInfo;
25 class X86TargetMachine;
27 /// N86 namespace - Native X86 register numbers
31 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
35 /// DWARFFlavour - Flavour of dwarf regnumbers
37 namespace DWARFFlavour {
39 X86_64 = 0, X86_32_Darwin = 1, X86_32_ELF = 2
43 class X86RegisterInfo : public X86GenRegisterInfo {
46 const TargetInstrInfo &TII;
49 /// Is64Bit - Is the target 64-bits.
53 /// SlotSize - Stack slot size in bytes.
57 /// StackAlign - Default stack alignment.
61 /// StackPtr - X86 physical register used as stack ptr.
65 /// FramePtr - X86 physical register used as frame ptr.
69 /// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1,
70 /// RegOp2MemOpTable2 - Load / store folding opcode maps.
72 DenseMap<unsigned*, unsigned> RegOp2MemOpTable2Addr;
73 DenseMap<unsigned*, unsigned> RegOp2MemOpTable0;
74 DenseMap<unsigned*, unsigned> RegOp2MemOpTable1;
75 DenseMap<unsigned*, unsigned> RegOp2MemOpTable2;
77 /// MemOp2RegOpTable - Load / store unfolding opcode map.
79 DenseMap<unsigned*, std::pair<unsigned, unsigned> > MemOp2RegOpTable;
82 X86RegisterInfo(X86TargetMachine &tm, const TargetInstrInfo &tii);
84 /// getX86RegNum - Returns the native X86 register number for the given LLVM
85 /// register identifier.
86 unsigned getX86RegNum(unsigned RegNo);
88 unsigned getStackAlignment() const { return StackAlign; }
90 /// getDwarfRegNum - allows modification of X86GenRegisterInfo::getDwarfRegNum
91 /// (created by TableGen) for target dependencies.
92 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
94 /// Code Generation virtual methods...
96 const TargetRegisterClass *
97 getCrossCopyRegClass(const TargetRegisterClass *RC) const;
99 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
100 unsigned DestReg, const MachineInstr *Orig) const;
102 /// foldMemoryOperand - If this target supports it, fold a load or store of
103 /// the specified stack slot into the specified machine instruction for the
104 /// specified operand(s). If this is possible, the target should perform the
105 /// folding and return true, otherwise it should return false. If it folds
106 /// the instruction, it is likely that the MachineInstruction the iterator
107 /// references has been changed.
108 MachineInstr* foldMemoryOperand(MachineInstr* MI,
109 SmallVectorImpl<unsigned> &Ops,
110 int FrameIndex) const;
112 /// foldMemoryOperand - Same as the previous version except it allows folding
113 /// of any load and store from / to any address, not just from a specific
115 MachineInstr* foldMemoryOperand(MachineInstr* MI,
116 SmallVectorImpl<unsigned> &Ops,
117 MachineInstr* LoadMI) const;
119 /// canFoldMemoryOperand - Returns true if the specified load / store is
120 /// folding is possible.
121 bool canFoldMemoryOperand(MachineInstr*, SmallVectorImpl<unsigned> &) const;
123 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
124 /// a store or a load and a store into two or more instruction. If this is
125 /// possible, returns true as well as the new instructions by reference.
126 bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
127 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
128 SmallVectorImpl<MachineInstr*> &NewMIs) const;
130 bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
131 SmallVectorImpl<SDNode*> &NewNodes) const;
133 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
134 /// instruction after load / store are unfolded from an instruction of the
135 /// specified opcode. It returns zero if the specified unfolding is not
137 unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
138 bool UnfoldLoad, bool UnfoldStore) const;
140 /// getCalleeSavedRegs - Return a null-terminated list of all of the
141 /// callee-save registers on this target.
142 const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
144 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
145 /// register classes to spill each callee-saved register with. The order and
146 /// length of this list match the getCalleeSavedRegs() list.
147 const TargetRegisterClass* const*
148 getCalleeSavedRegClasses(const MachineFunction *MF = 0) const;
150 /// getReservedRegs - Returns a bitset indexed by physical register number
151 /// indicating if a register is a special register that has particular uses and
152 /// should be considered unavailable at all times, e.g. SP, RA. This is used by
153 /// register scavenger to determine what registers are free.
154 BitVector getReservedRegs(const MachineFunction &MF) const;
156 bool hasFP(const MachineFunction &MF) const;
158 bool hasReservedCallFrame(MachineFunction &MF) const;
160 void eliminateCallFramePseudoInstr(MachineFunction &MF,
161 MachineBasicBlock &MBB,
162 MachineBasicBlock::iterator MI) const;
164 void eliminateFrameIndex(MachineBasicBlock::iterator MI,
165 int SPAdj, RegScavenger *RS = NULL) const;
167 void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
169 void emitPrologue(MachineFunction &MF) const;
170 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
172 // Debug information queries.
173 unsigned getRARegister() const;
174 unsigned getFrameRegister(MachineFunction &MF) const;
175 void getInitialFrameState(std::vector<MachineMove> &Moves) const;
177 // Exception handling queries.
178 unsigned getEHExceptionRegister() const;
179 unsigned getEHHandlerRegister() const;
182 MachineInstr* foldMemoryOperand(MachineInstr* MI,
184 SmallVector<MachineOperand,4> &MOs) const;
187 // getX86SubSuperRegister - X86 utility function. It returns the sub or super
188 // register of a specific X86 register.
189 // e.g. getX86SubSuperRegister(X86::EAX, MVT::i16) return X86:AX
190 unsigned getX86SubSuperRegister(unsigned, MVT::ValueType, bool High=false);
192 } // End llvm namespace