1 //===- X86RegisterInfo.h - X86 Register Information Impl --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef X86REGISTERINFO_H
15 #define X86REGISTERINFO_H
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/Target/MRegisterInfo.h"
20 #include "X86GenRegisterInfo.h.inc"
24 class TargetInstrInfo;
25 class X86TargetMachine;
27 /// N86 namespace - Native X86 register numbers
31 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
35 class X86RegisterInfo : public X86GenRegisterInfo {
38 const TargetInstrInfo &TII;
41 /// Is64Bit - Is the target 64-bits.
45 /// SlotSize - Stack slot size in bytes.
49 /// StackAlign - Default stack alignment.
53 /// StackPtr - X86 physical register used as stack ptr.
57 /// FramePtr - X86 physical register used as frame ptr.
61 /// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1,
62 /// RegOp2MemOpTable2 - Load / store folding opcode maps.
64 DenseMap<unsigned*, unsigned> RegOp2MemOpTable2Addr;
65 DenseMap<unsigned*, unsigned> RegOp2MemOpTable0;
66 DenseMap<unsigned*, unsigned> RegOp2MemOpTable1;
67 DenseMap<unsigned*, unsigned> RegOp2MemOpTable2;
69 /// MemOp2RegOpTable - Load / store unfolding opcode map.
71 DenseMap<unsigned*, std::pair<unsigned, unsigned> > MemOp2RegOpTable;
74 X86RegisterInfo(X86TargetMachine &tm, const TargetInstrInfo &tii);
76 /// getX86RegNum - Returns the native X86 register number for the given LLVM
77 /// register identifier.
78 unsigned getX86RegNum(unsigned RegNo);
80 /// getDwarfRegNum - allows modification of X86GenRegisterInfo::getDwarfRegNum
81 /// (created by TableGen) for target dependencies.
82 int getDwarfRegNum(unsigned RegNum) const;
84 /// Code Generation virtual methods...
86 bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
87 MachineBasicBlock::iterator MI,
88 const std::vector<CalleeSavedInfo> &CSI) const;
90 bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
91 MachineBasicBlock::iterator MI,
92 const std::vector<CalleeSavedInfo> &CSI) const;
94 void storeRegToStackSlot(MachineBasicBlock &MBB,
95 MachineBasicBlock::iterator MI,
96 unsigned SrcReg, int FrameIndex,
97 const TargetRegisterClass *RC) const;
99 void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
100 SmallVectorImpl<MachineOperand> &Addr,
101 const TargetRegisterClass *RC,
102 SmallVectorImpl<MachineInstr*> &NewMIs) const;
104 void loadRegFromStackSlot(MachineBasicBlock &MBB,
105 MachineBasicBlock::iterator MI,
106 unsigned DestReg, int FrameIndex,
107 const TargetRegisterClass *RC) const;
109 void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
110 SmallVectorImpl<MachineOperand> &Addr,
111 const TargetRegisterClass *RC,
112 SmallVectorImpl<MachineInstr*> &NewMIs) const;
114 void copyRegToReg(MachineBasicBlock &MBB,
115 MachineBasicBlock::iterator MI,
116 unsigned DestReg, unsigned SrcReg,
117 const TargetRegisterClass *DestRC,
118 const TargetRegisterClass *SrcRC) const;
120 const TargetRegisterClass *
121 getCrossCopyRegClass(const TargetRegisterClass *RC) const;
123 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
124 unsigned DestReg, const MachineInstr *Orig) const;
126 /// foldMemoryOperand - If this target supports it, fold a load or store of
127 /// the specified stack slot into the specified machine instruction for the
128 /// specified operand. If this is possible, the target should perform the
129 /// folding and return true, otherwise it should return false. If it folds
130 /// the instruction, it is likely that the MachineInstruction the iterator
131 /// references has been changed.
132 MachineInstr* foldMemoryOperand(MachineInstr* MI,
134 int FrameIndex) const;
136 /// foldMemoryOperand - Same as the previous version except it allows folding
137 /// of any load and store from / to any address, not just from a specific
139 MachineInstr* foldMemoryOperand(MachineInstr* MI,
141 MachineInstr* LoadMI) const;
143 /// getOpcodeAfterMemoryFold - Returns the opcode of the would be new
144 /// instruction after load / store is folded into an instruction of the
145 /// specified opcode. It returns zero if the specified unfolding is not
147 unsigned getOpcodeAfterMemoryFold(unsigned Opc, unsigned OpNum) const;
149 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
150 /// a store or a load and a store into two or more instruction. If this is
151 /// possible, returns true as well as the new instructions by reference.
152 bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
153 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
154 SmallVectorImpl<MachineInstr*> &NewMIs) const;
156 bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
157 SmallVectorImpl<SDNode*> &NewNodes) const;
159 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
160 /// instruction after load / store are unfolded from an instruction of the
161 /// specified opcode. It returns zero if the specified unfolding is not
163 unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
164 bool UnfoldLoad, bool UnfoldStore) const;
166 /// getCalleeSavedRegs - Return a null-terminated list of all of the
167 /// callee-save registers on this target.
168 const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
170 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
171 /// register classes to spill each callee-saved register with. The order and
172 /// length of this list match the getCalleeSavedRegs() list.
173 const TargetRegisterClass* const*
174 getCalleeSavedRegClasses(const MachineFunction *MF = 0) const;
176 /// getReservedRegs - Returns a bitset indexed by physical register number
177 /// indicating if a register is a special register that has particular uses and
178 /// should be considered unavailable at all times, e.g. SP, RA. This is used by
179 /// register scavenger to determine what registers are free.
180 BitVector getReservedRegs(const MachineFunction &MF) const;
182 bool hasFP(const MachineFunction &MF) const;
184 bool hasReservedCallFrame(MachineFunction &MF) const;
186 void eliminateCallFramePseudoInstr(MachineFunction &MF,
187 MachineBasicBlock &MBB,
188 MachineBasicBlock::iterator MI) const;
190 void eliminateFrameIndex(MachineBasicBlock::iterator MI,
191 int SPAdj, RegScavenger *RS = NULL) const;
193 void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
195 void emitPrologue(MachineFunction &MF) const;
196 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
198 // Debug information queries.
199 unsigned getRARegister() const;
200 unsigned getFrameRegister(MachineFunction &MF) const;
201 void getInitialFrameState(std::vector<MachineMove> &Moves) const;
203 // Exception handling queries.
204 unsigned getEHExceptionRegister() const;
205 unsigned getEHHandlerRegister() const;
208 MachineInstr* foldMemoryOperand(MachineInstr* MI,
210 SmallVector<MachineOperand,4> &MOs) const;
213 // getX86SubSuperRegister - X86 utility function. It returns the sub or super
214 // register of a specific X86 register.
215 // e.g. getX86SubSuperRegister(X86::EAX, MVT::i16) return X86:AX
216 unsigned getX86SubSuperRegister(unsigned, MVT::ValueType, bool High=false);
218 } // End llvm namespace