1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/Target/TargetAsmInfo.h"
33 #include "llvm/Target/TargetFrameInfo.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/ADT/BitVector.h"
38 #include "llvm/ADT/STLExtras.h"
41 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
42 const TargetInstrInfo &tii)
43 : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP),
45 // Cache some information.
46 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
47 Is64Bit = Subtarget->is64Bit();
48 IsWin64 = Subtarget->isTargetWin64();
49 StackAlign = TM.getFrameInfo()->getStackAlignment();
61 // getDwarfRegNum - This function maps LLVM register identifiers to the
62 // Dwarf specific numbering, used in debug info and exception tables.
64 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
65 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
66 unsigned Flavour = DWARFFlavour::X86_64;
67 if (!Subtarget->is64Bit()) {
68 if (Subtarget->isTargetDarwin()) {
70 Flavour = DWARFFlavour::X86_32_DarwinEH;
72 Flavour = DWARFFlavour::X86_32_Generic;
73 } else if (Subtarget->isTargetCygMing()) {
74 // Unsupported by now, just quick fallback
75 Flavour = DWARFFlavour::X86_32_Generic;
77 Flavour = DWARFFlavour::X86_32_Generic;
81 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
84 // getX86RegNum - This function maps LLVM register identifiers to their X86
85 // specific numbering, which is used in various places encoding instructions.
87 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) const {
89 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
90 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
91 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
92 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
93 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
95 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
97 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
99 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
102 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
104 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
106 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
108 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
110 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
112 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
114 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
116 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
119 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
120 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
121 return RegNo-X86::ST0;
123 case X86::XMM0: case X86::XMM8: case X86::MM0:
125 case X86::XMM1: case X86::XMM9: case X86::MM1:
127 case X86::XMM2: case X86::XMM10: case X86::MM2:
129 case X86::XMM3: case X86::XMM11: case X86::MM3:
131 case X86::XMM4: case X86::XMM12: case X86::MM4:
133 case X86::XMM5: case X86::XMM13: case X86::MM5:
135 case X86::XMM6: case X86::XMM14: case X86::MM6:
137 case X86::XMM7: case X86::XMM15: case X86::MM7:
141 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
142 assert(0 && "Register allocator hasn't allocated reg correctly yet!");
147 const TargetRegisterClass *
148 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
149 if (RC == &X86::CCRRegClass) {
151 return &X86::GR64RegClass;
153 return &X86::GR32RegClass;
159 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
160 static const unsigned CalleeSavedRegs32Bit[] = {
161 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
164 static const unsigned CalleeSavedRegs32EHRet[] = {
165 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
168 static const unsigned CalleeSavedRegs64Bit[] = {
169 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
172 static const unsigned CalleeSavedRegsWin64[] = {
173 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
174 X86::R12, X86::R13, X86::R14, X86::R15, 0
179 return CalleeSavedRegsWin64;
181 return CalleeSavedRegs64Bit;
184 MachineFrameInfo *MFI = MF->getFrameInfo();
185 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
186 if (MMI && MMI->callsEHReturn())
187 return CalleeSavedRegs32EHRet;
189 return CalleeSavedRegs32Bit;
193 const TargetRegisterClass* const*
194 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
195 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
196 &X86::GR32RegClass, &X86::GR32RegClass,
197 &X86::GR32RegClass, &X86::GR32RegClass, 0
199 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
200 &X86::GR32RegClass, &X86::GR32RegClass,
201 &X86::GR32RegClass, &X86::GR32RegClass,
202 &X86::GR32RegClass, &X86::GR32RegClass, 0
204 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
205 &X86::GR64RegClass, &X86::GR64RegClass,
206 &X86::GR64RegClass, &X86::GR64RegClass,
207 &X86::GR64RegClass, &X86::GR64RegClass, 0
209 static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = {
210 &X86::GR64RegClass, &X86::GR64RegClass,
211 &X86::GR64RegClass, &X86::GR64RegClass,
212 &X86::GR64RegClass, &X86::GR64RegClass,
213 &X86::GR64RegClass, &X86::GR64RegClass, 0
218 return CalleeSavedRegClassesWin64;
220 return CalleeSavedRegClasses64Bit;
223 MachineFrameInfo *MFI = MF->getFrameInfo();
224 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
225 if (MMI && MMI->callsEHReturn())
226 return CalleeSavedRegClasses32EHRet;
228 return CalleeSavedRegClasses32Bit;
233 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
234 BitVector Reserved(getNumRegs());
235 Reserved.set(X86::RSP);
236 Reserved.set(X86::ESP);
237 Reserved.set(X86::SP);
238 Reserved.set(X86::SPL);
240 Reserved.set(X86::RBP);
241 Reserved.set(X86::EBP);
242 Reserved.set(X86::BP);
243 Reserved.set(X86::BPL);
248 //===----------------------------------------------------------------------===//
249 // Stack Frame Processing methods
250 //===----------------------------------------------------------------------===//
252 // hasFP - Return true if the specified function should have a dedicated frame
253 // pointer register. This is true if the function has variable sized allocas or
254 // if frame pointer elimination is disabled.
256 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
257 MachineFrameInfo *MFI = MF.getFrameInfo();
258 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
260 return (NoFramePointerElim ||
261 MFI->hasVarSizedObjects() ||
262 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
263 (MMI && MMI->callsUnwindInit()));
266 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
267 return !MF.getFrameInfo()->hasVarSizedObjects();
270 void X86RegisterInfo::
271 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
272 MachineBasicBlock::iterator I) const {
273 if (!hasReservedCallFrame(MF)) {
274 // If the stack pointer can be changed after prologue, turn the
275 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
276 // adjcallstackdown instruction into 'add ESP, <amt>'
277 // TODO: consider using push / pop instead of sub + store / add
278 MachineInstr *Old = I;
279 uint64_t Amount = Old->getOperand(0).getImm();
281 // We need to keep the stack aligned properly. To do this, we round the
282 // amount of space needed for the outgoing arguments up to the next
283 // alignment boundary.
284 Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
286 MachineInstr *New = 0;
287 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
288 New=BuildMI(TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri), StackPtr)
289 .addReg(StackPtr).addImm(Amount);
291 assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
292 // factor out the amount the callee already popped.
293 uint64_t CalleeAmt = Old->getOperand(1).getImm();
296 unsigned Opc = (Amount < 128) ?
297 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
298 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
299 New = BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(Amount);
303 // Replace the pseudo instruction with a new instruction...
304 if (New) MBB.insert(I, New);
306 } else if (I->getOpcode() == X86::ADJCALLSTACKUP) {
307 // If we are performing frame pointer elimination and if the callee pops
308 // something off the stack pointer, add it back. We do this until we have
309 // more advanced stack pointer tracking ability.
310 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
311 unsigned Opc = (CalleeAmt < 128) ?
312 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
313 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
315 BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt);
323 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
324 int SPAdj, RegScavenger *RS) const{
325 assert(SPAdj == 0 && "Unexpected");
328 MachineInstr &MI = *II;
329 MachineFunction &MF = *MI.getParent()->getParent();
330 while (!MI.getOperand(i).isFrameIndex()) {
332 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
335 int FrameIndex = MI.getOperand(i).getIndex();
336 // This must be part of a four operand memory reference. Replace the
337 // FrameIndex with base register with EBP. Add an offset to the offset.
338 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? FramePtr : StackPtr, false);
340 // Now add the frame object offset to the offset from EBP.
341 int64_t Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
342 MI.getOperand(i+3).getImm()+SlotSize;
345 Offset += MF.getFrameInfo()->getStackSize();
347 Offset += SlotSize; // Skip the saved EBP
348 // Skip the RETADDR move area
349 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
350 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
351 if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
354 MI.getOperand(i+3).ChangeToImmediate(Offset);
358 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
359 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
360 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
361 if (TailCallReturnAddrDelta < 0) {
362 // create RETURNADDR area
372 CreateFixedObject(-TailCallReturnAddrDelta,
373 (-1*SlotSize)+TailCallReturnAddrDelta);
376 assert((TailCallReturnAddrDelta <= 0) &&
377 "The Delta should always be zero or negative");
378 // Create a frame entry for the EBP register that must be saved.
379 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,
381 TailCallReturnAddrDelta);
382 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
383 "Slot for EBP register must be last in order to be found!");
387 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
388 /// stack pointer by a constant value.
390 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
391 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
392 const TargetInstrInfo &TII) {
393 bool isSub = NumBytes < 0;
394 uint64_t Offset = isSub ? -NumBytes : NumBytes;
397 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
398 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
400 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
401 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
402 uint64_t Chunk = (1LL << 31) - 1;
405 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
406 BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(ThisVal);
411 // mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
413 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
414 unsigned StackPtr, uint64_t *NumBytes = NULL) {
415 if (MBBI == MBB.begin()) return;
417 MachineBasicBlock::iterator PI = prior(MBBI);
418 unsigned Opc = PI->getOpcode();
419 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
420 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
421 PI->getOperand(0).getReg() == StackPtr) {
423 *NumBytes += PI->getOperand(2).getImm();
425 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
426 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
427 PI->getOperand(0).getReg() == StackPtr) {
429 *NumBytes -= PI->getOperand(2).getImm();
434 // mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
436 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
437 MachineBasicBlock::iterator &MBBI,
438 unsigned StackPtr, uint64_t *NumBytes = NULL) {
441 if (MBBI == MBB.end()) return;
443 MachineBasicBlock::iterator NI = next(MBBI);
444 if (NI == MBB.end()) return;
446 unsigned Opc = NI->getOpcode();
447 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
448 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
449 NI->getOperand(0).getReg() == StackPtr) {
451 *NumBytes -= NI->getOperand(2).getImm();
454 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
455 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
456 NI->getOperand(0).getReg() == StackPtr) {
458 *NumBytes += NI->getOperand(2).getImm();
464 /// mergeSPUpdates - Checks the instruction before/after the passed
465 /// instruction. If it is an ADD/SUB instruction it is deleted
466 /// argument and the stack adjustment is returned as a positive value for ADD
467 /// and a negative for SUB.
468 static int mergeSPUpdates(MachineBasicBlock &MBB,
469 MachineBasicBlock::iterator &MBBI,
471 bool doMergeWithPrevious) {
473 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
474 (!doMergeWithPrevious && MBBI == MBB.end()))
479 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
480 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI);
481 unsigned Opc = PI->getOpcode();
482 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
483 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
484 PI->getOperand(0).getReg() == StackPtr){
485 Offset += PI->getOperand(2).getImm();
487 if (!doMergeWithPrevious) MBBI = NI;
488 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
489 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
490 PI->getOperand(0).getReg() == StackPtr) {
491 Offset -= PI->getOperand(2).getImm();
493 if (!doMergeWithPrevious) MBBI = NI;
499 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
500 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
501 MachineFrameInfo *MFI = MF.getFrameInfo();
502 const Function* Fn = MF.getFunction();
503 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
504 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
505 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
506 MachineBasicBlock::iterator MBBI = MBB.begin();
507 bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) || !Fn->doesNotThrow();
509 // Prepare for frame info.
510 unsigned FrameLabelId = 0;
512 // Get the number of bytes to allocate from the FrameInfo.
513 uint64_t StackSize = MFI->getStackSize();
514 // Add RETADDR move area to callee saved frame size.
515 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
516 if (TailCallReturnAddrDelta < 0)
517 X86FI->setCalleeSavedFrameSize(
518 X86FI->getCalleeSavedFrameSize() +(-TailCallReturnAddrDelta));
519 uint64_t NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
521 // Insert stack pointer adjustment for later moving of return addr. Only
522 // applies to tail call optimized functions where the callee argument stack
523 // size is bigger than the callers.
524 if (TailCallReturnAddrDelta < 0) {
525 BuildMI(MBB, MBBI, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
526 StackPtr).addReg(StackPtr).addImm(-TailCallReturnAddrDelta);
530 // Get the offset of the stack slot for the EBP register... which is
531 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
532 // Update the frame offset adjustment.
533 MFI->setOffsetAdjustment(SlotSize-NumBytes);
535 // Save EBP into the appropriate stack slot...
536 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
538 NumBytes -= SlotSize;
540 if (needsFrameMoves) {
541 // Mark effective beginning of when frame pointer becomes valid.
542 FrameLabelId = MMI->NextLabelID();
543 BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(FrameLabelId).addImm(0);
546 // Update EBP with the new base value...
547 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
551 unsigned ReadyLabelId = 0;
552 if (needsFrameMoves) {
553 // Mark effective beginning of when frame pointer is ready.
554 ReadyLabelId = MMI->NextLabelID();
555 BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(ReadyLabelId).addImm(0);
558 // Skip the callee-saved push instructions.
559 while (MBBI != MBB.end() &&
560 (MBBI->getOpcode() == X86::PUSH32r ||
561 MBBI->getOpcode() == X86::PUSH64r))
564 if (NumBytes) { // adjust stack pointer: ESP -= numbytes
565 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
566 // Check, whether EAX is livein for this function
567 bool isEAXAlive = false;
568 for (MachineRegisterInfo::livein_iterator
569 II = MF.getRegInfo().livein_begin(),
570 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
571 unsigned Reg = II->first;
572 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
573 Reg == X86::AH || Reg == X86::AL);
576 // Function prologue calls _alloca to probe the stack when allocating
577 // more than 4k bytes in one go. Touching the stack at 4K increments is
578 // necessary to ensure that the guard pages used by the OS virtual memory
579 // manager are allocated in correct sequence.
581 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes);
582 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
583 .addExternalSymbol("_alloca");
586 BuildMI(MBB, MBBI, TII.get(X86::PUSH32r), X86::EAX);
587 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
588 // allocated bytes for EAX.
589 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes-4);
590 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
591 .addExternalSymbol("_alloca");
593 MachineInstr *MI = addRegOffset(BuildMI(TII.get(X86::MOV32rm),X86::EAX),
594 StackPtr, NumBytes-4);
595 MBB.insert(MBBI, MI);
598 // If there is an SUB32ri of ESP immediately before this instruction,
599 // merge the two. This can be the case when tail call elimination is
600 // enabled and the callee has more arguments then the caller.
601 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
602 // If there is an ADD32ri or SUB32ri of ESP immediately after this
603 // instruction, merge the two instructions.
604 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
607 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
611 if (needsFrameMoves) {
612 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
613 const TargetData *TD = MF.getTarget().getTargetData();
615 // Calculate amount of bytes used for return address storing
617 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
618 TargetFrameInfo::StackGrowsUp ?
619 TD->getPointerSize() : -TD->getPointerSize());
622 // Show update of SP.
625 MachineLocation SPDst(MachineLocation::VirtualFP);
626 MachineLocation SPSrc(MachineLocation::VirtualFP, 2*stackGrowth);
627 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
629 MachineLocation SPDst(MachineLocation::VirtualFP);
630 MachineLocation SPSrc(MachineLocation::VirtualFP,
631 -StackSize+stackGrowth);
632 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
635 //FIXME: Verify & implement for FP
636 MachineLocation SPDst(StackPtr);
637 MachineLocation SPSrc(StackPtr, stackGrowth);
638 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
641 // Add callee saved registers to move list.
642 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
644 // FIXME: This is dirty hack. The code itself is pretty mess right now.
645 // It should be rewritten from scratch and generalized sometimes.
647 // Determine maximum offset (minumum due to stack growth)
648 int64_t MaxOffset = 0;
649 for (unsigned I = 0, E = CSI.size(); I!=E; ++I)
650 MaxOffset = std::min(MaxOffset,
651 MFI->getObjectOffset(CSI[I].getFrameIdx()));
654 int64_t saveAreaOffset = (hasFP(MF) ? 3 : 2)*stackGrowth;
655 for (unsigned I = 0, E = CSI.size(); I!=E; ++I) {
656 int64_t Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
657 unsigned Reg = CSI[I].getReg();
658 Offset = (MaxOffset-Offset+saveAreaOffset);
659 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
660 MachineLocation CSSrc(Reg);
661 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
666 MachineLocation FPDst(MachineLocation::VirtualFP, 2*stackGrowth);
667 MachineLocation FPSrc(FramePtr);
668 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
671 MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr);
672 MachineLocation FPSrc(MachineLocation::VirtualFP);
673 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
676 // If it's main() on Cygwin\Mingw32 we should align stack as well
677 if (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
678 Subtarget->isTargetCygMing()) {
679 BuildMI(MBB, MBBI, TII.get(X86::AND32ri), X86::ESP)
680 .addReg(X86::ESP).addImm(-StackAlign);
683 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(StackAlign);
684 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32)).addExternalSymbol("_alloca");
688 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
689 MachineBasicBlock &MBB) const {
690 const MachineFrameInfo *MFI = MF.getFrameInfo();
691 const Function* Fn = MF.getFunction();
692 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
693 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
694 MachineBasicBlock::iterator MBBI = prior(MBB.end());
695 unsigned RetOpcode = MBBI->getOpcode();
700 case X86::TCRETURNdi:
701 case X86::TCRETURNri:
702 case X86::TCRETURNri64:
703 case X86::TCRETURNdi64:
707 case X86::TAILJMPm: break; // These are ok
709 assert(0 && "Can only insert epilog into returning blocks");
712 // Get the number of bytes to allocate from the FrameInfo
713 uint64_t StackSize = MFI->getStackSize();
714 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
715 uint64_t NumBytes = StackSize - CSSize;
719 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
720 NumBytes -= SlotSize;
723 // Skip the callee-saved pop instructions.
724 while (MBBI != MBB.begin()) {
725 MachineBasicBlock::iterator PI = prior(MBBI);
726 unsigned Opc = PI->getOpcode();
727 if (Opc != X86::POP32r && Opc != X86::POP64r &&
728 !PI->getDesc().isTerminator())
733 // If there is an ADD32ri or SUB32ri of ESP immediately before this
734 // instruction, merge the two instructions.
735 if (NumBytes || MFI->hasVarSizedObjects())
736 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
738 // If dynamic alloca is used, then reset esp to point to the last callee-saved
739 // slot before popping them off! Also, if it's main() on Cygwin/Mingw32 we
740 // aligned stack in the prologue, - revert stack changes back. Note: we're
741 // assuming, that frame pointer was forced for main()
742 if (MFI->hasVarSizedObjects() ||
743 (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
744 Subtarget->isTargetCygMing())) {
745 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
747 MachineInstr *MI = addRegOffset(BuildMI(TII.get(Opc), StackPtr),
749 MBB.insert(MBBI, MI);
751 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
757 // adjust stack pointer back: ESP += numbytes
759 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
761 // We're returning from function via eh_return.
762 if (RetOpcode == X86::EH_RETURN) {
763 MBBI = prior(MBB.end());
764 MachineOperand &DestAddr = MBBI->getOperand(0);
765 assert(DestAddr.isRegister() && "Offset should be in register!");
766 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
767 addReg(DestAddr.getReg());
768 // Tail call return: adjust the stack pointer and jump to callee
769 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
770 RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
771 MBBI = prior(MBB.end());
772 MachineOperand &JumpTarget = MBBI->getOperand(0);
773 MachineOperand &StackAdjust = MBBI->getOperand(1);
774 assert( StackAdjust.isImmediate() && "Expecting immediate value.");
776 // Adjust stack pointer.
777 int StackAdj = StackAdjust.getImm();
778 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
780 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
781 // Incoporate the retaddr area.
782 Offset = StackAdj-MaxTCDelta;
783 assert(Offset >= 0 && "Offset should never be negative");
785 // Check for possible merge with preceeding ADD instruction.
786 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
787 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
789 // Jump to label or value in register.
790 if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
791 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPd)).
792 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
793 else if (RetOpcode== X86::TCRETURNri64) {
794 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
796 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr), JumpTarget.getReg());
797 // Delete the pseudo instruction TCRETURN.
799 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
800 (X86FI->getTCReturnAddrDelta() < 0)) {
801 // Add the return addr area delta back since we are not tail calling.
802 int delta = -1*X86FI->getTCReturnAddrDelta();
803 MBBI = prior(MBB.end());
804 // Check for possible merge with preceeding ADD instruction.
805 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
806 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
810 unsigned X86RegisterInfo::getRARegister() const {
812 return X86::RIP; // Should have dwarf #16
814 return X86::EIP; // Should have dwarf #8
817 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
818 return hasFP(MF) ? FramePtr : StackPtr;
822 X86RegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
823 int Offset = MF.getFrameInfo()->getObjectOffset(FI) + SlotSize;
825 return Offset + MF.getFrameInfo()->getStackSize();
827 Offset += SlotSize; // Skip the saved EBP
828 // Skip the RETADDR move area
829 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
830 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
831 if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
835 void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
837 // Calculate amount of bytes used for return address storing
838 int stackGrowth = (Is64Bit ? -8 : -4);
840 // Initial state of the frame pointer is esp+4.
841 MachineLocation Dst(MachineLocation::VirtualFP);
842 MachineLocation Src(StackPtr, stackGrowth);
843 Moves.push_back(MachineMove(0, Dst, Src));
845 // Add return address to move list
846 MachineLocation CSDst(StackPtr, stackGrowth);
847 MachineLocation CSSrc(getRARegister());
848 Moves.push_back(MachineMove(0, CSDst, CSSrc));
851 unsigned X86RegisterInfo::getEHExceptionRegister() const {
852 assert(0 && "What is the exception register");
856 unsigned X86RegisterInfo::getEHHandlerRegister() const {
857 assert(0 && "What is the exception handler register");
862 unsigned getX86SubSuperRegister(unsigned Reg, MVT::ValueType VT, bool High) {
869 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
871 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
873 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
875 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
881 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
883 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
885 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
887 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
889 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
891 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
893 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
895 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
897 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
899 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
901 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
903 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
905 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
907 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
909 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
911 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
918 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
920 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
922 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
924 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
926 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
928 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
930 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
932 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
934 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
936 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
938 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
940 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
942 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
944 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
946 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
948 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
954 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
956 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
958 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
960 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
962 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
964 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
966 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
968 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
970 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
972 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
974 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
976 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
978 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
980 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
982 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
984 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
990 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
992 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
994 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
996 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
998 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1000 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1002 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1004 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1006 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1008 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1010 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1012 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1014 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1016 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1018 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1020 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1029 #include "X86GenRegisterInfo.inc"