1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains code to lower X86 MachineInstrs to their corresponding
13 //===----------------------------------------------------------------------===//
15 #include "X86MCInstLower.h"
16 #include "X86AsmPrinter.h"
17 #include "X86COFFMachineModuleInfo.h"
18 #include "X86MCAsmInfo.h"
19 #include "llvm/Analysis/DebugInfo.h"
20 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCStreamer.h"
25 #include "llvm/MC/MCSymbol.h"
26 #include "llvm/Target/Mangler.h"
27 #include "llvm/Support/FormattedStream.h"
28 #include "llvm/ADT/SmallString.h"
29 #include "llvm/Type.h"
33 const X86Subtarget &X86MCInstLower::getSubtarget() const {
34 return AsmPrinter.getSubtarget();
37 MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const {
38 assert(getSubtarget().isTargetDarwin() &&"Can only get MachO info on darwin");
39 return AsmPrinter.MMI->getObjFileInfo<MachineModuleInfoMachO>();
43 MCSymbol *X86MCInstLower::GetPICBaseSymbol() const {
44 const TargetLowering *TLI = AsmPrinter.TM.getTargetLowering();
45 return static_cast<const X86TargetLowering*>(TLI)->
46 getPICBaseSymbol(AsmPrinter.MF, Ctx);
49 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
50 /// operand to an MCSymbol.
51 MCSymbol *X86MCInstLower::
52 GetSymbolFromOperand(const MachineOperand &MO) const {
53 assert((MO.isGlobal() || MO.isSymbol()) && "Isn't a symbol reference");
55 SmallString<128> Name;
58 assert(MO.isSymbol());
59 Name += AsmPrinter.MAI->getGlobalPrefix();
60 Name += MO.getSymbolName();
62 const GlobalValue *GV = MO.getGlobal();
63 bool isImplicitlyPrivate = false;
64 if (MO.getTargetFlags() == X86II::MO_DARWIN_STUB ||
65 MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY ||
66 MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY_PIC_BASE ||
67 MO.getTargetFlags() == X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE)
68 isImplicitlyPrivate = true;
70 Mang->getNameWithPrefix(Name, GV, isImplicitlyPrivate);
73 // If the target flags on the operand changes the name of the symbol, do that
74 // before we return the symbol.
75 switch (MO.getTargetFlags()) {
77 case X86II::MO_DLLIMPORT: {
78 // Handle dllimport linkage.
79 const char *Prefix = "__imp_";
80 Name.insert(Name.begin(), Prefix, Prefix+strlen(Prefix));
83 case X86II::MO_DARWIN_NONLAZY:
84 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: {
85 Name += "$non_lazy_ptr";
86 MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
88 MachineModuleInfoImpl::StubValueTy &StubSym =
89 getMachOMMI().getGVStubEntry(Sym);
90 if (StubSym.getPointer() == 0) {
91 assert(MO.isGlobal() && "Extern symbol not handled yet");
93 MachineModuleInfoImpl::
94 StubValueTy(AsmPrinter.Mang->getSymbol(MO.getGlobal()),
95 !MO.getGlobal()->hasInternalLinkage());
99 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: {
100 Name += "$non_lazy_ptr";
101 MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
102 MachineModuleInfoImpl::StubValueTy &StubSym =
103 getMachOMMI().getHiddenGVStubEntry(Sym);
104 if (StubSym.getPointer() == 0) {
105 assert(MO.isGlobal() && "Extern symbol not handled yet");
107 MachineModuleInfoImpl::
108 StubValueTy(AsmPrinter.Mang->getSymbol(MO.getGlobal()),
109 !MO.getGlobal()->hasInternalLinkage());
113 case X86II::MO_DARWIN_STUB: {
115 MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
116 MachineModuleInfoImpl::StubValueTy &StubSym =
117 getMachOMMI().getFnStubEntry(Sym);
118 if (StubSym.getPointer())
123 MachineModuleInfoImpl::
124 StubValueTy(AsmPrinter.Mang->getSymbol(MO.getGlobal()),
125 !MO.getGlobal()->hasInternalLinkage());
127 Name.erase(Name.end()-5, Name.end());
129 MachineModuleInfoImpl::
130 StubValueTy(Ctx.GetOrCreateSymbol(Name.str()), false);
136 return Ctx.GetOrCreateSymbol(Name.str());
139 MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
140 MCSymbol *Sym) const {
141 // FIXME: We would like an efficient form for this, so we don't have to do a
142 // lot of extra uniquing.
143 const MCExpr *Expr = 0;
144 MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None;
146 switch (MO.getTargetFlags()) {
147 default: llvm_unreachable("Unknown target flag on GV operand");
148 case X86II::MO_NO_FLAG: // No flag.
149 // These affect the name of the symbol, not any suffix.
150 case X86II::MO_DARWIN_NONLAZY:
151 case X86II::MO_DLLIMPORT:
152 case X86II::MO_DARWIN_STUB:
155 case X86II::MO_TLVP: RefKind = MCSymbolRefExpr::VK_TLVP; break;
156 case X86II::MO_TLVP_PIC_BASE:
157 Expr = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx);
158 // Subtract the pic base.
159 Expr = MCBinaryExpr::CreateSub(Expr,
160 MCSymbolRefExpr::Create(GetPICBaseSymbol(),
164 case X86II::MO_TLSGD: RefKind = MCSymbolRefExpr::VK_TLSGD; break;
165 case X86II::MO_GOTTPOFF: RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break;
166 case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break;
167 case X86II::MO_TPOFF: RefKind = MCSymbolRefExpr::VK_TPOFF; break;
168 case X86II::MO_NTPOFF: RefKind = MCSymbolRefExpr::VK_NTPOFF; break;
169 case X86II::MO_GOTPCREL: RefKind = MCSymbolRefExpr::VK_GOTPCREL; break;
170 case X86II::MO_GOT: RefKind = MCSymbolRefExpr::VK_GOT; break;
171 case X86II::MO_GOTOFF: RefKind = MCSymbolRefExpr::VK_GOTOFF; break;
172 case X86II::MO_PLT: RefKind = MCSymbolRefExpr::VK_PLT; break;
173 case X86II::MO_PIC_BASE_OFFSET:
174 case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
175 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
176 Expr = MCSymbolRefExpr::Create(Sym, Ctx);
177 // Subtract the pic base.
178 Expr = MCBinaryExpr::CreateSub(Expr,
179 MCSymbolRefExpr::Create(GetPICBaseSymbol(), Ctx),
181 if (MO.isJTI() && AsmPrinter.MAI->hasSetDirective()) {
182 // If .set directive is supported, use it to reduce the number of
183 // relocations the assembler will generate for differences between
184 // local labels. This is only safe when the symbols are in the same
185 // section so we are restricting it to jumptable references.
186 MCSymbol *Label = Ctx.CreateTempSymbol();
187 AsmPrinter.OutStreamer.EmitAssignment(Label, Expr);
188 Expr = MCSymbolRefExpr::Create(Label, Ctx);
194 Expr = MCSymbolRefExpr::Create(Sym, RefKind, Ctx);
196 if (!MO.isJTI() && MO.getOffset())
197 Expr = MCBinaryExpr::CreateAdd(Expr,
198 MCConstantExpr::Create(MO.getOffset(), Ctx),
200 return MCOperand::CreateExpr(Expr);
205 static void lower_subreg32(MCInst *MI, unsigned OpNo) {
206 // Convert registers in the addr mode according to subreg32.
207 unsigned Reg = MI->getOperand(OpNo).getReg();
209 MI->getOperand(OpNo).setReg(getX86SubSuperRegister(Reg, MVT::i32));
212 static void lower_lea64_32mem(MCInst *MI, unsigned OpNo) {
213 // Convert registers in the addr mode according to subreg64.
214 for (unsigned i = 0; i != 4; ++i) {
215 if (!MI->getOperand(OpNo+i).isReg()) continue;
217 unsigned Reg = MI->getOperand(OpNo+i).getReg();
218 if (Reg == 0) continue;
220 MI->getOperand(OpNo+i).setReg(getX86SubSuperRegister(Reg, MVT::i64));
224 /// LowerSubReg32_Op0 - Things like MOVZX16rr8 -> MOVZX32rr8.
225 static void LowerSubReg32_Op0(MCInst &OutMI, unsigned NewOpc) {
226 OutMI.setOpcode(NewOpc);
227 lower_subreg32(&OutMI, 0);
229 /// LowerUnaryToTwoAddr - R = setb -> R = sbb R, R
230 static void LowerUnaryToTwoAddr(MCInst &OutMI, unsigned NewOpc) {
231 OutMI.setOpcode(NewOpc);
232 OutMI.addOperand(OutMI.getOperand(0));
233 OutMI.addOperand(OutMI.getOperand(0));
236 /// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
237 /// a short fixed-register form.
238 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
239 unsigned ImmOp = Inst.getNumOperands() - 1;
240 assert(Inst.getOperand(0).isReg() && Inst.getOperand(ImmOp).isImm() &&
241 ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
242 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
243 Inst.getNumOperands() == 2) && "Unexpected instruction!");
245 // Check whether the destination register can be fixed.
246 unsigned Reg = Inst.getOperand(0).getReg();
247 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
250 // If so, rewrite the instruction.
251 MCOperand Saved = Inst.getOperand(ImmOp);
253 Inst.setOpcode(Opcode);
254 Inst.addOperand(Saved);
257 /// \brief Simplify things like MOV32rm to MOV32o32a.
258 static void SimplifyShortMoveForm(MCInst &Inst, unsigned Opcode) {
259 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
260 unsigned AddrBase = IsStore;
261 unsigned RegOp = IsStore ? 0 : 5;
262 unsigned AddrOp = AddrBase + 3;
263 assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
264 Inst.getOperand(AddrBase + 0).isReg() && // base
265 Inst.getOperand(AddrBase + 1).isImm() && // scale
266 Inst.getOperand(AddrBase + 2).isReg() && // index register
267 (Inst.getOperand(AddrOp).isExpr() || // address
268 Inst.getOperand(AddrOp).isImm())&&
269 Inst.getOperand(AddrBase + 4).isReg() && // segment
270 "Unexpected instruction!");
272 // Check whether the destination register can be fixed.
273 unsigned Reg = Inst.getOperand(RegOp).getReg();
274 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
277 // Check whether this is an absolute address.
278 // FIXME: We know TLVP symbol refs aren't, but there should be a better way
280 bool Absolute = true;
281 if (Inst.getOperand(AddrOp).isExpr()) {
282 const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr();
283 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE))
284 if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
289 (Inst.getOperand(AddrBase + 0).getReg() != 0 ||
290 Inst.getOperand(AddrBase + 2).getReg() != 0 ||
291 Inst.getOperand(AddrBase + 4).getReg() != 0 ||
292 Inst.getOperand(AddrBase + 1).getImm() != 1))
295 // If so, rewrite the instruction.
296 MCOperand Saved = Inst.getOperand(AddrOp);
298 Inst.setOpcode(Opcode);
299 Inst.addOperand(Saved);
302 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
303 OutMI.setOpcode(MI->getOpcode());
305 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
306 const MachineOperand &MO = MI->getOperand(i);
309 switch (MO.getType()) {
312 llvm_unreachable("unknown operand type");
313 case MachineOperand::MO_Register:
314 // Ignore all implicit register operands.
315 if (MO.isImplicit()) continue;
316 MCOp = MCOperand::CreateReg(MO.getReg());
318 case MachineOperand::MO_Immediate:
319 MCOp = MCOperand::CreateImm(MO.getImm());
321 case MachineOperand::MO_MachineBasicBlock:
322 MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create(
323 MO.getMBB()->getSymbol(), Ctx));
325 case MachineOperand::MO_GlobalAddress:
326 MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
328 case MachineOperand::MO_ExternalSymbol:
329 MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
331 case MachineOperand::MO_JumpTableIndex:
332 MCOp = LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex()));
334 case MachineOperand::MO_ConstantPoolIndex:
335 MCOp = LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex()));
337 case MachineOperand::MO_BlockAddress:
338 MCOp = LowerSymbolOperand(MO,
339 AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()));
343 OutMI.addOperand(MCOp);
346 // Handle a few special cases to eliminate operand modifiers.
347 switch (OutMI.getOpcode()) {
348 case X86::LEA64_32r: // Handle 'subreg rewriting' for the lea64_32mem operand.
349 lower_lea64_32mem(&OutMI, 1);
354 // LEA should have a segment register, but it must be empty.
355 assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands &&
356 "Unexpected # of LEA operands");
357 assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
358 "LEA has segment specified!");
360 case X86::MOVZX16rr8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr8); break;
361 case X86::MOVZX16rm8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm8); break;
362 case X86::MOVSX16rr8: LowerSubReg32_Op0(OutMI, X86::MOVSX32rr8); break;
363 case X86::MOVSX16rm8: LowerSubReg32_Op0(OutMI, X86::MOVSX32rm8); break;
364 case X86::MOVZX64rr32: LowerSubReg32_Op0(OutMI, X86::MOV32rr); break;
365 case X86::MOVZX64rm32: LowerSubReg32_Op0(OutMI, X86::MOV32rm); break;
366 case X86::MOV64ri64i32: LowerSubReg32_Op0(OutMI, X86::MOV32ri); break;
367 case X86::MOVZX64rr8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr8); break;
368 case X86::MOVZX64rm8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm8); break;
369 case X86::MOVZX64rr16: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr16); break;
370 case X86::MOVZX64rm16: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm16); break;
371 case X86::SETB_C8r: LowerUnaryToTwoAddr(OutMI, X86::SBB8rr); break;
372 case X86::SETB_C16r: LowerUnaryToTwoAddr(OutMI, X86::SBB16rr); break;
373 case X86::SETB_C32r: LowerUnaryToTwoAddr(OutMI, X86::SBB32rr); break;
374 case X86::SETB_C64r: LowerUnaryToTwoAddr(OutMI, X86::SBB64rr); break;
375 case X86::MOV8r0: LowerUnaryToTwoAddr(OutMI, X86::XOR8rr); break;
376 case X86::MOV32r0: LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); break;
377 case X86::MMX_V_SET0: LowerUnaryToTwoAddr(OutMI, X86::MMX_PXORrr); break;
378 case X86::MMX_V_SETALLONES:
379 LowerUnaryToTwoAddr(OutMI, X86::MMX_PCMPEQDrr); break;
380 case X86::FsFLD0SS: LowerUnaryToTwoAddr(OutMI, X86::PXORrr); break;
381 case X86::FsFLD0SD: LowerUnaryToTwoAddr(OutMI, X86::PXORrr); break;
382 case X86::V_SET0PS: LowerUnaryToTwoAddr(OutMI, X86::XORPSrr); break;
383 case X86::V_SET0PD: LowerUnaryToTwoAddr(OutMI, X86::XORPDrr); break;
384 case X86::V_SET0PI: LowerUnaryToTwoAddr(OutMI, X86::PXORrr); break;
385 case X86::V_SETALLONES: LowerUnaryToTwoAddr(OutMI, X86::PCMPEQDrr); break;
388 LowerSubReg32_Op0(OutMI, X86::MOV32r0); // MOV16r0 -> MOV32r0
389 LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); // MOV32r0 -> XOR32rr
392 LowerSubReg32_Op0(OutMI, X86::MOV32r0); // MOV64r0 -> MOV32r0
393 LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); // MOV32r0 -> XOR32rr
396 // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have
397 // register inputs modeled as normal uses instead of implicit uses. As such,
398 // truncate off all but the first operand (the callee). FIXME: Change isel.
399 case X86::TAILJMPr64:
401 case X86::CALL64pcrel32: {
402 unsigned Opcode = OutMI.getOpcode();
403 MCOperand Saved = OutMI.getOperand(0);
405 OutMI.setOpcode(Opcode);
406 OutMI.addOperand(Saved);
410 // TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions.
413 case X86::TAILJMPd64: {
415 switch (OutMI.getOpcode()) {
416 default: assert(0 && "Invalid opcode");
417 case X86::TAILJMPr: Opcode = X86::JMP32r; break;
419 case X86::TAILJMPd64: Opcode = X86::JMP_1; break;
422 MCOperand Saved = OutMI.getOperand(0);
424 OutMI.setOpcode(Opcode);
425 OutMI.addOperand(Saved);
429 // The assembler backend wants to see branches in their small form and relax
430 // them to their large form. The JIT can only handle the large form because
431 // it does not do relaxation. For now, translate the large form to the
433 case X86::JMP_4: OutMI.setOpcode(X86::JMP_1); break;
434 case X86::JO_4: OutMI.setOpcode(X86::JO_1); break;
435 case X86::JNO_4: OutMI.setOpcode(X86::JNO_1); break;
436 case X86::JB_4: OutMI.setOpcode(X86::JB_1); break;
437 case X86::JAE_4: OutMI.setOpcode(X86::JAE_1); break;
438 case X86::JE_4: OutMI.setOpcode(X86::JE_1); break;
439 case X86::JNE_4: OutMI.setOpcode(X86::JNE_1); break;
440 case X86::JBE_4: OutMI.setOpcode(X86::JBE_1); break;
441 case X86::JA_4: OutMI.setOpcode(X86::JA_1); break;
442 case X86::JS_4: OutMI.setOpcode(X86::JS_1); break;
443 case X86::JNS_4: OutMI.setOpcode(X86::JNS_1); break;
444 case X86::JP_4: OutMI.setOpcode(X86::JP_1); break;
445 case X86::JNP_4: OutMI.setOpcode(X86::JNP_1); break;
446 case X86::JL_4: OutMI.setOpcode(X86::JL_1); break;
447 case X86::JGE_4: OutMI.setOpcode(X86::JGE_1); break;
448 case X86::JLE_4: OutMI.setOpcode(X86::JLE_1); break;
449 case X86::JG_4: OutMI.setOpcode(X86::JG_1); break;
451 // We don't currently select the correct instruction form for instructions
452 // which have a short %eax, etc. form. Handle this by custom lowering, for
455 // Note, we are currently not handling the following instructions:
456 // MOV64ao8, MOV64o8a
457 // XCHG16ar, XCHG32ar, XCHG64ar
458 case X86::MOV8mr_NOREX:
459 case X86::MOV8mr: SimplifyShortMoveForm(OutMI, X86::MOV8ao8); break;
460 case X86::MOV8rm_NOREX:
461 case X86::MOV8rm: SimplifyShortMoveForm(OutMI, X86::MOV8o8a); break;
462 case X86::MOV16mr: SimplifyShortMoveForm(OutMI, X86::MOV16ao16); break;
463 case X86::MOV16rm: SimplifyShortMoveForm(OutMI, X86::MOV16o16a); break;
464 case X86::MOV32mr: SimplifyShortMoveForm(OutMI, X86::MOV32ao32); break;
465 case X86::MOV32rm: SimplifyShortMoveForm(OutMI, X86::MOV32o32a); break;
466 case X86::MOV64mr: SimplifyShortMoveForm(OutMI, X86::MOV64ao64); break;
467 case X86::MOV64rm: SimplifyShortMoveForm(OutMI, X86::MOV64o64a); break;
469 case X86::ADC8ri: SimplifyShortImmForm(OutMI, X86::ADC8i8); break;
470 case X86::ADC16ri: SimplifyShortImmForm(OutMI, X86::ADC16i16); break;
471 case X86::ADC32ri: SimplifyShortImmForm(OutMI, X86::ADC32i32); break;
472 case X86::ADC64ri32: SimplifyShortImmForm(OutMI, X86::ADC64i32); break;
473 case X86::ADD8ri: SimplifyShortImmForm(OutMI, X86::ADD8i8); break;
474 case X86::ADD16ri: SimplifyShortImmForm(OutMI, X86::ADD16i16); break;
475 case X86::ADD32ri: SimplifyShortImmForm(OutMI, X86::ADD32i32); break;
476 case X86::ADD64ri32: SimplifyShortImmForm(OutMI, X86::ADD64i32); break;
477 case X86::AND8ri: SimplifyShortImmForm(OutMI, X86::AND8i8); break;
478 case X86::AND16ri: SimplifyShortImmForm(OutMI, X86::AND16i16); break;
479 case X86::AND32ri: SimplifyShortImmForm(OutMI, X86::AND32i32); break;
480 case X86::AND64ri32: SimplifyShortImmForm(OutMI, X86::AND64i32); break;
481 case X86::CMP8ri: SimplifyShortImmForm(OutMI, X86::CMP8i8); break;
482 case X86::CMP16ri: SimplifyShortImmForm(OutMI, X86::CMP16i16); break;
483 case X86::CMP32ri: SimplifyShortImmForm(OutMI, X86::CMP32i32); break;
484 case X86::CMP64ri32: SimplifyShortImmForm(OutMI, X86::CMP64i32); break;
485 case X86::OR8ri: SimplifyShortImmForm(OutMI, X86::OR8i8); break;
486 case X86::OR16ri: SimplifyShortImmForm(OutMI, X86::OR16i16); break;
487 case X86::OR32ri: SimplifyShortImmForm(OutMI, X86::OR32i32); break;
488 case X86::OR64ri32: SimplifyShortImmForm(OutMI, X86::OR64i32); break;
489 case X86::SBB8ri: SimplifyShortImmForm(OutMI, X86::SBB8i8); break;
490 case X86::SBB16ri: SimplifyShortImmForm(OutMI, X86::SBB16i16); break;
491 case X86::SBB32ri: SimplifyShortImmForm(OutMI, X86::SBB32i32); break;
492 case X86::SBB64ri32: SimplifyShortImmForm(OutMI, X86::SBB64i32); break;
493 case X86::SUB8ri: SimplifyShortImmForm(OutMI, X86::SUB8i8); break;
494 case X86::SUB16ri: SimplifyShortImmForm(OutMI, X86::SUB16i16); break;
495 case X86::SUB32ri: SimplifyShortImmForm(OutMI, X86::SUB32i32); break;
496 case X86::SUB64ri32: SimplifyShortImmForm(OutMI, X86::SUB64i32); break;
497 case X86::TEST8ri: SimplifyShortImmForm(OutMI, X86::TEST8i8); break;
498 case X86::TEST16ri: SimplifyShortImmForm(OutMI, X86::TEST16i16); break;
499 case X86::TEST32ri: SimplifyShortImmForm(OutMI, X86::TEST32i32); break;
500 case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break;
501 case X86::XOR8ri: SimplifyShortImmForm(OutMI, X86::XOR8i8); break;
502 case X86::XOR16ri: SimplifyShortImmForm(OutMI, X86::XOR16i16); break;
503 case X86::XOR32ri: SimplifyShortImmForm(OutMI, X86::XOR32i32); break;
504 case X86::XOR64ri32: SimplifyShortImmForm(OutMI, X86::XOR64i32); break;
508 void X86AsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
510 // Only the target-dependent form of DBG_VALUE should get here.
511 // Referencing the offset and metadata as NOps-2 and NOps-1 is
512 // probably portable to other targets; frame pointer location is not.
513 unsigned NOps = MI->getNumOperands();
515 O << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
516 // cast away const; DIetc do not take const operands for some reason.
517 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
518 if (V.getContext().isSubprogram())
519 O << DISubprogram(V.getContext()).getDisplayName() << ":";
522 // Frame address. Currently handles register +- offset only.
524 if (MI->getOperand(0).isReg() && MI->getOperand(0).getReg())
525 printOperand(MI, 0, O);
528 O << '+'; printOperand(MI, 3, O);
531 printOperand(MI, NOps-2, O);
535 X86AsmPrinter::getDebugValueLocation(const MachineInstr *MI) const {
536 MachineLocation Location;
537 assert (MI->getNumOperands() == 7 && "Invalid no. of machine operands!");
538 // Frame address. Currently handles register +- offset only.
540 if (MI->getOperand(0).isReg() && MI->getOperand(3).isImm())
541 Location.set(MI->getOperand(0).getReg(), MI->getOperand(3).getImm());
546 void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
547 X86MCInstLower MCInstLowering(OutContext, Mang, *this);
548 switch (MI->getOpcode()) {
549 case TargetOpcode::DBG_VALUE:
550 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
552 raw_string_ostream OS(TmpStr);
553 PrintDebugValueComment(MI, OS);
554 OutStreamer.EmitRawText(StringRef(OS.str()));
560 case X86::TAILJMPd64:
561 // Lower these as normal, but add some comments.
562 OutStreamer.AddComment("TAILCALL");
565 case X86::MOVPC32r: {
567 // This is a pseudo op for a two instruction sequence with a label, which
574 MCSymbol *PICBase = MCInstLowering.GetPICBaseSymbol();
575 TmpInst.setOpcode(X86::CALLpcrel32);
576 // FIXME: We would like an efficient form for this, so we don't have to do a
577 // lot of extra uniquing.
578 TmpInst.addOperand(MCOperand::CreateExpr(MCSymbolRefExpr::Create(PICBase,
580 OutStreamer.EmitInstruction(TmpInst);
583 OutStreamer.EmitLabel(PICBase);
586 TmpInst.setOpcode(X86::POP32r);
587 TmpInst.getOperand(0) = MCOperand::CreateReg(MI->getOperand(0).getReg());
588 OutStreamer.EmitInstruction(TmpInst);
593 // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
594 if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS)
597 // Okay, we have something like:
598 // EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
600 // For this, we want to print something like:
601 // MYGLOBAL + (. - PICBASE)
602 // However, we can't generate a ".", so just emit a new label here and refer
604 MCSymbol *DotSym = OutContext.CreateTempSymbol();
605 OutStreamer.EmitLabel(DotSym);
607 // Now that we have emitted the label, lower the complex operand expression.
608 MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
610 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
611 const MCExpr *PICBase =
612 MCSymbolRefExpr::Create(MCInstLowering.GetPICBaseSymbol(), OutContext);
613 DotExpr = MCBinaryExpr::CreateSub(DotExpr, PICBase, OutContext);
615 DotExpr = MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(OpSym,OutContext),
616 DotExpr, OutContext);
619 TmpInst.setOpcode(X86::ADD32ri);
620 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
621 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
622 TmpInst.addOperand(MCOperand::CreateExpr(DotExpr));
623 OutStreamer.EmitInstruction(TmpInst);
629 MCInstLowering.Lower(MI, TmpInst);
630 OutStreamer.EmitInstruction(TmpInst);