1 //====- X86InstrX86-64.td - Describe the X86 Instruction Set ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the Evan Cheng and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86-64 instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Operand Definitions...
20 // 64-bits but only 32 bits are significant.
21 def i64i32imm : Operand<i64>;
22 // 64-bits but only 8 bits are significant.
23 def i64i8imm : Operand<i64>;
25 def lea64mem : Operand<i64> {
26 let PrintMethod = "printi64mem";
27 let MIOperandInfo = (ops GR64, i8imm, GR64, i32imm);
30 def lea64_32mem : Operand<i32> {
31 let PrintMethod = "printlea64_32mem";
32 let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
35 //===----------------------------------------------------------------------===//
36 // Complex Pattern Definitions...
38 def lea64addr : ComplexPattern<i64, 4, "SelectLEAAddr",
39 [add, mul, shl, or, frameindex, X86Wrapper],
42 //===----------------------------------------------------------------------===//
43 // Pattern fragments...
46 def i64immSExt32 : PatLeaf<(i64 imm), [{
47 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
48 // sign extended field.
49 return (int64_t)N->getValue() == (int32_t)N->getValue();
52 def i64immZExt32 : PatLeaf<(i64 imm), [{
53 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
54 // unsignedsign extended field.
55 return (uint64_t)N->getValue() == (uint32_t)N->getValue();
58 def i64immSExt8 : PatLeaf<(i64 imm), [{
59 // i64immSExt8 predicate - True if the 64-bit immediate fits in a 8-bit
60 // sign extended field.
61 return (int64_t)N->getValue() == (int8_t)N->getValue();
64 def sextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (sextloadi1 node:$ptr))>;
65 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
66 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
67 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
69 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
70 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
71 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
72 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
74 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
75 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
76 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
77 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
79 //===----------------------------------------------------------------------===//
80 // Instruction list...
83 def IMPLICIT_DEF_GR64 : I<0, Pseudo, (outs GR64:$dst), (ins),
85 [(set GR64:$dst, (undef))]>;
87 //===----------------------------------------------------------------------===//
88 // Call Instructions...
91 // All calls clobber the non-callee saved registers...
92 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
93 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
94 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
95 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
96 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15] in {
97 def CALL64pcrel32 : I<0xE8, RawFrm, (outs), (ins i64imm:$dst, variable_ops),
98 "call\t${dst:call}", []>;
99 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
100 "call\t{*}$dst", [(X86call GR64:$dst)]>;
101 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
102 "call\t{*}$dst", []>;
106 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
107 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
108 [(brind GR64:$dst)]>;
109 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
110 [(brind (loadi64 addr:$dst))]>;
113 //===----------------------------------------------------------------------===//
114 // Miscellaneous Instructions...
116 def LEAVE64 : I<0xC9, RawFrm,
117 (outs), (ins), "leave", []>, Imp<[RBP,RSP],[RBP,RSP]>;
118 def POP64r : I<0x58, AddRegFrm,
119 (outs GR64:$reg), (ins), "pop{q}\t$reg", []>, Imp<[RSP],[RSP]>;
120 def PUSH64r : I<0x50, AddRegFrm,
121 (outs), (ins GR64:$reg), "push{q}\t$reg", []>, Imp<[RSP],[RSP]>;
123 def LEA64_32r : I<0x8D, MRMSrcMem,
124 (outs GR32:$dst), (ins lea64_32mem:$src),
125 "lea{l}\t{$src|$dst}, {$dst|$src}",
126 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>;
128 def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src),
129 "lea{q}\t{$src|$dst}, {$dst|$src}",
130 [(set GR64:$dst, lea64addr:$src)]>;
132 let isTwoAddress = 1 in
133 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
135 [(set GR64:$dst, (bswap GR64:$src))]>, TB;
137 def XCHG64rr : RI<0x87, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
138 "xchg{q}\t{$src2|$src1}, {$src1|$src2}", []>;
139 def XCHG64mr : RI<0x87, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
140 "xchg{q}\t{$src2|$src1}, {$src1|$src2}", []>;
141 def XCHG64rm : RI<0x87, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
142 "xchg{q}\t{$src2|$src1}, {$src1|$src2}", []>;
145 def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
146 [(X86rep_movs i64)]>,
147 Imp<[RCX,RDI,RSI], [RCX,RDI,RSI]>, REP;
148 def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
149 [(X86rep_stos i64)]>,
150 Imp<[RAX,RCX,RDI], [RCX,RDI]>, REP;
152 //===----------------------------------------------------------------------===//
153 // Move Instructions...
156 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
157 "mov{q}\t{$src, $dst|$dst, $src}", []>;
159 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
160 "movabs{q}\t{$src, $dst|$dst, $src}",
161 [(set GR64:$dst, imm:$src)]>;
162 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
163 "mov{q}\t{$src, $dst|$dst, $src}",
164 [(set GR64:$dst, i64immSExt32:$src)]>;
167 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
168 "mov{q}\t{$src, $dst|$dst, $src}",
169 [(set GR64:$dst, (load addr:$src))]>;
171 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
172 "mov{q}\t{$src, $dst|$dst, $src}",
173 [(store GR64:$src, addr:$dst)]>;
174 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
175 "mov{q}\t{$src, $dst|$dst, $src}",
176 [(store i64immSExt32:$src, addr:$dst)]>;
178 // Sign/Zero extenders
180 def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
181 "movs{bq|x}\t{$src, $dst|$dst, $src}",
182 [(set GR64:$dst, (sext GR8:$src))]>, TB;
183 def MOVSX64rm8 : RI<0xBE, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
184 "movs{bq|x}\t{$src, $dst|$dst, $src}",
185 [(set GR64:$dst, (sextloadi64i8 addr:$src))]>, TB;
186 def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
187 "movs{wq|x}\t{$src, $dst|$dst, $src}",
188 [(set GR64:$dst, (sext GR16:$src))]>, TB;
189 def MOVSX64rm16: RI<0xBF, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
190 "movs{wq|x}\t{$src, $dst|$dst, $src}",
191 [(set GR64:$dst, (sextloadi64i16 addr:$src))]>, TB;
192 def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
193 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
194 [(set GR64:$dst, (sext GR32:$src))]>;
195 def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
196 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
197 [(set GR64:$dst, (sextloadi64i32 addr:$src))]>;
199 def MOVZX64rr8 : RI<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
200 "movz{bq|x}\t{$src, $dst|$dst, $src}",
201 [(set GR64:$dst, (zext GR8:$src))]>, TB;
202 def MOVZX64rm8 : RI<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
203 "movz{bq|x}\t{$src, $dst|$dst, $src}",
204 [(set GR64:$dst, (zextloadi64i8 addr:$src))]>, TB;
205 def MOVZX64rr16: RI<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
206 "movz{wq|x}\t{$src, $dst|$dst, $src}",
207 [(set GR64:$dst, (zext GR16:$src))]>, TB;
208 def MOVZX64rm16: RI<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
209 "movz{wq|x}\t{$src, $dst|$dst, $src}",
210 [(set GR64:$dst, (zextloadi64i16 addr:$src))]>, TB;
212 def CDQE : RI<0x98, RawFrm, (outs), (ins),
213 "{cltq|cdqe}", []>, Imp<[EAX],[RAX]>; // RAX = signext(EAX)
215 def CQO : RI<0x99, RawFrm, (outs), (ins),
216 "{cqto|cqo}", []>, Imp<[RAX],[RAX,RDX]>; // RDX:RAX = signext(RAX)
218 //===----------------------------------------------------------------------===//
219 // Arithmetic Instructions...
222 let isTwoAddress = 1 in {
223 let isConvertibleToThreeAddress = 1 in {
224 let isCommutable = 1 in
225 def ADD64rr : RI<0x01, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
226 "add{q}\t{$src2, $dst|$dst, $src2}",
227 [(set GR64:$dst, (add GR64:$src1, GR64:$src2))]>;
229 def ADD64ri32 : RIi32<0x81, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
230 "add{q}\t{$src2, $dst|$dst, $src2}",
231 [(set GR64:$dst, (add GR64:$src1, i64immSExt32:$src2))]>;
232 def ADD64ri8 : RIi8<0x83, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
233 "add{q}\t{$src2, $dst|$dst, $src2}",
234 [(set GR64:$dst, (add GR64:$src1, i64immSExt8:$src2))]>;
235 } // isConvertibleToThreeAddress
237 def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
238 "add{q}\t{$src2, $dst|$dst, $src2}",
239 [(set GR64:$dst, (add GR64:$src1, (load addr:$src2)))]>;
242 def ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
243 "add{q}\t{$src2, $dst|$dst, $src2}",
244 [(store (add (load addr:$dst), GR64:$src2), addr:$dst)]>;
245 def ADD64mi32 : RIi32<0x81, MRM0m, (outs), (ins i64mem:$dst, i64i32imm :$src2),
246 "add{q}\t{$src2, $dst|$dst, $src2}",
247 [(store (add (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
248 def ADD64mi8 : RIi8<0x83, MRM0m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
249 "add{q}\t{$src2, $dst|$dst, $src2}",
250 [(store (add (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
252 let isTwoAddress = 1 in {
253 let isCommutable = 1 in
254 def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
255 "adc{q}\t{$src2, $dst|$dst, $src2}",
256 [(set GR64:$dst, (adde GR64:$src1, GR64:$src2))]>;
258 def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
259 "adc{q}\t{$src2, $dst|$dst, $src2}",
260 [(set GR64:$dst, (adde GR64:$src1, (load addr:$src2)))]>;
262 def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
263 "adc{q}\t{$src2, $dst|$dst, $src2}",
264 [(set GR64:$dst, (adde GR64:$src1, i64immSExt32:$src2))]>;
265 def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
266 "adc{q}\t{$src2, $dst|$dst, $src2}",
267 [(set GR64:$dst, (adde GR64:$src1, i64immSExt8:$src2))]>;
270 def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
271 "adc{q}\t{$src2, $dst|$dst, $src2}",
272 [(store (adde (load addr:$dst), GR64:$src2), addr:$dst)]>;
273 def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
274 "adc{q}\t{$src2, $dst|$dst, $src2}",
275 [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
276 def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
277 "adc{q}\t{$src2, $dst|$dst, $src2}",
278 [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
280 let isTwoAddress = 1 in {
281 def SUB64rr : RI<0x29, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
282 "sub{q}\t{$src2, $dst|$dst, $src2}",
283 [(set GR64:$dst, (sub GR64:$src1, GR64:$src2))]>;
285 def SUB64rm : RI<0x2B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
286 "sub{q}\t{$src2, $dst|$dst, $src2}",
287 [(set GR64:$dst, (sub GR64:$src1, (load addr:$src2)))]>;
289 def SUB64ri32 : RIi32<0x81, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
290 "sub{q}\t{$src2, $dst|$dst, $src2}",
291 [(set GR64:$dst, (sub GR64:$src1, i64immSExt32:$src2))]>;
292 def SUB64ri8 : RIi8<0x83, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
293 "sub{q}\t{$src2, $dst|$dst, $src2}",
294 [(set GR64:$dst, (sub GR64:$src1, i64immSExt8:$src2))]>;
297 def SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
298 "sub{q}\t{$src2, $dst|$dst, $src2}",
299 [(store (sub (load addr:$dst), GR64:$src2), addr:$dst)]>;
300 def SUB64mi32 : RIi32<0x81, MRM5m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
301 "sub{q}\t{$src2, $dst|$dst, $src2}",
302 [(store (sub (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
303 def SUB64mi8 : RIi8<0x83, MRM5m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
304 "sub{q}\t{$src2, $dst|$dst, $src2}",
305 [(store (sub (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
307 let isTwoAddress = 1 in {
308 def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
309 "sbb{q}\t{$src2, $dst|$dst, $src2}",
310 [(set GR64:$dst, (sube GR64:$src1, GR64:$src2))]>;
312 def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
313 "sbb{q}\t{$src2, $dst|$dst, $src2}",
314 [(set GR64:$dst, (sube GR64:$src1, (load addr:$src2)))]>;
316 def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
317 "sbb{q}\t{$src2, $dst|$dst, $src2}",
318 [(set GR64:$dst, (sube GR64:$src1, i64immSExt32:$src2))]>;
319 def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
320 "sbb{q}\t{$src2, $dst|$dst, $src2}",
321 [(set GR64:$dst, (sube GR64:$src1, i64immSExt8:$src2))]>;
324 def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
325 "sbb{q}\t{$src2, $dst|$dst, $src2}",
326 [(store (sube (load addr:$dst), GR64:$src2), addr:$dst)]>;
327 def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
328 "sbb{q}\t{$src2, $dst|$dst, $src2}",
329 [(store (sube (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
330 def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
331 "sbb{q}\t{$src2, $dst|$dst, $src2}",
332 [(store (sube (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
334 // Unsigned multiplication
335 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
337 Imp<[RAX],[RAX,RDX]>; // RAX,RDX = RAX*GR64
338 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
340 Imp<[RAX],[RAX,RDX]>; // RAX,RDX = RAX*[mem64]
342 // Signed multiplication
343 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src),
344 "imul{q}\t$src", []>,
345 Imp<[RAX],[RAX,RDX]>; // RAX,RDX = RAX*GR64
346 def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
347 "imul{q}\t$src", []>,
348 Imp<[RAX],[RAX,RDX]>; // RAX,RDX = RAX*[mem64]
350 let isTwoAddress = 1 in {
351 let isCommutable = 1 in
352 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
353 "imul{q}\t{$src2, $dst|$dst, $src2}",
354 [(set GR64:$dst, (mul GR64:$src1, GR64:$src2))]>, TB;
356 def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
357 "imul{q}\t{$src2, $dst|$dst, $src2}",
358 [(set GR64:$dst, (mul GR64:$src1, (load addr:$src2)))]>, TB;
361 // Suprisingly enough, these are not two address instructions!
362 def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
363 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
364 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
365 [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2))]>;
366 def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
367 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
368 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
369 [(set GR64:$dst, (mul GR64:$src1, i64immSExt8:$src2))]>;
370 def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
371 (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
372 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
373 [(set GR64:$dst, (mul (load addr:$src1), i64immSExt32:$src2))]>;
374 def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
375 (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
376 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
377 [(set GR64:$dst, (mul (load addr:$src1), i64immSExt8:$src2))]>;
379 // Unsigned division / remainder
380 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
381 "div{q}\t$src", []>, Imp<[RAX,RDX],[RAX,RDX]>;
382 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
383 "div{q}\t$src", []>, Imp<[RAX,RDX],[RAX,RDX]>;
385 // Signed division / remainder
386 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
387 "idiv{q}\t$src", []>, Imp<[RAX,RDX],[RAX,RDX]>;
388 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
389 "idiv{q}\t$src", []>, Imp<[RAX,RDX],[RAX,RDX]>;
391 // Unary instructions
392 let CodeSize = 2 in {
393 let isTwoAddress = 1 in
394 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src), "neg{q}\t$dst",
395 [(set GR64:$dst, (ineg GR64:$src))]>;
396 def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
397 [(store (ineg (loadi64 addr:$dst)), addr:$dst)]>;
399 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
400 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src), "inc{q}\t$dst",
401 [(set GR64:$dst, (add GR64:$src, 1))]>;
402 def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
403 [(store (add (loadi64 addr:$dst), 1), addr:$dst)]>;
405 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
406 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src), "dec{q}\t$dst",
407 [(set GR64:$dst, (add GR64:$src, -1))]>;
408 def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
409 [(store (add (loadi64 addr:$dst), -1), addr:$dst)]>;
411 // In 64-bit mode, single byte INC and DEC cannot be encoded.
412 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in {
413 // Can transform into LEA.
414 def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
415 [(set GR16:$dst, (add GR16:$src, 1))]>,
416 OpSize, Requires<[In64BitMode]>;
417 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
418 [(set GR32:$dst, (add GR32:$src, 1))]>,
419 Requires<[In64BitMode]>;
420 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
421 [(set GR16:$dst, (add GR16:$src, -1))]>,
422 OpSize, Requires<[In64BitMode]>;
423 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
424 [(set GR32:$dst, (add GR32:$src, -1))]>,
425 Requires<[In64BitMode]>;
426 } // isConvertibleToThreeAddress
430 // Shift instructions
431 let isTwoAddress = 1 in {
432 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src),
433 "shl{q}\t{%cl, $dst|$dst, %CL}",
434 [(set GR64:$dst, (shl GR64:$src, CL))]>,
436 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
437 "shl{q}\t{$src2, $dst|$dst, $src2}",
438 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
439 def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
443 def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
444 "shl{q}\t{%cl, $dst|$dst, %CL}",
445 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>,
447 def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),
448 "shl{q}\t{$src, $dst|$dst, $src}",
449 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
450 def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
452 [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
454 let isTwoAddress = 1 in {
455 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src),
456 "shr{q}\t{%cl, $dst|$dst, %CL}",
457 [(set GR64:$dst, (srl GR64:$src, CL))]>,
459 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
460 "shr{q}\t{$src2, $dst|$dst, $src2}",
461 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>;
462 def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
464 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))]>;
467 def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
468 "shr{q}\t{%cl, $dst|$dst, %CL}",
469 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>,
471 def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src),
472 "shr{q}\t{$src, $dst|$dst, $src}",
473 [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
474 def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
476 [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
478 let isTwoAddress = 1 in {
479 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src),
480 "sar{q}\t{%cl, $dst|$dst, %CL}",
481 [(set GR64:$dst, (sra GR64:$src, CL))]>, Imp<[CL],[]>;
482 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
483 "sar{q}\t{$src2, $dst|$dst, $src2}",
484 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>;
485 def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
487 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>;
490 def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
491 "sar{q}\t{%cl, $dst|$dst, %CL}",
492 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>,
494 def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src),
495 "sar{q}\t{$src, $dst|$dst, $src}",
496 [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
497 def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
499 [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
501 // Rotate instructions
502 let isTwoAddress = 1 in {
503 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src),
504 "rol{q}\t{%cl, $dst|$dst, %CL}",
505 [(set GR64:$dst, (rotl GR64:$src, CL))]>, Imp<[CL],[]>;
506 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
507 "rol{q}\t{$src2, $dst|$dst, $src2}",
508 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>;
509 def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
511 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>;
514 def ROL64mCL : I<0xD3, MRM0m, (outs), (ins i64mem:$dst),
515 "rol{q}\t{%cl, $dst|$dst, %CL}",
516 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>,
518 def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src),
519 "rol{q}\t{$src, $dst|$dst, $src}",
520 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
521 def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
523 [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
525 let isTwoAddress = 1 in {
526 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src),
527 "ror{q}\t{%cl, $dst|$dst, %CL}",
528 [(set GR64:$dst, (rotr GR64:$src, CL))]>, Imp<[CL],[]>;
529 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
530 "ror{q}\t{$src2, $dst|$dst, $src2}",
531 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>;
532 def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
534 [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))]>;
537 def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
538 "ror{q}\t{%cl, $dst|$dst, %CL}",
539 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>,
541 def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src),
542 "ror{q}\t{$src, $dst|$dst, $src}",
543 [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
544 def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
546 [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
548 // Double shift instructions (generalizations of rotate)
549 let isTwoAddress = 1 in {
550 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
551 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}", []>,
553 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
554 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}", []>,
557 let isCommutable = 1 in { // FIXME: Update X86InstrInfo::commuteInstruction
558 def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
559 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3),
560 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
562 def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
563 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3),
564 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
569 // Temporary hack: there is no patterns associated with these instructions
570 // so we have to tell tblgen that these do not produce results.
571 def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
572 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}", []>,
574 def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
575 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}", []>,
577 def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
578 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
579 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
581 def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
582 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
583 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
586 //===----------------------------------------------------------------------===//
587 // Logical Instructions...
590 let isTwoAddress = 1 in
591 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src), "not{q}\t$dst",
592 [(set GR64:$dst, (not GR64:$src))]>;
593 def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
594 [(store (not (loadi64 addr:$dst)), addr:$dst)]>;
596 let isTwoAddress = 1 in {
597 let isCommutable = 1 in
598 def AND64rr : RI<0x21, MRMDestReg,
599 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
600 "and{q}\t{$src2, $dst|$dst, $src2}",
601 [(set GR64:$dst, (and GR64:$src1, GR64:$src2))]>;
602 def AND64rm : RI<0x23, MRMSrcMem,
603 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
604 "and{q}\t{$src2, $dst|$dst, $src2}",
605 [(set GR64:$dst, (and GR64:$src1, (load addr:$src2)))]>;
606 def AND64ri32 : RIi32<0x81, MRM4r,
607 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
608 "and{q}\t{$src2, $dst|$dst, $src2}",
609 [(set GR64:$dst, (and GR64:$src1, i64immSExt32:$src2))]>;
610 def AND64ri8 : RIi8<0x83, MRM4r,
611 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
612 "and{q}\t{$src2, $dst|$dst, $src2}",
613 [(set GR64:$dst, (and GR64:$src1, i64immSExt8:$src2))]>;
616 def AND64mr : RI<0x21, MRMDestMem,
617 (outs), (ins i64mem:$dst, GR64:$src),
618 "and{q}\t{$src, $dst|$dst, $src}",
619 [(store (and (load addr:$dst), GR64:$src), addr:$dst)]>;
620 def AND64mi32 : RIi32<0x81, MRM4m,
621 (outs), (ins i64mem:$dst, i64i32imm:$src),
622 "and{q}\t{$src, $dst|$dst, $src}",
623 [(store (and (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst)]>;
624 def AND64mi8 : RIi8<0x83, MRM4m,
625 (outs), (ins i64mem:$dst, i64i8imm :$src),
626 "and{q}\t{$src, $dst|$dst, $src}",
627 [(store (and (load addr:$dst), i64immSExt8:$src), addr:$dst)]>;
629 let isTwoAddress = 1 in {
630 let isCommutable = 1 in
631 def OR64rr : RI<0x09, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
632 "or{q}\t{$src2, $dst|$dst, $src2}",
633 [(set GR64:$dst, (or GR64:$src1, GR64:$src2))]>;
634 def OR64rm : RI<0x0B, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
635 "or{q}\t{$src2, $dst|$dst, $src2}",
636 [(set GR64:$dst, (or GR64:$src1, (load addr:$src2)))]>;
637 def OR64ri32 : RIi32<0x81, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
638 "or{q}\t{$src2, $dst|$dst, $src2}",
639 [(set GR64:$dst, (or GR64:$src1, i64immSExt32:$src2))]>;
640 def OR64ri8 : RIi8<0x83, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
641 "or{q}\t{$src2, $dst|$dst, $src2}",
642 [(set GR64:$dst, (or GR64:$src1, i64immSExt8:$src2))]>;
645 def OR64mr : RI<0x09, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
646 "or{q}\t{$src, $dst|$dst, $src}",
647 [(store (or (load addr:$dst), GR64:$src), addr:$dst)]>;
648 def OR64mi32 : RIi32<0x81, MRM1m, (outs), (ins i64mem:$dst, i64i32imm:$src),
649 "or{q}\t{$src, $dst|$dst, $src}",
650 [(store (or (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst)]>;
651 def OR64mi8 : RIi8<0x83, MRM1m, (outs), (ins i64mem:$dst, i64i8imm:$src),
652 "or{q}\t{$src, $dst|$dst, $src}",
653 [(store (or (load addr:$dst), i64immSExt8:$src), addr:$dst)]>;
655 let isTwoAddress = 1 in {
656 let isCommutable = 1 in
657 def XOR64rr : RI<0x31, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
658 "xor{q}\t{$src2, $dst|$dst, $src2}",
659 [(set GR64:$dst, (xor GR64:$src1, GR64:$src2))]>;
660 def XOR64rm : RI<0x33, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
661 "xor{q}\t{$src2, $dst|$dst, $src2}",
662 [(set GR64:$dst, (xor GR64:$src1, (load addr:$src2)))]>;
663 def XOR64ri32 : RIi32<0x81, MRM6r,
664 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
665 "xor{q}\t{$src2, $dst|$dst, $src2}",
666 [(set GR64:$dst, (xor GR64:$src1, i64immSExt32:$src2))]>;
667 def XOR64ri8 : RIi8<0x83, MRM6r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
668 "xor{q}\t{$src2, $dst|$dst, $src2}",
669 [(set GR64:$dst, (xor GR64:$src1, i64immSExt8:$src2))]>;
672 def XOR64mr : RI<0x31, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
673 "xor{q}\t{$src, $dst|$dst, $src}",
674 [(store (xor (load addr:$dst), GR64:$src), addr:$dst)]>;
675 def XOR64mi32 : RIi32<0x81, MRM6m, (outs), (ins i64mem:$dst, i64i32imm:$src),
676 "xor{q}\t{$src, $dst|$dst, $src}",
677 [(store (xor (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst)]>;
678 def XOR64mi8 : RIi8<0x83, MRM6m, (outs), (ins i64mem:$dst, i64i8imm :$src),
679 "xor{q}\t{$src, $dst|$dst, $src}",
680 [(store (xor (load addr:$dst), i64immSExt8:$src), addr:$dst)]>;
682 //===----------------------------------------------------------------------===//
683 // Comparison Instructions...
686 // Integer comparison
687 let isCommutable = 1 in
688 def TEST64rr : RI<0x85, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
689 "test{q}\t{$src2, $src1|$src1, $src2}",
690 [(X86cmp (and GR64:$src1, GR64:$src2), 0)]>;
691 def TEST64rm : RI<0x85, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
692 "test{q}\t{$src2, $src1|$src1, $src2}",
693 [(X86cmp (and GR64:$src1, (loadi64 addr:$src2)), 0)]>;
694 def TEST64ri32 : RIi32<0xF7, MRM0r, (outs), (ins GR64:$src1, i64i32imm:$src2),
695 "test{q}\t{$src2, $src1|$src1, $src2}",
696 [(X86cmp (and GR64:$src1, i64immSExt32:$src2), 0)]>;
697 def TEST64mi32 : RIi32<0xF7, MRM0m, (outs), (ins i64mem:$src1, i64i32imm:$src2),
698 "test{q}\t{$src2, $src1|$src1, $src2}",
699 [(X86cmp (and (loadi64 addr:$src1), i64immSExt32:$src2), 0)]>;
701 def CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
702 "cmp{q}\t{$src2, $src1|$src1, $src2}",
703 [(X86cmp GR64:$src1, GR64:$src2)]>;
704 def CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
705 "cmp{q}\t{$src2, $src1|$src1, $src2}",
706 [(X86cmp (loadi64 addr:$src1), GR64:$src2)]>;
707 def CMP64rm : RI<0x3B, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
708 "cmp{q}\t{$src2, $src1|$src1, $src2}",
709 [(X86cmp GR64:$src1, (loadi64 addr:$src2))]>;
710 def CMP64ri32 : RIi32<0x81, MRM7r, (outs), (ins GR64:$src1, i64i32imm:$src2),
711 "cmp{q}\t{$src2, $src1|$src1, $src2}",
712 [(X86cmp GR64:$src1, i64immSExt32:$src2)]>;
713 def CMP64mi32 : RIi32<0x81, MRM7m, (outs), (ins i64mem:$src1, i64i32imm:$src2),
714 "cmp{q}\t{$src2, $src1|$src1, $src2}",
715 [(X86cmp (loadi64 addr:$src1), i64immSExt32:$src2)]>;
716 def CMP64mi8 : RIi8<0x83, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
717 "cmp{q}\t{$src2, $src1|$src1, $src2}",
718 [(X86cmp (loadi64 addr:$src1), i64immSExt8:$src2)]>;
719 def CMP64ri8 : RIi8<0x83, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
720 "cmp{q}\t{$src2, $src1|$src1, $src2}",
721 [(X86cmp GR64:$src1, i64immSExt8:$src2)]>;
724 let isTwoAddress = 1 in {
725 def CMOVB64rr : RI<0x42, MRMSrcReg, // if <u, GR64 = GR64
726 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
727 "cmovb\t{$src2, $dst|$dst, $src2}",
728 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
730 def CMOVB64rm : RI<0x42, MRMSrcMem, // if <u, GR64 = [mem64]
731 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
732 "cmovb\t{$src2, $dst|$dst, $src2}",
733 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
735 def CMOVAE64rr: RI<0x43, MRMSrcReg, // if >=u, GR64 = GR64
736 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
737 "cmovae\t{$src2, $dst|$dst, $src2}",
738 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
740 def CMOVAE64rm: RI<0x43, MRMSrcMem, // if >=u, GR64 = [mem64]
741 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
742 "cmovae\t{$src2, $dst|$dst, $src2}",
743 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
745 def CMOVE64rr : RI<0x44, MRMSrcReg, // if ==, GR64 = GR64
746 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
747 "cmove\t{$src2, $dst|$dst, $src2}",
748 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
750 def CMOVE64rm : RI<0x44, MRMSrcMem, // if ==, GR64 = [mem64]
751 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
752 "cmove\t{$src2, $dst|$dst, $src2}",
753 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
755 def CMOVNE64rr: RI<0x45, MRMSrcReg, // if !=, GR64 = GR64
756 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
757 "cmovne\t{$src2, $dst|$dst, $src2}",
758 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
760 def CMOVNE64rm: RI<0x45, MRMSrcMem, // if !=, GR64 = [mem64]
761 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
762 "cmovne\t{$src2, $dst|$dst, $src2}",
763 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
765 def CMOVBE64rr: RI<0x46, MRMSrcReg, // if <=u, GR64 = GR64
766 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
767 "cmovbe\t{$src2, $dst|$dst, $src2}",
768 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
770 def CMOVBE64rm: RI<0x46, MRMSrcMem, // if <=u, GR64 = [mem64]
771 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
772 "cmovbe\t{$src2, $dst|$dst, $src2}",
773 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
775 def CMOVA64rr : RI<0x47, MRMSrcReg, // if >u, GR64 = GR64
776 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
777 "cmova\t{$src2, $dst|$dst, $src2}",
778 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
780 def CMOVA64rm : RI<0x47, MRMSrcMem, // if >u, GR64 = [mem64]
781 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
782 "cmova\t{$src2, $dst|$dst, $src2}",
783 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
785 def CMOVL64rr : RI<0x4C, MRMSrcReg, // if <s, GR64 = GR64
786 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
787 "cmovl\t{$src2, $dst|$dst, $src2}",
788 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
790 def CMOVL64rm : RI<0x4C, MRMSrcMem, // if <s, GR64 = [mem64]
791 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
792 "cmovl\t{$src2, $dst|$dst, $src2}",
793 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
795 def CMOVGE64rr: RI<0x4D, MRMSrcReg, // if >=s, GR64 = GR64
796 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
797 "cmovge\t{$src2, $dst|$dst, $src2}",
798 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
800 def CMOVGE64rm: RI<0x4D, MRMSrcMem, // if >=s, GR64 = [mem64]
801 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
802 "cmovge\t{$src2, $dst|$dst, $src2}",
803 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
805 def CMOVLE64rr: RI<0x4E, MRMSrcReg, // if <=s, GR64 = GR64
806 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
807 "cmovle\t{$src2, $dst|$dst, $src2}",
808 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
810 def CMOVLE64rm: RI<0x4E, MRMSrcMem, // if <=s, GR64 = [mem64]
811 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
812 "cmovle\t{$src2, $dst|$dst, $src2}",
813 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
815 def CMOVG64rr : RI<0x4F, MRMSrcReg, // if >s, GR64 = GR64
816 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
817 "cmovg\t{$src2, $dst|$dst, $src2}",
818 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
820 def CMOVG64rm : RI<0x4F, MRMSrcMem, // if >s, GR64 = [mem64]
821 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
822 "cmovg\t{$src2, $dst|$dst, $src2}",
823 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
825 def CMOVS64rr : RI<0x48, MRMSrcReg, // if signed, GR64 = GR64
826 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
827 "cmovs\t{$src2, $dst|$dst, $src2}",
828 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
830 def CMOVS64rm : RI<0x48, MRMSrcMem, // if signed, GR64 = [mem64]
831 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
832 "cmovs\t{$src2, $dst|$dst, $src2}",
833 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
835 def CMOVNS64rr: RI<0x49, MRMSrcReg, // if !signed, GR64 = GR64
836 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
837 "cmovns\t{$src2, $dst|$dst, $src2}",
838 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
840 def CMOVNS64rm: RI<0x49, MRMSrcMem, // if !signed, GR64 = [mem64]
841 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
842 "cmovns\t{$src2, $dst|$dst, $src2}",
843 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
845 def CMOVP64rr : RI<0x4A, MRMSrcReg, // if parity, GR64 = GR64
846 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
847 "cmovp\t{$src2, $dst|$dst, $src2}",
848 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
850 def CMOVP64rm : RI<0x4A, MRMSrcMem, // if parity, GR64 = [mem64]
851 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
852 "cmovp\t{$src2, $dst|$dst, $src2}",
853 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
855 def CMOVNP64rr : RI<0x4B, MRMSrcReg, // if !parity, GR64 = GR64
856 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
857 "cmovnp\t{$src2, $dst|$dst, $src2}",
858 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
860 def CMOVNP64rm : RI<0x4B, MRMSrcMem, // if !parity, GR64 = [mem64]
861 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
862 "cmovnp\t{$src2, $dst|$dst, $src2}",
863 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
867 //===----------------------------------------------------------------------===//
868 // Conversion Instructions...
872 def Int_CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
873 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
875 (int_x86_sse2_cvtsd2si64 VR128:$src))]>;
876 def Int_CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src),
877 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
878 [(set GR64:$dst, (int_x86_sse2_cvtsd2si64
879 (load addr:$src)))]>;
880 def CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
881 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
882 [(set GR64:$dst, (fp_to_sint FR64:$src))]>;
883 def CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f64mem:$src),
884 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
885 [(set GR64:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
886 def Int_CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
887 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
889 (int_x86_sse2_cvttsd2si64 VR128:$src))]>;
890 def Int_CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src),
891 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
893 (int_x86_sse2_cvttsd2si64
894 (load addr:$src)))]>;
897 def CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
898 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
899 [(set FR64:$dst, (sint_to_fp GR64:$src))]>;
900 def CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
901 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
902 [(set FR64:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
903 let isTwoAddress = 1 in {
904 def Int_CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg,
905 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
906 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
908 (int_x86_sse2_cvtsi642sd VR128:$src1,
910 def Int_CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem,
911 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
912 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
914 (int_x86_sse2_cvtsi642sd VR128:$src1,
915 (loadi64 addr:$src2)))]>;
919 def CVTSI2SS64rr: RSSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR64:$src),
920 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
921 [(set FR32:$dst, (sint_to_fp GR64:$src))]>;
922 def CVTSI2SS64rm: RSSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i64mem:$src),
923 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
924 [(set FR32:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
925 let isTwoAddress = 1 in {
926 def Int_CVTSI2SS64rr: RSSI<0x2A, MRMSrcReg,
927 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
928 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
929 []>; // TODO: add intrinsic
930 def Int_CVTSI2SS64rm: RSSI<0x2A, MRMSrcMem,
931 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
932 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
933 []>; // TODO: add intrinsic
937 def Int_CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
938 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
940 (int_x86_sse_cvtss2si64 VR128:$src))]>;
941 def Int_CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
942 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
943 [(set GR64:$dst, (int_x86_sse_cvtss2si64
944 (load addr:$src)))]>;
945 def CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
946 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
947 [(set GR64:$dst, (fp_to_sint FR32:$src))]>;
948 def CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
949 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
950 [(set GR64:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
951 def Int_CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
952 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
954 (int_x86_sse_cvttss2si64 VR128:$src))]>;
955 def Int_CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
956 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
958 (int_x86_sse_cvttss2si64 (load addr:$src)))]>;
960 let isTwoAddress = 1 in {
961 def Int_CVTSI642SSrr : RSSI<0x2A, MRMSrcReg,
962 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
963 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
965 (int_x86_sse_cvtsi642ss VR128:$src1,
967 def Int_CVTSI642SSrm : RSSI<0x2A, MRMSrcMem,
968 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
969 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
971 (int_x86_sse_cvtsi642ss VR128:$src1,
972 (loadi64 addr:$src2)))]>;
975 //===----------------------------------------------------------------------===//
976 // Alias Instructions
977 //===----------------------------------------------------------------------===//
980 // TODO: Remove this after proper i32 -> i64 zext support.
981 def PsMOVZX64rr32: I<0x89, MRMDestReg, (outs GR64:$dst), (ins GR32:$src),
982 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
983 [(set GR64:$dst, (zext GR32:$src))]>;
984 def PsMOVZX64rm32: I<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
985 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
986 [(set GR64:$dst, (zextloadi64i32 addr:$src))]>;
989 // Alias instructions that map movr0 to xor.
990 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
991 // FIXME: AddedComplexity gives MOV64r0 a higher priority than MOV64ri32. Remove
992 // when we have a better way to specify isel priority.
993 let AddedComplexity = 1 in
994 def MOV64r0 : RI<0x31, MRMInitReg, (outs GR64:$dst), (ins),
995 "xor{q}\t$dst, $dst",
996 [(set GR64:$dst, 0)]>;
998 // Materialize i64 constant where top 32-bits are zero.
999 let AddedComplexity = 1 in
1000 def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
1001 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
1002 [(set GR64:$dst, i64immZExt32:$src)]>;
1004 //===----------------------------------------------------------------------===//
1005 // Non-Instruction Patterns
1006 //===----------------------------------------------------------------------===//
1008 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
1009 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1010 (MOV64ri tconstpool :$dst)>, Requires<[NotSmallCode]>;
1011 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1012 (MOV64ri tjumptable :$dst)>, Requires<[NotSmallCode]>;
1013 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1014 (MOV64ri tglobaladdr :$dst)>, Requires<[NotSmallCode]>;
1015 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1016 (MOV64ri texternalsym:$dst)>, Requires<[NotSmallCode]>;
1018 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
1019 (MOV64mi32 addr:$dst, tconstpool:$src)>,
1020 Requires<[SmallCode, HasLow4G, IsStatic]>;
1021 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
1022 (MOV64mi32 addr:$dst, tjumptable:$src)>,
1023 Requires<[SmallCode, HasLow4G, IsStatic]>;
1024 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
1025 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
1026 Requires<[SmallCode, HasLow4G, IsStatic]>;
1027 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
1028 (MOV64mi32 addr:$dst, texternalsym:$src)>,
1029 Requires<[SmallCode, HasLow4G, IsStatic]>;
1032 // Direct PC relative function call for small code model. 32-bit displacement
1033 // sign extended to 64-bit.
1034 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1035 (CALL64pcrel32 tglobaladdr:$dst)>;
1036 def : Pat<(X86call (i64 texternalsym:$dst)),
1037 (CALL64pcrel32 texternalsym:$dst)>;
1039 def : Pat<(X86tailcall (i64 tglobaladdr:$dst)),
1040 (CALL64pcrel32 tglobaladdr:$dst)>;
1041 def : Pat<(X86tailcall (i64 texternalsym:$dst)),
1042 (CALL64pcrel32 texternalsym:$dst)>;
1044 def : Pat<(X86tailcall GR64:$dst),
1045 (CALL64r GR64:$dst)>;
1047 // {s|z}extload bool -> {s|z}extload byte
1048 def : Pat<(sextloadi64i1 addr:$src), (MOVSX64rm8 addr:$src)>;
1049 def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1052 def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1053 def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>;
1054 def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
1055 def : Pat<(extloadi64i32 addr:$src), (PsMOVZX64rm32 addr:$src)>;
1058 def : Pat<(i64 (anyext GR8 :$src)), (MOVZX64rr8 GR8 :$src)>;
1059 def : Pat<(i64 (anyext GR16:$src)), (MOVZX64rr16 GR16:$src)>;
1060 def : Pat<(i64 (anyext GR32:$src)), (PsMOVZX64rr32 GR32:$src)>;
1061 def : Pat<(i64 (anyext (loadi8 addr:$src))), (MOVZX64rm8 addr:$src)>;
1062 def : Pat<(i64 (anyext (loadi16 addr:$src))), (MOVZX64rm16 addr:$src)>;
1063 def : Pat<(i64 (anyext (loadi32 addr:$src))), (PsMOVZX64rm32 addr:$src)>;
1065 //===----------------------------------------------------------------------===//
1067 //===----------------------------------------------------------------------===//
1069 // (shl x, 1) ==> (add x, x)
1070 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1072 // (or (x >> c) | (y << (64 - c))) ==> (shrd64 x, y, c)
1073 def : Pat<(or (srl GR64:$src1, CL:$amt),
1074 (shl GR64:$src2, (sub 64, CL:$amt))),
1075 (SHRD64rrCL GR64:$src1, GR64:$src2)>;
1077 def : Pat<(store (or (srl (loadi64 addr:$dst), CL:$amt),
1078 (shl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
1079 (SHRD64mrCL addr:$dst, GR64:$src2)>;
1081 // (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
1082 def : Pat<(or (shl GR64:$src1, CL:$amt),
1083 (srl GR64:$src2, (sub 64, CL:$amt))),
1084 (SHLD64rrCL GR64:$src1, GR64:$src2)>;
1086 def : Pat<(store (or (shl (loadi64 addr:$dst), CL:$amt),
1087 (srl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
1088 (SHLD64mrCL addr:$dst, GR64:$src2)>;
1090 // X86 specific add which produces a flag.
1091 def : Pat<(addc GR64:$src1, GR64:$src2),
1092 (ADD64rr GR64:$src1, GR64:$src2)>;
1093 def : Pat<(addc GR64:$src1, (load addr:$src2)),
1094 (ADD64rm GR64:$src1, addr:$src2)>;
1095 def : Pat<(addc GR64:$src1, i64immSExt32:$src2),
1096 (ADD64ri32 GR64:$src1, imm:$src2)>;
1097 def : Pat<(addc GR64:$src1, i64immSExt8:$src2),
1098 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1100 def : Pat<(subc GR64:$src1, GR64:$src2),
1101 (SUB64rr GR64:$src1, GR64:$src2)>;
1102 def : Pat<(subc GR64:$src1, (load addr:$src2)),
1103 (SUB64rm GR64:$src1, addr:$src2)>;
1104 def : Pat<(subc GR64:$src1, imm:$src2),
1105 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1106 def : Pat<(subc GR64:$src1, i64immSExt8:$src2),
1107 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1110 //===----------------------------------------------------------------------===//
1111 // X86-64 SSE Instructions
1112 //===----------------------------------------------------------------------===//
1114 // Move instructions...
1116 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
1117 "mov{d|q}\t{$src, $dst|$dst, $src}",
1119 (v2i64 (scalar_to_vector GR64:$src)))]>;
1120 def MOV64toPQIrm : RPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1121 "mov{d|q}\t{$src, $dst|$dst, $src}",
1123 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>;
1125 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
1126 "mov{d|q}\t{$src, $dst|$dst, $src}",
1127 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
1129 def MOVPQIto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
1130 "mov{d|q}\t{$src, $dst|$dst, $src}",
1131 [(store (i64 (vector_extract (v2i64 VR128:$src),
1132 (iPTR 0))), addr:$dst)]>;
1134 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1135 "mov{d|q}\t{$src, $dst|$dst, $src}",
1136 [(set FR64:$dst, (bitconvert GR64:$src))]>;
1137 def MOV64toSDrm : RPDI<0x6E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
1138 "mov{d|q}\t{$src, $dst|$dst, $src}",
1139 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
1141 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1142 "mov{d|q}\t{$src, $dst|$dst, $src}",
1143 [(set GR64:$dst, (bitconvert FR64:$src))]>;
1144 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1145 "mov{d|q}\t{$src, $dst|$dst, $src}",
1146 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;