1 //====- X86InstrMMX.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 MMX instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 // All instructions that use MMX should be in this file, even if they also use
17 //===----------------------------------------------------------------------===//
19 //===----------------------------------------------------------------------===//
21 //===----------------------------------------------------------------------===//
23 let Constraints = "$src1 = $dst" in {
24 // MMXI_binop_rm - Simple MMX binary operator based on llvm operator.
25 multiclass MMXI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
26 ValueType OpVT, bit Commutable = 0> {
27 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
28 (ins VR64:$src1, VR64:$src2),
29 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
30 [(set VR64:$dst, (OpVT (OpNode VR64:$src1, VR64:$src2)))]> {
31 let isCommutable = Commutable;
33 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
34 (ins VR64:$src1, i64mem:$src2),
35 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
36 [(set VR64:$dst, (OpVT (OpNode VR64:$src1,
38 (load_mmx addr:$src2)))))]>;
41 // MMXI_binop_rm_int - Simple MMX binary operator based on intrinsic, with a
42 // different name for the generated instructions than MMXI_binop_rm uses.
43 // Thus int and rm can coexist for different implementations of the same
44 // instruction. This is temporary during transition to intrinsic-only
45 // implementation; eventually the non-intrinsic forms will go away. When
46 // When this is cleaned up, remove the FIXME from X86RecognizableInstr.cpp.
47 multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
49 def irr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
50 (ins VR64:$src1, VR64:$src2),
51 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
52 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]> {
53 let isCommutable = Commutable;
55 def irm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
56 (ins VR64:$src1, i64mem:$src2),
57 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
58 [(set VR64:$dst, (IntId VR64:$src1,
59 (bitconvert (load_mmx addr:$src2))))]>;
62 // MMXI_binop_rm_v1i64 - Simple MMX binary operator whose type is v1i64.
64 // FIXME: we could eliminate this and use MMXI_binop_rm instead if tblgen knew
65 // to collapse (bitconvert VT to VT) into its operand.
67 multiclass MMXI_binop_rm_v1i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
69 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
70 (ins VR64:$src1, VR64:$src2),
71 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
72 [(set VR64:$dst, (v1i64 (OpNode VR64:$src1, VR64:$src2)))]> {
73 let isCommutable = Commutable;
75 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
76 (ins VR64:$src1, i64mem:$src2),
77 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
79 (OpNode VR64:$src1,(load_mmx addr:$src2)))]>;
82 multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
83 string OpcodeStr, Intrinsic IntId,
85 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
86 (ins VR64:$src1, VR64:$src2),
87 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
88 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>;
89 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
90 (ins VR64:$src1, i64mem:$src2),
91 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
92 [(set VR64:$dst, (IntId VR64:$src1,
93 (bitconvert (load_mmx addr:$src2))))]>;
94 def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst),
95 (ins VR64:$src1, i32i8imm:$src2),
96 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
97 [(set VR64:$dst, (IntId2 VR64:$src1, (i32 imm:$src2)))]>;
101 /// Unary MMX instructions requiring SSSE3.
102 multiclass SS3I_unop_rm_int_mm<bits<8> opc, string OpcodeStr,
103 PatFrag mem_frag64, Intrinsic IntId64> {
104 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
105 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
106 [(set VR64:$dst, (IntId64 VR64:$src))]>;
108 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
109 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
111 (IntId64 (bitconvert (mem_frag64 addr:$src))))]>;
114 /// Binary MMX instructions requiring SSSE3.
115 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
116 multiclass SS3I_binop_rm_int_mm<bits<8> opc, string OpcodeStr,
117 PatFrag mem_frag64, Intrinsic IntId64> {
118 let isCommutable = 0 in
119 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
120 (ins VR64:$src1, VR64:$src2),
121 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
122 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]>;
123 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
124 (ins VR64:$src1, i64mem:$src2),
125 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
128 (bitconvert (mem_frag64 addr:$src2))))]>;
132 /// PALIGN MMX instructions (require SSSE3).
133 multiclass ssse3_palign_mm<string asm, Intrinsic IntId> {
134 def R64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
135 (ins VR64:$src1, VR64:$src2, i8imm:$src3),
136 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>;
137 def R64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
138 (ins VR64:$src1, i64mem:$src2, i8imm:$src3),
139 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>;
140 def R64irr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
141 (ins VR64:$src1, VR64:$src2, i8imm:$src3),
142 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
143 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2, (i8 imm:$src3)))]>;
144 def R64irm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
145 (ins VR64:$src1, i64mem:$src2, i8imm:$src3),
146 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
147 [(set VR64:$dst, (IntId VR64:$src1,
148 (bitconvert (load_mmx addr:$src2)), (i8 imm:$src3)))]>;
151 multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
152 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
153 string asm, Domain d> {
154 def irr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
155 [(set DstRC:$dst, (Int SrcRC:$src))], d>;
156 def irm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
157 [(set DstRC:$dst, (Int (ld_frag addr:$src)))], d>;
160 multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC,
161 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
162 PatFrag ld_frag, string asm, Domain d> {
163 def irr : PI<opc, MRMSrcReg, (outs DstRC:$dst),(ins DstRC:$src1, SrcRC:$src2),
164 asm, [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))], d>;
165 def irm : PI<opc, MRMSrcMem, (outs DstRC:$dst),
166 (ins DstRC:$src1, x86memop:$src2), asm,
167 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))], d>;
170 //===----------------------------------------------------------------------===//
171 // MMX EMMS & FEMMS Instructions
172 //===----------------------------------------------------------------------===//
174 def MMX_EMMS : MMXI<0x77, RawFrm, (outs), (ins), "emms",
175 [(int_x86_mmx_emms)]>;
176 def MMX_FEMMS : MMXI<0x0E, RawFrm, (outs), (ins), "femms",
177 [(int_x86_mmx_femms)]>;
179 //===----------------------------------------------------------------------===//
180 // MMX Scalar Instructions
181 //===----------------------------------------------------------------------===//
183 // Data Transfer Instructions
184 def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
185 "movd\t{$src, $dst|$dst, $src}",
187 (v2i32 (scalar_to_vector GR32:$src)))]>;
188 let canFoldAsLoad = 1, isReMaterializable = 1 in
189 def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
190 "movd\t{$src, $dst|$dst, $src}",
192 (v2i32 (scalar_to_vector (loadi32 addr:$src))))]>;
194 def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src),
195 "movd\t{$src, $dst|$dst, $src}", []>;
196 def MMX_MOVD64grr : MMXI<0x7E, MRMDestReg, (outs), (ins GR32:$dst, VR64:$src),
197 "movd\t{$src, $dst|$dst, $src}", []>;
199 let neverHasSideEffects = 1 in
200 def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
201 "movd\t{$src, $dst|$dst, $src}",
204 let neverHasSideEffects = 1 in
205 // These are 64 bit moves, but since the OS X assembler doesn't
206 // recognize a register-register movq, we write them as
208 def MMX_MOVD64from64rr : MMXRI<0x7E, MRMDestReg,
209 (outs GR64:$dst), (ins VR64:$src),
210 "movd\t{$src, $dst|$dst, $src}", []>;
211 def MMX_MOVD64rrv164 : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
212 "movd\t{$src, $dst|$dst, $src}",
214 (v1i64 (scalar_to_vector GR64:$src)))]>;
216 let neverHasSideEffects = 1 in
217 def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
218 "movq\t{$src, $dst|$dst, $src}", []>;
219 let canFoldAsLoad = 1, isReMaterializable = 1 in
220 def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
221 "movq\t{$src, $dst|$dst, $src}",
222 [(set VR64:$dst, (load_mmx addr:$src))]>;
223 def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
224 "movq\t{$src, $dst|$dst, $src}",
225 [(store (v1i64 VR64:$src), addr:$dst)]>;
227 def MMX_MOVDQ2Qrr : SDIi8<0xD6, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
228 "movdq2q\t{$src, $dst|$dst, $src}",
231 (i64 (vector_extract (v2i64 VR128:$src),
234 def MMX_MOVQ2DQrr : SSDIi8<0xD6, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
235 "movq2dq\t{$src, $dst|$dst, $src}",
238 (v2i64 (scalar_to_vector
239 (i64 (bitconvert (v1i64 VR64:$src)))))))]>;
241 let neverHasSideEffects = 1 in
242 def MMX_MOVQ2FR64rr: SSDIi8<0xD6, MRMSrcReg, (outs FR64:$dst), (ins VR64:$src),
243 "movq2dq\t{$src, $dst|$dst, $src}", []>;
245 def MMX_MOVFR642Qrr: SDIi8<0xD6, MRMSrcReg, (outs VR64:$dst), (ins FR64:$src),
246 "movdq2q\t{$src, $dst|$dst, $src}", []>;
248 def MMX_MOVNTQmr : MMXI<0xE7, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
249 "movntq\t{$src, $dst|$dst, $src}",
250 [(int_x86_mmx_movnt_dq addr:$dst, VR64:$src)]>;
252 let AddedComplexity = 15 in
253 // movd to MMX register zero-extends
254 def MMX_MOVZDI2PDIrr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
255 "movd\t{$src, $dst|$dst, $src}",
257 (v2i32 (X86vzmovl (v2i32 (scalar_to_vector GR32:$src)))))]>;
258 let AddedComplexity = 20 in
259 def MMX_MOVZDI2PDIrm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst),
261 "movd\t{$src, $dst|$dst, $src}",
263 (v2i32 (X86vzmovl (v2i32
264 (scalar_to_vector (loadi32 addr:$src))))))]>;
266 // Arithmetic Instructions
267 defm MMX_PABSB : SS3I_unop_rm_int_mm<0x1C, "pabsb", memopv8i8,
268 int_x86_ssse3_pabs_b>;
269 defm MMX_PABSW : SS3I_unop_rm_int_mm<0x1D, "pabsw", memopv4i16,
270 int_x86_ssse3_pabs_w>;
271 defm MMX_PABSD : SS3I_unop_rm_int_mm<0x1E, "pabsd", memopv2i32,
272 int_x86_ssse3_pabs_d>;
274 defm MMX_PADDB : MMXI_binop_rm<0xFC, "paddb", add, v8i8, 1>,
275 MMXI_binop_rm_int<0xFC, "paddb", int_x86_mmx_padd_b, 1>;
276 defm MMX_PADDW : MMXI_binop_rm<0xFD, "paddw", add, v4i16, 1>,
277 MMXI_binop_rm_int<0xFD, "paddw", int_x86_mmx_padd_w, 1>;
278 defm MMX_PADDD : MMXI_binop_rm<0xFE, "paddd", add, v2i32, 1>,
279 MMXI_binop_rm_int<0xFE, "paddd", int_x86_mmx_padd_d, 1>;
280 defm MMX_PADDQ : MMXI_binop_rm<0xD4, "paddq", add, v1i64, 1>,
281 MMXI_binop_rm_int<0xD4, "paddq", int_x86_mmx_padd_q, 1>;
282 defm MMX_PADDSB : MMXI_binop_rm_int<0xEC, "paddsb" , int_x86_mmx_padds_b, 1>;
283 defm MMX_PADDSW : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w, 1>;
285 defm MMX_PADDUSB : MMXI_binop_rm_int<0xDC, "paddusb", int_x86_mmx_paddus_b, 1>;
286 defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w, 1>;
288 defm MMX_PHADDW : SS3I_binop_rm_int_mm<0x01, "phaddw", memopv4i16,
289 int_x86_ssse3_phadd_w>;
290 defm MMX_PHADD : SS3I_binop_rm_int_mm<0x02, "phaddd", memopv2i32,
291 int_x86_ssse3_phadd_d>;
292 defm MMX_PHADDSW : SS3I_binop_rm_int_mm<0x03, "phaddsw", memopv4i16,
293 int_x86_ssse3_phadd_sw>;
297 defm MMX_PSUBB : MMXI_binop_rm<0xF8, "psubb", sub, v8i8>,
298 MMXI_binop_rm_int<0xF8, "psubb", int_x86_mmx_psub_b>;
299 defm MMX_PSUBW : MMXI_binop_rm<0xF9, "psubw", sub, v4i16>,
300 MMXI_binop_rm_int<0xF9, "psubw", int_x86_mmx_psub_w>;
301 defm MMX_PSUBD : MMXI_binop_rm<0xFA, "psubd", sub, v2i32>,
302 MMXI_binop_rm_int<0xFA, "psubd", int_x86_mmx_psub_d>;
303 defm MMX_PSUBQ : MMXI_binop_rm<0xFB, "psubq", sub, v1i64>,
304 MMXI_binop_rm_int<0xFB, "psubq", int_x86_mmx_psub_q>;
306 defm MMX_PSUBSB : MMXI_binop_rm_int<0xE8, "psubsb" , int_x86_mmx_psubs_b>;
307 defm MMX_PSUBSW : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w>;
309 defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b>;
310 defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w>;
312 defm MMX_PHSUBW : SS3I_binop_rm_int_mm<0x05, "phsubw", memopv4i16,
313 int_x86_ssse3_phsub_w>;
314 defm MMX_PHSUBD : SS3I_binop_rm_int_mm<0x06, "phsubd", memopv2i32,
315 int_x86_ssse3_phsub_d>;
316 defm MMX_PHSUBSW : SS3I_binop_rm_int_mm<0x07, "phsubsw", memopv4i16,
317 int_x86_ssse3_phsub_sw>;
320 defm MMX_PMULLW : MMXI_binop_rm<0xD5, "pmullw", mul, v4i16, 1>,
321 MMXI_binop_rm_int<0xD5, "pmullw", int_x86_mmx_pmull_w, 1>;
323 defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw", int_x86_mmx_pmulh_w, 1>;
324 defm MMX_PMULHUW : MMXI_binop_rm_int<0xE4, "pmulhuw", int_x86_mmx_pmulhu_w, 1>;
325 defm MMX_PMULUDQ : MMXI_binop_rm_int<0xF4, "pmuludq", int_x86_mmx_pmulu_dq, 1>;
326 let isCommutable = 1 in
327 defm MMX_PMULHRSW : SS3I_binop_rm_int_mm<0x0B, "pmulhrsw", memopv4i16,
328 int_x86_ssse3_pmul_hr_sw>;
331 defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd, 1>;
333 defm MMX_PMADDUBSW : SS3I_binop_rm_int_mm<0x04, "pmaddubsw", memopv8i8,
334 int_x86_ssse3_pmadd_ub_sw>;
335 defm MMX_PAVGB : MMXI_binop_rm_int<0xE0, "pavgb", int_x86_mmx_pavg_b, 1>;
336 defm MMX_PAVGW : MMXI_binop_rm_int<0xE3, "pavgw", int_x86_mmx_pavg_w, 1>;
338 defm MMX_PMINUB : MMXI_binop_rm_int<0xDA, "pminub", int_x86_mmx_pminu_b, 1>;
339 defm MMX_PMINSW : MMXI_binop_rm_int<0xEA, "pminsw", int_x86_mmx_pmins_w, 1>;
341 defm MMX_PMAXUB : MMXI_binop_rm_int<0xDE, "pmaxub", int_x86_mmx_pmaxu_b, 1>;
342 defm MMX_PMAXSW : MMXI_binop_rm_int<0xEE, "pmaxsw", int_x86_mmx_pmaxs_w, 1>;
344 defm MMX_PSADBW : MMXI_binop_rm_int<0xF6, "psadbw", int_x86_mmx_psad_bw, 1>;
346 defm MMX_PSIGNB : SS3I_binop_rm_int_mm<0x08, "psignb", memopv8i8,
347 int_x86_ssse3_psign_b>;
348 defm MMX_PSIGNW : SS3I_binop_rm_int_mm<0x09, "psignw", memopv4i16,
349 int_x86_ssse3_psign_w>;
350 defm MMX_PSIGND : SS3I_binop_rm_int_mm<0x0A, "psignd", memopv2i32,
351 int_x86_ssse3_psign_d>;
352 let Constraints = "$src1 = $dst" in
353 defm MMX_PALIGN : ssse3_palign_mm<"palignr", int_x86_mmx_palignr_b>;
355 let AddedComplexity = 5 in {
357 def : Pat<(v1i64 (palign:$src3 VR64:$src1, VR64:$src2)),
358 (MMX_PALIGNR64rr VR64:$src2, VR64:$src1,
359 (SHUFFLE_get_palign_imm VR64:$src3))>,
360 Requires<[HasSSSE3]>;
361 def : Pat<(v2i32 (palign:$src3 VR64:$src1, VR64:$src2)),
362 (MMX_PALIGNR64rr VR64:$src2, VR64:$src1,
363 (SHUFFLE_get_palign_imm VR64:$src3))>,
364 Requires<[HasSSSE3]>;
365 def : Pat<(v4i16 (palign:$src3 VR64:$src1, VR64:$src2)),
366 (MMX_PALIGNR64rr VR64:$src2, VR64:$src1,
367 (SHUFFLE_get_palign_imm VR64:$src3))>,
368 Requires<[HasSSSE3]>;
369 def : Pat<(v8i8 (palign:$src3 VR64:$src1, VR64:$src2)),
370 (MMX_PALIGNR64rr VR64:$src2, VR64:$src1,
371 (SHUFFLE_get_palign_imm VR64:$src3))>,
372 Requires<[HasSSSE3]>;
375 // Logical Instructions
376 defm MMX_PAND : MMXI_binop_rm_v1i64<0xDB, "pand", and, 1>,
377 MMXI_binop_rm_int<0xDB, "pand", int_x86_mmx_pand, 1>;
378 defm MMX_POR : MMXI_binop_rm_v1i64<0xEB, "por" , or, 1>,
379 MMXI_binop_rm_int<0xEB, "por" , int_x86_mmx_por, 1>;
380 defm MMX_PXOR : MMXI_binop_rm_v1i64<0xEF, "pxor", xor, 1>,
381 MMXI_binop_rm_int<0xEF, "pxor", int_x86_mmx_pxor, 1>;
382 defm MMX_PANDN : MMXI_binop_rm_int<0xDF, "pandn", int_x86_mmx_pandn, 1>;
384 let Constraints = "$src1 = $dst" in {
385 def MMX_PANDNrr : MMXI<0xDF, MRMSrcReg,
386 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
387 "pandn\t{$src2, $dst|$dst, $src2}",
388 [(set VR64:$dst, (v1i64 (and (vnot VR64:$src1),
390 def MMX_PANDNrm : MMXI<0xDF, MRMSrcMem,
391 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
392 "pandn\t{$src2, $dst|$dst, $src2}",
393 [(set VR64:$dst, (v1i64 (and (vnot VR64:$src1),
394 (load addr:$src2))))]>;
397 // Shift Instructions
398 defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
399 int_x86_mmx_psrl_w, int_x86_mmx_psrli_w>;
400 defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
401 int_x86_mmx_psrl_d, int_x86_mmx_psrli_d>;
402 defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
403 int_x86_mmx_psrl_q, int_x86_mmx_psrli_q>;
405 defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
406 int_x86_mmx_psll_w, int_x86_mmx_pslli_w>;
407 defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
408 int_x86_mmx_psll_d, int_x86_mmx_pslli_d>;
409 defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
410 int_x86_mmx_psll_q, int_x86_mmx_pslli_q>;
412 defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
413 int_x86_mmx_psra_w, int_x86_mmx_psrai_w>;
414 defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
415 int_x86_mmx_psra_d, int_x86_mmx_psrai_d>;
417 // Shift up / down and insert zero's.
418 def : Pat<(v1i64 (X86vshl VR64:$src, (i8 imm:$amt))),
419 (MMX_PSLLQri VR64:$src, (GetLo32XForm imm:$amt))>;
420 def : Pat<(v1i64 (X86vshr VR64:$src, (i8 imm:$amt))),
421 (MMX_PSRLQri VR64:$src, (GetLo32XForm imm:$amt))>;
423 // Comparison Instructions
424 defm MMX_PCMPEQB : MMXI_binop_rm_int<0x74, "pcmpeqb", int_x86_mmx_pcmpeq_b>;
425 defm MMX_PCMPEQW : MMXI_binop_rm_int<0x75, "pcmpeqw", int_x86_mmx_pcmpeq_w>;
426 defm MMX_PCMPEQD : MMXI_binop_rm_int<0x76, "pcmpeqd", int_x86_mmx_pcmpeq_d>;
428 defm MMX_PCMPGTB : MMXI_binop_rm_int<0x64, "pcmpgtb", int_x86_mmx_pcmpgt_b>;
429 defm MMX_PCMPGTW : MMXI_binop_rm_int<0x65, "pcmpgtw", int_x86_mmx_pcmpgt_w>;
430 defm MMX_PCMPGTD : MMXI_binop_rm_int<0x66, "pcmpgtd", int_x86_mmx_pcmpgt_d>;
432 // Conversion Instructions
434 // -- Unpack Instructions
435 let Constraints = "$src1 = $dst" in {
436 // Unpack High Packed Data Instructions
437 def MMX_PUNPCKHBWrr : MMXI<0x68, MRMSrcReg,
438 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
439 "punpckhbw\t{$src2, $dst|$dst, $src2}",
441 (v8i8 (mmx_unpckh VR64:$src1, VR64:$src2)))]>;
442 def MMX_PUNPCKHBWrm : MMXI<0x68, MRMSrcMem,
443 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
444 "punpckhbw\t{$src2, $dst|$dst, $src2}",
446 (v8i8 (mmx_unpckh VR64:$src1,
447 (bc_v8i8 (load_mmx addr:$src2)))))]>;
449 def MMX_PUNPCKHWDrr : MMXI<0x69, MRMSrcReg,
450 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
451 "punpckhwd\t{$src2, $dst|$dst, $src2}",
453 (v4i16 (mmx_unpckh VR64:$src1, VR64:$src2)))]>;
454 def MMX_PUNPCKHWDrm : MMXI<0x69, MRMSrcMem,
455 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
456 "punpckhwd\t{$src2, $dst|$dst, $src2}",
458 (v4i16 (mmx_unpckh VR64:$src1,
459 (bc_v4i16 (load_mmx addr:$src2)))))]>;
461 def MMX_PUNPCKHDQrr : MMXI<0x6A, MRMSrcReg,
462 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
463 "punpckhdq\t{$src2, $dst|$dst, $src2}",
465 (v2i32 (mmx_unpckh VR64:$src1, VR64:$src2)))]>;
466 def MMX_PUNPCKHDQrm : MMXI<0x6A, MRMSrcMem,
467 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
468 "punpckhdq\t{$src2, $dst|$dst, $src2}",
470 (v2i32 (mmx_unpckh VR64:$src1,
471 (bc_v2i32 (load_mmx addr:$src2)))))]>;
473 // Unpack Low Packed Data Instructions
474 def MMX_PUNPCKLBWrr : MMXI<0x60, MRMSrcReg,
475 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
476 "punpcklbw\t{$src2, $dst|$dst, $src2}",
478 (v8i8 (mmx_unpckl VR64:$src1, VR64:$src2)))]>;
479 def MMX_PUNPCKLBWrm : MMXI<0x60, MRMSrcMem,
480 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
481 "punpcklbw\t{$src2, $dst|$dst, $src2}",
483 (v8i8 (mmx_unpckl VR64:$src1,
484 (bc_v8i8 (load_mmx addr:$src2)))))]>;
486 def MMX_PUNPCKLWDrr : MMXI<0x61, MRMSrcReg,
487 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
488 "punpcklwd\t{$src2, $dst|$dst, $src2}",
490 (v4i16 (mmx_unpckl VR64:$src1, VR64:$src2)))]>;
491 def MMX_PUNPCKLWDrm : MMXI<0x61, MRMSrcMem,
492 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
493 "punpcklwd\t{$src2, $dst|$dst, $src2}",
495 (v4i16 (mmx_unpckl VR64:$src1,
496 (bc_v4i16 (load_mmx addr:$src2)))))]>;
498 def MMX_PUNPCKLDQrr : MMXI<0x62, MRMSrcReg,
499 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
500 "punpckldq\t{$src2, $dst|$dst, $src2}",
502 (v2i32 (mmx_unpckl VR64:$src1, VR64:$src2)))]>;
503 def MMX_PUNPCKLDQrm : MMXI<0x62, MRMSrcMem,
504 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
505 "punpckldq\t{$src2, $dst|$dst, $src2}",
507 (v2i32 (mmx_unpckl VR64:$src1,
508 (bc_v2i32 (load_mmx addr:$src2)))))]>;
510 defm MMX_PUNPCKHBW : MMXI_binop_rm_int<0x68, "punpckhbw",
511 int_x86_mmx_punpckhbw>;
512 defm MMX_PUNPCKHWD : MMXI_binop_rm_int<0x69, "punpckhwd",
513 int_x86_mmx_punpckhwd>;
514 defm MMX_PUNPCKHDQ : MMXI_binop_rm_int<0x6A, "punpckhdq",
515 int_x86_mmx_punpckhdq>;
516 defm MMX_PUNPCKLBW : MMXI_binop_rm_int<0x60, "punpcklbw",
517 int_x86_mmx_punpcklbw>;
518 defm MMX_PUNPCKLWD : MMXI_binop_rm_int<0x61, "punpcklwd",
519 int_x86_mmx_punpcklwd>;
520 defm MMX_PUNPCKLDQ : MMXI_binop_rm_int<0x62, "punpckldq",
521 int_x86_mmx_punpckldq>;
523 // -- Pack Instructions
524 defm MMX_PACKSSWB : MMXI_binop_rm_int<0x63, "packsswb", int_x86_mmx_packsswb>;
525 defm MMX_PACKSSDW : MMXI_binop_rm_int<0x6B, "packssdw", int_x86_mmx_packssdw>;
526 defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb>;
528 // -- Shuffle Instructions
529 def MMX_PSHUFWri : MMXIi8<0x70, MRMSrcReg,
530 (outs VR64:$dst), (ins VR64:$src1, i8imm:$src2),
531 "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
533 (v4i16 (mmx_pshufw:$src2 VR64:$src1, (undef))))]>;
534 def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
535 (outs VR64:$dst), (ins i64mem:$src1, i8imm:$src2),
536 "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
538 (mmx_pshufw:$src2 (bc_v4i16 (load_mmx addr:$src1)),
541 defm MMX_PSHUFB : SS3I_binop_rm_int_mm<0x00, "pshufb", memopv8i8,
542 int_x86_ssse3_pshuf_b>;
543 // Shuffle with PALIGN
544 def : Pat<(v1i64 (X86PAlign VR64:$src1, VR64:$src2, (i8 imm:$imm))),
545 (MMX_PALIGNR64rr VR64:$src2, VR64:$src1, imm:$imm)>;
546 def : Pat<(v2i32 (X86PAlign VR64:$src1, VR64:$src2, (i8 imm:$imm))),
547 (MMX_PALIGNR64rr VR64:$src2, VR64:$src1, imm:$imm)>;
548 def : Pat<(v4i16 (X86PAlign VR64:$src1, VR64:$src2, (i8 imm:$imm))),
549 (MMX_PALIGNR64rr VR64:$src2, VR64:$src1, imm:$imm)>;
550 def : Pat<(v8i8 (X86PAlign VR64:$src1, VR64:$src2, (i8 imm:$imm))),
551 (MMX_PALIGNR64rr VR64:$src2, VR64:$src1, imm:$imm)>;
553 // -- Conversion Instructions
554 let neverHasSideEffects = 1 in {
555 def MMX_CVTPI2PDrr : MMX2I<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
556 "cvtpi2pd\t{$src, $dst|$dst, $src}", []>;
558 def MMX_CVTPI2PDrm : MMX2I<0x2A, MRMSrcMem, (outs VR128:$dst),
560 "cvtpi2pd\t{$src, $dst|$dst, $src}", []>;
562 def MMX_CVTPI2PSrr : MMXI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
563 "cvtpi2ps\t{$src, $dst|$dst, $src}", []>;
565 def MMX_CVTPI2PSrm : MMXI<0x2A, MRMSrcMem, (outs VR128:$dst),
567 "cvtpi2ps\t{$src, $dst|$dst, $src}", []>;
569 def MMX_CVTTPD2PIrr : MMX2I<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
570 "cvttpd2pi\t{$src, $dst|$dst, $src}", []>;
572 def MMX_CVTTPD2PIrm : MMX2I<0x2C, MRMSrcMem, (outs VR64:$dst),
574 "cvttpd2pi\t{$src, $dst|$dst, $src}", []>;
576 def MMX_CVTTPS2PIrr : MMXI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
577 "cvttps2pi\t{$src, $dst|$dst, $src}", []>;
579 def MMX_CVTTPS2PIrm : MMXI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
580 "cvttps2pi\t{$src, $dst|$dst, $src}", []>;
581 } // end neverHasSideEffects
584 defm MMX_CVTPS2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtps2pi,
585 f64mem, load, "cvtps2pi\t{$src, $dst|$dst, $src}",
586 SSEPackedSingle>, TB;
587 defm MMX_CVTPD2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtpd2pi,
588 f128mem, memop, "cvtpd2pi\t{$src, $dst|$dst, $src}",
589 SSEPackedDouble>, TB, OpSize;
590 defm MMX_CVTTPS2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttps2pi,
591 f64mem, load, "cvttps2pi\t{$src, $dst|$dst, $src}",
592 SSEPackedSingle>, TB;
593 defm MMX_CVTTPD2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttpd2pi,
594 f128mem, memop, "cvttpd2pi\t{$src, $dst|$dst, $src}",
595 SSEPackedDouble>, TB, OpSize;
596 defm MMX_CVTPI2PD : sse12_cvt_pint<0x2A, VR64, VR128, int_x86_sse_cvtpi2pd,
597 i64mem, load, "cvtpi2pd\t{$src, $dst|$dst, $src}",
598 SSEPackedDouble>, TB, OpSize;
599 let Constraints = "$src1 = $dst" in {
600 defm MMX_CVTPI2PS : sse12_cvt_pint_3addr<0x2A, VR64, VR128,
601 int_x86_sse_cvtpi2ps,
602 i64mem, load, "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
603 SSEPackedSingle>, TB;
605 // MMX->MMX vector casts.
606 def : Pat<(v2f64 (sint_to_fp (v2i32 VR64:$src))),
607 (MMX_CVTPI2PDrr VR64:$src)>, Requires<[HasSSE2]>;
608 def : Pat<(v2i32 (fp_to_sint (v2f64 VR128:$src))),
609 (MMX_CVTTPD2PIrr VR128:$src)>, Requires<[HasSSE2]>;
612 def MMX_X86pinsrw : SDNode<"X86ISD::MMX_PINSRW",
613 SDTypeProfile<1, 3, [SDTCisVT<0, v4i16>, SDTCisSameAs<0,1>,
614 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
617 def MMX_PEXTRWri : MMXIi8<0xC5, MRMSrcReg,
618 (outs GR32:$dst), (ins VR64:$src1, i16i8imm:$src2),
619 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
620 [(set GR32:$dst, (X86pextrw (v4i16 VR64:$src1),
621 (iPTR imm:$src2)))]>;
622 def MMX_PEXTRWirri: MMXIi8<0xC5, MRMSrcReg,
623 (outs GR32:$dst), (ins VR64:$src1, i32i8imm:$src2),
624 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
625 [(set GR32:$dst, (int_x86_mmx_pextr_w VR64:$src1,
626 (iPTR imm:$src2)))]>;
627 let Constraints = "$src1 = $dst" in {
628 def MMX_PINSRWrri : MMXIi8<0xC4, MRMSrcReg,
630 (ins VR64:$src1, GR32:$src2,i16i8imm:$src3),
631 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
632 [(set VR64:$dst, (v4i16 (MMX_X86pinsrw (v4i16 VR64:$src1),
633 GR32:$src2,(iPTR imm:$src3))))]>;
634 def MMX_PINSRWrmi : MMXIi8<0xC4, MRMSrcMem,
636 (ins VR64:$src1, i16mem:$src2, i16i8imm:$src3),
637 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
639 (v4i16 (MMX_X86pinsrw (v4i16 VR64:$src1),
640 (i32 (anyext (loadi16 addr:$src2))),
641 (iPTR imm:$src3))))]>;
642 def MMX_PINSRWirri : MMXIi8<0xC4, MRMSrcReg,
644 (ins VR64:$src1, GR32:$src2, i32i8imm:$src3),
645 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
646 [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1,
647 GR32:$src2, (iPTR imm:$src3)))]>;
649 def MMX_PINSRWirmi : MMXIi8<0xC4, MRMSrcMem,
651 (ins VR64:$src1, i16mem:$src2, i32i8imm:$src3),
652 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
653 [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1,
654 (i32 (anyext (loadi16 addr:$src2))),
655 (iPTR imm:$src3)))]>;
658 // MMX to XMM for vector types
659 def MMX_X86movq2dq : SDNode<"X86ISD::MOVQ2DQ", SDTypeProfile<1, 1,
660 [SDTCisVT<0, v2i64>, SDTCisVT<1, v1i64>]>>;
662 def : Pat<(v2i64 (MMX_X86movq2dq VR64:$src)),
663 (v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
665 def : Pat<(v2i64 (MMX_X86movq2dq (load_mmx addr:$src))),
666 (v2i64 (MOVQI2PQIrm addr:$src))>;
668 def : Pat<(v2i64 (MMX_X86movq2dq (v1i64 (bitconvert
669 (v2i32 (scalar_to_vector (loadi32 addr:$src))))))),
670 (v2i64 (MOVDI2PDIrm addr:$src))>;
673 def MMX_PMOVMSKBrr : MMXI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR64:$src),
674 "pmovmskb\t{$src, $dst|$dst, $src}",
675 [(set GR32:$dst, (int_x86_mmx_pmovmskb VR64:$src))]>;
679 def MMX_MASKMOVQ : MMXI<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask),
680 "maskmovq\t{$mask, $src|$src, $mask}",
681 [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, EDI)]>;
683 def MMX_MASKMOVQ64: MMXI64<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask),
684 "maskmovq\t{$mask, $src|$src, $mask}",
685 [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, RDI)]>;
687 //===----------------------------------------------------------------------===//
688 // Alias Instructions
689 //===----------------------------------------------------------------------===//
691 // Alias instructions that map zero vector to pxor.
692 let isReMaterializable = 1, isCodeGenOnly = 1 in {
693 // FIXME: Change encoding to pseudo.
694 def MMX_V_SET0 : MMXI<0xEF, MRMInitReg, (outs VR64:$dst), (ins), "",
695 [(set VR64:$dst, (v2i32 immAllZerosV))]>;
696 def MMX_V_SETALLONES : MMXI<0x76, MRMInitReg, (outs VR64:$dst), (ins), "",
697 [(set VR64:$dst, (v2i32 immAllOnesV))]>;
700 let Predicates = [HasMMX] in {
701 def : Pat<(v1i64 immAllZerosV), (MMX_V_SET0)>;
702 def : Pat<(v4i16 immAllZerosV), (MMX_V_SET0)>;
703 def : Pat<(v8i8 immAllZerosV), (MMX_V_SET0)>;
706 //===----------------------------------------------------------------------===//
707 // Non-Instruction Patterns
708 //===----------------------------------------------------------------------===//
710 // Store 64-bit integer vector values.
711 def : Pat<(store (v8i8 VR64:$src), addr:$dst),
712 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
713 def : Pat<(store (v4i16 VR64:$src), addr:$dst),
714 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
715 def : Pat<(store (v2i32 VR64:$src), addr:$dst),
716 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
717 def : Pat<(store (v1i64 VR64:$src), addr:$dst),
718 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
721 def : Pat<(v8i8 (bitconvert (v1i64 VR64:$src))), (v8i8 VR64:$src)>;
722 def : Pat<(v8i8 (bitconvert (v2i32 VR64:$src))), (v8i8 VR64:$src)>;
723 def : Pat<(v8i8 (bitconvert (v4i16 VR64:$src))), (v8i8 VR64:$src)>;
724 def : Pat<(v4i16 (bitconvert (v1i64 VR64:$src))), (v4i16 VR64:$src)>;
725 def : Pat<(v4i16 (bitconvert (v2i32 VR64:$src))), (v4i16 VR64:$src)>;
726 def : Pat<(v4i16 (bitconvert (v8i8 VR64:$src))), (v4i16 VR64:$src)>;
727 def : Pat<(v2i32 (bitconvert (v1i64 VR64:$src))), (v2i32 VR64:$src)>;
728 def : Pat<(v2i32 (bitconvert (v4i16 VR64:$src))), (v2i32 VR64:$src)>;
729 def : Pat<(v2i32 (bitconvert (v8i8 VR64:$src))), (v2i32 VR64:$src)>;
730 def : Pat<(v1i64 (bitconvert (v2i32 VR64:$src))), (v1i64 VR64:$src)>;
731 def : Pat<(v1i64 (bitconvert (v4i16 VR64:$src))), (v1i64 VR64:$src)>;
732 def : Pat<(v1i64 (bitconvert (v8i8 VR64:$src))), (v1i64 VR64:$src)>;
734 // 64-bit bit convert.
735 def : Pat<(v1i64 (bitconvert (i64 GR64:$src))),
736 (MMX_MOVD64to64rr GR64:$src)>;
737 def : Pat<(v2i32 (bitconvert (i64 GR64:$src))),
738 (MMX_MOVD64to64rr GR64:$src)>;
739 def : Pat<(v4i16 (bitconvert (i64 GR64:$src))),
740 (MMX_MOVD64to64rr GR64:$src)>;
741 def : Pat<(v8i8 (bitconvert (i64 GR64:$src))),
742 (MMX_MOVD64to64rr GR64:$src)>;
743 def : Pat<(i64 (bitconvert (v1i64 VR64:$src))),
744 (MMX_MOVD64from64rr VR64:$src)>;
745 def : Pat<(i64 (bitconvert (v2i32 VR64:$src))),
746 (MMX_MOVD64from64rr VR64:$src)>;
747 def : Pat<(i64 (bitconvert (v4i16 VR64:$src))),
748 (MMX_MOVD64from64rr VR64:$src)>;
749 def : Pat<(i64 (bitconvert (v8i8 VR64:$src))),
750 (MMX_MOVD64from64rr VR64:$src)>;
751 def : Pat<(f64 (bitconvert (v1i64 VR64:$src))),
752 (MMX_MOVQ2FR64rr VR64:$src)>;
753 def : Pat<(f64 (bitconvert (v2i32 VR64:$src))),
754 (MMX_MOVQ2FR64rr VR64:$src)>;
755 def : Pat<(f64 (bitconvert (v4i16 VR64:$src))),
756 (MMX_MOVQ2FR64rr VR64:$src)>;
757 def : Pat<(f64 (bitconvert (v8i8 VR64:$src))),
758 (MMX_MOVQ2FR64rr VR64:$src)>;
759 def : Pat<(v1i64 (bitconvert (f64 FR64:$src))),
760 (MMX_MOVFR642Qrr FR64:$src)>;
761 def : Pat<(v2i32 (bitconvert (f64 FR64:$src))),
762 (MMX_MOVFR642Qrr FR64:$src)>;
763 def : Pat<(v4i16 (bitconvert (f64 FR64:$src))),
764 (MMX_MOVFR642Qrr FR64:$src)>;
765 def : Pat<(v8i8 (bitconvert (f64 FR64:$src))),
766 (MMX_MOVFR642Qrr FR64:$src)>;
768 let AddedComplexity = 20 in {
769 def : Pat<(v2i32 (X86vzmovl (bc_v2i32 (load_mmx addr:$src)))),
770 (MMX_MOVZDI2PDIrm addr:$src)>;
774 let AddedComplexity = 15 in {
775 def : Pat<(v2i32 (X86vzmovl VR64:$src)),
776 (MMX_PUNPCKLDQrr VR64:$src, (v2i32 (MMX_V_SET0)))>;
779 // Patterns to perform canonical versions of vector shuffling.
780 let AddedComplexity = 10 in {
781 def : Pat<(v8i8 (mmx_unpckl_undef VR64:$src, (undef))),
782 (MMX_PUNPCKLBWrr VR64:$src, VR64:$src)>;
783 def : Pat<(v4i16 (mmx_unpckl_undef VR64:$src, (undef))),
784 (MMX_PUNPCKLWDrr VR64:$src, VR64:$src)>;
785 def : Pat<(v2i32 (mmx_unpckl_undef VR64:$src, (undef))),
786 (MMX_PUNPCKLDQrr VR64:$src, VR64:$src)>;
789 let AddedComplexity = 10 in {
790 def : Pat<(v8i8 (mmx_unpckh_undef VR64:$src, (undef))),
791 (MMX_PUNPCKHBWrr VR64:$src, VR64:$src)>;
792 def : Pat<(v4i16 (mmx_unpckh_undef VR64:$src, (undef))),
793 (MMX_PUNPCKHWDrr VR64:$src, VR64:$src)>;
794 def : Pat<(v2i32 (mmx_unpckh_undef VR64:$src, (undef))),
795 (MMX_PUNPCKHDQrr VR64:$src, VR64:$src)>;
798 // Some special case PANDN patterns.
799 // FIXME: Get rid of these.
800 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v2i32 immAllOnesV))),
802 (MMX_PANDNrr VR64:$src1, VR64:$src2)>;
803 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v2i32 immAllOnesV))),
805 (MMX_PANDNrm VR64:$src1, addr:$src2)>;
807 // Move MMX to lower 64-bit of XMM
808 def : Pat<(v2i64 (scalar_to_vector (i64 (bitconvert (v8i8 VR64:$src))))),
809 (v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
810 def : Pat<(v2i64 (scalar_to_vector (i64 (bitconvert (v4i16 VR64:$src))))),
811 (v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
812 def : Pat<(v2i64 (scalar_to_vector (i64 (bitconvert (v2i32 VR64:$src))))),
813 (v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
814 def : Pat<(v2i64 (scalar_to_vector (i64 (bitconvert (v1i64 VR64:$src))))),
815 (v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
817 // Move lower 64-bit of XMM to MMX.
818 def : Pat<(v2i32 (bitconvert (i64 (vector_extract (v2i64 VR128:$src),
820 (v2i32 (MMX_MOVDQ2Qrr VR128:$src))>;
821 def : Pat<(v4i16 (bitconvert (i64 (vector_extract (v2i64 VR128:$src),
823 (v4i16 (MMX_MOVDQ2Qrr VR128:$src))>;
824 def : Pat<(v8i8 (bitconvert (i64 (vector_extract (v2i64 VR128:$src),
826 (v8i8 (MMX_MOVDQ2Qrr VR128:$src))>;
828 // Patterns for vector comparisons
829 def : Pat<(v8i8 (X86pcmpeqb VR64:$src1, VR64:$src2)),
830 (MMX_PCMPEQBirr VR64:$src1, VR64:$src2)>;
831 def : Pat<(v8i8 (X86pcmpeqb VR64:$src1, (bitconvert (load_mmx addr:$src2)))),
832 (MMX_PCMPEQBirm VR64:$src1, addr:$src2)>;
833 def : Pat<(v4i16 (X86pcmpeqw VR64:$src1, VR64:$src2)),
834 (MMX_PCMPEQWirr VR64:$src1, VR64:$src2)>;
835 def : Pat<(v4i16 (X86pcmpeqw VR64:$src1, (bitconvert (load_mmx addr:$src2)))),
836 (MMX_PCMPEQWirm VR64:$src1, addr:$src2)>;
837 def : Pat<(v2i32 (X86pcmpeqd VR64:$src1, VR64:$src2)),
838 (MMX_PCMPEQDirr VR64:$src1, VR64:$src2)>;
839 def : Pat<(v2i32 (X86pcmpeqd VR64:$src1, (bitconvert (load_mmx addr:$src2)))),
840 (MMX_PCMPEQDirm VR64:$src1, addr:$src2)>;
842 def : Pat<(v8i8 (X86pcmpgtb VR64:$src1, VR64:$src2)),
843 (MMX_PCMPGTBirr VR64:$src1, VR64:$src2)>;
844 def : Pat<(v8i8 (X86pcmpgtb VR64:$src1, (bitconvert (load_mmx addr:$src2)))),
845 (MMX_PCMPGTBirm VR64:$src1, addr:$src2)>;
846 def : Pat<(v4i16 (X86pcmpgtw VR64:$src1, VR64:$src2)),
847 (MMX_PCMPGTWirr VR64:$src1, VR64:$src2)>;
848 def : Pat<(v4i16 (X86pcmpgtw VR64:$src1, (bitconvert (load_mmx addr:$src2)))),
849 (MMX_PCMPGTWirm VR64:$src1, addr:$src2)>;
850 def : Pat<(v2i32 (X86pcmpgtd VR64:$src1, VR64:$src2)),
851 (MMX_PCMPGTDirr VR64:$src1, VR64:$src2)>;
852 def : Pat<(v2i32 (X86pcmpgtd VR64:$src1, (bitconvert (load_mmx addr:$src2)))),
853 (MMX_PCMPGTDirm VR64:$src1, addr:$src2)>;
855 // CMOV* - Used to implement the SELECT DAG operation. Expanded after
856 // instruction selection into a branch sequence.
857 let Uses = [EFLAGS], usesCustomInserter = 1 in {
858 def CMOV_V1I64 : I<0, Pseudo,
859 (outs VR64:$dst), (ins VR64:$t, VR64:$f, i8imm:$cond),
860 "#CMOV_V1I64 PSEUDO!",
862 (v1i64 (X86cmov VR64:$t, VR64:$f, imm:$cond,