1 //====- X86InstrMMX.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Evan Cheng and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 MMX instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // Some 'special' instructions
17 def IMPLICIT_DEF_VR64 : I<0, Pseudo, (outs VR64:$dst), (ins),
19 [(set VR64:$dst, (v8i8 (undef)))]>,
22 // 64-bit vector undef's.
23 def : Pat<(v8i8 (undef)), (IMPLICIT_DEF_VR64)>;
24 def : Pat<(v4i16 (undef)), (IMPLICIT_DEF_VR64)>;
25 def : Pat<(v2i32 (undef)), (IMPLICIT_DEF_VR64)>;
26 def : Pat<(v1i64 (undef)), (IMPLICIT_DEF_VR64)>;
28 //===----------------------------------------------------------------------===//
29 // MMX Pattern Fragments
30 //===----------------------------------------------------------------------===//
32 def load_mmx : PatFrag<(ops node:$ptr), (v1i64 (load node:$ptr))>;
34 def bc_v8i8 : PatFrag<(ops node:$in), (v8i8 (bitconvert node:$in))>;
35 def bc_v4i16 : PatFrag<(ops node:$in), (v4i16 (bitconvert node:$in))>;
36 def bc_v2i32 : PatFrag<(ops node:$in), (v2i32 (bitconvert node:$in))>;
37 def bc_v1i64 : PatFrag<(ops node:$in), (v1i64 (bitconvert node:$in))>;
39 //===----------------------------------------------------------------------===//
41 //===----------------------------------------------------------------------===//
43 // MMX_SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to
45 def MMX_SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
46 return getI8Imm(X86::getShuffleSHUFImmediate(N));
49 // Patterns for: vector_shuffle v1, v2, <2, 6, 3, 7, ...>
50 def MMX_UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
51 return X86::isUNPCKHMask(N);
54 // Patterns for: vector_shuffle v1, v2, <0, 4, 2, 5, ...>
55 def MMX_UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
56 return X86::isUNPCKLMask(N);
59 // Patterns for: vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
60 def MMX_UNPCKH_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
61 return X86::isUNPCKH_v_undef_Mask(N);
64 // Patterns for: vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
65 def MMX_UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
66 return X86::isUNPCKL_v_undef_Mask(N);
69 // Patterns for shuffling.
70 def MMX_PSHUFW_shuffle_mask : PatLeaf<(build_vector), [{
71 return X86::isPSHUFDMask(N);
72 }], MMX_SHUFFLE_get_shuf_imm>;
74 // Patterns for: vector_shuffle v1, v2, <4, 5, 2, 3>; etc.
75 def MMX_MOVL_shuffle_mask : PatLeaf<(build_vector), [{
76 return X86::isMOVLMask(N);
79 //===----------------------------------------------------------------------===//
81 //===----------------------------------------------------------------------===//
83 let isTwoAddress = 1 in {
84 // MMXI_binop_rm - Simple MMX binary operator.
85 multiclass MMXI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
86 ValueType OpVT, bit Commutable = 0> {
87 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
88 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
89 [(set VR64:$dst, (OpVT (OpNode VR64:$src1, VR64:$src2)))]> {
90 let isCommutable = Commutable;
92 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
93 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
94 [(set VR64:$dst, (OpVT (OpNode VR64:$src1,
96 (load_mmx addr:$src2)))))]>;
99 multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
100 bit Commutable = 0> {
101 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
102 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
103 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]> {
104 let isCommutable = Commutable;
106 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
107 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
108 [(set VR64:$dst, (IntId VR64:$src1,
109 (bitconvert (load_mmx addr:$src2))))]>;
112 // MMXI_binop_rm_v1i64 - Simple MMX binary operator whose type is v1i64.
114 // FIXME: we could eliminate this and use MMXI_binop_rm instead if tblgen knew
115 // to collapse (bitconvert VT to VT) into its operand.
117 multiclass MMXI_binop_rm_v1i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
118 bit Commutable = 0> {
119 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
120 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
121 [(set VR64:$dst, (v1i64 (OpNode VR64:$src1, VR64:$src2)))]> {
122 let isCommutable = Commutable;
124 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
125 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
127 (OpNode VR64:$src1,(load_mmx addr:$src2)))]>;
130 multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
131 string OpcodeStr, Intrinsic IntId> {
132 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
133 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
134 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>;
135 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
136 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
137 [(set VR64:$dst, (IntId VR64:$src1,
138 (bitconvert (load_mmx addr:$src2))))]>;
139 def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst), (ins VR64:$src1, i32i8imm:$src2),
140 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
141 [(set VR64:$dst, (IntId VR64:$src1,
142 (scalar_to_vector (i32 imm:$src2))))]>;
146 //===----------------------------------------------------------------------===//
147 // MMX EMMS & FEMMS Instructions
148 //===----------------------------------------------------------------------===//
150 def MMX_EMMS : MMXI<0x77, RawFrm, (outs), (ins), "emms", [(int_x86_mmx_emms)]>;
151 def MMX_FEMMS : MMXI<0x0E, RawFrm, (outs), (ins), "femms", [(int_x86_mmx_femms)]>;
153 //===----------------------------------------------------------------------===//
154 // MMX Scalar Instructions
155 //===----------------------------------------------------------------------===//
157 // Data Transfer Instructions
158 def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
159 "movd {$src, $dst|$dst, $src}", []>;
160 def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
161 "movd {$src, $dst|$dst, $src}", []>;
162 def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src),
163 "movd {$src, $dst|$dst, $src}", []>;
165 def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
166 "movd {$src, $dst|$dst, $src}", []>;
168 def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
169 "movq {$src, $dst|$dst, $src}", []>;
170 def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
171 "movq {$src, $dst|$dst, $src}",
172 [(set VR64:$dst, (load_mmx addr:$src))]>;
173 def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
174 "movq {$src, $dst|$dst, $src}",
175 [(store (v1i64 VR64:$src), addr:$dst)]>;
177 def MMX_MOVDQ2Qrr : MMXID<0xD6, MRMDestMem, (outs VR64:$dst), (ins VR128:$src),
178 "movdq2q {$src, $dst|$dst, $src}",
180 (v1i64 (vector_extract (v2i64 VR128:$src),
183 def MMX_MOVQ2DQrr : MMXIS<0xD6, MRMDestMem, (outs VR128:$dst), (ins VR64:$src),
184 "movq2dq {$src, $dst|$dst, $src}",
186 (bitconvert (v1i64 VR64:$src)))]>;
188 def MMX_MOVNTQmr : MMXI<0xE7, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
189 "movntq {$src, $dst|$dst, $src}",
190 [(int_x86_mmx_movnt_dq addr:$dst, VR64:$src)]>;
192 let AddedComplexity = 15 in
193 // movd to MMX register zero-extends
194 def MMX_MOVZDI2PDIrr : MMX2I<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
195 "movd {$src, $dst|$dst, $src}",
197 (v2i32 (vector_shuffle immAllZerosV,
198 (v2i32 (scalar_to_vector GR32:$src)),
199 MMX_MOVL_shuffle_mask)))]>;
200 let AddedComplexity = 20 in
201 def MMX_MOVZDI2PDIrm : MMX2I<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
202 "movd {$src, $dst|$dst, $src}",
204 (v2i32 (vector_shuffle immAllZerosV,
205 (v2i32 (scalar_to_vector
206 (loadi32 addr:$src))),
207 MMX_MOVL_shuffle_mask)))]>;
209 // Arithmetic Instructions
212 defm MMX_PADDB : MMXI_binop_rm<0xFC, "paddb", add, v8i8, 1>;
213 defm MMX_PADDW : MMXI_binop_rm<0xFD, "paddw", add, v4i16, 1>;
214 defm MMX_PADDD : MMXI_binop_rm<0xFE, "paddd", add, v2i32, 1>;
215 defm MMX_PADDQ : MMXI_binop_rm<0xD4, "paddq", add, v1i64, 1>;
217 defm MMX_PADDSB : MMXI_binop_rm_int<0xEC, "paddsb" , int_x86_mmx_padds_b, 1>;
218 defm MMX_PADDSW : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w, 1>;
220 defm MMX_PADDUSB : MMXI_binop_rm_int<0xDC, "paddusb", int_x86_mmx_paddus_b, 1>;
221 defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w, 1>;
224 defm MMX_PSUBB : MMXI_binop_rm<0xF8, "psubb", sub, v8i8>;
225 defm MMX_PSUBW : MMXI_binop_rm<0xF9, "psubw", sub, v4i16>;
226 defm MMX_PSUBD : MMXI_binop_rm<0xFA, "psubd", sub, v2i32>;
227 defm MMX_PSUBQ : MMXI_binop_rm<0xFB, "psubq", sub, v1i64>;
229 defm MMX_PSUBSB : MMXI_binop_rm_int<0xE8, "psubsb" , int_x86_mmx_psubs_b>;
230 defm MMX_PSUBSW : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w>;
232 defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b>;
233 defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w>;
236 defm MMX_PMULLW : MMXI_binop_rm<0xD5, "pmullw", mul, v4i16, 1>;
238 defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw", int_x86_mmx_pmulh_w, 1>;
239 defm MMX_PMULHUW : MMXI_binop_rm_int<0xE4, "pmulhuw", int_x86_mmx_pmulhu_w, 1>;
240 defm MMX_PMULUDQ : MMXI_binop_rm_int<0xF4, "pmuludq", int_x86_mmx_pmulu_dq, 1>;
243 defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd, 1>;
245 defm MMX_PAVGB : MMXI_binop_rm_int<0xE0, "pavgb", int_x86_mmx_pavg_b, 1>;
246 defm MMX_PAVGW : MMXI_binop_rm_int<0xE3, "pavgw", int_x86_mmx_pavg_w, 1>;
248 defm MMX_PMINUB : MMXI_binop_rm_int<0xDA, "pminub", int_x86_mmx_pminu_b, 1>;
249 defm MMX_PMINSW : MMXI_binop_rm_int<0xEA, "pminsw", int_x86_mmx_pmins_w, 1>;
251 defm MMX_PMAXUB : MMXI_binop_rm_int<0xDE, "pmaxub", int_x86_mmx_pmaxu_b, 1>;
252 defm MMX_PMAXSW : MMXI_binop_rm_int<0xEE, "pmaxsw", int_x86_mmx_pmaxs_w, 1>;
254 defm MMX_PSADBW : MMXI_binop_rm_int<0xE0, "psadbw", int_x86_mmx_psad_bw, 1>;
256 // Logical Instructions
257 defm MMX_PAND : MMXI_binop_rm_v1i64<0xDB, "pand", and, 1>;
258 defm MMX_POR : MMXI_binop_rm_v1i64<0xEB, "por" , or, 1>;
259 defm MMX_PXOR : MMXI_binop_rm_v1i64<0xEF, "pxor", xor, 1>;
261 let isTwoAddress = 1 in {
262 def MMX_PANDNrr : MMXI<0xDF, MRMSrcReg,
263 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
264 "pandn {$src2, $dst|$dst, $src2}",
265 [(set VR64:$dst, (v1i64 (and (vnot VR64:$src1),
267 def MMX_PANDNrm : MMXI<0xDF, MRMSrcMem,
268 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
269 "pandn {$src2, $dst|$dst, $src2}",
270 [(set VR64:$dst, (v1i64 (and (vnot VR64:$src1),
271 (load addr:$src2))))]>;
274 // Shift Instructions
275 defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
277 defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
279 defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
282 defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
284 defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
286 defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
289 defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
291 defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
294 // Comparison Instructions
295 defm MMX_PCMPEQB : MMXI_binop_rm_int<0x74, "pcmpeqb", int_x86_mmx_pcmpeq_b>;
296 defm MMX_PCMPEQW : MMXI_binop_rm_int<0x75, "pcmpeqw", int_x86_mmx_pcmpeq_w>;
297 defm MMX_PCMPEQD : MMXI_binop_rm_int<0x76, "pcmpeqd", int_x86_mmx_pcmpeq_d>;
299 defm MMX_PCMPGTB : MMXI_binop_rm_int<0x64, "pcmpgtb", int_x86_mmx_pcmpgt_b>;
300 defm MMX_PCMPGTW : MMXI_binop_rm_int<0x65, "pcmpgtw", int_x86_mmx_pcmpgt_w>;
301 defm MMX_PCMPGTD : MMXI_binop_rm_int<0x66, "pcmpgtd", int_x86_mmx_pcmpgt_d>;
303 // Conversion Instructions
305 // -- Unpack Instructions
306 let isTwoAddress = 1 in {
307 // Unpack High Packed Data Instructions
308 def MMX_PUNPCKHBWrr : MMXI<0x68, MRMSrcReg,
309 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
310 "punpckhbw {$src2, $dst|$dst, $src2}",
312 (v8i8 (vector_shuffle VR64:$src1, VR64:$src2,
313 MMX_UNPCKH_shuffle_mask)))]>;
314 def MMX_PUNPCKHBWrm : MMXI<0x68, MRMSrcMem,
315 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
316 "punpckhbw {$src2, $dst|$dst, $src2}",
318 (v8i8 (vector_shuffle VR64:$src1,
319 (bc_v8i8 (load_mmx addr:$src2)),
320 MMX_UNPCKH_shuffle_mask)))]>;
322 def MMX_PUNPCKHWDrr : MMXI<0x69, MRMSrcReg,
323 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
324 "punpckhwd {$src2, $dst|$dst, $src2}",
326 (v4i16 (vector_shuffle VR64:$src1, VR64:$src2,
327 MMX_UNPCKH_shuffle_mask)))]>;
328 def MMX_PUNPCKHWDrm : MMXI<0x69, MRMSrcMem,
329 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
330 "punpckhwd {$src2, $dst|$dst, $src2}",
332 (v4i16 (vector_shuffle VR64:$src1,
333 (bc_v4i16 (load_mmx addr:$src2)),
334 MMX_UNPCKH_shuffle_mask)))]>;
336 def MMX_PUNPCKHDQrr : MMXI<0x6A, MRMSrcReg,
337 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
338 "punpckhdq {$src2, $dst|$dst, $src2}",
340 (v2i32 (vector_shuffle VR64:$src1, VR64:$src2,
341 MMX_UNPCKH_shuffle_mask)))]>;
342 def MMX_PUNPCKHDQrm : MMXI<0x6A, MRMSrcMem,
343 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
344 "punpckhdq {$src2, $dst|$dst, $src2}",
346 (v2i32 (vector_shuffle VR64:$src1,
347 (bc_v2i32 (load_mmx addr:$src2)),
348 MMX_UNPCKH_shuffle_mask)))]>;
350 // Unpack Low Packed Data Instructions
351 def MMX_PUNPCKLBWrr : MMXI<0x60, MRMSrcReg,
352 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
353 "punpcklbw {$src2, $dst|$dst, $src2}",
355 (v8i8 (vector_shuffle VR64:$src1, VR64:$src2,
356 MMX_UNPCKL_shuffle_mask)))]>;
357 def MMX_PUNPCKLBWrm : MMXI<0x60, MRMSrcMem,
358 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
359 "punpcklbw {$src2, $dst|$dst, $src2}",
361 (v8i8 (vector_shuffle VR64:$src1,
362 (bc_v8i8 (load_mmx addr:$src2)),
363 MMX_UNPCKL_shuffle_mask)))]>;
365 def MMX_PUNPCKLWDrr : MMXI<0x61, MRMSrcReg,
366 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
367 "punpcklwd {$src2, $dst|$dst, $src2}",
369 (v4i16 (vector_shuffle VR64:$src1, VR64:$src2,
370 MMX_UNPCKL_shuffle_mask)))]>;
371 def MMX_PUNPCKLWDrm : MMXI<0x61, MRMSrcMem,
372 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
373 "punpcklwd {$src2, $dst|$dst, $src2}",
375 (v4i16 (vector_shuffle VR64:$src1,
376 (bc_v4i16 (load_mmx addr:$src2)),
377 MMX_UNPCKL_shuffle_mask)))]>;
379 def MMX_PUNPCKLDQrr : MMXI<0x62, MRMSrcReg,
380 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
381 "punpckldq {$src2, $dst|$dst, $src2}",
383 (v2i32 (vector_shuffle VR64:$src1, VR64:$src2,
384 MMX_UNPCKL_shuffle_mask)))]>;
385 def MMX_PUNPCKLDQrm : MMXI<0x62, MRMSrcMem,
386 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
387 "punpckldq {$src2, $dst|$dst, $src2}",
389 (v2i32 (vector_shuffle VR64:$src1,
390 (bc_v2i32 (load_mmx addr:$src2)),
391 MMX_UNPCKL_shuffle_mask)))]>;
394 // -- Pack Instructions
395 defm MMX_PACKSSWB : MMXI_binop_rm_int<0x63, "packsswb", int_x86_mmx_packsswb>;
396 defm MMX_PACKSSDW : MMXI_binop_rm_int<0x6B, "packssdw", int_x86_mmx_packssdw>;
397 defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb>;
399 // -- Shuffle Instructions
400 def MMX_PSHUFWri : MMXIi8<0x70, MRMSrcReg,
401 (outs VR64:$dst), (ins VR64:$src1, i8imm:$src2),
402 "pshufw {$src2, $src1, $dst|$dst, $src1, $src2}",
404 (v4i16 (vector_shuffle
406 MMX_PSHUFW_shuffle_mask:$src2)))]>;
407 def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
408 (outs VR64:$dst), (ins i64mem:$src1, i8imm:$src2),
409 "pshufw {$src2, $src1, $dst|$dst, $src1, $src2}",
411 (v4i16 (vector_shuffle
412 (bc_v4i16 (load_mmx addr:$src1)),
414 MMX_PSHUFW_shuffle_mask:$src2)))]>;
416 // -- Conversion Instructions
417 def MMX_CVTPD2PIrr : MMX2I<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
418 "cvtpd2pi {$src, $dst|$dst, $src}", []>;
419 def MMX_CVTPD2PIrm : MMX2I<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
420 "cvtpd2pi {$src, $dst|$dst, $src}", []>;
422 def MMX_CVTPI2PDrr : MMX2I<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
423 "cvtpi2pd {$src, $dst|$dst, $src}", []>;
424 def MMX_CVTPI2PDrm : MMX2I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
425 "cvtpi2pd {$src, $dst|$dst, $src}", []>;
427 def MMX_CVTPI2PSrr : MMXI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
428 "cvtpi2ps {$src, $dst|$dst, $src}", []>;
429 def MMX_CVTPI2PSrm : MMXI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
430 "cvtpi2ps {$src, $dst|$dst, $src}", []>;
432 def MMX_CVTPS2PIrr : MMXI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
433 "cvtps2pi {$src, $dst|$dst, $src}", []>;
434 def MMX_CVTPS2PIrm : MMXI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
435 "cvtps2pi {$src, $dst|$dst, $src}", []>;
437 def MMX_CVTTPD2PIrr : MMX2I<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
438 "cvttpd2pi {$src, $dst|$dst, $src}", []>;
439 def MMX_CVTTPD2PIrm : MMX2I<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
440 "cvttpd2pi {$src, $dst|$dst, $src}", []>;
442 def MMX_CVTTPS2PIrr : MMXI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
443 "cvttps2pi {$src, $dst|$dst, $src}", []>;
444 def MMX_CVTTPS2PIrm : MMXI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
445 "cvttps2pi {$src, $dst|$dst, $src}", []>;
448 def MMX_X86pextrw : SDNode<"X86ISD::PEXTRW", SDTypeProfile<1, 2, []>, []>;
449 def MMX_X86pinsrw : SDNode<"X86ISD::PINSRW", SDTypeProfile<1, 3, []>, []>;
451 def MMX_PEXTRWri : MMXIi8<0xC5, MRMSrcReg,
452 (outs GR32:$dst), (ins VR64:$src1, i16i8imm:$src2),
453 "pextrw {$src2, $src1, $dst|$dst, $src1, $src2}",
454 [(set GR32:$dst, (MMX_X86pextrw (v4i16 VR64:$src1),
455 (iPTR imm:$src2)))]>;
456 let isTwoAddress = 1 in {
457 def MMX_PINSRWrri : MMXIi8<0xC4, MRMSrcReg,
458 (outs VR64:$dst), (ins VR64:$src1, GR32:$src2, i16i8imm:$src3),
459 "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
460 [(set VR64:$dst, (v4i16 (MMX_X86pinsrw (v4i16 VR64:$src1),
461 GR32:$src2, (iPTR imm:$src3))))]>;
462 def MMX_PINSRWrmi : MMXIi8<0xC4, MRMSrcMem,
463 (outs VR64:$dst), (ins VR64:$src1, i16mem:$src2, i16i8imm:$src3),
464 "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
466 (v4i16 (MMX_X86pinsrw (v4i16 VR64:$src1),
467 (i32 (anyext (loadi16 addr:$src2))),
468 (iPTR imm:$src3))))]>;
472 def MMX_PMOVMSKBrr : MMXI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR64:$src),
473 "pmovmskb {$src, $dst|$dst, $src}",
474 [(set GR32:$dst, (int_x86_mmx_pmovmskb VR64:$src))]>;
477 def MMX_MASKMOVQ : MMXI<0xF7, MRMDestMem, (outs), (ins VR64:$src, VR64:$mask),
478 "maskmovq {$mask, $src|$src, $mask}",
479 [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, EDI)]>,
482 //===----------------------------------------------------------------------===//
483 // Alias Instructions
484 //===----------------------------------------------------------------------===//
486 // Alias instructions that map zero vector to pxor.
487 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
488 let isReMaterializable = 1 in {
489 def MMX_V_SET0 : MMXI<0xEF, MRMInitReg, (outs VR64:$dst), (ins),
491 [(set VR64:$dst, (v1i64 immAllZerosV))]>;
492 def MMX_V_SETALLONES : MMXI<0x76, MRMInitReg, (outs VR64:$dst), (ins),
493 "pcmpeqd $dst, $dst",
494 [(set VR64:$dst, (v1i64 immAllOnesV))]>;
497 //===----------------------------------------------------------------------===//
498 // Non-Instruction Patterns
499 //===----------------------------------------------------------------------===//
501 // Store 64-bit integer vector values.
502 def : Pat<(store (v8i8 VR64:$src), addr:$dst),
503 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
504 def : Pat<(store (v4i16 VR64:$src), addr:$dst),
505 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
506 def : Pat<(store (v2i32 VR64:$src), addr:$dst),
507 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
508 def : Pat<(store (v1i64 VR64:$src), addr:$dst),
509 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
511 // 64-bit vector all zero's.
512 def : Pat<(v8i8 immAllZerosV), (MMX_V_SET0)>;
513 def : Pat<(v4i16 immAllZerosV), (MMX_V_SET0)>;
514 def : Pat<(v2i32 immAllZerosV), (MMX_V_SET0)>;
515 def : Pat<(v1i64 immAllZerosV), (MMX_V_SET0)>;
517 // 64-bit vector all one's.
518 def : Pat<(v8i8 immAllOnesV), (MMX_V_SETALLONES)>;
519 def : Pat<(v4i16 immAllOnesV), (MMX_V_SETALLONES)>;
520 def : Pat<(v2i32 immAllOnesV), (MMX_V_SETALLONES)>;
521 def : Pat<(v1i64 immAllOnesV), (MMX_V_SETALLONES)>;
524 def : Pat<(v8i8 (bitconvert (v1i64 VR64:$src))), (v8i8 VR64:$src)>;
525 def : Pat<(v8i8 (bitconvert (v2i32 VR64:$src))), (v8i8 VR64:$src)>;
526 def : Pat<(v8i8 (bitconvert (v4i16 VR64:$src))), (v8i8 VR64:$src)>;
527 def : Pat<(v4i16 (bitconvert (v1i64 VR64:$src))), (v4i16 VR64:$src)>;
528 def : Pat<(v4i16 (bitconvert (v2i32 VR64:$src))), (v4i16 VR64:$src)>;
529 def : Pat<(v4i16 (bitconvert (v8i8 VR64:$src))), (v4i16 VR64:$src)>;
530 def : Pat<(v2i32 (bitconvert (v1i64 VR64:$src))), (v2i32 VR64:$src)>;
531 def : Pat<(v2i32 (bitconvert (v4i16 VR64:$src))), (v2i32 VR64:$src)>;
532 def : Pat<(v2i32 (bitconvert (v8i8 VR64:$src))), (v2i32 VR64:$src)>;
533 def : Pat<(v1i64 (bitconvert (v2i32 VR64:$src))), (v1i64 VR64:$src)>;
534 def : Pat<(v1i64 (bitconvert (v4i16 VR64:$src))), (v1i64 VR64:$src)>;
535 def : Pat<(v1i64 (bitconvert (v8i8 VR64:$src))), (v1i64 VR64:$src)>;
537 // 64-bit bit convert.
538 def : Pat<(v1i64 (bitconvert (i64 GR64:$src))),
539 (MMX_MOVD64to64rr GR64:$src)>;
540 def : Pat<(v2i32 (bitconvert (i64 GR64:$src))),
541 (MMX_MOVD64to64rr GR64:$src)>;
542 def : Pat<(v4i16 (bitconvert (i64 GR64:$src))),
543 (MMX_MOVD64to64rr GR64:$src)>;
544 def : Pat<(v8i8 (bitconvert (i64 GR64:$src))),
545 (MMX_MOVD64to64rr GR64:$src)>;
547 def MMX_X86s2vec : SDNode<"X86ISD::S2VEC", SDTypeProfile<1, 1, []>, []>;
549 // Move scalar to XMM zero-extended
550 // movd to XMM register zero-extends
551 let AddedComplexity = 15 in {
552 def : Pat<(v8i8 (vector_shuffle immAllZerosV,
553 (v8i8 (MMX_X86s2vec GR32:$src)), MMX_MOVL_shuffle_mask)),
554 (MMX_MOVZDI2PDIrr GR32:$src)>;
555 def : Pat<(v4i16 (vector_shuffle immAllZerosV,
556 (v4i16 (MMX_X86s2vec GR32:$src)), MMX_MOVL_shuffle_mask)),
557 (MMX_MOVZDI2PDIrr GR32:$src)>;
558 def : Pat<(v2i32 (vector_shuffle immAllZerosV,
559 (v2i32 (MMX_X86s2vec GR32:$src)), MMX_MOVL_shuffle_mask)),
560 (MMX_MOVZDI2PDIrr GR32:$src)>;
563 // Scalar to v2i32 / v4i16 / v8i8. The source may be a GR32, but only the lower
564 // 8 or 16-bits matter.
565 def : Pat<(v8i8 (MMX_X86s2vec GR32:$src)), (MMX_MOVD64rr GR32:$src)>;
566 def : Pat<(v4i16 (MMX_X86s2vec GR32:$src)), (MMX_MOVD64rr GR32:$src)>;
567 def : Pat<(v2i32 (MMX_X86s2vec GR32:$src)), (MMX_MOVD64rr GR32:$src)>;
569 // Patterns to perform canonical versions of vector shuffling.
570 let AddedComplexity = 10 in {
571 def : Pat<(v8i8 (vector_shuffle VR64:$src, (undef),
572 MMX_UNPCKL_v_undef_shuffle_mask)),
573 (MMX_PUNPCKLBWrr VR64:$src, VR64:$src)>;
574 def : Pat<(v4i16 (vector_shuffle VR64:$src, (undef),
575 MMX_UNPCKL_v_undef_shuffle_mask)),
576 (MMX_PUNPCKLWDrr VR64:$src, VR64:$src)>;
577 def : Pat<(v2i32 (vector_shuffle VR64:$src, (undef),
578 MMX_UNPCKL_v_undef_shuffle_mask)),
579 (MMX_PUNPCKLDQrr VR64:$src, VR64:$src)>;
582 let AddedComplexity = 10 in {
583 def : Pat<(v8i8 (vector_shuffle VR64:$src, (undef),
584 MMX_UNPCKH_v_undef_shuffle_mask)),
585 (MMX_PUNPCKHBWrr VR64:$src, VR64:$src)>;
586 def : Pat<(v4i16 (vector_shuffle VR64:$src, (undef),
587 MMX_UNPCKH_v_undef_shuffle_mask)),
588 (MMX_PUNPCKHWDrr VR64:$src, VR64:$src)>;
589 def : Pat<(v2i32 (vector_shuffle VR64:$src, (undef),
590 MMX_UNPCKH_v_undef_shuffle_mask)),
591 (MMX_PUNPCKHDQrr VR64:$src, VR64:$src)>;
594 // Patterns to perform vector shuffling with a zeroed out vector.
595 let AddedComplexity = 20 in {
596 def : Pat<(bc_v2i32 (vector_shuffle immAllZerosV,
597 (v2i32 (scalar_to_vector (load_mmx addr:$src))),
598 MMX_UNPCKL_shuffle_mask)),
599 (MMX_PUNPCKLDQrm VR64:$src, VR64:$src)>;
602 // Some special case PANDN patterns.
603 // FIXME: Get rid of these.
604 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v2i32 immAllOnesV))),
606 (MMX_PANDNrr VR64:$src1, VR64:$src2)>;
607 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v4i16 immAllOnesV))),
609 (MMX_PANDNrr VR64:$src1, VR64:$src2)>;
610 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v8i8 immAllOnesV))),
612 (MMX_PANDNrr VR64:$src1, VR64:$src2)>;
614 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v2i32 immAllOnesV))),
616 (MMX_PANDNrm VR64:$src1, addr:$src2)>;
617 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v4i16 immAllOnesV))),
619 (MMX_PANDNrm VR64:$src1, addr:$src2)>;
620 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v8i8 immAllOnesV))),
622 (MMX_PANDNrm VR64:$src1, addr:$src2)>;