1 //===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmps : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
27 //def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
29 def SDTX86Cmov : SDTypeProfile<1, 4,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
33 // Unary and binary operator instructions that set EFLAGS as a side-effect.
34 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
36 SDTCisInt<0>, SDTCisVT<1, i32>]>;
38 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
41 SDTCisInt<0>, SDTCisVT<1, i32>]>;
43 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
44 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
50 // RES1, RES2, FLAGS = op LHS, RHS
51 def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2,
55 SDTCisInt<0>, SDTCisVT<1, i32>]>;
56 def SDTX86BrCond : SDTypeProfile<0, 3,
57 [SDTCisVT<0, OtherVT>,
58 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
60 def SDTX86SetCC : SDTypeProfile<1, 2,
62 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
63 def SDTX86SetCC_C : SDTypeProfile<1, 2,
65 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
67 def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>;
69 def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>;
71 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
73 def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
75 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
76 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
77 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
79 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
80 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
83 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
85 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
89 def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
95 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
97 def SDTX86Void : SDTypeProfile<0, 0, []>;
99 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
101 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
103 def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
105 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
107 def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
109 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
111 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
113 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
115 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
116 [SDNPHasChain,SDNPSideEffect]>;
117 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
119 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
121 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
125 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
126 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
127 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
128 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
130 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
131 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
133 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
134 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
136 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
137 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
139 def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>;
141 def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand,
142 [SDNPHasChain, SDNPSideEffect]>;
144 def X86rdseed : SDNode<"X86ISD::RDSEED", SDTX86rdrand,
145 [SDNPHasChain, SDNPSideEffect]>;
147 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
148 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
149 SDNPMayLoad, SDNPMemOperand]>;
150 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair,
151 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
152 SDNPMayLoad, SDNPMemOperand]>;
153 def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair,
154 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
155 SDNPMayLoad, SDNPMemOperand]>;
157 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
158 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
159 def X86iret : SDNode<"X86ISD::IRET", SDTX86Ret,
160 [SDNPHasChain, SDNPOptInGlue]>;
162 def X86vastart_save_xmm_regs :
163 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
164 SDT_X86VASTART_SAVE_XMM_REGS,
165 [SDNPHasChain, SDNPVariadic]>;
167 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64,
168 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
170 def X86callseq_start :
171 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
172 [SDNPHasChain, SDNPOutGlue]>;
174 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
175 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
177 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
178 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
181 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
182 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>;
183 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
184 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
187 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
188 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
189 def X86rdtscp : SDNode<"X86ISD::RDTSCP_DAG", SDTX86Void,
190 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
191 def X86rdpmc : SDNode<"X86ISD::RDPMC_DAG", SDTX86Void,
192 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
194 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
195 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
197 def X86RecoverFrameAlloc : SDNode<"ISD::LOCAL_RECOVER",
198 SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
201 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
202 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
204 def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR,
205 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
207 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
210 def X86eh_sjlj_setjmp : SDNode<"X86ISD::EH_SJLJ_SETJMP",
211 SDTypeProfile<1, 1, [SDTCisInt<0>,
213 [SDNPHasChain, SDNPSideEffect]>;
214 def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP",
215 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
216 [SDNPHasChain, SDNPSideEffect]>;
218 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
219 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
221 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
223 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
224 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
226 def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags,
228 def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>;
229 def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>;
231 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
232 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
233 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
235 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
237 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
240 def X86bextr : SDNode<"X86ISD::BEXTR", SDTIntBinOp>;
242 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
244 def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void,
245 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
247 def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA,
250 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
251 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
253 //===----------------------------------------------------------------------===//
254 // X86 Operand Definitions.
257 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
258 // the index operand of an address, to conform to x86 encoding restrictions.
259 def ptr_rc_nosp : PointerLikeRegClass<1>;
261 // *mem - Operand definitions for the funky X86 addressing mode operands.
263 def X86MemAsmOperand : AsmOperandClass {
266 let RenderMethod = "addMemOperands" in {
267 def X86Mem8AsmOperand : AsmOperandClass { let Name = "Mem8"; }
268 def X86Mem16AsmOperand : AsmOperandClass { let Name = "Mem16"; }
269 def X86Mem32AsmOperand : AsmOperandClass { let Name = "Mem32"; }
270 def X86Mem64AsmOperand : AsmOperandClass { let Name = "Mem64"; }
271 def X86Mem80AsmOperand : AsmOperandClass { let Name = "Mem80"; }
272 def X86Mem128AsmOperand : AsmOperandClass { let Name = "Mem128"; }
273 def X86Mem256AsmOperand : AsmOperandClass { let Name = "Mem256"; }
274 def X86Mem512AsmOperand : AsmOperandClass { let Name = "Mem512"; }
275 // Gather mem operands
276 def X86MemVX32Operand : AsmOperandClass { let Name = "MemVX32"; }
277 def X86MemVY32Operand : AsmOperandClass { let Name = "MemVY32"; }
278 def X86MemVZ32Operand : AsmOperandClass { let Name = "MemVZ32"; }
279 def X86MemVX64Operand : AsmOperandClass { let Name = "MemVX64"; }
280 def X86MemVY64Operand : AsmOperandClass { let Name = "MemVY64"; }
281 def X86MemVZ64Operand : AsmOperandClass { let Name = "MemVZ64"; }
282 def X86MemVX32XOperand : AsmOperandClass { let Name = "MemVX32X"; }
283 def X86MemVY32XOperand : AsmOperandClass { let Name = "MemVY32X"; }
284 def X86MemVX64XOperand : AsmOperandClass { let Name = "MemVX64X"; }
285 def X86MemVY64XOperand : AsmOperandClass { let Name = "MemVY64X"; }
288 def X86AbsMemAsmOperand : AsmOperandClass {
290 let SuperClasses = [X86MemAsmOperand];
293 class X86MemOperand<string printMethod,
294 AsmOperandClass parserMatchClass = X86MemAsmOperand> : Operand<iPTR> {
295 let PrintMethod = printMethod;
296 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
297 let ParserMatchClass = parserMatchClass;
298 let OperandType = "OPERAND_MEMORY";
301 // Gather mem operands
302 class X86VMemOperand<RegisterClass RC, string printMethod,
303 AsmOperandClass parserMatchClass>
304 : X86MemOperand<printMethod, parserMatchClass> {
305 let MIOperandInfo = (ops ptr_rc, i8imm, RC, i32imm, i8imm);
308 def anymem : X86MemOperand<"printanymem">;
310 def opaque32mem : X86MemOperand<"printopaquemem">;
311 def opaque48mem : X86MemOperand<"printopaquemem">;
312 def opaque80mem : X86MemOperand<"printopaquemem">;
313 def opaque512mem : X86MemOperand<"printopaquemem">;
315 def i8mem : X86MemOperand<"printi8mem", X86Mem8AsmOperand>;
316 def i16mem : X86MemOperand<"printi16mem", X86Mem16AsmOperand>;
317 def i32mem : X86MemOperand<"printi32mem", X86Mem32AsmOperand>;
318 def i64mem : X86MemOperand<"printi64mem", X86Mem64AsmOperand>;
319 def i128mem : X86MemOperand<"printi128mem", X86Mem128AsmOperand>;
320 def i256mem : X86MemOperand<"printi256mem", X86Mem256AsmOperand>;
321 def i512mem : X86MemOperand<"printi512mem", X86Mem512AsmOperand>;
322 def f32mem : X86MemOperand<"printf32mem", X86Mem32AsmOperand>;
323 def f64mem : X86MemOperand<"printf64mem", X86Mem64AsmOperand>;
324 def f80mem : X86MemOperand<"printf80mem", X86Mem80AsmOperand>;
325 def f128mem : X86MemOperand<"printf128mem", X86Mem128AsmOperand>;
326 def f256mem : X86MemOperand<"printf256mem", X86Mem256AsmOperand>;
327 def f512mem : X86MemOperand<"printf512mem", X86Mem512AsmOperand>;
329 def v512mem : X86VMemOperand<VR512, "printf512mem", X86Mem512AsmOperand>;
331 // Gather mem operands
332 def vx32mem : X86VMemOperand<VR128, "printi32mem", X86MemVX32Operand>;
333 def vy32mem : X86VMemOperand<VR256, "printi32mem", X86MemVY32Operand>;
334 def vx64mem : X86VMemOperand<VR128, "printi64mem", X86MemVX64Operand>;
335 def vy64mem : X86VMemOperand<VR256, "printi64mem", X86MemVY64Operand>;
337 def vx32xmem : X86VMemOperand<VR128X, "printi32mem", X86MemVX32XOperand>;
338 def vx64xmem : X86VMemOperand<VR128X, "printi32mem", X86MemVX64XOperand>;
339 def vy32xmem : X86VMemOperand<VR256X, "printi32mem", X86MemVY32XOperand>;
340 def vy64xmem : X86VMemOperand<VR256X, "printi64mem", X86MemVY64XOperand>;
341 def vz32mem : X86VMemOperand<VR512, "printi32mem", X86MemVZ32Operand>;
342 def vz64mem : X86VMemOperand<VR512, "printi64mem", X86MemVZ64Operand>;
344 // A version of i8mem for use on x86-64 and x32 that uses a NOREX GPR instead
345 // of a plain GPR, so that it doesn't potentially require a REX prefix.
346 def ptr_rc_norex : PointerLikeRegClass<2>;
347 def ptr_rc_norex_nosp : PointerLikeRegClass<3>;
349 def i8mem_NOREX : Operand<iPTR> {
350 let PrintMethod = "printi8mem";
351 let MIOperandInfo = (ops ptr_rc_norex, i8imm, ptr_rc_norex_nosp, i32imm, i8imm);
352 let ParserMatchClass = X86Mem8AsmOperand;
353 let OperandType = "OPERAND_MEMORY";
356 // GPRs available for tailcall.
357 // It represents GR32_TC, GR64_TC or GR64_TCW64.
358 def ptr_rc_tailcall : PointerLikeRegClass<4>;
360 // Special i32mem for addresses of load folding tail calls. These are not
361 // allowed to use callee-saved registers since they must be scheduled
362 // after callee-saved register are popped.
363 def i32mem_TC : Operand<i32> {
364 let PrintMethod = "printi32mem";
365 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall,
367 let ParserMatchClass = X86Mem32AsmOperand;
368 let OperandType = "OPERAND_MEMORY";
371 // Special i64mem for addresses of load folding tail calls. These are not
372 // allowed to use callee-saved registers since they must be scheduled
373 // after callee-saved register are popped.
374 def i64mem_TC : Operand<i64> {
375 let PrintMethod = "printi64mem";
376 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm,
377 ptr_rc_tailcall, i32imm, i8imm);
378 let ParserMatchClass = X86Mem64AsmOperand;
379 let OperandType = "OPERAND_MEMORY";
382 let OperandType = "OPERAND_PCREL",
383 ParserMatchClass = X86AbsMemAsmOperand,
384 PrintMethod = "printPCRelImm" in {
385 def i32imm_pcrel : Operand<i32>;
386 def i16imm_pcrel : Operand<i16>;
388 // Branch targets have OtherVT type and print as pc-relative values.
389 def brtarget : Operand<OtherVT>;
390 def brtarget8 : Operand<OtherVT>;
394 // Special parser to detect 16-bit mode to select 16-bit displacement.
395 def X86AbsMem16AsmOperand : AsmOperandClass {
396 let Name = "AbsMem16";
397 let RenderMethod = "addAbsMemOperands";
398 let SuperClasses = [X86AbsMemAsmOperand];
401 // Branch targets have OtherVT type and print as pc-relative values.
402 let OperandType = "OPERAND_PCREL",
403 PrintMethod = "printPCRelImm" in {
404 let ParserMatchClass = X86AbsMem16AsmOperand in
405 def brtarget16 : Operand<OtherVT>;
406 let ParserMatchClass = X86AbsMemAsmOperand in
407 def brtarget32 : Operand<OtherVT>;
410 let RenderMethod = "addSrcIdxOperands" in {
411 def X86SrcIdx8Operand : AsmOperandClass {
412 let Name = "SrcIdx8";
413 let SuperClasses = [X86Mem8AsmOperand];
415 def X86SrcIdx16Operand : AsmOperandClass {
416 let Name = "SrcIdx16";
417 let SuperClasses = [X86Mem16AsmOperand];
419 def X86SrcIdx32Operand : AsmOperandClass {
420 let Name = "SrcIdx32";
421 let SuperClasses = [X86Mem32AsmOperand];
423 def X86SrcIdx64Operand : AsmOperandClass {
424 let Name = "SrcIdx64";
425 let SuperClasses = [X86Mem64AsmOperand];
427 } // RenderMethod = "addSrcIdxOperands"
429 let RenderMethod = "addDstIdxOperands" in {
430 def X86DstIdx8Operand : AsmOperandClass {
431 let Name = "DstIdx8";
432 let SuperClasses = [X86Mem8AsmOperand];
434 def X86DstIdx16Operand : AsmOperandClass {
435 let Name = "DstIdx16";
436 let SuperClasses = [X86Mem16AsmOperand];
438 def X86DstIdx32Operand : AsmOperandClass {
439 let Name = "DstIdx32";
440 let SuperClasses = [X86Mem32AsmOperand];
442 def X86DstIdx64Operand : AsmOperandClass {
443 let Name = "DstIdx64";
444 let SuperClasses = [X86Mem64AsmOperand];
446 } // RenderMethod = "addDstIdxOperands"
448 let RenderMethod = "addMemOffsOperands" in {
449 def X86MemOffs16_8AsmOperand : AsmOperandClass {
450 let Name = "MemOffs16_8";
451 let SuperClasses = [X86Mem8AsmOperand];
453 def X86MemOffs16_16AsmOperand : AsmOperandClass {
454 let Name = "MemOffs16_16";
455 let SuperClasses = [X86Mem16AsmOperand];
457 def X86MemOffs16_32AsmOperand : AsmOperandClass {
458 let Name = "MemOffs16_32";
459 let SuperClasses = [X86Mem32AsmOperand];
461 def X86MemOffs32_8AsmOperand : AsmOperandClass {
462 let Name = "MemOffs32_8";
463 let SuperClasses = [X86Mem8AsmOperand];
465 def X86MemOffs32_16AsmOperand : AsmOperandClass {
466 let Name = "MemOffs32_16";
467 let SuperClasses = [X86Mem16AsmOperand];
469 def X86MemOffs32_32AsmOperand : AsmOperandClass {
470 let Name = "MemOffs32_32";
471 let SuperClasses = [X86Mem32AsmOperand];
473 def X86MemOffs32_64AsmOperand : AsmOperandClass {
474 let Name = "MemOffs32_64";
475 let SuperClasses = [X86Mem64AsmOperand];
477 def X86MemOffs64_8AsmOperand : AsmOperandClass {
478 let Name = "MemOffs64_8";
479 let SuperClasses = [X86Mem8AsmOperand];
481 def X86MemOffs64_16AsmOperand : AsmOperandClass {
482 let Name = "MemOffs64_16";
483 let SuperClasses = [X86Mem16AsmOperand];
485 def X86MemOffs64_32AsmOperand : AsmOperandClass {
486 let Name = "MemOffs64_32";
487 let SuperClasses = [X86Mem32AsmOperand];
489 def X86MemOffs64_64AsmOperand : AsmOperandClass {
490 let Name = "MemOffs64_64";
491 let SuperClasses = [X86Mem64AsmOperand];
493 } // RenderMethod = "addMemOffsOperands"
495 class X86SrcIdxOperand<string printMethod, AsmOperandClass parserMatchClass>
496 : X86MemOperand<printMethod, parserMatchClass> {
497 let MIOperandInfo = (ops ptr_rc, i8imm);
500 class X86DstIdxOperand<string printMethod, AsmOperandClass parserMatchClass>
501 : X86MemOperand<printMethod, parserMatchClass> {
502 let MIOperandInfo = (ops ptr_rc);
505 def srcidx8 : X86SrcIdxOperand<"printSrcIdx8", X86SrcIdx8Operand>;
506 def srcidx16 : X86SrcIdxOperand<"printSrcIdx16", X86SrcIdx16Operand>;
507 def srcidx32 : X86SrcIdxOperand<"printSrcIdx32", X86SrcIdx32Operand>;
508 def srcidx64 : X86SrcIdxOperand<"printSrcIdx64", X86SrcIdx64Operand>;
509 def dstidx8 : X86DstIdxOperand<"printDstIdx8", X86DstIdx8Operand>;
510 def dstidx16 : X86DstIdxOperand<"printDstIdx16", X86DstIdx16Operand>;
511 def dstidx32 : X86DstIdxOperand<"printDstIdx32", X86DstIdx32Operand>;
512 def dstidx64 : X86DstIdxOperand<"printDstIdx64", X86DstIdx64Operand>;
514 class X86MemOffsOperand<Operand immOperand, string printMethod,
515 AsmOperandClass parserMatchClass>
516 : X86MemOperand<printMethod, parserMatchClass> {
517 let MIOperandInfo = (ops immOperand, i8imm);
520 def offset16_8 : X86MemOffsOperand<i16imm, "printMemOffs8",
521 X86MemOffs16_8AsmOperand>;
522 def offset16_16 : X86MemOffsOperand<i16imm, "printMemOffs16",
523 X86MemOffs16_16AsmOperand>;
524 def offset16_32 : X86MemOffsOperand<i16imm, "printMemOffs32",
525 X86MemOffs16_32AsmOperand>;
526 def offset32_8 : X86MemOffsOperand<i32imm, "printMemOffs8",
527 X86MemOffs32_8AsmOperand>;
528 def offset32_16 : X86MemOffsOperand<i32imm, "printMemOffs16",
529 X86MemOffs32_16AsmOperand>;
530 def offset32_32 : X86MemOffsOperand<i32imm, "printMemOffs32",
531 X86MemOffs32_32AsmOperand>;
532 def offset32_64 : X86MemOffsOperand<i32imm, "printMemOffs64",
533 X86MemOffs32_64AsmOperand>;
534 def offset64_8 : X86MemOffsOperand<i64imm, "printMemOffs8",
535 X86MemOffs64_8AsmOperand>;
536 def offset64_16 : X86MemOffsOperand<i64imm, "printMemOffs16",
537 X86MemOffs64_16AsmOperand>;
538 def offset64_32 : X86MemOffsOperand<i64imm, "printMemOffs32",
539 X86MemOffs64_32AsmOperand>;
540 def offset64_64 : X86MemOffsOperand<i64imm, "printMemOffs64",
541 X86MemOffs64_64AsmOperand>;
543 def SSECC : Operand<i8> {
544 let PrintMethod = "printSSEAVXCC";
545 let OperandType = "OPERAND_IMMEDIATE";
548 def i8immZExt3 : ImmLeaf<i8, [{
549 return Imm >= 0 && Imm < 8;
552 def AVXCC : Operand<i8> {
553 let PrintMethod = "printSSEAVXCC";
554 let OperandType = "OPERAND_IMMEDIATE";
557 def i8immZExt5 : ImmLeaf<i8, [{
558 return Imm >= 0 && Imm < 32;
561 def AVX512ICC : Operand<i8> {
562 let PrintMethod = "printSSEAVXCC";
563 let OperandType = "OPERAND_IMMEDIATE";
566 def XOPCC : Operand<i8> {
567 let PrintMethod = "printXOPCC";
568 let OperandType = "OPERAND_IMMEDIATE";
571 class ImmSExtAsmOperandClass : AsmOperandClass {
572 let SuperClasses = [ImmAsmOperand];
573 let RenderMethod = "addImmOperands";
576 def X86GR32orGR64AsmOperand : AsmOperandClass {
577 let Name = "GR32orGR64";
580 def GR32orGR64 : RegisterOperand<GR32> {
581 let ParserMatchClass = X86GR32orGR64AsmOperand;
583 def AVX512RCOperand : AsmOperandClass {
584 let Name = "AVX512RC";
586 def AVX512RC : Operand<i32> {
587 let PrintMethod = "printRoundingControl";
588 let OperandType = "OPERAND_IMMEDIATE";
589 let ParserMatchClass = AVX512RCOperand;
592 // Sign-extended immediate classes. We don't need to define the full lattice
593 // here because there is no instruction with an ambiguity between ImmSExti64i32
596 // The strange ranges come from the fact that the assembler always works with
597 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
598 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
601 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
602 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
603 let Name = "ImmSExti64i32";
606 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
607 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
608 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
609 let Name = "ImmSExti16i8";
610 let SuperClasses = [ImmSExti64i32AsmOperand];
613 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
614 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
615 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
616 let Name = "ImmSExti32i8";
620 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
621 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
622 let Name = "ImmSExti64i8";
623 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
624 ImmSExti64i32AsmOperand];
627 // Unsigned immediate used by SSE/AVX instructions
629 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
630 def ImmUnsignedi8AsmOperand : AsmOperandClass {
631 let Name = "ImmUnsignedi8";
632 let RenderMethod = "addImmOperands";
635 // A couple of more descriptive operand definitions.
636 // 16-bits but only 8 bits are significant.
637 def i16i8imm : Operand<i16> {
638 let ParserMatchClass = ImmSExti16i8AsmOperand;
639 let OperandType = "OPERAND_IMMEDIATE";
641 // 32-bits but only 8 bits are significant.
642 def i32i8imm : Operand<i32> {
643 let ParserMatchClass = ImmSExti32i8AsmOperand;
644 let OperandType = "OPERAND_IMMEDIATE";
647 // 64-bits but only 32 bits are significant.
648 def i64i32imm : Operand<i64> {
649 let ParserMatchClass = ImmSExti64i32AsmOperand;
650 let OperandType = "OPERAND_IMMEDIATE";
653 // 64-bits but only 8 bits are significant.
654 def i64i8imm : Operand<i64> {
655 let ParserMatchClass = ImmSExti64i8AsmOperand;
656 let OperandType = "OPERAND_IMMEDIATE";
659 // Unsigned 8-bit immediate used by SSE/AVX instructions.
660 def u8imm : Operand<i8> {
661 let PrintMethod = "printU8Imm";
662 let ParserMatchClass = ImmUnsignedi8AsmOperand;
663 let OperandType = "OPERAND_IMMEDIATE";
666 // 32-bit immediate but only 8-bits are significant and they are unsigned.
667 // Used by some SSE/AVX instructions that use intrinsics.
668 def i32u8imm : Operand<i32> {
669 let PrintMethod = "printU8Imm";
670 let ParserMatchClass = ImmUnsignedi8AsmOperand;
671 let OperandType = "OPERAND_IMMEDIATE";
674 // 64-bits but only 32 bits are significant, and those bits are treated as being
676 def i64i32imm_pcrel : Operand<i64> {
677 let PrintMethod = "printPCRelImm";
678 let ParserMatchClass = X86AbsMemAsmOperand;
679 let OperandType = "OPERAND_PCREL";
682 def lea64_32mem : Operand<i32> {
683 let PrintMethod = "printanymem";
684 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
685 let ParserMatchClass = X86MemAsmOperand;
688 // Memory operands that use 64-bit pointers in both ILP32 and LP64.
689 def lea64mem : Operand<i64> {
690 let PrintMethod = "printanymem";
691 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
692 let ParserMatchClass = X86MemAsmOperand;
696 //===----------------------------------------------------------------------===//
697 // X86 Complex Pattern Definitions.
700 // Define X86-specific addressing mode.
701 def addr : ComplexPattern<iPTR, 5, "selectAddr", [], [SDNPWantParent]>;
702 def lea32addr : ComplexPattern<i32, 5, "selectLEAAddr",
703 [add, sub, mul, X86mul_imm, shl, or, frameindex],
705 // In 64-bit mode 32-bit LEAs can use RIP-relative addressing.
706 def lea64_32addr : ComplexPattern<i32, 5, "selectLEA64_32Addr",
707 [add, sub, mul, X86mul_imm, shl, or,
708 frameindex, X86WrapperRIP],
711 def tls32addr : ComplexPattern<i32, 5, "selectTLSADDRAddr",
712 [tglobaltlsaddr], []>;
714 def tls32baseaddr : ComplexPattern<i32, 5, "selectTLSADDRAddr",
715 [tglobaltlsaddr], []>;
717 def lea64addr : ComplexPattern<i64, 5, "selectLEAAddr",
718 [add, sub, mul, X86mul_imm, shl, or, frameindex,
721 def tls64addr : ComplexPattern<i64, 5, "selectTLSADDRAddr",
722 [tglobaltlsaddr], []>;
724 def tls64baseaddr : ComplexPattern<i64, 5, "selectTLSADDRAddr",
725 [tglobaltlsaddr], []>;
727 def vectoraddr : ComplexPattern<iPTR, 5, "selectVectorAddr", [],[SDNPWantParent]>;
729 //===----------------------------------------------------------------------===//
730 // X86 Instruction Predicate Definitions.
731 def HasCMov : Predicate<"Subtarget->hasCMov()">;
732 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
734 def HasMMX : Predicate<"Subtarget->hasMMX()">;
735 def Has3DNow : Predicate<"Subtarget->has3DNow()">;
736 def Has3DNowA : Predicate<"Subtarget->has3DNowA()">;
737 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
738 def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">;
739 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
740 def UseSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">;
741 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
742 def UseSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">;
743 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
744 def UseSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">;
745 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
746 def NoSSE41 : Predicate<"!Subtarget->hasSSE41()">;
747 def UseSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">;
748 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
749 def UseSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">;
750 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
751 def HasAVX : Predicate<"Subtarget->hasAVX()">;
752 def HasAVX2 : Predicate<"Subtarget->hasAVX2()">;
753 def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">;
754 def HasAVX512 : Predicate<"Subtarget->hasAVX512()">,
755 AssemblerPredicate<"FeatureAVX512", "AVX-512 ISA">;
756 def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">;
757 def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">;
758 def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">;
759 def HasCDI : Predicate<"Subtarget->hasCDI()">,
760 AssemblerPredicate<"FeatureCDI", "AVX-512 CD ISA">;
761 def HasPFI : Predicate<"Subtarget->hasPFI()">,
762 AssemblerPredicate<"FeaturePFI", "AVX-512 PF ISA">;
763 def HasERI : Predicate<"Subtarget->hasERI()">,
764 AssemblerPredicate<"FeatureERI", "AVX-512 ER ISA">;
765 def HasDQI : Predicate<"Subtarget->hasDQI()">,
766 AssemblerPredicate<"FeatureDQI", "AVX-512 DQ ISA">;
767 def NoDQI : Predicate<"!Subtarget->hasDQI()">;
768 def HasBWI : Predicate<"Subtarget->hasBWI()">,
769 AssemblerPredicate<"FeatureBWI", "AVX-512 BW ISA">;
770 def NoBWI : Predicate<"!Subtarget->hasBWI()">;
771 def HasVLX : Predicate<"Subtarget->hasVLX()">,
772 AssemblerPredicate<"FeatureVLX", "AVX-512 VL ISA">;
773 def NoVLX : Predicate<"!Subtarget->hasVLX()">;
774 def NoVLX_Or_NoBWI : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasBWI()">;
775 def NoVLX_Or_NoDQI : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasDQI()">;
776 def PKU : Predicate<"!Subtarget->hasPKU()">;
778 def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;
779 def HasAES : Predicate<"Subtarget->hasAES()">;
780 def HasFXSR : Predicate<"Subtarget->hasFXSR()">;
781 def HasXSAVE : Predicate<"Subtarget->hasXSAVE()">;
782 def HasXSAVEOPT : Predicate<"Subtarget->hasXSAVEOPT()">;
783 def HasXSAVEC : Predicate<"Subtarget->hasXSAVEC()">;
784 def HasXSAVES : Predicate<"Subtarget->hasXSAVES()">;
785 def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">;
786 def HasFMA : Predicate<"Subtarget->hasFMA()">;
787 def UseFMAOnAVX : Predicate<"Subtarget->hasFMA() && !Subtarget->hasAVX512()">;
788 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
789 def HasXOP : Predicate<"Subtarget->hasXOP()">;
790 def HasTBM : Predicate<"Subtarget->hasTBM()">;
791 def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">;
792 def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;
793 def HasF16C : Predicate<"Subtarget->hasF16C()">;
794 def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">;
795 def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">;
796 def HasBMI : Predicate<"Subtarget->hasBMI()">;
797 def HasBMI2 : Predicate<"Subtarget->hasBMI2()">;
798 def HasRTM : Predicate<"Subtarget->hasRTM()">;
799 def HasHLE : Predicate<"Subtarget->hasHLE()">;
800 def HasTSX : Predicate<"Subtarget->hasRTM() || Subtarget->hasHLE()">;
801 def HasADX : Predicate<"Subtarget->hasADX()">;
802 def HasSHA : Predicate<"Subtarget->hasSHA()">;
803 def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">;
804 def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">;
805 def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">;
806 def HasLAHFSAHF : Predicate<"Subtarget->hasLAHFSAHF()">;
807 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
808 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
809 def HasMPX : Predicate<"Subtarget->hasMPX()">;
810 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
811 def Not64BitMode : Predicate<"!Subtarget->is64Bit()">,
812 AssemblerPredicate<"!Mode64Bit", "Not 64-bit mode">;
813 def In64BitMode : Predicate<"Subtarget->is64Bit()">,
814 AssemblerPredicate<"Mode64Bit", "64-bit mode">;
815 def IsLP64 : Predicate<"Subtarget->isTarget64BitLP64()">;
816 def NotLP64 : Predicate<"!Subtarget->isTarget64BitLP64()">;
817 def In16BitMode : Predicate<"Subtarget->is16Bit()">,
818 AssemblerPredicate<"Mode16Bit", "16-bit mode">;
819 def Not16BitMode : Predicate<"!Subtarget->is16Bit()">,
820 AssemblerPredicate<"!Mode16Bit", "Not 16-bit mode">;
821 def In32BitMode : Predicate<"Subtarget->is32Bit()">,
822 AssemblerPredicate<"Mode32Bit", "32-bit mode">;
823 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
824 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
825 def NotWin64WithoutFP : Predicate<"!Subtarget->isTargetWin64() ||"
826 "Subtarget->getFrameLowering()->hasFP(*MF)">;
827 def IsPS4 : Predicate<"Subtarget->isTargetPS4()">;
828 def NotPS4 : Predicate<"!Subtarget->isTargetPS4()">;
829 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
830 def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
831 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
832 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
833 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
834 "TM.getCodeModel() != CodeModel::Kernel">;
835 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
836 "TM.getCodeModel() == CodeModel::Kernel">;
837 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
838 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
839 def OptForSize : Predicate<"OptForSize">;
840 def OptForMinSize : Predicate<"OptForMinSize">;
841 def OptForSpeed : Predicate<"!OptForSize">;
842 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
843 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
844 def FavorMemIndirectCall : Predicate<"!Subtarget->callRegIndirect()">;
845 def NotSlowIncDec : Predicate<"!Subtarget->slowIncDec()">;
846 def HasFastMem32 : Predicate<"!Subtarget->isUnalignedMem32Slow()">;
848 //===----------------------------------------------------------------------===//
849 // X86 Instruction Format Definitions.
852 include "X86InstrFormats.td"
854 //===----------------------------------------------------------------------===//
855 // Pattern fragments.
858 // X86 specific condition code. These correspond to CondCode in
859 // X86InstrInfo.h. They must be kept in synch.
860 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
861 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
862 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
863 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
864 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
865 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
866 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
867 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
868 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
869 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
870 def X86_COND_NO : PatLeaf<(i8 10)>;
871 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
872 def X86_COND_NS : PatLeaf<(i8 12)>;
873 def X86_COND_O : PatLeaf<(i8 13)>;
874 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
875 def X86_COND_S : PatLeaf<(i8 15)>;
877 // Predicate used to help when pattern matching LZCNT/TZCNT.
878 def X86_COND_E_OR_NE : ImmLeaf<i8, [{
879 return (Imm == X86::COND_E) || (Imm == X86::COND_NE);
883 def i16immSExt8 : ImmLeaf<i16, [{ return isInt<8>(Imm); }]>;
884 def i32immSExt8 : ImmLeaf<i32, [{ return isInt<8>(Imm); }]>;
885 def i64immSExt8 : ImmLeaf<i64, [{ return isInt<8>(Imm); }]>;
887 // If we have multiple users of an immediate, it's much smaller to reuse
888 // the register, rather than encode the immediate in every instruction.
889 // This has the risk of increasing register pressure from stretched live
890 // ranges, however, the immediates should be trivial to rematerialize by
891 // the RA in the event of high register pressure.
892 // TODO : This is currently enabled for stores and binary ops. There are more
893 // cases for which this can be enabled, though this catches the bulk of the
895 // TODO2 : This should really also be enabled under O2, but there's currently
896 // an issue with RA where we don't pull the constants into their users
897 // when we rematerialize them. I'll follow-up on enabling O2 after we fix that
899 // TODO3 : This is currently limited to single basic blocks (DAG creation
900 // pulls block immediates to the top and merges them if necessary).
901 // Eventually, it would be nice to allow ConstantHoisting to merge constants
902 // globally for potentially added savings.
904 def imm8_su : PatLeaf<(i8 imm), [{
905 return !shouldAvoidImmediateInstFormsForSize(N);
907 def imm16_su : PatLeaf<(i16 imm), [{
908 return !shouldAvoidImmediateInstFormsForSize(N);
910 def imm32_su : PatLeaf<(i32 imm), [{
911 return !shouldAvoidImmediateInstFormsForSize(N);
914 def i16immSExt8_su : PatLeaf<(i16immSExt8), [{
915 return !shouldAvoidImmediateInstFormsForSize(N);
917 def i32immSExt8_su : PatLeaf<(i32immSExt8), [{
918 return !shouldAvoidImmediateInstFormsForSize(N);
922 def i64immSExt32 : ImmLeaf<i64, [{ return isInt<32>(Imm); }]>;
925 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
927 def i64immZExt32 : ImmLeaf<i64, [{ return isUInt<32>(Imm); }]>;
929 def i64immZExt32SExt8 : ImmLeaf<i64, [{
930 return isUInt<32>(Imm) && isInt<8>(static_cast<int32_t>(Imm));
933 // Helper fragments for loads.
934 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
935 // known to be 32-bit aligned or better. Ditto for i8 to i16.
936 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
937 LoadSDNode *LD = cast<LoadSDNode>(N);
938 ISD::LoadExtType ExtType = LD->getExtensionType();
939 if (ExtType == ISD::NON_EXTLOAD)
941 if (ExtType == ISD::EXTLOAD)
942 return LD->getAlignment() >= 2 && !LD->isVolatile();
946 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
947 LoadSDNode *LD = cast<LoadSDNode>(N);
948 ISD::LoadExtType ExtType = LD->getExtensionType();
949 if (ExtType == ISD::EXTLOAD)
950 return LD->getAlignment() >= 2 && !LD->isVolatile();
954 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
955 LoadSDNode *LD = cast<LoadSDNode>(N);
956 ISD::LoadExtType ExtType = LD->getExtensionType();
957 if (ExtType == ISD::NON_EXTLOAD)
959 if (ExtType == ISD::EXTLOAD)
960 return LD->getAlignment() >= 4 && !LD->isVolatile();
964 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
965 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
966 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
967 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
968 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
969 def loadf128 : PatFrag<(ops node:$ptr), (f128 (load node:$ptr))>;
971 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
972 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
973 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
974 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
975 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
976 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
978 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
979 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
980 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
981 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
982 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
983 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
984 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
985 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
986 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
987 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
989 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
990 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
991 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
992 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
993 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
994 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
995 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
996 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
997 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
998 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
1001 // An 'and' node with a single use.
1002 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
1003 return N->hasOneUse();
1005 // An 'srl' node with a single use.
1006 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
1007 return N->hasOneUse();
1009 // An 'trunc' node with a single use.
1010 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
1011 return N->hasOneUse();
1014 //===----------------------------------------------------------------------===//
1015 // Instruction list.
1019 let hasSideEffects = 0, SchedRW = [WriteZero] in {
1020 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>;
1021 def NOOPW : I<0x1f, MRMXm, (outs), (ins i16mem:$zero),
1022 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize16;
1023 def NOOPL : I<0x1f, MRMXm, (outs), (ins i32mem:$zero),
1024 "nop{l}\t$zero", [], IIC_NOP>, TB, OpSize32;
1028 // Constructing a stack frame.
1029 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
1030 "enter\t$len, $lvl", [], IIC_ENTER>, Sched<[WriteMicrocoded]>;
1032 let SchedRW = [WriteALU] in {
1033 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, hasSideEffects=0 in
1034 def LEAVE : I<0xC9, RawFrm,
1035 (outs), (ins), "leave", [], IIC_LEAVE>,
1036 Requires<[Not64BitMode]>;
1038 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, hasSideEffects = 0 in
1039 def LEAVE64 : I<0xC9, RawFrm,
1040 (outs), (ins), "leave", [], IIC_LEAVE>,
1041 Requires<[In64BitMode]>;
1044 //===----------------------------------------------------------------------===//
1045 // Miscellaneous Instructions.
1048 let Defs = [ESP], Uses = [ESP], hasSideEffects=0 in {
1049 let mayLoad = 1, SchedRW = [WriteLoad] in {
1050 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
1051 IIC_POP_REG16>, OpSize16;
1052 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
1053 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>;
1054 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
1055 IIC_POP_REG>, OpSize16;
1056 def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", [],
1057 IIC_POP_MEM>, OpSize16;
1058 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
1059 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>;
1060 def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", [],
1061 IIC_POP_MEM>, OpSize32, Requires<[Not64BitMode]>;
1062 } // mayLoad, SchedRW
1064 let mayStore = 1, SchedRW = [WriteStore] in {
1065 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
1066 IIC_PUSH_REG>, OpSize16;
1067 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
1068 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>;
1069 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
1070 IIC_PUSH_REG>, OpSize16;
1071 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
1072 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>;
1074 def PUSH16i8 : Ii8<0x6a, RawFrm, (outs), (ins i16i8imm:$imm),
1075 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16;
1076 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
1077 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16;
1079 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
1080 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
1081 Requires<[Not64BitMode]>;
1082 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
1083 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
1084 Requires<[Not64BitMode]>;
1085 } // mayStore, SchedRW
1087 let mayLoad = 1, mayStore = 1, SchedRW = [WriteRMW] in {
1088 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[],
1089 IIC_PUSH_MEM>, OpSize16;
1090 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[],
1091 IIC_PUSH_MEM>, OpSize32, Requires<[Not64BitMode]>;
1092 } // mayLoad, mayStore, SchedRW
1096 let mayLoad = 1, mayStore = 1, usesCustomInserter = 1,
1097 SchedRW = [WriteRMW], Defs = [ESP] in {
1098 let Uses = [ESP, EFLAGS] in
1099 def RDFLAGS32 : PseudoI<(outs GR32:$dst), (ins),
1100 [(set GR32:$dst, (int_x86_flags_read_u32))]>,
1101 Requires<[Not64BitMode]>;
1103 let Uses = [RSP, EFLAGS] in
1104 def RDFLAGS64 : PseudoI<(outs GR64:$dst), (ins),
1105 [(set GR64:$dst, (int_x86_flags_read_u64))]>,
1106 Requires<[In64BitMode]>;
1109 let mayLoad = 1, mayStore = 1, usesCustomInserter = 1,
1110 SchedRW = [WriteRMW] in {
1111 let Defs = [ESP, EFLAGS], Uses = [ESP] in
1112 def WRFLAGS32 : PseudoI<(outs), (ins GR32:$src),
1113 [(int_x86_flags_write_u32 GR32:$src)]>,
1114 Requires<[Not64BitMode]>;
1116 let Defs = [RSP, EFLAGS], Uses = [RSP] in
1117 def WRFLAGS64 : PseudoI<(outs), (ins GR64:$src),
1118 [(int_x86_flags_write_u64 GR64:$src)]>,
1119 Requires<[In64BitMode]>;
1122 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, hasSideEffects=0,
1123 SchedRW = [WriteLoad] in {
1124 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>,
1126 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [], IIC_POP_FD>,
1127 OpSize32, Requires<[Not64BitMode]>;
1130 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, hasSideEffects=0,
1131 SchedRW = [WriteStore] in {
1132 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>,
1134 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", [], IIC_PUSH_F>,
1135 OpSize32, Requires<[Not64BitMode]>;
1138 let Defs = [RSP], Uses = [RSP], hasSideEffects=0 in {
1139 let mayLoad = 1, SchedRW = [WriteLoad] in {
1140 def POP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
1141 IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>;
1142 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
1143 IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>;
1144 def POP64rmm: I<0x8F, MRM0m, (outs), (ins i64mem:$dst), "pop{q}\t$dst", [],
1145 IIC_POP_MEM>, OpSize32, Requires<[In64BitMode]>;
1146 } // mayLoad, SchedRW
1147 let mayStore = 1, SchedRW = [WriteStore] in {
1148 def PUSH64r : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
1149 IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>;
1150 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
1151 IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>;
1152 } // mayStore, SchedRW
1153 let mayLoad = 1, mayStore = 1, SchedRW = [WriteRMW] in {
1154 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", [],
1155 IIC_PUSH_MEM>, OpSize32, Requires<[In64BitMode]>;
1156 } // mayLoad, mayStore, SchedRW
1159 let Defs = [RSP], Uses = [RSP], hasSideEffects = 0, mayStore = 1,
1160 SchedRW = [WriteStore] in {
1161 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
1162 "push{q}\t$imm", [], IIC_PUSH_IMM>, Requires<[In64BitMode]>;
1163 def PUSH64i32 : Ii32S<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
1164 "push{q}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
1165 Requires<[In64BitMode]>;
1168 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in
1169 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", [], IIC_POP_FD>,
1170 OpSize32, Requires<[In64BitMode]>, Sched<[WriteLoad]>;
1171 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, hasSideEffects=0 in
1172 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>,
1173 OpSize32, Requires<[In64BitMode]>, Sched<[WriteStore]>;
1175 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
1176 mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteLoad] in {
1177 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popal", [], IIC_POP_A>,
1178 OpSize32, Requires<[Not64BitMode]>;
1179 def POPA16 : I<0x61, RawFrm, (outs), (ins), "popaw", [], IIC_POP_A>,
1180 OpSize16, Requires<[Not64BitMode]>;
1182 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
1183 mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
1184 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pushal", [], IIC_PUSH_A>,
1185 OpSize32, Requires<[Not64BitMode]>;
1186 def PUSHA16 : I<0x60, RawFrm, (outs), (ins), "pushaw", [], IIC_PUSH_A>,
1187 OpSize16, Requires<[Not64BitMode]>;
1190 let Constraints = "$src = $dst", SchedRW = [WriteALU] in {
1191 // GR32 = bswap GR32
1192 def BSWAP32r : I<0xC8, AddRegFrm,
1193 (outs GR32:$dst), (ins GR32:$src),
1195 [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, OpSize32, TB;
1197 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
1199 [(set GR64:$dst, (bswap GR64:$src))], IIC_BSWAP>, TB;
1200 } // Constraints = "$src = $dst", SchedRW
1202 // Bit scan instructions.
1203 let Defs = [EFLAGS] in {
1204 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1205 "bsf{w}\t{$src, $dst|$dst, $src}",
1206 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))],
1207 IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>;
1208 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1209 "bsf{w}\t{$src, $dst|$dst, $src}",
1210 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))],
1211 IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>;
1212 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1213 "bsf{l}\t{$src, $dst|$dst, $src}",
1214 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))],
1215 IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>;
1216 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1217 "bsf{l}\t{$src, $dst|$dst, $src}",
1218 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))],
1219 IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>;
1220 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1221 "bsf{q}\t{$src, $dst|$dst, $src}",
1222 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))],
1223 IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>;
1224 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1225 "bsf{q}\t{$src, $dst|$dst, $src}",
1226 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))],
1227 IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>;
1229 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1230 "bsr{w}\t{$src, $dst|$dst, $src}",
1231 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))],
1232 IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>;
1233 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1234 "bsr{w}\t{$src, $dst|$dst, $src}",
1235 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))],
1236 IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>;
1237 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1238 "bsr{l}\t{$src, $dst|$dst, $src}",
1239 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))],
1240 IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>;
1241 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1242 "bsr{l}\t{$src, $dst|$dst, $src}",
1243 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))],
1244 IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>;
1245 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1246 "bsr{q}\t{$src, $dst|$dst, $src}",
1247 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))],
1248 IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>;
1249 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1250 "bsr{q}\t{$src, $dst|$dst, $src}",
1251 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))],
1252 IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>;
1253 } // Defs = [EFLAGS]
1255 let SchedRW = [WriteMicrocoded] in {
1256 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1257 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
1258 def MOVSB : I<0xA4, RawFrmDstSrc, (outs dstidx8:$dst), (ins srcidx8:$src),
1259 "movsb\t{$src, $dst|$dst, $src}", [], IIC_MOVS>;
1260 def MOVSW : I<0xA5, RawFrmDstSrc, (outs dstidx16:$dst), (ins srcidx16:$src),
1261 "movsw\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize16;
1262 def MOVSL : I<0xA5, RawFrmDstSrc, (outs dstidx32:$dst), (ins srcidx32:$src),
1263 "movs{l|d}\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize32;
1264 def MOVSQ : RI<0xA5, RawFrmDstSrc, (outs dstidx64:$dst), (ins srcidx64:$src),
1265 "movsq\t{$src, $dst|$dst, $src}", [], IIC_MOVS>;
1268 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1269 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
1270 def STOSB : I<0xAA, RawFrmDst, (outs dstidx8:$dst), (ins),
1271 "stosb\t{%al, $dst|$dst, al}", [], IIC_STOS>;
1272 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
1273 def STOSW : I<0xAB, RawFrmDst, (outs dstidx16:$dst), (ins),
1274 "stosw\t{%ax, $dst|$dst, ax}", [], IIC_STOS>, OpSize16;
1275 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
1276 def STOSL : I<0xAB, RawFrmDst, (outs dstidx32:$dst), (ins),
1277 "stos{l|d}\t{%eax, $dst|$dst, eax}", [], IIC_STOS>, OpSize32;
1278 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
1279 def STOSQ : RI<0xAB, RawFrmDst, (outs dstidx64:$dst), (ins),
1280 "stosq\t{%rax, $dst|$dst, rax}", [], IIC_STOS>;
1282 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1283 let Defs = [EDI,EFLAGS], Uses = [AL,EDI,EFLAGS] in
1284 def SCASB : I<0xAE, RawFrmDst, (outs), (ins dstidx8:$dst),
1285 "scasb\t{$dst, %al|al, $dst}", [], IIC_SCAS>;
1286 let Defs = [EDI,EFLAGS], Uses = [AX,EDI,EFLAGS] in
1287 def SCASW : I<0xAF, RawFrmDst, (outs), (ins dstidx16:$dst),
1288 "scasw\t{$dst, %ax|ax, $dst}", [], IIC_SCAS>, OpSize16;
1289 let Defs = [EDI,EFLAGS], Uses = [EAX,EDI,EFLAGS] in
1290 def SCASL : I<0xAF, RawFrmDst, (outs), (ins dstidx32:$dst),
1291 "scas{l|d}\t{$dst, %eax|eax, $dst}", [], IIC_SCAS>, OpSize32;
1292 let Defs = [EDI,EFLAGS], Uses = [RAX,EDI,EFLAGS] in
1293 def SCASQ : RI<0xAF, RawFrmDst, (outs), (ins dstidx64:$dst),
1294 "scasq\t{$dst, %rax|rax, $dst}", [], IIC_SCAS>;
1296 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1297 let Defs = [EDI,ESI,EFLAGS], Uses = [EDI,ESI,EFLAGS] in {
1298 def CMPSB : I<0xA6, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src),
1299 "cmpsb\t{$dst, $src|$src, $dst}", [], IIC_CMPS>;
1300 def CMPSW : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src),
1301 "cmpsw\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize16;
1302 def CMPSL : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src),
1303 "cmps{l|d}\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize32;
1304 def CMPSQ : RI<0xA7, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src),
1305 "cmpsq\t{$dst, $src|$src, $dst}", [], IIC_CMPS>;
1309 //===----------------------------------------------------------------------===//
1310 // Move Instructions.
1312 let SchedRW = [WriteMove] in {
1313 let hasSideEffects = 0 in {
1314 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
1315 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1316 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1317 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1318 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1319 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
1320 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1321 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1324 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
1325 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
1326 "mov{b}\t{$src, $dst|$dst, $src}",
1327 [(set GR8:$dst, imm:$src)], IIC_MOV>;
1328 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
1329 "mov{w}\t{$src, $dst|$dst, $src}",
1330 [(set GR16:$dst, imm:$src)], IIC_MOV>, OpSize16;
1331 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
1332 "mov{l}\t{$src, $dst|$dst, $src}",
1333 [(set GR32:$dst, imm:$src)], IIC_MOV>, OpSize32;
1334 def MOV64ri32 : RIi32S<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
1335 "mov{q}\t{$src, $dst|$dst, $src}",
1336 [(set GR64:$dst, i64immSExt32:$src)], IIC_MOV>;
1338 let isReMaterializable = 1 in {
1339 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
1340 "movabs{q}\t{$src, $dst|$dst, $src}",
1341 [(set GR64:$dst, imm:$src)], IIC_MOV>;
1344 // Longer forms that use a ModR/M byte. Needed for disassembler
1345 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
1346 def MOV8ri_alt : Ii8 <0xC6, MRM0r, (outs GR8 :$dst), (ins i8imm :$src),
1347 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1348 def MOV16ri_alt : Ii16<0xC7, MRM0r, (outs GR16:$dst), (ins i16imm:$src),
1349 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1350 def MOV32ri_alt : Ii32<0xC7, MRM0r, (outs GR32:$dst), (ins i32imm:$src),
1351 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
1355 let SchedRW = [WriteStore] in {
1356 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
1357 "mov{b}\t{$src, $dst|$dst, $src}",
1358 [(store (i8 imm8_su:$src), addr:$dst)], IIC_MOV_MEM>;
1359 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
1360 "mov{w}\t{$src, $dst|$dst, $src}",
1361 [(store (i16 imm16_su:$src), addr:$dst)], IIC_MOV_MEM>, OpSize16;
1362 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
1363 "mov{l}\t{$src, $dst|$dst, $src}",
1364 [(store (i32 imm32_su:$src), addr:$dst)], IIC_MOV_MEM>, OpSize32;
1365 def MOV64mi32 : RIi32S<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1366 "mov{q}\t{$src, $dst|$dst, $src}",
1367 [(store i64immSExt32:$src, addr:$dst)], IIC_MOV_MEM>;
1370 let hasSideEffects = 0 in {
1372 /// Memory offset versions of moves. The immediate is an address mode sized
1373 /// offset from the segment base.
1374 let SchedRW = [WriteALU] in {
1375 let mayLoad = 1 in {
1377 def MOV8ao32 : Ii32<0xA0, RawFrmMemOffs, (outs), (ins offset32_8:$src),
1378 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>,
1381 def MOV16ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_16:$src),
1382 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>,
1385 def MOV32ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_32:$src),
1386 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
1389 def MOV64ao32 : RIi32<0xA1, RawFrmMemOffs, (outs), (ins offset32_64:$src),
1390 "mov{q}\t{$src, %rax|rax, $src}", [], IIC_MOV_MEM>,
1394 def MOV8ao16 : Ii16<0xA0, RawFrmMemOffs, (outs), (ins offset16_8:$src),
1395 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>, AdSize16;
1397 def MOV16ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_16:$src),
1398 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>,
1401 def MOV32ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_32:$src),
1402 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
1405 let mayStore = 1 in {
1407 def MOV8o32a : Ii32<0xA2, RawFrmMemOffs, (outs offset32_8:$dst), (ins),
1408 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, AdSize32;
1410 def MOV16o32a : Ii32<0xA3, RawFrmMemOffs, (outs offset32_16:$dst), (ins),
1411 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
1414 def MOV32o32a : Ii32<0xA3, RawFrmMemOffs, (outs offset32_32:$dst), (ins),
1415 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
1418 def MOV64o32a : RIi32<0xA3, RawFrmMemOffs, (outs offset32_64:$dst), (ins),
1419 "mov{q}\t{%rax, $dst|$dst, rax}", [], IIC_MOV_MEM>,
1423 def MOV8o16a : Ii16<0xA2, RawFrmMemOffs, (outs offset16_8:$dst), (ins),
1424 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, AdSize16;
1426 def MOV16o16a : Ii16<0xA3, RawFrmMemOffs, (outs offset16_16:$dst), (ins),
1427 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
1430 def MOV32o16a : Ii16<0xA3, RawFrmMemOffs, (outs offset16_32:$dst), (ins),
1431 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
1436 // These forms all have full 64-bit absolute addresses in their instructions
1437 // and use the movabs mnemonic to indicate this specific form.
1438 let mayLoad = 1 in {
1440 def MOV8ao64 : RIi64_NOREX<0xA0, RawFrmMemOffs, (outs), (ins offset64_8:$src),
1441 "movabs{b}\t{$src, %al|al, $src}", []>, AdSize64;
1443 def MOV16ao64 : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset64_16:$src),
1444 "movabs{w}\t{$src, %ax|ax, $src}", []>, OpSize16, AdSize64;
1446 def MOV32ao64 : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset64_32:$src),
1447 "movabs{l}\t{$src, %eax|eax, $src}", []>, OpSize32,
1450 def MOV64ao64 : RIi64<0xA1, RawFrmMemOffs, (outs), (ins offset64_64:$src),
1451 "movabs{q}\t{$src, %rax|rax, $src}", []>, AdSize64;
1454 let mayStore = 1 in {
1456 def MOV8o64a : RIi64_NOREX<0xA2, RawFrmMemOffs, (outs offset64_8:$dst), (ins),
1457 "movabs{b}\t{%al, $dst|$dst, al}", []>, AdSize64;
1459 def MOV16o64a : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset64_16:$dst), (ins),
1460 "movabs{w}\t{%ax, $dst|$dst, ax}", []>, OpSize16, AdSize64;
1462 def MOV32o64a : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset64_32:$dst), (ins),
1463 "movabs{l}\t{%eax, $dst|$dst, eax}", []>, OpSize32,
1466 def MOV64o64a : RIi64<0xA3, RawFrmMemOffs, (outs offset64_64:$dst), (ins),
1467 "movabs{q}\t{%rax, $dst|$dst, rax}", []>, AdSize64;
1469 } // hasSideEffects = 0
1471 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
1472 SchedRW = [WriteMove] in {
1473 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1474 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1475 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1476 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1477 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1478 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
1479 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1480 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1483 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1484 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1485 "mov{b}\t{$src, $dst|$dst, $src}",
1486 [(set GR8:$dst, (loadi8 addr:$src))], IIC_MOV_MEM>;
1487 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1488 "mov{w}\t{$src, $dst|$dst, $src}",
1489 [(set GR16:$dst, (loadi16 addr:$src))], IIC_MOV_MEM>, OpSize16;
1490 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1491 "mov{l}\t{$src, $dst|$dst, $src}",
1492 [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>, OpSize32;
1493 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1494 "mov{q}\t{$src, $dst|$dst, $src}",
1495 [(set GR64:$dst, (load addr:$src))], IIC_MOV_MEM>;
1498 let SchedRW = [WriteStore] in {
1499 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1500 "mov{b}\t{$src, $dst|$dst, $src}",
1501 [(store GR8:$src, addr:$dst)], IIC_MOV_MEM>;
1502 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1503 "mov{w}\t{$src, $dst|$dst, $src}",
1504 [(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize16;
1505 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1506 "mov{l}\t{$src, $dst|$dst, $src}",
1507 [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>, OpSize32;
1508 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1509 "mov{q}\t{$src, $dst|$dst, $src}",
1510 [(store GR64:$src, addr:$dst)], IIC_MOV_MEM>;
1513 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1514 // that they can be used for copying and storing h registers, which can't be
1515 // encoded when a REX prefix is present.
1516 let isCodeGenOnly = 1 in {
1517 let hasSideEffects = 0 in
1518 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1519 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1520 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], IIC_MOV>,
1522 let mayStore = 1, hasSideEffects = 0 in
1523 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1524 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1525 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1526 IIC_MOV_MEM>, Sched<[WriteStore]>;
1527 let mayLoad = 1, hasSideEffects = 0,
1528 canFoldAsLoad = 1, isReMaterializable = 1 in
1529 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1530 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1531 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1532 IIC_MOV_MEM>, Sched<[WriteLoad]>;
1536 // Condition code ops, incl. set if equal/not equal/...
1537 let SchedRW = [WriteALU] in {
1538 let Defs = [EFLAGS], Uses = [AH] in
1539 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf",
1540 [(set EFLAGS, (X86sahf AH))], IIC_AHF>,
1541 Requires<[HasLAHFSAHF]>;
1542 let Defs = [AH], Uses = [EFLAGS], hasSideEffects = 0 in
1543 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", [],
1544 IIC_AHF>, // AH = flags
1545 Requires<[HasLAHFSAHF]>;
1548 //===----------------------------------------------------------------------===//
1549 // Bit tests instructions: BT, BTS, BTR, BTC.
1551 let Defs = [EFLAGS] in {
1552 let SchedRW = [WriteALU] in {
1553 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1554 "bt{w}\t{$src2, $src1|$src1, $src2}",
1555 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))], IIC_BT_RR>,
1557 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1558 "bt{l}\t{$src2, $src1|$src1, $src2}",
1559 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>,
1561 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1562 "bt{q}\t{$src2, $src1|$src1, $src2}",
1563 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))], IIC_BT_RR>, TB;
1566 // Unlike with the register+register form, the memory+register form of the
1567 // bt instruction does not ignore the high bits of the index. From ISel's
1568 // perspective, this is pretty bizarre. Make these instructions disassembly
1571 let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteALULd] in {
1572 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1573 "bt{w}\t{$src2, $src1|$src1, $src2}",
1574 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
1575 // (implicit EFLAGS)]
1577 >, OpSize16, TB, Requires<[FastBTMem]>;
1578 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1579 "bt{l}\t{$src2, $src1|$src1, $src2}",
1580 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
1581 // (implicit EFLAGS)]
1583 >, OpSize32, TB, Requires<[FastBTMem]>;
1584 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1585 "bt{q}\t{$src2, $src1|$src1, $src2}",
1586 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1587 // (implicit EFLAGS)]
1592 let SchedRW = [WriteALU] in {
1593 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1594 "bt{w}\t{$src2, $src1|$src1, $src2}",
1595 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))],
1596 IIC_BT_RI>, OpSize16, TB;
1597 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1598 "bt{l}\t{$src2, $src1|$src1, $src2}",
1599 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))],
1600 IIC_BT_RI>, OpSize32, TB;
1601 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1602 "bt{q}\t{$src2, $src1|$src1, $src2}",
1603 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))],
1607 // Note that these instructions don't need FastBTMem because that
1608 // only applies when the other operand is in a register. When it's
1609 // an immediate, bt is still fast.
1610 let SchedRW = [WriteALU] in {
1611 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1612 "bt{w}\t{$src2, $src1|$src1, $src2}",
1613 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
1614 ], IIC_BT_MI>, OpSize16, TB;
1615 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1616 "bt{l}\t{$src2, $src1|$src1, $src2}",
1617 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
1618 ], IIC_BT_MI>, OpSize32, TB;
1619 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1620 "bt{q}\t{$src2, $src1|$src1, $src2}",
1621 [(set EFLAGS, (X86bt (loadi64 addr:$src1),
1622 i64immSExt8:$src2))], IIC_BT_MI>, TB;
1625 let hasSideEffects = 0 in {
1626 let SchedRW = [WriteALU] in {
1627 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1628 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1630 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1631 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1633 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1634 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1637 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1638 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1639 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1641 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1642 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1644 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1645 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1648 let SchedRW = [WriteALU] in {
1649 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1650 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1652 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1653 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1655 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1656 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1659 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1660 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1661 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1663 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1664 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1666 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1667 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1670 let SchedRW = [WriteALU] in {
1671 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1672 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1674 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1675 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1677 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1678 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1681 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1682 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1683 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1685 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1686 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1688 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1689 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1692 let SchedRW = [WriteALU] in {
1693 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1694 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1696 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1697 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1699 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1700 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1703 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1704 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1705 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1707 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1708 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1710 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1711 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1714 let SchedRW = [WriteALU] in {
1715 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1716 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1718 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1719 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1721 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1722 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1725 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1726 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1727 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1729 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1730 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1732 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1733 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1736 let SchedRW = [WriteALU] in {
1737 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1738 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1740 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1741 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1743 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1744 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1747 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1748 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1749 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1751 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1752 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1754 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1755 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1757 } // hasSideEffects = 0
1758 } // Defs = [EFLAGS]
1761 //===----------------------------------------------------------------------===//
1765 // Atomic swap. These are just normal xchg instructions. But since a memory
1766 // operand is referenced, the atomicity is ensured.
1767 multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag,
1768 InstrItinClass itin> {
1769 let Constraints = "$val = $dst", SchedRW = [WriteALULd, WriteRMW] in {
1770 def NAME#8rm : I<opc8, MRMSrcMem, (outs GR8:$dst),
1771 (ins GR8:$val, i8mem:$ptr),
1772 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
1775 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
1777 def NAME#16rm : I<opc, MRMSrcMem, (outs GR16:$dst),
1778 (ins GR16:$val, i16mem:$ptr),
1779 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
1782 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
1784 def NAME#32rm : I<opc, MRMSrcMem, (outs GR32:$dst),
1785 (ins GR32:$val, i32mem:$ptr),
1786 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
1789 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
1791 def NAME#64rm : RI<opc, MRMSrcMem, (outs GR64:$dst),
1792 (ins GR64:$val, i64mem:$ptr),
1793 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
1796 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
1801 defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap", IIC_XCHG_MEM>;
1803 // Swap between registers.
1804 let SchedRW = [WriteALU] in {
1805 let Constraints = "$val = $dst" in {
1806 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
1807 "xchg{b}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1808 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
1809 "xchg{w}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>,
1811 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
1812 "xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>,
1814 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1815 "xchg{q}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1818 // Swap between EAX and other registers.
1819 let Uses = [AX], Defs = [AX] in
1820 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
1821 "xchg{w}\t{$src, %ax|ax, $src}", [], IIC_XCHG_REG>, OpSize16;
1822 let Uses = [EAX], Defs = [EAX] in
1823 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
1824 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
1825 OpSize32, Requires<[Not64BitMode]>;
1826 let Uses = [EAX], Defs = [EAX] in
1827 // Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding.
1828 // xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP.
1829 def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
1830 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
1831 OpSize32, Requires<[In64BitMode]>;
1832 let Uses = [RAX], Defs = [RAX] in
1833 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1834 "xchg{q}\t{$src, %rax|rax, $src}", [], IIC_XCHG_REG>;
1837 let SchedRW = [WriteALU] in {
1838 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1839 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1840 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1841 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1843 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1844 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1846 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1847 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1850 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1851 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1852 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1853 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1854 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1856 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1857 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1859 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1860 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1864 let SchedRW = [WriteALU] in {
1865 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1866 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1867 IIC_CMPXCHG_REG8>, TB;
1868 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1869 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1870 IIC_CMPXCHG_REG>, TB, OpSize16;
1871 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1872 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1873 IIC_CMPXCHG_REG>, TB, OpSize32;
1874 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1875 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1876 IIC_CMPXCHG_REG>, TB;
1879 let SchedRW = [WriteALULd, WriteRMW] in {
1880 let mayLoad = 1, mayStore = 1 in {
1881 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1882 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1883 IIC_CMPXCHG_MEM8>, TB;
1884 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1885 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1886 IIC_CMPXCHG_MEM>, TB, OpSize16;
1887 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1888 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1889 IIC_CMPXCHG_MEM>, TB, OpSize32;
1890 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1891 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1892 IIC_CMPXCHG_MEM>, TB;
1895 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
1896 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
1897 "cmpxchg8b\t$dst", [], IIC_CMPXCHG_8B>, TB;
1899 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1900 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1901 "cmpxchg16b\t$dst", [], IIC_CMPXCHG_16B>,
1902 TB, Requires<[HasCmpxchg16b]>;
1906 // Lock instruction prefix
1907 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
1909 // Rex64 instruction prefix
1910 def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>,
1911 Requires<[In64BitMode]>;
1913 // Data16 instruction prefix
1914 def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>;
1916 // Repeat string operation instruction prefixes
1917 // These uses the DF flag in the EFLAGS register to inc or dec ECX
1918 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
1919 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
1920 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
1921 // Repeat while not equal (used with CMPS and SCAS)
1922 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
1926 // String manipulation instructions
1927 let SchedRW = [WriteMicrocoded] in {
1928 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1929 let Defs = [AL,ESI], Uses = [ESI,EFLAGS] in
1930 def LODSB : I<0xAC, RawFrmSrc, (outs), (ins srcidx8:$src),
1931 "lodsb\t{$src, %al|al, $src}", [], IIC_LODS>;
1932 let Defs = [AX,ESI], Uses = [ESI,EFLAGS] in
1933 def LODSW : I<0xAD, RawFrmSrc, (outs), (ins srcidx16:$src),
1934 "lodsw\t{$src, %ax|ax, $src}", [], IIC_LODS>, OpSize16;
1935 let Defs = [EAX,ESI], Uses = [ESI,EFLAGS] in
1936 def LODSL : I<0xAD, RawFrmSrc, (outs), (ins srcidx32:$src),
1937 "lods{l|d}\t{$src, %eax|eax, $src}", [], IIC_LODS>, OpSize32;
1938 let Defs = [RAX,ESI], Uses = [ESI,EFLAGS] in
1939 def LODSQ : RI<0xAD, RawFrmSrc, (outs), (ins srcidx64:$src),
1940 "lodsq\t{$src, %rax|rax, $src}", [], IIC_LODS>;
1943 let SchedRW = [WriteSystem] in {
1944 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1945 let Defs = [ESI], Uses = [DX,ESI,EFLAGS] in {
1946 def OUTSB : I<0x6E, RawFrmSrc, (outs), (ins srcidx8:$src),
1947 "outsb\t{$src, %dx|dx, $src}", [], IIC_OUTS>;
1948 def OUTSW : I<0x6F, RawFrmSrc, (outs), (ins srcidx16:$src),
1949 "outsw\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize16;
1950 def OUTSL : I<0x6F, RawFrmSrc, (outs), (ins srcidx32:$src),
1951 "outs{l|d}\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize32;
1954 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1955 let Defs = [EDI], Uses = [DX,EDI,EFLAGS] in {
1956 def INSB : I<0x6C, RawFrmDst, (outs dstidx8:$dst), (ins),
1957 "insb\t{%dx, $dst|$dst, dx}", [], IIC_INS>;
1958 def INSW : I<0x6D, RawFrmDst, (outs dstidx16:$dst), (ins),
1959 "insw\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize16;
1960 def INSL : I<0x6D, RawFrmDst, (outs dstidx32:$dst), (ins),
1961 "ins{l|d}\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize32;
1965 // Flag instructions
1966 let SchedRW = [WriteALU] in {
1967 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC>;
1968 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_STC>;
1969 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>;
1970 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>;
1971 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", [], IIC_CLD>;
1972 def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>;
1973 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CMC>;
1975 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB;
1978 // Table lookup instructions
1979 let Uses = [AL,EBX], Defs = [AL], hasSideEffects = 0, mayLoad = 1 in
1980 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", [], IIC_XLAT>,
1983 let SchedRW = [WriteMicrocoded] in {
1984 // ASCII Adjust After Addition
1985 let Uses = [AL,EFLAGS], Defs = [AX,EFLAGS], hasSideEffects = 0 in
1986 def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", [], IIC_AAA>,
1987 Requires<[Not64BitMode]>;
1989 // ASCII Adjust AX Before Division
1990 let Uses = [AX], Defs = [AX,EFLAGS], hasSideEffects = 0 in
1991 def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src),
1992 "aad\t$src", [], IIC_AAD>, Requires<[Not64BitMode]>;
1994 // ASCII Adjust AX After Multiply
1995 let Uses = [AL], Defs = [AX,EFLAGS], hasSideEffects = 0 in
1996 def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src),
1997 "aam\t$src", [], IIC_AAM>, Requires<[Not64BitMode]>;
1999 // ASCII Adjust AL After Subtraction - sets
2000 let Uses = [AL,EFLAGS], Defs = [AX,EFLAGS], hasSideEffects = 0 in
2001 def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", [], IIC_AAS>,
2002 Requires<[Not64BitMode]>;
2004 // Decimal Adjust AL after Addition
2005 let Uses = [AL,EFLAGS], Defs = [AL,EFLAGS], hasSideEffects = 0 in
2006 def DAA : I<0x27, RawFrm, (outs), (ins), "daa", [], IIC_DAA>,
2007 Requires<[Not64BitMode]>;
2009 // Decimal Adjust AL after Subtraction
2010 let Uses = [AL,EFLAGS], Defs = [AL,EFLAGS], hasSideEffects = 0 in
2011 def DAS : I<0x2F, RawFrm, (outs), (ins), "das", [], IIC_DAS>,
2012 Requires<[Not64BitMode]>;
2015 let SchedRW = [WriteSystem] in {
2016 // Check Array Index Against Bounds
2017 def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
2018 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize16,
2019 Requires<[Not64BitMode]>;
2020 def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
2021 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize32,
2022 Requires<[Not64BitMode]>;
2024 // Adjust RPL Field of Segment Selector
2025 def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
2026 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_REG>,
2027 Requires<[Not64BitMode]>;
2028 def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
2029 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_MEM>,
2030 Requires<[Not64BitMode]>;
2033 //===----------------------------------------------------------------------===//
2034 // MOVBE Instructions
2036 let Predicates = [HasMOVBE] in {
2037 let SchedRW = [WriteALULd] in {
2038 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
2039 "movbe{w}\t{$src, $dst|$dst, $src}",
2040 [(set GR16:$dst, (bswap (loadi16 addr:$src)))], IIC_MOVBE>,
2042 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
2043 "movbe{l}\t{$src, $dst|$dst, $src}",
2044 [(set GR32:$dst, (bswap (loadi32 addr:$src)))], IIC_MOVBE>,
2046 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
2047 "movbe{q}\t{$src, $dst|$dst, $src}",
2048 [(set GR64:$dst, (bswap (loadi64 addr:$src)))], IIC_MOVBE>,
2051 let SchedRW = [WriteStore] in {
2052 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
2053 "movbe{w}\t{$src, $dst|$dst, $src}",
2054 [(store (bswap GR16:$src), addr:$dst)], IIC_MOVBE>,
2056 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2057 "movbe{l}\t{$src, $dst|$dst, $src}",
2058 [(store (bswap GR32:$src), addr:$dst)], IIC_MOVBE>,
2060 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
2061 "movbe{q}\t{$src, $dst|$dst, $src}",
2062 [(store (bswap GR64:$src), addr:$dst)], IIC_MOVBE>,
2067 //===----------------------------------------------------------------------===//
2068 // RDRAND Instruction
2070 let Predicates = [HasRDRAND], Defs = [EFLAGS] in {
2071 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
2073 [(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize16, TB;
2074 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
2076 [(set GR32:$dst, EFLAGS, (X86rdrand))]>, OpSize32, TB;
2077 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
2079 [(set GR64:$dst, EFLAGS, (X86rdrand))]>, TB;
2082 //===----------------------------------------------------------------------===//
2083 // RDSEED Instruction
2085 let Predicates = [HasRDSEED], Defs = [EFLAGS] in {
2086 def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins),
2088 [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize16, TB;
2089 def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins),
2091 [(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize32, TB;
2092 def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins),
2094 [(set GR64:$dst, EFLAGS, (X86rdseed))]>, TB;
2097 //===----------------------------------------------------------------------===//
2098 // LZCNT Instruction
2100 let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
2101 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
2102 "lzcnt{w}\t{$src, $dst|$dst, $src}",
2103 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS,
2105 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
2106 "lzcnt{w}\t{$src, $dst|$dst, $src}",
2107 [(set GR16:$dst, (ctlz (loadi16 addr:$src))),
2108 (implicit EFLAGS)]>, XS, OpSize16;
2110 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
2111 "lzcnt{l}\t{$src, $dst|$dst, $src}",
2112 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS,
2114 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
2115 "lzcnt{l}\t{$src, $dst|$dst, $src}",
2116 [(set GR32:$dst, (ctlz (loadi32 addr:$src))),
2117 (implicit EFLAGS)]>, XS, OpSize32;
2119 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
2120 "lzcnt{q}\t{$src, $dst|$dst, $src}",
2121 [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>,
2123 def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
2124 "lzcnt{q}\t{$src, $dst|$dst, $src}",
2125 [(set GR64:$dst, (ctlz (loadi64 addr:$src))),
2126 (implicit EFLAGS)]>, XS;
2129 let Predicates = [HasLZCNT] in {
2130 def : Pat<(X86cmov (ctlz GR16:$src), (i16 16), (X86_COND_E_OR_NE),
2131 (X86cmp GR16:$src, (i16 0))),
2132 (LZCNT16rr GR16:$src)>;
2133 def : Pat<(X86cmov (ctlz GR32:$src), (i32 32), (X86_COND_E_OR_NE),
2134 (X86cmp GR32:$src, (i32 0))),
2135 (LZCNT32rr GR32:$src)>;
2136 def : Pat<(X86cmov (ctlz GR64:$src), (i64 64), (X86_COND_E_OR_NE),
2137 (X86cmp GR64:$src, (i64 0))),
2138 (LZCNT64rr GR64:$src)>;
2139 def : Pat<(X86cmov (i16 16), (ctlz GR16:$src), (X86_COND_E_OR_NE),
2140 (X86cmp GR16:$src, (i16 0))),
2141 (LZCNT16rr GR16:$src)>;
2142 def : Pat<(X86cmov (i32 32), (ctlz GR32:$src), (X86_COND_E_OR_NE),
2143 (X86cmp GR32:$src, (i32 0))),
2144 (LZCNT32rr GR32:$src)>;
2145 def : Pat<(X86cmov (i64 64), (ctlz GR64:$src), (X86_COND_E_OR_NE),
2146 (X86cmp GR64:$src, (i64 0))),
2147 (LZCNT64rr GR64:$src)>;
2149 def : Pat<(X86cmov (ctlz (loadi16 addr:$src)), (i16 16), (X86_COND_E_OR_NE),
2150 (X86cmp (loadi16 addr:$src), (i16 0))),
2151 (LZCNT16rm addr:$src)>;
2152 def : Pat<(X86cmov (ctlz (loadi32 addr:$src)), (i32 32), (X86_COND_E_OR_NE),
2153 (X86cmp (loadi32 addr:$src), (i32 0))),
2154 (LZCNT32rm addr:$src)>;
2155 def : Pat<(X86cmov (ctlz (loadi64 addr:$src)), (i64 64), (X86_COND_E_OR_NE),
2156 (X86cmp (loadi64 addr:$src), (i64 0))),
2157 (LZCNT64rm addr:$src)>;
2158 def : Pat<(X86cmov (i16 16), (ctlz (loadi16 addr:$src)), (X86_COND_E_OR_NE),
2159 (X86cmp (loadi16 addr:$src), (i16 0))),
2160 (LZCNT16rm addr:$src)>;
2161 def : Pat<(X86cmov (i32 32), (ctlz (loadi32 addr:$src)), (X86_COND_E_OR_NE),
2162 (X86cmp (loadi32 addr:$src), (i32 0))),
2163 (LZCNT32rm addr:$src)>;
2164 def : Pat<(X86cmov (i64 64), (ctlz (loadi64 addr:$src)), (X86_COND_E_OR_NE),
2165 (X86cmp (loadi64 addr:$src), (i64 0))),
2166 (LZCNT64rm addr:$src)>;
2169 //===----------------------------------------------------------------------===//
2172 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2173 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
2174 "tzcnt{w}\t{$src, $dst|$dst, $src}",
2175 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS,
2177 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
2178 "tzcnt{w}\t{$src, $dst|$dst, $src}",
2179 [(set GR16:$dst, (cttz (loadi16 addr:$src))),
2180 (implicit EFLAGS)]>, XS, OpSize16;
2182 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
2183 "tzcnt{l}\t{$src, $dst|$dst, $src}",
2184 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS,
2186 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
2187 "tzcnt{l}\t{$src, $dst|$dst, $src}",
2188 [(set GR32:$dst, (cttz (loadi32 addr:$src))),
2189 (implicit EFLAGS)]>, XS, OpSize32;
2191 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
2192 "tzcnt{q}\t{$src, $dst|$dst, $src}",
2193 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>,
2195 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
2196 "tzcnt{q}\t{$src, $dst|$dst, $src}",
2197 [(set GR64:$dst, (cttz (loadi64 addr:$src))),
2198 (implicit EFLAGS)]>, XS;
2201 multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,
2202 RegisterClass RC, X86MemOperand x86memop> {
2203 let hasSideEffects = 0 in {
2204 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
2205 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
2208 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
2209 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
2214 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2215 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem>;
2216 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem>, VEX_W;
2217 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem>;
2218 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem>, VEX_W;
2219 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem>;
2220 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem>, VEX_W;
2223 //===----------------------------------------------------------------------===//
2224 // Pattern fragments to auto generate BMI instructions.
2225 //===----------------------------------------------------------------------===//
2227 let Predicates = [HasBMI] in {
2228 // FIXME: patterns for the load versions are not implemented
2229 def : Pat<(and GR32:$src, (add GR32:$src, -1)),
2230 (BLSR32rr GR32:$src)>;
2231 def : Pat<(and GR64:$src, (add GR64:$src, -1)),
2232 (BLSR64rr GR64:$src)>;
2234 def : Pat<(xor GR32:$src, (add GR32:$src, -1)),
2235 (BLSMSK32rr GR32:$src)>;
2236 def : Pat<(xor GR64:$src, (add GR64:$src, -1)),
2237 (BLSMSK64rr GR64:$src)>;
2239 def : Pat<(and GR32:$src, (ineg GR32:$src)),
2240 (BLSI32rr GR32:$src)>;
2241 def : Pat<(and GR64:$src, (ineg GR64:$src)),
2242 (BLSI64rr GR64:$src)>;
2245 let Predicates = [HasBMI] in {
2246 def : Pat<(X86cmov (cttz GR16:$src), (i16 16), (X86_COND_E_OR_NE),
2247 (X86cmp GR16:$src, (i16 0))),
2248 (TZCNT16rr GR16:$src)>;
2249 def : Pat<(X86cmov (cttz GR32:$src), (i32 32), (X86_COND_E_OR_NE),
2250 (X86cmp GR32:$src, (i32 0))),
2251 (TZCNT32rr GR32:$src)>;
2252 def : Pat<(X86cmov (cttz GR64:$src), (i64 64), (X86_COND_E_OR_NE),
2253 (X86cmp GR64:$src, (i64 0))),
2254 (TZCNT64rr GR64:$src)>;
2255 def : Pat<(X86cmov (i16 16), (cttz GR16:$src), (X86_COND_E_OR_NE),
2256 (X86cmp GR16:$src, (i16 0))),
2257 (TZCNT16rr GR16:$src)>;
2258 def : Pat<(X86cmov (i32 32), (cttz GR32:$src), (X86_COND_E_OR_NE),
2259 (X86cmp GR32:$src, (i32 0))),
2260 (TZCNT32rr GR32:$src)>;
2261 def : Pat<(X86cmov (i64 64), (cttz GR64:$src), (X86_COND_E_OR_NE),
2262 (X86cmp GR64:$src, (i64 0))),
2263 (TZCNT64rr GR64:$src)>;
2265 def : Pat<(X86cmov (cttz (loadi16 addr:$src)), (i16 16), (X86_COND_E_OR_NE),
2266 (X86cmp (loadi16 addr:$src), (i16 0))),
2267 (TZCNT16rm addr:$src)>;
2268 def : Pat<(X86cmov (cttz (loadi32 addr:$src)), (i32 32), (X86_COND_E_OR_NE),
2269 (X86cmp (loadi32 addr:$src), (i32 0))),
2270 (TZCNT32rm addr:$src)>;
2271 def : Pat<(X86cmov (cttz (loadi64 addr:$src)), (i64 64), (X86_COND_E_OR_NE),
2272 (X86cmp (loadi64 addr:$src), (i64 0))),
2273 (TZCNT64rm addr:$src)>;
2274 def : Pat<(X86cmov (i16 16), (cttz (loadi16 addr:$src)), (X86_COND_E_OR_NE),
2275 (X86cmp (loadi16 addr:$src), (i16 0))),
2276 (TZCNT16rm addr:$src)>;
2277 def : Pat<(X86cmov (i32 32), (cttz (loadi32 addr:$src)), (X86_COND_E_OR_NE),
2278 (X86cmp (loadi32 addr:$src), (i32 0))),
2279 (TZCNT32rm addr:$src)>;
2280 def : Pat<(X86cmov (i64 64), (cttz (loadi64 addr:$src)), (X86_COND_E_OR_NE),
2281 (X86cmp (loadi64 addr:$src), (i64 0))),
2282 (TZCNT64rm addr:$src)>;
2286 multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC,
2287 X86MemOperand x86memop, Intrinsic Int,
2289 def rr : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2290 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2291 [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>,
2293 def rm : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
2294 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2295 [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)),
2296 (implicit EFLAGS)]>, T8PS, VEX_4VOp3;
2299 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2300 defm BEXTR32 : bmi_bextr_bzhi<0xF7, "bextr{l}", GR32, i32mem,
2301 int_x86_bmi_bextr_32, loadi32>;
2302 defm BEXTR64 : bmi_bextr_bzhi<0xF7, "bextr{q}", GR64, i64mem,
2303 int_x86_bmi_bextr_64, loadi64>, VEX_W;
2306 let Predicates = [HasBMI2], Defs = [EFLAGS] in {
2307 defm BZHI32 : bmi_bextr_bzhi<0xF5, "bzhi{l}", GR32, i32mem,
2308 int_x86_bmi_bzhi_32, loadi32>;
2309 defm BZHI64 : bmi_bextr_bzhi<0xF5, "bzhi{q}", GR64, i64mem,
2310 int_x86_bmi_bzhi_64, loadi64>, VEX_W;
2314 def CountTrailingOnes : SDNodeXForm<imm, [{
2315 // Count the trailing ones in the immediate.
2316 return getI8Imm(countTrailingOnes(N->getZExtValue()), SDLoc(N));
2319 def BZHIMask : ImmLeaf<i64, [{
2320 return isMask_64(Imm) && (countTrailingOnes<uint64_t>(Imm) > 32);
2323 let Predicates = [HasBMI2] in {
2324 def : Pat<(and GR64:$src, BZHIMask:$mask),
2325 (BZHI64rr GR64:$src,
2326 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2327 (MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>;
2329 def : Pat<(and GR32:$src, (add (shl 1, GR8:$lz), -1)),
2330 (BZHI32rr GR32:$src,
2331 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2333 def : Pat<(and (loadi32 addr:$src), (add (shl 1, GR8:$lz), -1)),
2334 (BZHI32rm addr:$src,
2335 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2337 def : Pat<(and GR64:$src, (add (shl 1, GR8:$lz), -1)),
2338 (BZHI64rr GR64:$src,
2339 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2341 def : Pat<(and (loadi64 addr:$src), (add (shl 1, GR8:$lz), -1)),
2342 (BZHI64rm addr:$src,
2343 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2346 let Predicates = [HasBMI] in {
2347 def : Pat<(X86bextr GR32:$src1, GR32:$src2),
2348 (BEXTR32rr GR32:$src1, GR32:$src2)>;
2349 def : Pat<(X86bextr (loadi32 addr:$src1), GR32:$src2),
2350 (BEXTR32rm addr:$src1, GR32:$src2)>;
2351 def : Pat<(X86bextr GR64:$src1, GR64:$src2),
2352 (BEXTR64rr GR64:$src1, GR64:$src2)>;
2353 def : Pat<(X86bextr (loadi64 addr:$src1), GR64:$src2),
2354 (BEXTR64rm addr:$src1, GR64:$src2)>;
2357 multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
2358 X86MemOperand x86memop, Intrinsic Int,
2360 def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2361 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2362 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>,
2364 def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2365 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2366 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, VEX_4V;
2369 let Predicates = [HasBMI2] in {
2370 defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem,
2371 int_x86_bmi_pdep_32, loadi32>, T8XD;
2372 defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem,
2373 int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W;
2374 defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem,
2375 int_x86_bmi_pext_32, loadi32>, T8XS;
2376 defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem,
2377 int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W;
2380 //===----------------------------------------------------------------------===//
2383 let Predicates = [HasTBM], Defs = [EFLAGS] in {
2385 multiclass tbm_ternary_imm_intr<bits<8> opc, RegisterClass RC, string OpcodeStr,
2386 X86MemOperand x86memop, PatFrag ld_frag,
2387 Intrinsic Int, Operand immtype,
2388 SDPatternOperator immoperator> {
2389 def ri : Ii32<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, immtype:$cntl),
2390 !strconcat(OpcodeStr,
2391 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
2392 [(set RC:$dst, (Int RC:$src1, immoperator:$cntl))]>,
2394 def mi : Ii32<opc, MRMSrcMem, (outs RC:$dst),
2395 (ins x86memop:$src1, immtype:$cntl),
2396 !strconcat(OpcodeStr,
2397 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
2398 [(set RC:$dst, (Int (ld_frag addr:$src1), immoperator:$cntl))]>,
2402 defm BEXTRI32 : tbm_ternary_imm_intr<0x10, GR32, "bextr", i32mem, loadi32,
2403 int_x86_tbm_bextri_u32, i32imm, imm>;
2404 let ImmT = Imm32S in
2405 defm BEXTRI64 : tbm_ternary_imm_intr<0x10, GR64, "bextr", i64mem, loadi64,
2406 int_x86_tbm_bextri_u64, i64i32imm,
2407 i64immSExt32>, VEX_W;
2409 multiclass tbm_binary_rm<bits<8> opc, Format FormReg, Format FormMem,
2410 RegisterClass RC, string OpcodeStr,
2411 X86MemOperand x86memop, PatFrag ld_frag> {
2412 let hasSideEffects = 0 in {
2413 def rr : I<opc, FormReg, (outs RC:$dst), (ins RC:$src),
2414 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
2417 def rm : I<opc, FormMem, (outs RC:$dst), (ins x86memop:$src),
2418 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
2423 multiclass tbm_binary_intr<bits<8> opc, string OpcodeStr,
2424 Format FormReg, Format FormMem> {
2425 defm NAME#32 : tbm_binary_rm<opc, FormReg, FormMem, GR32, OpcodeStr, i32mem,
2427 defm NAME#64 : tbm_binary_rm<opc, FormReg, FormMem, GR64, OpcodeStr, i64mem,
2431 defm BLCFILL : tbm_binary_intr<0x01, "blcfill", MRM1r, MRM1m>;
2432 defm BLCI : tbm_binary_intr<0x02, "blci", MRM6r, MRM6m>;
2433 defm BLCIC : tbm_binary_intr<0x01, "blcic", MRM5r, MRM5m>;
2434 defm BLCMSK : tbm_binary_intr<0x02, "blcmsk", MRM1r, MRM1m>;
2435 defm BLCS : tbm_binary_intr<0x01, "blcs", MRM3r, MRM3m>;
2436 defm BLSFILL : tbm_binary_intr<0x01, "blsfill", MRM2r, MRM2m>;
2437 defm BLSIC : tbm_binary_intr<0x01, "blsic", MRM6r, MRM6m>;
2438 defm T1MSKC : tbm_binary_intr<0x01, "t1mskc", MRM7r, MRM7m>;
2439 defm TZMSK : tbm_binary_intr<0x01, "tzmsk", MRM4r, MRM4m>;
2442 //===----------------------------------------------------------------------===//
2443 // MONITORX/MWAITX Instructions
2445 let SchedRW = [WriteSystem] in {
2446 let Uses = [EAX, ECX, EDX] in
2447 def MONITORXrrr : I<0x01, MRM_FA, (outs), (ins), "monitorx", [],
2448 IIC_SSE_MONITOR>, TB;
2449 let Uses = [ECX, EAX, EBX] in
2450 def MWAITXrr : I<0x01, MRM_FB, (outs), (ins), "mwaitx", [], IIC_SSE_MWAIT>,
2454 def : InstAlias<"mwaitx\t{%eax, %ecx, %ebx|ebx, ecx, eax}", (MWAITXrr)>, Requires<[Not64BitMode]>;
2455 def : InstAlias<"mwaitx\t{%rax, %rcx, %rbx|rbx, rcx, rax}", (MWAITXrr)>, Requires<[In64BitMode]>;
2457 def : InstAlias<"monitorx\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORXrrr)>,
2458 Requires<[Not64BitMode]>;
2459 def : InstAlias<"monitorx\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORXrrr)>,
2460 Requires<[In64BitMode]>;
2462 //===----------------------------------------------------------------------===//
2463 // CLZERO Instruction
2466 def CLZEROr : I<0x01, MRM_FC, (outs), (ins), "clzero", []>, TB;
2468 //===----------------------------------------------------------------------===//
2469 // Pattern fragments to auto generate TBM instructions.
2470 //===----------------------------------------------------------------------===//
2472 let Predicates = [HasTBM] in {
2473 def : Pat<(X86bextr GR32:$src1, (i32 imm:$src2)),
2474 (BEXTRI32ri GR32:$src1, imm:$src2)>;
2475 def : Pat<(X86bextr (loadi32 addr:$src1), (i32 imm:$src2)),
2476 (BEXTRI32mi addr:$src1, imm:$src2)>;
2477 def : Pat<(X86bextr GR64:$src1, i64immSExt32:$src2),
2478 (BEXTRI64ri GR64:$src1, i64immSExt32:$src2)>;
2479 def : Pat<(X86bextr (loadi64 addr:$src1), i64immSExt32:$src2),
2480 (BEXTRI64mi addr:$src1, i64immSExt32:$src2)>;
2482 // FIXME: patterns for the load versions are not implemented
2483 def : Pat<(and GR32:$src, (add GR32:$src, 1)),
2484 (BLCFILL32rr GR32:$src)>;
2485 def : Pat<(and GR64:$src, (add GR64:$src, 1)),
2486 (BLCFILL64rr GR64:$src)>;
2488 def : Pat<(or GR32:$src, (not (add GR32:$src, 1))),
2489 (BLCI32rr GR32:$src)>;
2490 def : Pat<(or GR64:$src, (not (add GR64:$src, 1))),
2491 (BLCI64rr GR64:$src)>;
2493 // Extra patterns because opt can optimize the above patterns to this.
2494 def : Pat<(or GR32:$src, (sub -2, GR32:$src)),
2495 (BLCI32rr GR32:$src)>;
2496 def : Pat<(or GR64:$src, (sub -2, GR64:$src)),
2497 (BLCI64rr GR64:$src)>;
2499 def : Pat<(and (not GR32:$src), (add GR32:$src, 1)),
2500 (BLCIC32rr GR32:$src)>;
2501 def : Pat<(and (not GR64:$src), (add GR64:$src, 1)),
2502 (BLCIC64rr GR64:$src)>;
2504 def : Pat<(xor GR32:$src, (add GR32:$src, 1)),
2505 (BLCMSK32rr GR32:$src)>;
2506 def : Pat<(xor GR64:$src, (add GR64:$src, 1)),
2507 (BLCMSK64rr GR64:$src)>;
2509 def : Pat<(or GR32:$src, (add GR32:$src, 1)),
2510 (BLCS32rr GR32:$src)>;
2511 def : Pat<(or GR64:$src, (add GR64:$src, 1)),
2512 (BLCS64rr GR64:$src)>;
2514 def : Pat<(or GR32:$src, (add GR32:$src, -1)),
2515 (BLSFILL32rr GR32:$src)>;
2516 def : Pat<(or GR64:$src, (add GR64:$src, -1)),
2517 (BLSFILL64rr GR64:$src)>;
2519 def : Pat<(or (not GR32:$src), (add GR32:$src, -1)),
2520 (BLSIC32rr GR32:$src)>;
2521 def : Pat<(or (not GR64:$src), (add GR64:$src, -1)),
2522 (BLSIC64rr GR64:$src)>;
2524 def : Pat<(or (not GR32:$src), (add GR32:$src, 1)),
2525 (T1MSKC32rr GR32:$src)>;
2526 def : Pat<(or (not GR64:$src), (add GR64:$src, 1)),
2527 (T1MSKC64rr GR64:$src)>;
2529 def : Pat<(and (not GR32:$src), (add GR32:$src, -1)),
2530 (TZMSK32rr GR32:$src)>;
2531 def : Pat<(and (not GR64:$src), (add GR64:$src, -1)),
2532 (TZMSK64rr GR64:$src)>;
2535 //===----------------------------------------------------------------------===//
2536 // Memory Instructions
2539 def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2540 "clflushopt\t$src", []>, PD;
2541 def CLWB : I<0xAE, MRM6m, (outs), (ins i8mem:$src), "clwb\t$src", []>, PD;
2542 def PCOMMIT : I<0xAE, MRM_F8, (outs), (ins), "pcommit", []>, PD;
2545 //===----------------------------------------------------------------------===//
2547 //===----------------------------------------------------------------------===//
2549 include "X86InstrArithmetic.td"
2550 include "X86InstrCMovSetCC.td"
2551 include "X86InstrExtension.td"
2552 include "X86InstrControl.td"
2553 include "X86InstrShiftRotate.td"
2555 // X87 Floating Point Stack.
2556 include "X86InstrFPStack.td"
2558 // SIMD support (SSE, MMX and AVX)
2559 include "X86InstrFragmentsSIMD.td"
2561 // FMA - Fused Multiply-Add support (requires FMA)
2562 include "X86InstrFMA.td"
2565 include "X86InstrXOP.td"
2567 // SSE, MMX and 3DNow! vector support.
2568 include "X86InstrSSE.td"
2569 include "X86InstrAVX512.td"
2570 include "X86InstrMMX.td"
2571 include "X86Instr3DNow.td"
2574 include "X86InstrMPX.td"
2576 include "X86InstrVMX.td"
2577 include "X86InstrSVM.td"
2579 include "X86InstrTSX.td"
2580 include "X86InstrSGX.td"
2582 // System instructions.
2583 include "X86InstrSystem.td"
2585 // Compiler Pseudo Instructions and Pat Patterns
2586 include "X86InstrCompiler.td"
2588 //===----------------------------------------------------------------------===//
2589 // Assembler Mnemonic Aliases
2590 //===----------------------------------------------------------------------===//
2592 def : MnemonicAlias<"call", "callw", "att">, Requires<[In16BitMode]>;
2593 def : MnemonicAlias<"call", "calll", "att">, Requires<[In32BitMode]>;
2594 def : MnemonicAlias<"call", "callq", "att">, Requires<[In64BitMode]>;
2596 def : MnemonicAlias<"cbw", "cbtw", "att">;
2597 def : MnemonicAlias<"cwde", "cwtl", "att">;
2598 def : MnemonicAlias<"cwd", "cwtd", "att">;
2599 def : MnemonicAlias<"cdq", "cltd", "att">;
2600 def : MnemonicAlias<"cdqe", "cltq", "att">;
2601 def : MnemonicAlias<"cqo", "cqto", "att">;
2603 // In 64-bit mode lret maps to lretl; it is not ambiguous with lretq.
2604 def : MnemonicAlias<"lret", "lretw", "att">, Requires<[In16BitMode]>;
2605 def : MnemonicAlias<"lret", "lretl", "att">, Requires<[Not16BitMode]>;
2607 def : MnemonicAlias<"leavel", "leave", "att">, Requires<[Not64BitMode]>;
2608 def : MnemonicAlias<"leaveq", "leave", "att">, Requires<[In64BitMode]>;
2610 def : MnemonicAlias<"loopz", "loope">;
2611 def : MnemonicAlias<"loopnz", "loopne">;
2613 def : MnemonicAlias<"pop", "popw", "att">, Requires<[In16BitMode]>;
2614 def : MnemonicAlias<"pop", "popl", "att">, Requires<[In32BitMode]>;
2615 def : MnemonicAlias<"pop", "popq", "att">, Requires<[In64BitMode]>;
2616 def : MnemonicAlias<"popf", "popfw", "att">, Requires<[In16BitMode]>;
2617 def : MnemonicAlias<"popf", "popfl", "att">, Requires<[In32BitMode]>;
2618 def : MnemonicAlias<"popf", "popfq", "att">, Requires<[In64BitMode]>;
2619 def : MnemonicAlias<"popfd", "popfl", "att">;
2621 // FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in
2622 // all modes. However: "push (addr)" and "push $42" should default to
2623 // pushl/pushq depending on the current mode. Similar for "pop %bx"
2624 def : MnemonicAlias<"push", "pushw", "att">, Requires<[In16BitMode]>;
2625 def : MnemonicAlias<"push", "pushl", "att">, Requires<[In32BitMode]>;
2626 def : MnemonicAlias<"push", "pushq", "att">, Requires<[In64BitMode]>;
2627 def : MnemonicAlias<"pushf", "pushfw", "att">, Requires<[In16BitMode]>;
2628 def : MnemonicAlias<"pushf", "pushfl", "att">, Requires<[In32BitMode]>;
2629 def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>;
2630 def : MnemonicAlias<"pushfd", "pushfl", "att">;
2632 def : MnemonicAlias<"popad", "popal", "intel">, Requires<[Not64BitMode]>;
2633 def : MnemonicAlias<"pushad", "pushal", "intel">, Requires<[Not64BitMode]>;
2634 def : MnemonicAlias<"popa", "popaw", "intel">, Requires<[In16BitMode]>;
2635 def : MnemonicAlias<"pusha", "pushaw", "intel">, Requires<[In16BitMode]>;
2636 def : MnemonicAlias<"popa", "popal", "intel">, Requires<[In32BitMode]>;
2637 def : MnemonicAlias<"pusha", "pushal", "intel">, Requires<[In32BitMode]>;
2639 def : MnemonicAlias<"popa", "popaw", "att">, Requires<[In16BitMode]>;
2640 def : MnemonicAlias<"pusha", "pushaw", "att">, Requires<[In16BitMode]>;
2641 def : MnemonicAlias<"popa", "popal", "att">, Requires<[In32BitMode]>;
2642 def : MnemonicAlias<"pusha", "pushal", "att">, Requires<[In32BitMode]>;
2644 def : MnemonicAlias<"repe", "rep">;
2645 def : MnemonicAlias<"repz", "rep">;
2646 def : MnemonicAlias<"repnz", "repne">;
2648 def : MnemonicAlias<"ret", "retw", "att">, Requires<[In16BitMode]>;
2649 def : MnemonicAlias<"ret", "retl", "att">, Requires<[In32BitMode]>;
2650 def : MnemonicAlias<"ret", "retq", "att">, Requires<[In64BitMode]>;
2652 def : MnemonicAlias<"sal", "shl", "intel">;
2653 def : MnemonicAlias<"salb", "shlb", "att">;
2654 def : MnemonicAlias<"salw", "shlw", "att">;
2655 def : MnemonicAlias<"sall", "shll", "att">;
2656 def : MnemonicAlias<"salq", "shlq", "att">;
2658 def : MnemonicAlias<"smovb", "movsb", "att">;
2659 def : MnemonicAlias<"smovw", "movsw", "att">;
2660 def : MnemonicAlias<"smovl", "movsl", "att">;
2661 def : MnemonicAlias<"smovq", "movsq", "att">;
2663 def : MnemonicAlias<"ud2a", "ud2", "att">;
2664 def : MnemonicAlias<"verrw", "verr", "att">;
2666 // System instruction aliases.
2667 def : MnemonicAlias<"iret", "iretw", "att">, Requires<[In16BitMode]>;
2668 def : MnemonicAlias<"iret", "iretl", "att">, Requires<[Not16BitMode]>;
2669 def : MnemonicAlias<"sysret", "sysretl", "att">;
2670 def : MnemonicAlias<"sysexit", "sysexitl", "att">;
2672 def : MnemonicAlias<"lgdt", "lgdtw", "att">, Requires<[In16BitMode]>;
2673 def : MnemonicAlias<"lgdt", "lgdtl", "att">, Requires<[In32BitMode]>;
2674 def : MnemonicAlias<"lgdt", "lgdtq", "att">, Requires<[In64BitMode]>;
2675 def : MnemonicAlias<"lidt", "lidtw", "att">, Requires<[In16BitMode]>;
2676 def : MnemonicAlias<"lidt", "lidtl", "att">, Requires<[In32BitMode]>;
2677 def : MnemonicAlias<"lidt", "lidtq", "att">, Requires<[In64BitMode]>;
2678 def : MnemonicAlias<"sgdt", "sgdtw", "att">, Requires<[In16BitMode]>;
2679 def : MnemonicAlias<"sgdt", "sgdtl", "att">, Requires<[In32BitMode]>;
2680 def : MnemonicAlias<"sgdt", "sgdtq", "att">, Requires<[In64BitMode]>;
2681 def : MnemonicAlias<"sidt", "sidtw", "att">, Requires<[In16BitMode]>;
2682 def : MnemonicAlias<"sidt", "sidtl", "att">, Requires<[In32BitMode]>;
2683 def : MnemonicAlias<"sidt", "sidtq", "att">, Requires<[In64BitMode]>;
2686 // Floating point stack aliases.
2687 def : MnemonicAlias<"fcmovz", "fcmove", "att">;
2688 def : MnemonicAlias<"fcmova", "fcmovnbe", "att">;
2689 def : MnemonicAlias<"fcmovnae", "fcmovb", "att">;
2690 def : MnemonicAlias<"fcmovna", "fcmovbe", "att">;
2691 def : MnemonicAlias<"fcmovae", "fcmovnb", "att">;
2692 def : MnemonicAlias<"fcomip", "fcompi">;
2693 def : MnemonicAlias<"fildq", "fildll", "att">;
2694 def : MnemonicAlias<"fistpq", "fistpll", "att">;
2695 def : MnemonicAlias<"fisttpq", "fisttpll", "att">;
2696 def : MnemonicAlias<"fldcww", "fldcw", "att">;
2697 def : MnemonicAlias<"fnstcww", "fnstcw", "att">;
2698 def : MnemonicAlias<"fnstsww", "fnstsw", "att">;
2699 def : MnemonicAlias<"fucomip", "fucompi">;
2700 def : MnemonicAlias<"fwait", "wait">;
2702 def : MnemonicAlias<"fxsaveq", "fxsave64", "att">;
2703 def : MnemonicAlias<"fxrstorq", "fxrstor64", "att">;
2704 def : MnemonicAlias<"xsaveq", "xsave64", "att">;
2705 def : MnemonicAlias<"xrstorq", "xrstor64", "att">;
2706 def : MnemonicAlias<"xsaveoptq", "xsaveopt64", "att">;
2707 def : MnemonicAlias<"xrstorsq", "xrstors64", "att">;
2708 def : MnemonicAlias<"xsavecq", "xsavec64", "att">;
2709 def : MnemonicAlias<"xsavesq", "xsaves64", "att">;
2711 class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond,
2713 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix),
2714 !strconcat(Prefix, NewCond, Suffix), VariantName>;
2716 /// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of
2717 /// MnemonicAlias's that canonicalize the condition code in a mnemonic, for
2718 /// example "setz" -> "sete".
2719 multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix,
2721 def C : CondCodeAlias<Prefix, Suffix, "c", "b", V>; // setc -> setb
2722 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e", V>; // setz -> sete
2723 def NA : CondCodeAlias<Prefix, Suffix, "na", "be", V>; // setna -> setbe
2724 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae", V>; // setnb -> setae
2725 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae", V>; // setnc -> setae
2726 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le", V>; // setng -> setle
2727 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge", V>; // setnl -> setge
2728 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne", V>; // setnz -> setne
2729 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p", V>; // setpe -> setp
2730 def PO : CondCodeAlias<Prefix, Suffix, "po", "np", V>; // setpo -> setnp
2732 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b", V>; // setnae -> setb
2733 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a", V>; // setnbe -> seta
2734 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l", V>; // setnge -> setl
2735 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g", V>; // setnle -> setg
2738 // Aliases for set<CC>
2739 defm : IntegerCondCodeMnemonicAlias<"set", "">;
2740 // Aliases for j<CC>
2741 defm : IntegerCondCodeMnemonicAlias<"j", "">;
2742 // Aliases for cmov<CC>{w,l,q}
2743 defm : IntegerCondCodeMnemonicAlias<"cmov", "w", "att">;
2744 defm : IntegerCondCodeMnemonicAlias<"cmov", "l", "att">;
2745 defm : IntegerCondCodeMnemonicAlias<"cmov", "q", "att">;
2746 // No size suffix for intel-style asm.
2747 defm : IntegerCondCodeMnemonicAlias<"cmov", "", "intel">;
2750 //===----------------------------------------------------------------------===//
2751 // Assembler Instruction Aliases
2752 //===----------------------------------------------------------------------===//
2754 // aad/aam default to base 10 if no operand is specified.
2755 def : InstAlias<"aad", (AAD8i8 10)>, Requires<[Not64BitMode]>;
2756 def : InstAlias<"aam", (AAM8i8 10)>, Requires<[Not64BitMode]>;
2758 // Disambiguate the mem/imm form of bt-without-a-suffix as btl.
2759 // Likewise for btc/btr/bts.
2760 def : InstAlias<"bt {$imm, $mem|$mem, $imm}",
2761 (BT32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2762 def : InstAlias<"btc {$imm, $mem|$mem, $imm}",
2763 (BTC32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2764 def : InstAlias<"btr {$imm, $mem|$mem, $imm}",
2765 (BTR32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2766 def : InstAlias<"bts {$imm, $mem|$mem, $imm}",
2767 (BTS32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2770 def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg), 0>;
2771 def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg), 0>;
2772 def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg), 0>;
2773 def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg), 0>;
2775 // lods aliases. Accept the destination being omitted because it's implicit
2776 // in the mnemonic, or the mnemonic suffix being omitted because it's implicit
2777 // in the destination.
2778 def : InstAlias<"lodsb $src", (LODSB srcidx8:$src), 0>;
2779 def : InstAlias<"lodsw $src", (LODSW srcidx16:$src), 0>;
2780 def : InstAlias<"lods{l|d} $src", (LODSL srcidx32:$src), 0>;
2781 def : InstAlias<"lodsq $src", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>;
2782 def : InstAlias<"lods {$src, %al|al, $src}", (LODSB srcidx8:$src), 0>;
2783 def : InstAlias<"lods {$src, %ax|ax, $src}", (LODSW srcidx16:$src), 0>;
2784 def : InstAlias<"lods {$src, %eax|eax, $src}", (LODSL srcidx32:$src), 0>;
2785 def : InstAlias<"lods {$src, %rax|rax, $src}", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>;
2787 // stos aliases. Accept the source being omitted because it's implicit in
2788 // the mnemonic, or the mnemonic suffix being omitted because it's implicit
2790 def : InstAlias<"stosb $dst", (STOSB dstidx8:$dst), 0>;
2791 def : InstAlias<"stosw $dst", (STOSW dstidx16:$dst), 0>;
2792 def : InstAlias<"stos{l|d} $dst", (STOSL dstidx32:$dst), 0>;
2793 def : InstAlias<"stosq $dst", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2794 def : InstAlias<"stos {%al, $dst|$dst, al}", (STOSB dstidx8:$dst), 0>;
2795 def : InstAlias<"stos {%ax, $dst|$dst, ax}", (STOSW dstidx16:$dst), 0>;
2796 def : InstAlias<"stos {%eax, $dst|$dst, eax}", (STOSL dstidx32:$dst), 0>;
2797 def : InstAlias<"stos {%rax, $dst|$dst, rax}", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2799 // scas aliases. Accept the destination being omitted because it's implicit
2800 // in the mnemonic, or the mnemonic suffix being omitted because it's implicit
2801 // in the destination.
2802 def : InstAlias<"scasb $dst", (SCASB dstidx8:$dst), 0>;
2803 def : InstAlias<"scasw $dst", (SCASW dstidx16:$dst), 0>;
2804 def : InstAlias<"scas{l|d} $dst", (SCASL dstidx32:$dst), 0>;
2805 def : InstAlias<"scasq $dst", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2806 def : InstAlias<"scas {$dst, %al|al, $dst}", (SCASB dstidx8:$dst), 0>;
2807 def : InstAlias<"scas {$dst, %ax|ax, $dst}", (SCASW dstidx16:$dst), 0>;
2808 def : InstAlias<"scas {$dst, %eax|eax, $dst}", (SCASL dstidx32:$dst), 0>;
2809 def : InstAlias<"scas {$dst, %rax|rax, $dst}", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2811 // div and idiv aliases for explicit A register.
2812 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>;
2813 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16r GR16:$src)>;
2814 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32r GR32:$src)>;
2815 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64r GR64:$src)>;
2816 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8m i8mem :$src)>;
2817 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16m i16mem:$src)>;
2818 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32m i32mem:$src)>;
2819 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64m i64mem:$src)>;
2820 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8r GR8 :$src)>;
2821 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16r GR16:$src)>;
2822 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32r GR32:$src)>;
2823 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64r GR64:$src)>;
2824 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8m i8mem :$src)>;
2825 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16m i16mem:$src)>;
2826 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32m i32mem:$src)>;
2827 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64m i64mem:$src)>;
2831 // Various unary fpstack operations default to operating on on ST1.
2832 // For example, "fxch" -> "fxch %st(1)"
2833 def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>;
2834 def: InstAlias<"fadd", (ADD_FPrST0 ST1), 0>;
2835 def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>;
2836 def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>;
2837 def : InstAlias<"fmul", (MUL_FPrST0 ST1), 0>;
2838 def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>;
2839 def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>;
2840 def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>;
2841 def : InstAlias<"fxch", (XCH_F ST1), 0>;
2842 def : InstAlias<"fcom", (COM_FST0r ST1), 0>;
2843 def : InstAlias<"fcomp", (COMP_FST0r ST1), 0>;
2844 def : InstAlias<"fcomi", (COM_FIr ST1), 0>;
2845 def : InstAlias<"fcompi", (COM_FIPr ST1), 0>;
2846 def : InstAlias<"fucom", (UCOM_Fr ST1), 0>;
2847 def : InstAlias<"fucomp", (UCOM_FPr ST1), 0>;
2848 def : InstAlias<"fucomi", (UCOM_FIr ST1), 0>;
2849 def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>;
2851 // Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op.
2852 // For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate
2853 // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
2855 multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> {
2856 def : InstAlias<!strconcat(Mnemonic, "\t{$op, %st(0)|st(0), $op}"),
2857 (Inst RST:$op), EmitAlias>;
2858 def : InstAlias<!strconcat(Mnemonic, "\t{%st(0), %st(0)|st(0), st(0)}"),
2859 (Inst ST0), EmitAlias>;
2862 defm : FpUnaryAlias<"fadd", ADD_FST0r>;
2863 defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>;
2864 defm : FpUnaryAlias<"fsub", SUB_FST0r>;
2865 defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0>;
2866 defm : FpUnaryAlias<"fsubr", SUBR_FST0r>;
2867 defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0>;
2868 defm : FpUnaryAlias<"fmul", MUL_FST0r>;
2869 defm : FpUnaryAlias<"fmulp", MUL_FPrST0>;
2870 defm : FpUnaryAlias<"fdiv", DIV_FST0r>;
2871 defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0>;
2872 defm : FpUnaryAlias<"fdivr", DIVR_FST0r>;
2873 defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0>;
2874 defm : FpUnaryAlias<"fcomi", COM_FIr, 0>;
2875 defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>;
2876 defm : FpUnaryAlias<"fcompi", COM_FIPr>;
2877 defm : FpUnaryAlias<"fucompi", UCOM_FIPr>;
2880 // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
2881 // commute. We also allow fdiv[r]p/fsubrp even though they don't commute,
2882 // solely because gas supports it.
2883 def : InstAlias<"faddp\t{%st(0), $op|$op, st(0)}", (ADD_FPrST0 RST:$op), 0>;
2884 def : InstAlias<"fmulp\t{%st(0), $op|$op, st(0)}", (MUL_FPrST0 RST:$op)>;
2885 def : InstAlias<"fsub{|r}p\t{%st(0), $op|$op, st(0)}", (SUBR_FPrST0 RST:$op)>;
2886 def : InstAlias<"fsub{r|}p\t{%st(0), $op|$op, st(0)}", (SUB_FPrST0 RST:$op)>;
2887 def : InstAlias<"fdiv{|r}p\t{%st(0), $op|$op, st(0)}", (DIVR_FPrST0 RST:$op)>;
2888 def : InstAlias<"fdiv{r|}p\t{%st(0), $op|$op, st(0)}", (DIV_FPrST0 RST:$op)>;
2890 // We accept "fnstsw %eax" even though it only writes %ax.
2891 def : InstAlias<"fnstsw\t{%eax|eax}", (FNSTSW16r)>;
2892 def : InstAlias<"fnstsw\t{%al|al}" , (FNSTSW16r)>;
2893 def : InstAlias<"fnstsw" , (FNSTSW16r)>;
2895 // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but
2896 // this is compatible with what GAS does.
2897 def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg), 0>, Requires<[Not16BitMode]>;
2898 def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg), 0>, Requires<[Not16BitMode]>;
2899 def : InstAlias<"lcall {*}$dst", (FARCALL32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>;
2900 def : InstAlias<"ljmp {*}$dst", (FARJMP32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>;
2901 def : InstAlias<"lcall $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>;
2902 def : InstAlias<"ljmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>;
2903 def : InstAlias<"lcall {*}$dst", (FARCALL16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>;
2904 def : InstAlias<"ljmp {*}$dst", (FARJMP16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>;
2906 def : InstAlias<"call {*}$dst", (CALL64m i64mem:$dst), 0>, Requires<[In64BitMode]>;
2907 def : InstAlias<"jmp {*}$dst", (JMP64m i64mem:$dst), 0>, Requires<[In64BitMode]>;
2908 def : InstAlias<"call {*}$dst", (CALL32m i32mem:$dst), 0>, Requires<[In32BitMode]>;
2909 def : InstAlias<"jmp {*}$dst", (JMP32m i32mem:$dst), 0>, Requires<[In32BitMode]>;
2910 def : InstAlias<"call {*}$dst", (CALL16m i16mem:$dst), 0>, Requires<[In16BitMode]>;
2911 def : InstAlias<"jmp {*}$dst", (JMP16m i16mem:$dst), 0>, Requires<[In16BitMode]>;
2914 // "imul <imm>, B" is an alias for "imul <imm>, B, B".
2915 def : InstAlias<"imul{w} {$imm, $r|$r, $imm}", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm), 0>;
2916 def : InstAlias<"imul{w} {$imm, $r|$r, $imm}", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm), 0>;
2917 def : InstAlias<"imul{l} {$imm, $r|$r, $imm}", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm), 0>;
2918 def : InstAlias<"imul{l} {$imm, $r|$r, $imm}", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm), 0>;
2919 def : InstAlias<"imul{q} {$imm, $r|$r, $imm}", (IMUL64rri32 GR64:$r, GR64:$r, i64i32imm:$imm), 0>;
2920 def : InstAlias<"imul{q} {$imm, $r|$r, $imm}", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm), 0>;
2922 // inb %dx -> inb %al, %dx
2923 def : InstAlias<"inb\t{%dx|dx}", (IN8rr), 0>;
2924 def : InstAlias<"inw\t{%dx|dx}", (IN16rr), 0>;
2925 def : InstAlias<"inl\t{%dx|dx}", (IN32rr), 0>;
2926 def : InstAlias<"inb\t$port", (IN8ri u8imm:$port), 0>;
2927 def : InstAlias<"inw\t$port", (IN16ri u8imm:$port), 0>;
2928 def : InstAlias<"inl\t$port", (IN32ri u8imm:$port), 0>;
2931 // jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp
2932 def : InstAlias<"call $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2933 def : InstAlias<"jmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2934 def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2935 def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2936 def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>;
2937 def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>;
2938 def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
2939 def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
2941 // Force mov without a suffix with a segment and mem to prefer the 'l' form of
2942 // the move. All segment/mem forms are equivalent, this has the shortest
2944 def : InstAlias<"mov {$mem, $seg|$seg, $mem}", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem), 0>;
2945 def : InstAlias<"mov {$seg, $mem|$mem, $seg}", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg), 0>;
2947 // Match 'movq <largeimm>, <reg>' as an alias for movabsq.
2948 def : InstAlias<"movq {$imm, $reg|$reg, $imm}", (MOV64ri GR64:$reg, i64imm:$imm), 0>;
2950 // Match 'movq GR64, MMX' as an alias for movd.
2951 def : InstAlias<"movq {$src, $dst|$dst, $src}",
2952 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>;
2953 def : InstAlias<"movq {$src, $dst|$dst, $src}",
2954 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>;
2957 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>;
2958 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>;
2959 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>;
2960 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>;
2961 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>;
2962 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>;
2963 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>;
2966 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>;
2967 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>;
2968 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>;
2969 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>;
2970 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>;
2971 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>;
2972 // Note: No GR32->GR64 movzx form.
2974 // outb %dx -> outb %al, %dx
2975 def : InstAlias<"outb\t{%dx|dx}", (OUT8rr), 0>;
2976 def : InstAlias<"outw\t{%dx|dx}", (OUT16rr), 0>;
2977 def : InstAlias<"outl\t{%dx|dx}", (OUT32rr), 0>;
2978 def : InstAlias<"outb\t$port", (OUT8ir u8imm:$port), 0>;
2979 def : InstAlias<"outw\t$port", (OUT16ir u8imm:$port), 0>;
2980 def : InstAlias<"outl\t$port", (OUT32ir u8imm:$port), 0>;
2982 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
2983 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
2984 // errors, since its encoding is the most compact.
2985 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem), 0>;
2987 // shld/shrd op,op -> shld op, op, CL
2988 def : InstAlias<"shld{w}\t{$r2, $r1|$r1, $r2}", (SHLD16rrCL GR16:$r1, GR16:$r2), 0>;
2989 def : InstAlias<"shld{l}\t{$r2, $r1|$r1, $r2}", (SHLD32rrCL GR32:$r1, GR32:$r2), 0>;
2990 def : InstAlias<"shld{q}\t{$r2, $r1|$r1, $r2}", (SHLD64rrCL GR64:$r1, GR64:$r2), 0>;
2991 def : InstAlias<"shrd{w}\t{$r2, $r1|$r1, $r2}", (SHRD16rrCL GR16:$r1, GR16:$r2), 0>;
2992 def : InstAlias<"shrd{l}\t{$r2, $r1|$r1, $r2}", (SHRD32rrCL GR32:$r1, GR32:$r2), 0>;
2993 def : InstAlias<"shrd{q}\t{$r2, $r1|$r1, $r2}", (SHRD64rrCL GR64:$r1, GR64:$r2), 0>;
2995 def : InstAlias<"shld{w}\t{$reg, $mem|$mem, $reg}", (SHLD16mrCL i16mem:$mem, GR16:$reg), 0>;
2996 def : InstAlias<"shld{l}\t{$reg, $mem|$mem, $reg}", (SHLD32mrCL i32mem:$mem, GR32:$reg), 0>;
2997 def : InstAlias<"shld{q}\t{$reg, $mem|$mem, $reg}", (SHLD64mrCL i64mem:$mem, GR64:$reg), 0>;
2998 def : InstAlias<"shrd{w}\t{$reg, $mem|$mem, $reg}", (SHRD16mrCL i16mem:$mem, GR16:$reg), 0>;
2999 def : InstAlias<"shrd{l}\t{$reg, $mem|$mem, $reg}", (SHRD32mrCL i32mem:$mem, GR32:$reg), 0>;
3000 def : InstAlias<"shrd{q}\t{$reg, $mem|$mem, $reg}", (SHRD64mrCL i64mem:$mem, GR64:$reg), 0>;
3002 /* FIXME: This is disabled because the asm matcher is currently incapable of
3003 * matching a fixed immediate like $1.
3004 // "shl X, $1" is an alias for "shl X".
3005 multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> {
3006 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
3007 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>;
3008 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
3009 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>;
3010 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
3011 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>;
3012 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
3013 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>;
3014 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
3015 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>;
3016 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
3017 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>;
3018 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
3019 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>;
3020 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
3021 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>;
3024 defm : ShiftRotateByOneAlias<"rcl", "RCL">;
3025 defm : ShiftRotateByOneAlias<"rcr", "RCR">;
3026 defm : ShiftRotateByOneAlias<"rol", "ROL">;
3027 defm : ShiftRotateByOneAlias<"ror", "ROR">;
3030 // test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
3031 def : InstAlias<"test{b}\t{$val, $mem|$mem, $val}",
3032 (TEST8rm GR8 :$val, i8mem :$mem), 0>;
3033 def : InstAlias<"test{w}\t{$val, $mem|$mem, $val}",
3034 (TEST16rm GR16:$val, i16mem:$mem), 0>;
3035 def : InstAlias<"test{l}\t{$val, $mem|$mem, $val}",
3036 (TEST32rm GR32:$val, i32mem:$mem), 0>;
3037 def : InstAlias<"test{q}\t{$val, $mem|$mem, $val}",
3038 (TEST64rm GR64:$val, i64mem:$mem), 0>;
3040 // xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms.
3041 def : InstAlias<"xchg{b}\t{$mem, $val|$val, $mem}",
3042 (XCHG8rm GR8 :$val, i8mem :$mem), 0>;
3043 def : InstAlias<"xchg{w}\t{$mem, $val|$val, $mem}",
3044 (XCHG16rm GR16:$val, i16mem:$mem), 0>;
3045 def : InstAlias<"xchg{l}\t{$mem, $val|$val, $mem}",
3046 (XCHG32rm GR32:$val, i32mem:$mem), 0>;
3047 def : InstAlias<"xchg{q}\t{$mem, $val|$val, $mem}",
3048 (XCHG64rm GR64:$val, i64mem:$mem), 0>;
3050 // xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms.
3051 def : InstAlias<"xchg{w}\t{%ax, $src|$src, ax}", (XCHG16ar GR16:$src), 0>;
3052 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}",
3053 (XCHG32ar GR32:$src), 0>, Requires<[Not64BitMode]>;
3054 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}",
3055 (XCHG32ar64 GR32_NOAX:$src), 0>, Requires<[In64BitMode]>;
3056 def : InstAlias<"xchg{q}\t{%rax, $src|$src, rax}", (XCHG64ar GR64:$src), 0>;
3058 // These aliases exist to get the parser to prioritize matching 8-bit
3059 // immediate encodings over matching the implicit ax/eax/rax encodings. By
3060 // explicitly mentioning the A register here, these entries will be ordered
3061 // first due to the more explicit immediate type.
3062 def : InstAlias<"adc{w}\t{$imm, %ax|ax, $imm}", (ADC16ri8 AX, i16i8imm:$imm), 0>;
3063 def : InstAlias<"add{w}\t{$imm, %ax|ax, $imm}", (ADD16ri8 AX, i16i8imm:$imm), 0>;
3064 def : InstAlias<"and{w}\t{$imm, %ax|ax, $imm}", (AND16ri8 AX, i16i8imm:$imm), 0>;
3065 def : InstAlias<"cmp{w}\t{$imm, %ax|ax, $imm}", (CMP16ri8 AX, i16i8imm:$imm), 0>;
3066 def : InstAlias<"or{w}\t{$imm, %ax|ax, $imm}", (OR16ri8 AX, i16i8imm:$imm), 0>;
3067 def : InstAlias<"sbb{w}\t{$imm, %ax|ax, $imm}", (SBB16ri8 AX, i16i8imm:$imm), 0>;
3068 def : InstAlias<"sub{w}\t{$imm, %ax|ax, $imm}", (SUB16ri8 AX, i16i8imm:$imm), 0>;
3069 def : InstAlias<"xor{w}\t{$imm, %ax|ax, $imm}", (XOR16ri8 AX, i16i8imm:$imm), 0>;
3071 def : InstAlias<"adc{l}\t{$imm, %eax|eax, $imm}", (ADC32ri8 EAX, i32i8imm:$imm), 0>;
3072 def : InstAlias<"add{l}\t{$imm, %eax|eax, $imm}", (ADD32ri8 EAX, i32i8imm:$imm), 0>;
3073 def : InstAlias<"and{l}\t{$imm, %eax|eax, $imm}", (AND32ri8 EAX, i32i8imm:$imm), 0>;
3074 def : InstAlias<"cmp{l}\t{$imm, %eax|eax, $imm}", (CMP32ri8 EAX, i32i8imm:$imm), 0>;
3075 def : InstAlias<"or{l}\t{$imm, %eax|eax, $imm}", (OR32ri8 EAX, i32i8imm:$imm), 0>;
3076 def : InstAlias<"sbb{l}\t{$imm, %eax|eax, $imm}", (SBB32ri8 EAX, i32i8imm:$imm), 0>;
3077 def : InstAlias<"sub{l}\t{$imm, %eax|eax, $imm}", (SUB32ri8 EAX, i32i8imm:$imm), 0>;
3078 def : InstAlias<"xor{l}\t{$imm, %eax|eax, $imm}", (XOR32ri8 EAX, i32i8imm:$imm), 0>;
3080 def : InstAlias<"adc{q}\t{$imm, %rax|rax, $imm}", (ADC64ri8 RAX, i64i8imm:$imm), 0>;
3081 def : InstAlias<"add{q}\t{$imm, %rax|rax, $imm}", (ADD64ri8 RAX, i64i8imm:$imm), 0>;
3082 def : InstAlias<"and{q}\t{$imm, %rax|rax, $imm}", (AND64ri8 RAX, i64i8imm:$imm), 0>;
3083 def : InstAlias<"cmp{q}\t{$imm, %rax|rax, $imm}", (CMP64ri8 RAX, i64i8imm:$imm), 0>;
3084 def : InstAlias<"or{q}\t{$imm, %rax|rax, $imm}", (OR64ri8 RAX, i64i8imm:$imm), 0>;
3085 def : InstAlias<"sbb{q}\t{$imm, %rax|rax, $imm}", (SBB64ri8 RAX, i64i8imm:$imm), 0>;
3086 def : InstAlias<"sub{q}\t{$imm, %rax|rax, $imm}", (SUB64ri8 RAX, i64i8imm:$imm), 0>;
3087 def : InstAlias<"xor{q}\t{$imm, %rax|rax, $imm}", (XOR64ri8 RAX, i64i8imm:$imm), 0>;