1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
16 #include "X86GenInstrInfo.inc"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/LLVMContext.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/LiveVariables.h"
29 #include "llvm/CodeGen/PseudoSourceValue.h"
30 #include "llvm/MC/MCInst.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetOptions.h"
36 #include "llvm/MC/MCAsmInfo.h"
42 NoFusing("disable-spill-fusing",
43 cl::desc("Disable fusing of spill code into instructions"));
45 PrintFailedFusing("print-failed-fuse-candidates",
46 cl::desc("Print instructions that the allocator wants to"
47 " fuse, but the X86 backend currently can't"),
50 ReMatPICStubLoad("remat-pic-stub-load",
51 cl::desc("Re-materialize load from stub in PIC mode"),
52 cl::init(false), cl::Hidden);
54 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
55 : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)),
56 TM(tm), RI(tm, *this) {
58 TB_NOT_REVERSABLE = 1U << 31,
59 TB_FLAGS = TB_NOT_REVERSABLE
62 static const unsigned OpTbl2Addr[][2] = {
63 { X86::ADC32ri, X86::ADC32mi },
64 { X86::ADC32ri8, X86::ADC32mi8 },
65 { X86::ADC32rr, X86::ADC32mr },
66 { X86::ADC64ri32, X86::ADC64mi32 },
67 { X86::ADC64ri8, X86::ADC64mi8 },
68 { X86::ADC64rr, X86::ADC64mr },
69 { X86::ADD16ri, X86::ADD16mi },
70 { X86::ADD16ri8, X86::ADD16mi8 },
71 { X86::ADD16ri_DB, X86::ADD16mi | TB_NOT_REVERSABLE },
72 { X86::ADD16ri8_DB, X86::ADD16mi8 | TB_NOT_REVERSABLE },
73 { X86::ADD16rr, X86::ADD16mr },
74 { X86::ADD16rr_DB, X86::ADD16mr | TB_NOT_REVERSABLE },
75 { X86::ADD32ri, X86::ADD32mi },
76 { X86::ADD32ri8, X86::ADD32mi8 },
77 { X86::ADD32ri_DB, X86::ADD32mi | TB_NOT_REVERSABLE },
78 { X86::ADD32ri8_DB, X86::ADD32mi8 | TB_NOT_REVERSABLE },
79 { X86::ADD32rr, X86::ADD32mr },
80 { X86::ADD32rr_DB, X86::ADD32mr | TB_NOT_REVERSABLE },
81 { X86::ADD64ri32, X86::ADD64mi32 },
82 { X86::ADD64ri8, X86::ADD64mi8 },
83 { X86::ADD64ri32_DB,X86::ADD64mi32 | TB_NOT_REVERSABLE },
84 { X86::ADD64ri8_DB, X86::ADD64mi8 | TB_NOT_REVERSABLE },
85 { X86::ADD64rr, X86::ADD64mr },
86 { X86::ADD64rr_DB, X86::ADD64mr | TB_NOT_REVERSABLE },
87 { X86::ADD8ri, X86::ADD8mi },
88 { X86::ADD8rr, X86::ADD8mr },
89 { X86::AND16ri, X86::AND16mi },
90 { X86::AND16ri8, X86::AND16mi8 },
91 { X86::AND16rr, X86::AND16mr },
92 { X86::AND32ri, X86::AND32mi },
93 { X86::AND32ri8, X86::AND32mi8 },
94 { X86::AND32rr, X86::AND32mr },
95 { X86::AND64ri32, X86::AND64mi32 },
96 { X86::AND64ri8, X86::AND64mi8 },
97 { X86::AND64rr, X86::AND64mr },
98 { X86::AND8ri, X86::AND8mi },
99 { X86::AND8rr, X86::AND8mr },
100 { X86::DEC16r, X86::DEC16m },
101 { X86::DEC32r, X86::DEC32m },
102 { X86::DEC64_16r, X86::DEC64_16m },
103 { X86::DEC64_32r, X86::DEC64_32m },
104 { X86::DEC64r, X86::DEC64m },
105 { X86::DEC8r, X86::DEC8m },
106 { X86::INC16r, X86::INC16m },
107 { X86::INC32r, X86::INC32m },
108 { X86::INC64_16r, X86::INC64_16m },
109 { X86::INC64_32r, X86::INC64_32m },
110 { X86::INC64r, X86::INC64m },
111 { X86::INC8r, X86::INC8m },
112 { X86::NEG16r, X86::NEG16m },
113 { X86::NEG32r, X86::NEG32m },
114 { X86::NEG64r, X86::NEG64m },
115 { X86::NEG8r, X86::NEG8m },
116 { X86::NOT16r, X86::NOT16m },
117 { X86::NOT32r, X86::NOT32m },
118 { X86::NOT64r, X86::NOT64m },
119 { X86::NOT8r, X86::NOT8m },
120 { X86::OR16ri, X86::OR16mi },
121 { X86::OR16ri8, X86::OR16mi8 },
122 { X86::OR16rr, X86::OR16mr },
123 { X86::OR32ri, X86::OR32mi },
124 { X86::OR32ri8, X86::OR32mi8 },
125 { X86::OR32rr, X86::OR32mr },
126 { X86::OR64ri32, X86::OR64mi32 },
127 { X86::OR64ri8, X86::OR64mi8 },
128 { X86::OR64rr, X86::OR64mr },
129 { X86::OR8ri, X86::OR8mi },
130 { X86::OR8rr, X86::OR8mr },
131 { X86::ROL16r1, X86::ROL16m1 },
132 { X86::ROL16rCL, X86::ROL16mCL },
133 { X86::ROL16ri, X86::ROL16mi },
134 { X86::ROL32r1, X86::ROL32m1 },
135 { X86::ROL32rCL, X86::ROL32mCL },
136 { X86::ROL32ri, X86::ROL32mi },
137 { X86::ROL64r1, X86::ROL64m1 },
138 { X86::ROL64rCL, X86::ROL64mCL },
139 { X86::ROL64ri, X86::ROL64mi },
140 { X86::ROL8r1, X86::ROL8m1 },
141 { X86::ROL8rCL, X86::ROL8mCL },
142 { X86::ROL8ri, X86::ROL8mi },
143 { X86::ROR16r1, X86::ROR16m1 },
144 { X86::ROR16rCL, X86::ROR16mCL },
145 { X86::ROR16ri, X86::ROR16mi },
146 { X86::ROR32r1, X86::ROR32m1 },
147 { X86::ROR32rCL, X86::ROR32mCL },
148 { X86::ROR32ri, X86::ROR32mi },
149 { X86::ROR64r1, X86::ROR64m1 },
150 { X86::ROR64rCL, X86::ROR64mCL },
151 { X86::ROR64ri, X86::ROR64mi },
152 { X86::ROR8r1, X86::ROR8m1 },
153 { X86::ROR8rCL, X86::ROR8mCL },
154 { X86::ROR8ri, X86::ROR8mi },
155 { X86::SAR16r1, X86::SAR16m1 },
156 { X86::SAR16rCL, X86::SAR16mCL },
157 { X86::SAR16ri, X86::SAR16mi },
158 { X86::SAR32r1, X86::SAR32m1 },
159 { X86::SAR32rCL, X86::SAR32mCL },
160 { X86::SAR32ri, X86::SAR32mi },
161 { X86::SAR64r1, X86::SAR64m1 },
162 { X86::SAR64rCL, X86::SAR64mCL },
163 { X86::SAR64ri, X86::SAR64mi },
164 { X86::SAR8r1, X86::SAR8m1 },
165 { X86::SAR8rCL, X86::SAR8mCL },
166 { X86::SAR8ri, X86::SAR8mi },
167 { X86::SBB32ri, X86::SBB32mi },
168 { X86::SBB32ri8, X86::SBB32mi8 },
169 { X86::SBB32rr, X86::SBB32mr },
170 { X86::SBB64ri32, X86::SBB64mi32 },
171 { X86::SBB64ri8, X86::SBB64mi8 },
172 { X86::SBB64rr, X86::SBB64mr },
173 { X86::SHL16rCL, X86::SHL16mCL },
174 { X86::SHL16ri, X86::SHL16mi },
175 { X86::SHL32rCL, X86::SHL32mCL },
176 { X86::SHL32ri, X86::SHL32mi },
177 { X86::SHL64rCL, X86::SHL64mCL },
178 { X86::SHL64ri, X86::SHL64mi },
179 { X86::SHL8rCL, X86::SHL8mCL },
180 { X86::SHL8ri, X86::SHL8mi },
181 { X86::SHLD16rrCL, X86::SHLD16mrCL },
182 { X86::SHLD16rri8, X86::SHLD16mri8 },
183 { X86::SHLD32rrCL, X86::SHLD32mrCL },
184 { X86::SHLD32rri8, X86::SHLD32mri8 },
185 { X86::SHLD64rrCL, X86::SHLD64mrCL },
186 { X86::SHLD64rri8, X86::SHLD64mri8 },
187 { X86::SHR16r1, X86::SHR16m1 },
188 { X86::SHR16rCL, X86::SHR16mCL },
189 { X86::SHR16ri, X86::SHR16mi },
190 { X86::SHR32r1, X86::SHR32m1 },
191 { X86::SHR32rCL, X86::SHR32mCL },
192 { X86::SHR32ri, X86::SHR32mi },
193 { X86::SHR64r1, X86::SHR64m1 },
194 { X86::SHR64rCL, X86::SHR64mCL },
195 { X86::SHR64ri, X86::SHR64mi },
196 { X86::SHR8r1, X86::SHR8m1 },
197 { X86::SHR8rCL, X86::SHR8mCL },
198 { X86::SHR8ri, X86::SHR8mi },
199 { X86::SHRD16rrCL, X86::SHRD16mrCL },
200 { X86::SHRD16rri8, X86::SHRD16mri8 },
201 { X86::SHRD32rrCL, X86::SHRD32mrCL },
202 { X86::SHRD32rri8, X86::SHRD32mri8 },
203 { X86::SHRD64rrCL, X86::SHRD64mrCL },
204 { X86::SHRD64rri8, X86::SHRD64mri8 },
205 { X86::SUB16ri, X86::SUB16mi },
206 { X86::SUB16ri8, X86::SUB16mi8 },
207 { X86::SUB16rr, X86::SUB16mr },
208 { X86::SUB32ri, X86::SUB32mi },
209 { X86::SUB32ri8, X86::SUB32mi8 },
210 { X86::SUB32rr, X86::SUB32mr },
211 { X86::SUB64ri32, X86::SUB64mi32 },
212 { X86::SUB64ri8, X86::SUB64mi8 },
213 { X86::SUB64rr, X86::SUB64mr },
214 { X86::SUB8ri, X86::SUB8mi },
215 { X86::SUB8rr, X86::SUB8mr },
216 { X86::XOR16ri, X86::XOR16mi },
217 { X86::XOR16ri8, X86::XOR16mi8 },
218 { X86::XOR16rr, X86::XOR16mr },
219 { X86::XOR32ri, X86::XOR32mi },
220 { X86::XOR32ri8, X86::XOR32mi8 },
221 { X86::XOR32rr, X86::XOR32mr },
222 { X86::XOR64ri32, X86::XOR64mi32 },
223 { X86::XOR64ri8, X86::XOR64mi8 },
224 { X86::XOR64rr, X86::XOR64mr },
225 { X86::XOR8ri, X86::XOR8mi },
226 { X86::XOR8rr, X86::XOR8mr }
229 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
230 unsigned RegOp = OpTbl2Addr[i][0];
231 unsigned MemOp = OpTbl2Addr[i][1] & ~TB_FLAGS;
232 assert(!RegOp2MemOpTable2Addr.count(RegOp) && "Duplicated entries?");
233 RegOp2MemOpTable2Addr[RegOp] = std::make_pair(MemOp, 0U);
235 // If this is not a reversible operation (because there is a many->one)
236 // mapping, don't insert the reverse of the operation into MemOp2RegOpTable.
237 if (OpTbl2Addr[i][1] & TB_NOT_REVERSABLE)
240 // Index 0, folded load and store, no alignment requirement.
241 unsigned AuxInfo = 0 | (1 << 4) | (1 << 5);
243 assert(!MemOp2RegOpTable.count(MemOp) &&
244 "Duplicated entries in unfolding maps?");
245 MemOp2RegOpTable[MemOp] = std::make_pair(RegOp, AuxInfo);
248 // If the third value is 1, then it's folding either a load or a store.
249 static const unsigned OpTbl0[][4] = {
250 { X86::BT16ri8, X86::BT16mi8, 1, 0 },
251 { X86::BT32ri8, X86::BT32mi8, 1, 0 },
252 { X86::BT64ri8, X86::BT64mi8, 1, 0 },
253 { X86::CALL32r, X86::CALL32m, 1, 0 },
254 { X86::CALL64r, X86::CALL64m, 1, 0 },
255 { X86::WINCALL64r, X86::WINCALL64m, 1, 0 },
256 { X86::CMP16ri, X86::CMP16mi, 1, 0 },
257 { X86::CMP16ri8, X86::CMP16mi8, 1, 0 },
258 { X86::CMP16rr, X86::CMP16mr, 1, 0 },
259 { X86::CMP32ri, X86::CMP32mi, 1, 0 },
260 { X86::CMP32ri8, X86::CMP32mi8, 1, 0 },
261 { X86::CMP32rr, X86::CMP32mr, 1, 0 },
262 { X86::CMP64ri32, X86::CMP64mi32, 1, 0 },
263 { X86::CMP64ri8, X86::CMP64mi8, 1, 0 },
264 { X86::CMP64rr, X86::CMP64mr, 1, 0 },
265 { X86::CMP8ri, X86::CMP8mi, 1, 0 },
266 { X86::CMP8rr, X86::CMP8mr, 1, 0 },
267 { X86::DIV16r, X86::DIV16m, 1, 0 },
268 { X86::DIV32r, X86::DIV32m, 1, 0 },
269 { X86::DIV64r, X86::DIV64m, 1, 0 },
270 { X86::DIV8r, X86::DIV8m, 1, 0 },
271 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, 0, 16 },
272 { X86::FsMOVAPDrr, X86::MOVSDmr | TB_NOT_REVERSABLE , 0, 0 },
273 { X86::FsMOVAPSrr, X86::MOVSSmr | TB_NOT_REVERSABLE , 0, 0 },
274 { X86::IDIV16r, X86::IDIV16m, 1, 0 },
275 { X86::IDIV32r, X86::IDIV32m, 1, 0 },
276 { X86::IDIV64r, X86::IDIV64m, 1, 0 },
277 { X86::IDIV8r, X86::IDIV8m, 1, 0 },
278 { X86::IMUL16r, X86::IMUL16m, 1, 0 },
279 { X86::IMUL32r, X86::IMUL32m, 1, 0 },
280 { X86::IMUL64r, X86::IMUL64m, 1, 0 },
281 { X86::IMUL8r, X86::IMUL8m, 1, 0 },
282 { X86::JMP32r, X86::JMP32m, 1, 0 },
283 { X86::JMP64r, X86::JMP64m, 1, 0 },
284 { X86::MOV16ri, X86::MOV16mi, 0, 0 },
285 { X86::MOV16rr, X86::MOV16mr, 0, 0 },
286 { X86::MOV32ri, X86::MOV32mi, 0, 0 },
287 { X86::MOV32rr, X86::MOV32mr, 0, 0 },
288 { X86::MOV64ri32, X86::MOV64mi32, 0, 0 },
289 { X86::MOV64rr, X86::MOV64mr, 0, 0 },
290 { X86::MOV8ri, X86::MOV8mi, 0, 0 },
291 { X86::MOV8rr, X86::MOV8mr, 0, 0 },
292 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, 0, 0 },
293 { X86::MOVAPDrr, X86::MOVAPDmr, 0, 16 },
294 { X86::MOVAPSrr, X86::MOVAPSmr, 0, 16 },
295 { X86::MOVDQArr, X86::MOVDQAmr, 0, 16 },
296 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0, 0 },
297 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0, 0 },
298 { X86::MOVSDto64rr, X86::MOVSDto64mr, 0, 0 },
299 { X86::MOVSS2DIrr, X86::MOVSS2DImr, 0, 0 },
300 { X86::MOVUPDrr, X86::MOVUPDmr, 0, 0 },
301 { X86::MOVUPSrr, X86::MOVUPSmr, 0, 0 },
302 { X86::MUL16r, X86::MUL16m, 1, 0 },
303 { X86::MUL32r, X86::MUL32m, 1, 0 },
304 { X86::MUL64r, X86::MUL64m, 1, 0 },
305 { X86::MUL8r, X86::MUL8m, 1, 0 },
306 { X86::SETAEr, X86::SETAEm, 0, 0 },
307 { X86::SETAr, X86::SETAm, 0, 0 },
308 { X86::SETBEr, X86::SETBEm, 0, 0 },
309 { X86::SETBr, X86::SETBm, 0, 0 },
310 { X86::SETEr, X86::SETEm, 0, 0 },
311 { X86::SETGEr, X86::SETGEm, 0, 0 },
312 { X86::SETGr, X86::SETGm, 0, 0 },
313 { X86::SETLEr, X86::SETLEm, 0, 0 },
314 { X86::SETLr, X86::SETLm, 0, 0 },
315 { X86::SETNEr, X86::SETNEm, 0, 0 },
316 { X86::SETNOr, X86::SETNOm, 0, 0 },
317 { X86::SETNPr, X86::SETNPm, 0, 0 },
318 { X86::SETNSr, X86::SETNSm, 0, 0 },
319 { X86::SETOr, X86::SETOm, 0, 0 },
320 { X86::SETPr, X86::SETPm, 0, 0 },
321 { X86::SETSr, X86::SETSm, 0, 0 },
322 { X86::TAILJMPr, X86::TAILJMPm, 1, 0 },
323 { X86::TAILJMPr64, X86::TAILJMPm64, 1, 0 },
324 { X86::TEST16ri, X86::TEST16mi, 1, 0 },
325 { X86::TEST32ri, X86::TEST32mi, 1, 0 },
326 { X86::TEST64ri32, X86::TEST64mi32, 1, 0 },
327 { X86::TEST8ri, X86::TEST8mi, 1, 0 }
330 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
331 unsigned RegOp = OpTbl0[i][0];
332 unsigned MemOp = OpTbl0[i][1] & ~TB_FLAGS;
333 unsigned FoldedLoad = OpTbl0[i][2];
334 unsigned Align = OpTbl0[i][3];
335 assert(!RegOp2MemOpTable0.count(RegOp) && "Duplicated entries?");
336 RegOp2MemOpTable0[RegOp] = std::make_pair(MemOp, Align);
338 // If this is not a reversible operation (because there is a many->one)
339 // mapping, don't insert the reverse of the operation into MemOp2RegOpTable.
340 if (OpTbl0[i][1] & TB_NOT_REVERSABLE)
343 // Index 0, folded load or store.
344 unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5);
345 assert(!MemOp2RegOpTable.count(MemOp) && "Duplicated entries?");
346 MemOp2RegOpTable[MemOp] = std::make_pair(RegOp, AuxInfo);
349 static const unsigned OpTbl1[][3] = {
350 { X86::CMP16rr, X86::CMP16rm, 0 },
351 { X86::CMP32rr, X86::CMP32rm, 0 },
352 { X86::CMP64rr, X86::CMP64rm, 0 },
353 { X86::CMP8rr, X86::CMP8rm, 0 },
354 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
355 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
356 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
357 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
358 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
359 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
360 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
361 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
362 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
363 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
364 { X86::FsMOVAPDrr, X86::MOVSDrm | TB_NOT_REVERSABLE , 0 },
365 { X86::FsMOVAPSrr, X86::MOVSSrm | TB_NOT_REVERSABLE , 0 },
366 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
367 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
368 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
369 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
370 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
371 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
372 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
373 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
374 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm, 16 },
375 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm, 16 },
376 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm, 16 },
377 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm, 16 },
378 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm, 16 },
379 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm, 0 },
380 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 },
381 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 },
382 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
383 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
384 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
385 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
386 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
387 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
388 { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm, 0 },
389 { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm, 0 },
390 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, 16 },
391 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, 16 },
392 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
393 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
394 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
395 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
396 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
397 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
398 { X86::MOV16rr, X86::MOV16rm, 0 },
399 { X86::MOV32rr, X86::MOV32rm, 0 },
400 { X86::MOV64rr, X86::MOV64rm, 0 },
401 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
402 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
403 { X86::MOV8rr, X86::MOV8rm, 0 },
404 { X86::MOVAPDrr, X86::MOVAPDrm, 16 },
405 { X86::MOVAPSrr, X86::MOVAPSrm, 16 },
406 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
407 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
408 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
409 { X86::MOVDQArr, X86::MOVDQArm, 16 },
410 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, 16 },
411 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, 16 },
412 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
413 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
414 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
415 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
416 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
417 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
418 { X86::MOVUPDrr, X86::MOVUPDrm, 16 },
419 { X86::MOVUPSrr, X86::MOVUPSrm, 0 },
420 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm, 0 },
421 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 },
422 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, 16 },
423 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
424 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
425 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
426 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
427 { X86::MOVZX64rr16, X86::MOVZX64rm16, 0 },
428 { X86::MOVZX64rr32, X86::MOVZX64rm32, 0 },
429 { X86::MOVZX64rr8, X86::MOVZX64rm8, 0 },
430 { X86::PSHUFDri, X86::PSHUFDmi, 16 },
431 { X86::PSHUFHWri, X86::PSHUFHWmi, 16 },
432 { X86::PSHUFLWri, X86::PSHUFLWmi, 16 },
433 { X86::RCPPSr, X86::RCPPSm, 16 },
434 { X86::RCPPSr_Int, X86::RCPPSm_Int, 16 },
435 { X86::RSQRTPSr, X86::RSQRTPSm, 16 },
436 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, 16 },
437 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
438 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
439 { X86::SQRTPDr, X86::SQRTPDm, 16 },
440 { X86::SQRTPDr_Int, X86::SQRTPDm_Int, 16 },
441 { X86::SQRTPSr, X86::SQRTPSm, 16 },
442 { X86::SQRTPSr_Int, X86::SQRTPSm_Int, 16 },
443 { X86::SQRTSDr, X86::SQRTSDm, 0 },
444 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
445 { X86::SQRTSSr, X86::SQRTSSm, 0 },
446 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
447 { X86::TEST16rr, X86::TEST16rm, 0 },
448 { X86::TEST32rr, X86::TEST32rm, 0 },
449 { X86::TEST64rr, X86::TEST64rm, 0 },
450 { X86::TEST8rr, X86::TEST8rm, 0 },
451 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
452 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
453 { X86::UCOMISSrr, X86::UCOMISSrm, 0 }
456 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
457 unsigned RegOp = OpTbl1[i][0];
458 unsigned MemOp = OpTbl1[i][1] & ~TB_FLAGS;
459 unsigned Align = OpTbl1[i][2];
460 assert(!RegOp2MemOpTable1.count(RegOp) && "Duplicate entries");
461 RegOp2MemOpTable1[RegOp] = std::make_pair(MemOp, Align);
463 // If this is not a reversible operation (because there is a many->one)
464 // mapping, don't insert the reverse of the operation into MemOp2RegOpTable.
465 if (OpTbl1[i][1] & TB_NOT_REVERSABLE)
468 // Index 1, folded load
469 unsigned AuxInfo = 1 | (1 << 4);
470 assert(!MemOp2RegOpTable.count(MemOp) && "Duplicate entries");
471 MemOp2RegOpTable[MemOp] = std::make_pair(RegOp, AuxInfo);
474 static const unsigned OpTbl2[][3] = {
475 { X86::ADC32rr, X86::ADC32rm, 0 },
476 { X86::ADC64rr, X86::ADC64rm, 0 },
477 { X86::ADD16rr, X86::ADD16rm, 0 },
478 { X86::ADD16rr_DB, X86::ADD16rm | TB_NOT_REVERSABLE, 0 },
479 { X86::ADD32rr, X86::ADD32rm, 0 },
480 { X86::ADD32rr_DB, X86::ADD32rm | TB_NOT_REVERSABLE, 0 },
481 { X86::ADD64rr, X86::ADD64rm, 0 },
482 { X86::ADD64rr_DB, X86::ADD64rm | TB_NOT_REVERSABLE, 0 },
483 { X86::ADD8rr, X86::ADD8rm, 0 },
484 { X86::ADDPDrr, X86::ADDPDrm, 16 },
485 { X86::ADDPSrr, X86::ADDPSrm, 16 },
486 { X86::ADDSDrr, X86::ADDSDrm, 0 },
487 { X86::ADDSSrr, X86::ADDSSrm, 0 },
488 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, 16 },
489 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, 16 },
490 { X86::AND16rr, X86::AND16rm, 0 },
491 { X86::AND32rr, X86::AND32rm, 0 },
492 { X86::AND64rr, X86::AND64rm, 0 },
493 { X86::AND8rr, X86::AND8rm, 0 },
494 { X86::ANDNPDrr, X86::ANDNPDrm, 16 },
495 { X86::ANDNPSrr, X86::ANDNPSrm, 16 },
496 { X86::ANDPDrr, X86::ANDPDrm, 16 },
497 { X86::ANDPSrr, X86::ANDPSrm, 16 },
498 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
499 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
500 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
501 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
502 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
503 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
504 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
505 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
506 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
507 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
508 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
509 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
510 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
511 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
512 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
513 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
514 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
515 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
516 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
517 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
518 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
519 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
520 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
521 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
522 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
523 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
524 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
525 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
526 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
527 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
528 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
529 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
530 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
531 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
532 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
533 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
534 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
535 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
536 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
537 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
538 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
539 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
540 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
541 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
542 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
543 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
544 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
545 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
546 { X86::CMPPDrri, X86::CMPPDrmi, 16 },
547 { X86::CMPPSrri, X86::CMPPSrmi, 16 },
548 { X86::CMPSDrr, X86::CMPSDrm, 0 },
549 { X86::CMPSSrr, X86::CMPSSrm, 0 },
550 { X86::DIVPDrr, X86::DIVPDrm, 16 },
551 { X86::DIVPSrr, X86::DIVPSrm, 16 },
552 { X86::DIVSDrr, X86::DIVSDrm, 0 },
553 { X86::DIVSSrr, X86::DIVSSrm, 0 },
554 { X86::FsANDNPDrr, X86::FsANDNPDrm, 16 },
555 { X86::FsANDNPSrr, X86::FsANDNPSrm, 16 },
556 { X86::FsANDPDrr, X86::FsANDPDrm, 16 },
557 { X86::FsANDPSrr, X86::FsANDPSrm, 16 },
558 { X86::FsORPDrr, X86::FsORPDrm, 16 },
559 { X86::FsORPSrr, X86::FsORPSrm, 16 },
560 { X86::FsXORPDrr, X86::FsXORPDrm, 16 },
561 { X86::FsXORPSrr, X86::FsXORPSrm, 16 },
562 { X86::HADDPDrr, X86::HADDPDrm, 16 },
563 { X86::HADDPSrr, X86::HADDPSrm, 16 },
564 { X86::HSUBPDrr, X86::HSUBPDrm, 16 },
565 { X86::HSUBPSrr, X86::HSUBPSrm, 16 },
566 { X86::IMUL16rr, X86::IMUL16rm, 0 },
567 { X86::IMUL32rr, X86::IMUL32rm, 0 },
568 { X86::IMUL64rr, X86::IMUL64rm, 0 },
569 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
570 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
571 { X86::MAXPDrr, X86::MAXPDrm, 16 },
572 { X86::MAXPDrr_Int, X86::MAXPDrm_Int, 16 },
573 { X86::MAXPSrr, X86::MAXPSrm, 16 },
574 { X86::MAXPSrr_Int, X86::MAXPSrm_Int, 16 },
575 { X86::MAXSDrr, X86::MAXSDrm, 0 },
576 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 },
577 { X86::MAXSSrr, X86::MAXSSrm, 0 },
578 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 },
579 { X86::MINPDrr, X86::MINPDrm, 16 },
580 { X86::MINPDrr_Int, X86::MINPDrm_Int, 16 },
581 { X86::MINPSrr, X86::MINPSrm, 16 },
582 { X86::MINPSrr_Int, X86::MINPSrm_Int, 16 },
583 { X86::MINSDrr, X86::MINSDrm, 0 },
584 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 },
585 { X86::MINSSrr, X86::MINSSrm, 0 },
586 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 },
587 { X86::MULPDrr, X86::MULPDrm, 16 },
588 { X86::MULPSrr, X86::MULPSrm, 16 },
589 { X86::MULSDrr, X86::MULSDrm, 0 },
590 { X86::MULSSrr, X86::MULSSrm, 0 },
591 { X86::OR16rr, X86::OR16rm, 0 },
592 { X86::OR32rr, X86::OR32rm, 0 },
593 { X86::OR64rr, X86::OR64rm, 0 },
594 { X86::OR8rr, X86::OR8rm, 0 },
595 { X86::ORPDrr, X86::ORPDrm, 16 },
596 { X86::ORPSrr, X86::ORPSrm, 16 },
597 { X86::PACKSSDWrr, X86::PACKSSDWrm, 16 },
598 { X86::PACKSSWBrr, X86::PACKSSWBrm, 16 },
599 { X86::PACKUSWBrr, X86::PACKUSWBrm, 16 },
600 { X86::PADDBrr, X86::PADDBrm, 16 },
601 { X86::PADDDrr, X86::PADDDrm, 16 },
602 { X86::PADDQrr, X86::PADDQrm, 16 },
603 { X86::PADDSBrr, X86::PADDSBrm, 16 },
604 { X86::PADDSWrr, X86::PADDSWrm, 16 },
605 { X86::PADDWrr, X86::PADDWrm, 16 },
606 { X86::PANDNrr, X86::PANDNrm, 16 },
607 { X86::PANDrr, X86::PANDrm, 16 },
608 { X86::PAVGBrr, X86::PAVGBrm, 16 },
609 { X86::PAVGWrr, X86::PAVGWrm, 16 },
610 { X86::PCMPEQBrr, X86::PCMPEQBrm, 16 },
611 { X86::PCMPEQDrr, X86::PCMPEQDrm, 16 },
612 { X86::PCMPEQWrr, X86::PCMPEQWrm, 16 },
613 { X86::PCMPGTBrr, X86::PCMPGTBrm, 16 },
614 { X86::PCMPGTDrr, X86::PCMPGTDrm, 16 },
615 { X86::PCMPGTWrr, X86::PCMPGTWrm, 16 },
616 { X86::PINSRWrri, X86::PINSRWrmi, 16 },
617 { X86::PMADDWDrr, X86::PMADDWDrm, 16 },
618 { X86::PMAXSWrr, X86::PMAXSWrm, 16 },
619 { X86::PMAXUBrr, X86::PMAXUBrm, 16 },
620 { X86::PMINSWrr, X86::PMINSWrm, 16 },
621 { X86::PMINUBrr, X86::PMINUBrm, 16 },
622 { X86::PMULDQrr, X86::PMULDQrm, 16 },
623 { X86::PMULHUWrr, X86::PMULHUWrm, 16 },
624 { X86::PMULHWrr, X86::PMULHWrm, 16 },
625 { X86::PMULLDrr, X86::PMULLDrm, 16 },
626 { X86::PMULLWrr, X86::PMULLWrm, 16 },
627 { X86::PMULUDQrr, X86::PMULUDQrm, 16 },
628 { X86::PORrr, X86::PORrm, 16 },
629 { X86::PSADBWrr, X86::PSADBWrm, 16 },
630 { X86::PSLLDrr, X86::PSLLDrm, 16 },
631 { X86::PSLLQrr, X86::PSLLQrm, 16 },
632 { X86::PSLLWrr, X86::PSLLWrm, 16 },
633 { X86::PSRADrr, X86::PSRADrm, 16 },
634 { X86::PSRAWrr, X86::PSRAWrm, 16 },
635 { X86::PSRLDrr, X86::PSRLDrm, 16 },
636 { X86::PSRLQrr, X86::PSRLQrm, 16 },
637 { X86::PSRLWrr, X86::PSRLWrm, 16 },
638 { X86::PSUBBrr, X86::PSUBBrm, 16 },
639 { X86::PSUBDrr, X86::PSUBDrm, 16 },
640 { X86::PSUBSBrr, X86::PSUBSBrm, 16 },
641 { X86::PSUBSWrr, X86::PSUBSWrm, 16 },
642 { X86::PSUBWrr, X86::PSUBWrm, 16 },
643 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, 16 },
644 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, 16 },
645 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, 16 },
646 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, 16 },
647 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, 16 },
648 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, 16 },
649 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, 16 },
650 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, 16 },
651 { X86::PXORrr, X86::PXORrm, 16 },
652 { X86::SBB32rr, X86::SBB32rm, 0 },
653 { X86::SBB64rr, X86::SBB64rm, 0 },
654 { X86::SHUFPDrri, X86::SHUFPDrmi, 16 },
655 { X86::SHUFPSrri, X86::SHUFPSrmi, 16 },
656 { X86::SUB16rr, X86::SUB16rm, 0 },
657 { X86::SUB32rr, X86::SUB32rm, 0 },
658 { X86::SUB64rr, X86::SUB64rm, 0 },
659 { X86::SUB8rr, X86::SUB8rm, 0 },
660 { X86::SUBPDrr, X86::SUBPDrm, 16 },
661 { X86::SUBPSrr, X86::SUBPSrm, 16 },
662 { X86::SUBSDrr, X86::SUBSDrm, 0 },
663 { X86::SUBSSrr, X86::SUBSSrm, 0 },
664 // FIXME: TEST*rr -> swapped operand of TEST*mr.
665 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, 16 },
666 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, 16 },
667 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, 16 },
668 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, 16 },
669 { X86::XOR16rr, X86::XOR16rm, 0 },
670 { X86::XOR32rr, X86::XOR32rm, 0 },
671 { X86::XOR64rr, X86::XOR64rm, 0 },
672 { X86::XOR8rr, X86::XOR8rm, 0 },
673 { X86::XORPDrr, X86::XORPDrm, 16 },
674 { X86::XORPSrr, X86::XORPSrm, 16 }
677 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
678 unsigned RegOp = OpTbl2[i][0];
679 unsigned MemOp = OpTbl2[i][1] & ~TB_FLAGS;
680 unsigned Align = OpTbl2[i][2];
682 assert(!RegOp2MemOpTable2.count(RegOp) && "Duplicate entry!");
683 RegOp2MemOpTable2[RegOp] = std::make_pair(MemOp, Align);
685 // If this is not a reversible operation (because there is a many->one)
686 // mapping, don't insert the reverse of the operation into MemOp2RegOpTable.
687 if (OpTbl2[i][1] & TB_NOT_REVERSABLE)
690 // Index 2, folded load
691 unsigned AuxInfo = 2 | (1 << 4);
692 assert(!MemOp2RegOpTable.count(MemOp) &&
693 "Duplicated entries in unfolding maps?");
694 MemOp2RegOpTable[MemOp] = std::make_pair(RegOp, AuxInfo);
699 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
700 unsigned &SrcReg, unsigned &DstReg,
701 unsigned &SubIdx) const {
702 switch (MI.getOpcode()) {
704 case X86::MOVSX16rr8:
705 case X86::MOVZX16rr8:
706 case X86::MOVSX32rr8:
707 case X86::MOVZX32rr8:
708 case X86::MOVSX64rr8:
709 case X86::MOVZX64rr8:
710 if (!TM.getSubtarget<X86Subtarget>().is64Bit())
711 // It's not always legal to reference the low 8-bit of the larger
712 // register in 32-bit mode.
714 case X86::MOVSX32rr16:
715 case X86::MOVZX32rr16:
716 case X86::MOVSX64rr16:
717 case X86::MOVZX64rr16:
718 case X86::MOVSX64rr32:
719 case X86::MOVZX64rr32: {
720 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
723 SrcReg = MI.getOperand(1).getReg();
724 DstReg = MI.getOperand(0).getReg();
725 switch (MI.getOpcode()) {
729 case X86::MOVSX16rr8:
730 case X86::MOVZX16rr8:
731 case X86::MOVSX32rr8:
732 case X86::MOVZX32rr8:
733 case X86::MOVSX64rr8:
734 case X86::MOVZX64rr8:
735 SubIdx = X86::sub_8bit;
737 case X86::MOVSX32rr16:
738 case X86::MOVZX32rr16:
739 case X86::MOVSX64rr16:
740 case X86::MOVZX64rr16:
741 SubIdx = X86::sub_16bit;
743 case X86::MOVSX64rr32:
744 case X86::MOVZX64rr32:
745 SubIdx = X86::sub_32bit;
754 /// isFrameOperand - Return true and the FrameIndex if the specified
755 /// operand and follow operands form a reference to the stack frame.
756 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
757 int &FrameIndex) const {
758 if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() &&
759 MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() &&
760 MI->getOperand(Op+1).getImm() == 1 &&
761 MI->getOperand(Op+2).getReg() == 0 &&
762 MI->getOperand(Op+3).getImm() == 0) {
763 FrameIndex = MI->getOperand(Op).getIndex();
769 static bool isFrameLoadOpcode(int Opcode) {
782 case X86::MMX_MOVD64rm:
783 case X86::MMX_MOVQ64rm:
790 static bool isFrameStoreOpcode(int Opcode) {
803 case X86::MMX_MOVD64mr:
804 case X86::MMX_MOVQ64mr:
805 case X86::MMX_MOVNTQmr:
811 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
812 int &FrameIndex) const {
813 if (isFrameLoadOpcode(MI->getOpcode()))
814 if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
815 return MI->getOperand(0).getReg();
819 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
820 int &FrameIndex) const {
821 if (isFrameLoadOpcode(MI->getOpcode())) {
823 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
825 // Check for post-frame index elimination operations
826 const MachineMemOperand *Dummy;
827 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
832 bool X86InstrInfo::hasLoadFromStackSlot(const MachineInstr *MI,
833 const MachineMemOperand *&MMO,
834 int &FrameIndex) const {
835 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
836 oe = MI->memoperands_end();
839 if ((*o)->isLoad() && (*o)->getValue())
840 if (const FixedStackPseudoSourceValue *Value =
841 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
842 FrameIndex = Value->getFrameIndex();
850 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
851 int &FrameIndex) const {
852 if (isFrameStoreOpcode(MI->getOpcode()))
853 if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
854 isFrameOperand(MI, 0, FrameIndex))
855 return MI->getOperand(X86::AddrNumOperands).getReg();
859 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
860 int &FrameIndex) const {
861 if (isFrameStoreOpcode(MI->getOpcode())) {
863 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
865 // Check for post-frame index elimination operations
866 const MachineMemOperand *Dummy;
867 return hasStoreToStackSlot(MI, Dummy, FrameIndex);
872 bool X86InstrInfo::hasStoreToStackSlot(const MachineInstr *MI,
873 const MachineMemOperand *&MMO,
874 int &FrameIndex) const {
875 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
876 oe = MI->memoperands_end();
879 if ((*o)->isStore() && (*o)->getValue())
880 if (const FixedStackPseudoSourceValue *Value =
881 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
882 FrameIndex = Value->getFrameIndex();
890 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by
892 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
893 bool isPICBase = false;
894 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
895 E = MRI.def_end(); I != E; ++I) {
896 MachineInstr *DefMI = I.getOperand().getParent();
897 if (DefMI->getOpcode() != X86::MOVPC32r)
899 assert(!isPICBase && "More than one PIC base?");
906 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
907 AliasAnalysis *AA) const {
908 switch (MI->getOpcode()) {
921 case X86::MMX_MOVD64rm:
922 case X86::MMX_MOVQ64rm:
923 case X86::FsMOVAPSrm:
924 case X86::FsMOVAPDrm: {
925 // Loads from constant pools are trivially rematerializable.
926 if (MI->getOperand(1).isReg() &&
927 MI->getOperand(2).isImm() &&
928 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
929 MI->isInvariantLoad(AA)) {
930 unsigned BaseReg = MI->getOperand(1).getReg();
931 if (BaseReg == 0 || BaseReg == X86::RIP)
933 // Allow re-materialization of PIC load.
934 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
936 const MachineFunction &MF = *MI->getParent()->getParent();
937 const MachineRegisterInfo &MRI = MF.getRegInfo();
938 bool isPICBase = false;
939 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
940 E = MRI.def_end(); I != E; ++I) {
941 MachineInstr *DefMI = I.getOperand().getParent();
942 if (DefMI->getOpcode() != X86::MOVPC32r)
944 assert(!isPICBase && "More than one PIC base?");
954 if (MI->getOperand(2).isImm() &&
955 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
956 !MI->getOperand(4).isReg()) {
957 // lea fi#, lea GV, etc. are all rematerializable.
958 if (!MI->getOperand(1).isReg())
960 unsigned BaseReg = MI->getOperand(1).getReg();
963 // Allow re-materialization of lea PICBase + x.
964 const MachineFunction &MF = *MI->getParent()->getParent();
965 const MachineRegisterInfo &MRI = MF.getRegInfo();
966 return regIsPICBase(BaseReg, MRI);
972 // All other instructions marked M_REMATERIALIZABLE are always trivially
977 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
978 /// would clobber the EFLAGS condition register. Note the result may be
979 /// conservative. If it cannot definitely determine the safety after visiting
980 /// a few instructions in each direction it assumes it's not safe.
981 static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
982 MachineBasicBlock::iterator I) {
983 MachineBasicBlock::iterator E = MBB.end();
985 // It's always safe to clobber EFLAGS at the end of a block.
989 // For compile time consideration, if we are not able to determine the
990 // safety after visiting 4 instructions in each direction, we will assume
992 MachineBasicBlock::iterator Iter = I;
993 for (unsigned i = 0; i < 4; ++i) {
994 bool SeenDef = false;
995 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
996 MachineOperand &MO = Iter->getOperand(j);
999 if (MO.getReg() == X86::EFLAGS) {
1007 // This instruction defines EFLAGS, no need to look any further.
1010 // Skip over DBG_VALUE.
1011 while (Iter != E && Iter->isDebugValue())
1014 // If we make it to the end of the block, it's safe to clobber EFLAGS.
1019 MachineBasicBlock::iterator B = MBB.begin();
1021 for (unsigned i = 0; i < 4; ++i) {
1022 // If we make it to the beginning of the block, it's safe to clobber
1023 // EFLAGS iff EFLAGS is not live-in.
1025 return !MBB.isLiveIn(X86::EFLAGS);
1028 // Skip over DBG_VALUE.
1029 while (Iter != B && Iter->isDebugValue())
1032 bool SawKill = false;
1033 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1034 MachineOperand &MO = Iter->getOperand(j);
1035 if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
1036 if (MO.isDef()) return MO.isDead();
1037 if (MO.isKill()) SawKill = true;
1042 // This instruction kills EFLAGS and doesn't redefine it, so
1043 // there's no need to look further.
1047 // Conservative answer.
1051 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
1052 MachineBasicBlock::iterator I,
1053 unsigned DestReg, unsigned SubIdx,
1054 const MachineInstr *Orig,
1055 const TargetRegisterInfo &TRI) const {
1056 DebugLoc DL = Orig->getDebugLoc();
1058 // MOV32r0 etc. are implemented with xor which clobbers condition code.
1059 // Re-materialize them as movri instructions to avoid side effects.
1061 unsigned Opc = Orig->getOpcode();
1067 case X86::MOV64r0: {
1068 if (!isSafeToClobberEFLAGS(MBB, I)) {
1071 case X86::MOV8r0: Opc = X86::MOV8ri; break;
1072 case X86::MOV16r0: Opc = X86::MOV16ri; break;
1073 case X86::MOV32r0: Opc = X86::MOV32ri; break;
1074 case X86::MOV64r0: Opc = X86::MOV64ri64i32; break;
1083 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1086 BuildMI(MBB, I, DL, get(Opc)).addOperand(Orig->getOperand(0)).addImm(0);
1089 MachineInstr *NewMI = prior(I);
1090 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1093 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
1094 /// is not marked dead.
1095 static bool hasLiveCondCodeDef(MachineInstr *MI) {
1096 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1097 MachineOperand &MO = MI->getOperand(i);
1098 if (MO.isReg() && MO.isDef() &&
1099 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1106 /// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
1107 /// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
1108 /// to a 32-bit superregister and then truncating back down to a 16-bit
1111 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
1112 MachineFunction::iterator &MFI,
1113 MachineBasicBlock::iterator &MBBI,
1114 LiveVariables *LV) const {
1115 MachineInstr *MI = MBBI;
1116 unsigned Dest = MI->getOperand(0).getReg();
1117 unsigned Src = MI->getOperand(1).getReg();
1118 bool isDead = MI->getOperand(0).isDead();
1119 bool isKill = MI->getOperand(1).isKill();
1121 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
1122 ? X86::LEA64_32r : X86::LEA32r;
1123 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1124 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1125 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1127 // Build and insert into an implicit UNDEF value. This is OK because
1128 // well be shifting and then extracting the lower 16-bits.
1129 // This has the potential to cause partial register stall. e.g.
1130 // movw (%rbp,%rcx,2), %dx
1131 // leal -65(%rdx), %esi
1132 // But testing has shown this *does* help performance in 64-bit mode (at
1133 // least on modern x86 machines).
1134 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1135 MachineInstr *InsMI =
1136 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
1137 .addReg(leaInReg, RegState::Define, X86::sub_16bit)
1138 .addReg(Src, getKillRegState(isKill));
1140 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
1141 get(Opc), leaOutReg);
1144 llvm_unreachable(0);
1146 case X86::SHL16ri: {
1147 unsigned ShAmt = MI->getOperand(2).getImm();
1148 MIB.addReg(0).addImm(1 << ShAmt)
1149 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
1153 case X86::INC64_16r:
1154 addRegOffset(MIB, leaInReg, true, 1);
1157 case X86::DEC64_16r:
1158 addRegOffset(MIB, leaInReg, true, -1);
1162 case X86::ADD16ri_DB:
1163 case X86::ADD16ri8_DB:
1164 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
1167 case X86::ADD16rr_DB: {
1168 unsigned Src2 = MI->getOperand(2).getReg();
1169 bool isKill2 = MI->getOperand(2).isKill();
1170 unsigned leaInReg2 = 0;
1171 MachineInstr *InsMI2 = 0;
1173 // ADD16rr %reg1028<kill>, %reg1028
1174 // just a single insert_subreg.
1175 addRegReg(MIB, leaInReg, true, leaInReg, false);
1177 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1178 // Build and insert into an implicit UNDEF value. This is OK because
1179 // well be shifting and then extracting the lower 16-bits.
1180 BuildMI(*MFI, MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2);
1182 BuildMI(*MFI, MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
1183 .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
1184 .addReg(Src2, getKillRegState(isKill2));
1185 addRegReg(MIB, leaInReg, true, leaInReg2, true);
1187 if (LV && isKill2 && InsMI2)
1188 LV->replaceKillInstruction(Src2, MI, InsMI2);
1193 MachineInstr *NewMI = MIB;
1194 MachineInstr *ExtMI =
1195 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
1196 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1197 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
1200 // Update live variables
1201 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
1202 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
1204 LV->replaceKillInstruction(Src, MI, InsMI);
1206 LV->replaceKillInstruction(Dest, MI, ExtMI);
1212 /// convertToThreeAddress - This method must be implemented by targets that
1213 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
1214 /// may be able to convert a two-address instruction into a true
1215 /// three-address instruction on demand. This allows the X86 target (for
1216 /// example) to convert ADD and SHL instructions into LEA instructions if they
1217 /// would require register copies due to two-addressness.
1219 /// This method returns a null pointer if the transformation cannot be
1220 /// performed, otherwise it returns the new instruction.
1223 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
1224 MachineBasicBlock::iterator &MBBI,
1225 LiveVariables *LV) const {
1226 MachineInstr *MI = MBBI;
1227 MachineFunction &MF = *MI->getParent()->getParent();
1228 // All instructions input are two-addr instructions. Get the known operands.
1229 unsigned Dest = MI->getOperand(0).getReg();
1230 unsigned Src = MI->getOperand(1).getReg();
1231 bool isDead = MI->getOperand(0).isDead();
1232 bool isKill = MI->getOperand(1).isKill();
1234 MachineInstr *NewMI = NULL;
1235 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
1236 // we have better subtarget support, enable the 16-bit LEA generation here.
1237 // 16-bit LEA is also slow on Core2.
1238 bool DisableLEA16 = true;
1239 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1241 unsigned MIOpc = MI->getOpcode();
1243 case X86::SHUFPSrri: {
1244 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
1245 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1247 unsigned B = MI->getOperand(1).getReg();
1248 unsigned C = MI->getOperand(2).getReg();
1249 if (B != C) return 0;
1250 unsigned A = MI->getOperand(0).getReg();
1251 unsigned M = MI->getOperand(3).getImm();
1252 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
1253 .addReg(A, RegState::Define | getDeadRegState(isDead))
1254 .addReg(B, getKillRegState(isKill)).addImm(M);
1257 case X86::SHL64ri: {
1258 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1259 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1260 // the flags produced by a shift yet, so this is safe.
1261 unsigned ShAmt = MI->getOperand(2).getImm();
1262 if (ShAmt == 0 || ShAmt >= 4) return 0;
1264 // LEA can't handle RSP.
1265 if (TargetRegisterInfo::isVirtualRegister(Src) &&
1266 !MF.getRegInfo().constrainRegClass(Src, &X86::GR64_NOSPRegClass))
1269 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1270 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1271 .addReg(0).addImm(1 << ShAmt)
1272 .addReg(Src, getKillRegState(isKill))
1273 .addImm(0).addReg(0);
1276 case X86::SHL32ri: {
1277 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1278 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1279 // the flags produced by a shift yet, so this is safe.
1280 unsigned ShAmt = MI->getOperand(2).getImm();
1281 if (ShAmt == 0 || ShAmt >= 4) return 0;
1283 // LEA can't handle ESP.
1284 if (TargetRegisterInfo::isVirtualRegister(Src) &&
1285 !MF.getRegInfo().constrainRegClass(Src, &X86::GR32_NOSPRegClass))
1288 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1289 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
1290 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1291 .addReg(0).addImm(1 << ShAmt)
1292 .addReg(Src, getKillRegState(isKill)).addImm(0).addReg(0);
1295 case X86::SHL16ri: {
1296 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1297 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1298 // the flags produced by a shift yet, so this is safe.
1299 unsigned ShAmt = MI->getOperand(2).getImm();
1300 if (ShAmt == 0 || ShAmt >= 4) return 0;
1303 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1304 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1305 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1306 .addReg(0).addImm(1 << ShAmt)
1307 .addReg(Src, getKillRegState(isKill))
1308 .addImm(0).addReg(0);
1312 // The following opcodes also sets the condition code register(s). Only
1313 // convert them to equivalent lea if the condition code register def's
1315 if (hasLiveCondCodeDef(MI))
1322 case X86::INC64_32r: {
1323 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1324 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
1325 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1327 // LEA can't handle RSP.
1328 if (TargetRegisterInfo::isVirtualRegister(Src) &&
1329 !MF.getRegInfo().constrainRegClass(Src,
1330 MIOpc == X86::INC64r ? X86::GR64_NOSPRegisterClass :
1331 X86::GR32_NOSPRegisterClass))
1334 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1335 .addReg(Dest, RegState::Define |
1336 getDeadRegState(isDead)),
1341 case X86::INC64_16r:
1343 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1344 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1345 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1346 .addReg(Dest, RegState::Define |
1347 getDeadRegState(isDead)),
1352 case X86::DEC64_32r: {
1353 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1354 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1355 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1356 // LEA can't handle RSP.
1357 if (TargetRegisterInfo::isVirtualRegister(Src) &&
1358 !MF.getRegInfo().constrainRegClass(Src,
1359 MIOpc == X86::DEC64r ? X86::GR64_NOSPRegisterClass :
1360 X86::GR32_NOSPRegisterClass))
1363 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1364 .addReg(Dest, RegState::Define |
1365 getDeadRegState(isDead)),
1370 case X86::DEC64_16r:
1372 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1373 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1374 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1375 .addReg(Dest, RegState::Define |
1376 getDeadRegState(isDead)),
1380 case X86::ADD64rr_DB:
1382 case X86::ADD32rr_DB: {
1383 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1385 TargetRegisterClass *RC;
1386 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB) {
1388 RC = X86::GR64_NOSPRegisterClass;
1390 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1391 RC = X86::GR32_NOSPRegisterClass;
1395 unsigned Src2 = MI->getOperand(2).getReg();
1396 bool isKill2 = MI->getOperand(2).isKill();
1398 // LEA can't handle RSP.
1399 if (TargetRegisterInfo::isVirtualRegister(Src2) &&
1400 !MF.getRegInfo().constrainRegClass(Src2, RC))
1403 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1404 .addReg(Dest, RegState::Define |
1405 getDeadRegState(isDead)),
1406 Src, isKill, Src2, isKill2);
1408 LV->replaceKillInstruction(Src2, MI, NewMI);
1412 case X86::ADD16rr_DB: {
1414 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1415 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1416 unsigned Src2 = MI->getOperand(2).getReg();
1417 bool isKill2 = MI->getOperand(2).isKill();
1418 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1419 .addReg(Dest, RegState::Define |
1420 getDeadRegState(isDead)),
1421 Src, isKill, Src2, isKill2);
1423 LV->replaceKillInstruction(Src2, MI, NewMI);
1426 case X86::ADD64ri32:
1428 case X86::ADD64ri32_DB:
1429 case X86::ADD64ri8_DB:
1430 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1431 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1432 .addReg(Dest, RegState::Define |
1433 getDeadRegState(isDead)),
1434 Src, isKill, MI->getOperand(2).getImm());
1438 case X86::ADD32ri_DB:
1439 case X86::ADD32ri8_DB: {
1440 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1441 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1442 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1443 .addReg(Dest, RegState::Define |
1444 getDeadRegState(isDead)),
1445 Src, isKill, MI->getOperand(2).getImm());
1450 case X86::ADD16ri_DB:
1451 case X86::ADD16ri8_DB:
1453 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1454 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1455 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1456 .addReg(Dest, RegState::Define |
1457 getDeadRegState(isDead)),
1458 Src, isKill, MI->getOperand(2).getImm());
1464 if (!NewMI) return 0;
1466 if (LV) { // Update live variables
1468 LV->replaceKillInstruction(Src, MI, NewMI);
1470 LV->replaceKillInstruction(Dest, MI, NewMI);
1473 MFI->insert(MBBI, NewMI); // Insert the new inst
1477 /// commuteInstruction - We have a few instructions that must be hacked on to
1481 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1482 switch (MI->getOpcode()) {
1483 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1484 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1485 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1486 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1487 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1488 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1491 switch (MI->getOpcode()) {
1492 default: llvm_unreachable("Unreachable!");
1493 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1494 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1495 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1496 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1497 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1498 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1500 unsigned Amt = MI->getOperand(3).getImm();
1502 MachineFunction &MF = *MI->getParent()->getParent();
1503 MI = MF.CloneMachineInstr(MI);
1506 MI->setDesc(get(Opc));
1507 MI->getOperand(3).setImm(Size-Amt);
1508 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1510 case X86::CMOVB16rr:
1511 case X86::CMOVB32rr:
1512 case X86::CMOVB64rr:
1513 case X86::CMOVAE16rr:
1514 case X86::CMOVAE32rr:
1515 case X86::CMOVAE64rr:
1516 case X86::CMOVE16rr:
1517 case X86::CMOVE32rr:
1518 case X86::CMOVE64rr:
1519 case X86::CMOVNE16rr:
1520 case X86::CMOVNE32rr:
1521 case X86::CMOVNE64rr:
1522 case X86::CMOVBE16rr:
1523 case X86::CMOVBE32rr:
1524 case X86::CMOVBE64rr:
1525 case X86::CMOVA16rr:
1526 case X86::CMOVA32rr:
1527 case X86::CMOVA64rr:
1528 case X86::CMOVL16rr:
1529 case X86::CMOVL32rr:
1530 case X86::CMOVL64rr:
1531 case X86::CMOVGE16rr:
1532 case X86::CMOVGE32rr:
1533 case X86::CMOVGE64rr:
1534 case X86::CMOVLE16rr:
1535 case X86::CMOVLE32rr:
1536 case X86::CMOVLE64rr:
1537 case X86::CMOVG16rr:
1538 case X86::CMOVG32rr:
1539 case X86::CMOVG64rr:
1540 case X86::CMOVS16rr:
1541 case X86::CMOVS32rr:
1542 case X86::CMOVS64rr:
1543 case X86::CMOVNS16rr:
1544 case X86::CMOVNS32rr:
1545 case X86::CMOVNS64rr:
1546 case X86::CMOVP16rr:
1547 case X86::CMOVP32rr:
1548 case X86::CMOVP64rr:
1549 case X86::CMOVNP16rr:
1550 case X86::CMOVNP32rr:
1551 case X86::CMOVNP64rr:
1552 case X86::CMOVO16rr:
1553 case X86::CMOVO32rr:
1554 case X86::CMOVO64rr:
1555 case X86::CMOVNO16rr:
1556 case X86::CMOVNO32rr:
1557 case X86::CMOVNO64rr: {
1559 switch (MI->getOpcode()) {
1561 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
1562 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
1563 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
1564 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
1565 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
1566 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
1567 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
1568 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
1569 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
1570 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
1571 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
1572 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
1573 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
1574 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
1575 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
1576 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
1577 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
1578 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
1579 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
1580 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
1581 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
1582 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
1583 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
1584 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
1585 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
1586 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
1587 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
1588 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
1589 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
1590 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
1591 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
1592 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
1593 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
1594 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
1595 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
1596 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
1597 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
1598 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
1599 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
1600 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
1601 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
1602 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
1603 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
1604 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
1605 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
1606 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
1607 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
1608 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
1611 MachineFunction &MF = *MI->getParent()->getParent();
1612 MI = MF.CloneMachineInstr(MI);
1615 MI->setDesc(get(Opc));
1616 // Fallthrough intended.
1619 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1623 static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
1625 default: return X86::COND_INVALID;
1626 case X86::JE_4: return X86::COND_E;
1627 case X86::JNE_4: return X86::COND_NE;
1628 case X86::JL_4: return X86::COND_L;
1629 case X86::JLE_4: return X86::COND_LE;
1630 case X86::JG_4: return X86::COND_G;
1631 case X86::JGE_4: return X86::COND_GE;
1632 case X86::JB_4: return X86::COND_B;
1633 case X86::JBE_4: return X86::COND_BE;
1634 case X86::JA_4: return X86::COND_A;
1635 case X86::JAE_4: return X86::COND_AE;
1636 case X86::JS_4: return X86::COND_S;
1637 case X86::JNS_4: return X86::COND_NS;
1638 case X86::JP_4: return X86::COND_P;
1639 case X86::JNP_4: return X86::COND_NP;
1640 case X86::JO_4: return X86::COND_O;
1641 case X86::JNO_4: return X86::COND_NO;
1645 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
1647 default: llvm_unreachable("Illegal condition code!");
1648 case X86::COND_E: return X86::JE_4;
1649 case X86::COND_NE: return X86::JNE_4;
1650 case X86::COND_L: return X86::JL_4;
1651 case X86::COND_LE: return X86::JLE_4;
1652 case X86::COND_G: return X86::JG_4;
1653 case X86::COND_GE: return X86::JGE_4;
1654 case X86::COND_B: return X86::JB_4;
1655 case X86::COND_BE: return X86::JBE_4;
1656 case X86::COND_A: return X86::JA_4;
1657 case X86::COND_AE: return X86::JAE_4;
1658 case X86::COND_S: return X86::JS_4;
1659 case X86::COND_NS: return X86::JNS_4;
1660 case X86::COND_P: return X86::JP_4;
1661 case X86::COND_NP: return X86::JNP_4;
1662 case X86::COND_O: return X86::JO_4;
1663 case X86::COND_NO: return X86::JNO_4;
1667 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
1668 /// e.g. turning COND_E to COND_NE.
1669 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
1671 default: llvm_unreachable("Illegal condition code!");
1672 case X86::COND_E: return X86::COND_NE;
1673 case X86::COND_NE: return X86::COND_E;
1674 case X86::COND_L: return X86::COND_GE;
1675 case X86::COND_LE: return X86::COND_G;
1676 case X86::COND_G: return X86::COND_LE;
1677 case X86::COND_GE: return X86::COND_L;
1678 case X86::COND_B: return X86::COND_AE;
1679 case X86::COND_BE: return X86::COND_A;
1680 case X86::COND_A: return X86::COND_BE;
1681 case X86::COND_AE: return X86::COND_B;
1682 case X86::COND_S: return X86::COND_NS;
1683 case X86::COND_NS: return X86::COND_S;
1684 case X86::COND_P: return X86::COND_NP;
1685 case X86::COND_NP: return X86::COND_P;
1686 case X86::COND_O: return X86::COND_NO;
1687 case X86::COND_NO: return X86::COND_O;
1691 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
1692 const TargetInstrDesc &TID = MI->getDesc();
1693 if (!TID.isTerminator()) return false;
1695 // Conditional branch is a special case.
1696 if (TID.isBranch() && !TID.isBarrier())
1698 if (!TID.isPredicable())
1700 return !isPredicated(MI);
1703 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
1704 MachineBasicBlock *&TBB,
1705 MachineBasicBlock *&FBB,
1706 SmallVectorImpl<MachineOperand> &Cond,
1707 bool AllowModify) const {
1708 // Start from the bottom of the block and work up, examining the
1709 // terminator instructions.
1710 MachineBasicBlock::iterator I = MBB.end();
1711 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
1712 while (I != MBB.begin()) {
1714 if (I->isDebugValue())
1717 // Working from the bottom, when we see a non-terminator instruction, we're
1719 if (!isUnpredicatedTerminator(I))
1722 // A terminator that isn't a branch can't easily be handled by this
1724 if (!I->getDesc().isBranch())
1727 // Handle unconditional branches.
1728 if (I->getOpcode() == X86::JMP_4) {
1732 TBB = I->getOperand(0).getMBB();
1736 // If the block has any instructions after a JMP, delete them.
1737 while (llvm::next(I) != MBB.end())
1738 llvm::next(I)->eraseFromParent();
1743 // Delete the JMP if it's equivalent to a fall-through.
1744 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
1746 I->eraseFromParent();
1748 UnCondBrIter = MBB.end();
1752 // TBB is used to indicate the unconditional destination.
1753 TBB = I->getOperand(0).getMBB();
1757 // Handle conditional branches.
1758 X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode());
1759 if (BranchCode == X86::COND_INVALID)
1760 return true; // Can't handle indirect branch.
1762 // Working from the bottom, handle the first conditional branch.
1764 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
1765 if (AllowModify && UnCondBrIter != MBB.end() &&
1766 MBB.isLayoutSuccessor(TargetBB)) {
1767 // If we can modify the code and it ends in something like:
1775 // Then we can change this to:
1782 // Which is a bit more efficient.
1783 // We conditionally jump to the fall-through block.
1784 BranchCode = GetOppositeBranchCondition(BranchCode);
1785 unsigned JNCC = GetCondBranchFromCond(BranchCode);
1786 MachineBasicBlock::iterator OldInst = I;
1788 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
1789 .addMBB(UnCondBrIter->getOperand(0).getMBB());
1790 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4))
1792 MBB.addSuccessor(TargetBB);
1794 OldInst->eraseFromParent();
1795 UnCondBrIter->eraseFromParent();
1797 // Restart the analysis.
1798 UnCondBrIter = MBB.end();
1804 TBB = I->getOperand(0).getMBB();
1805 Cond.push_back(MachineOperand::CreateImm(BranchCode));
1809 // Handle subsequent conditional branches. Only handle the case where all
1810 // conditional branches branch to the same destination and their condition
1811 // opcodes fit one of the special multi-branch idioms.
1812 assert(Cond.size() == 1);
1815 // Only handle the case where all conditional branches branch to the same
1817 if (TBB != I->getOperand(0).getMBB())
1820 // If the conditions are the same, we can leave them alone.
1821 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
1822 if (OldBranchCode == BranchCode)
1825 // If they differ, see if they fit one of the known patterns. Theoretically,
1826 // we could handle more patterns here, but we shouldn't expect to see them
1827 // if instruction selection has done a reasonable job.
1828 if ((OldBranchCode == X86::COND_NP &&
1829 BranchCode == X86::COND_E) ||
1830 (OldBranchCode == X86::COND_E &&
1831 BranchCode == X86::COND_NP))
1832 BranchCode = X86::COND_NP_OR_E;
1833 else if ((OldBranchCode == X86::COND_P &&
1834 BranchCode == X86::COND_NE) ||
1835 (OldBranchCode == X86::COND_NE &&
1836 BranchCode == X86::COND_P))
1837 BranchCode = X86::COND_NE_OR_P;
1841 // Update the MachineOperand.
1842 Cond[0].setImm(BranchCode);
1848 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
1849 MachineBasicBlock::iterator I = MBB.end();
1852 while (I != MBB.begin()) {
1854 if (I->isDebugValue())
1856 if (I->getOpcode() != X86::JMP_4 &&
1857 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
1859 // Remove the branch.
1860 I->eraseFromParent();
1869 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
1870 MachineBasicBlock *FBB,
1871 const SmallVectorImpl<MachineOperand> &Cond,
1872 DebugLoc DL) const {
1873 // Shouldn't be a fall through.
1874 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
1875 assert((Cond.size() == 1 || Cond.size() == 0) &&
1876 "X86 branch conditions have one component!");
1879 // Unconditional branch?
1880 assert(!FBB && "Unconditional branch with multiple successors!");
1881 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB);
1885 // Conditional branch.
1887 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
1889 case X86::COND_NP_OR_E:
1890 // Synthesize NP_OR_E with two branches.
1891 BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB);
1893 BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB);
1896 case X86::COND_NE_OR_P:
1897 // Synthesize NE_OR_P with two branches.
1898 BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB);
1900 BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB);
1904 unsigned Opc = GetCondBranchFromCond(CC);
1905 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
1910 // Two-way Conditional branch. Insert the second branch.
1911 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB);
1917 /// isHReg - Test if the given register is a physical h register.
1918 static bool isHReg(unsigned Reg) {
1919 return X86::GR8_ABCD_HRegClass.contains(Reg);
1922 // Try and copy between VR128/VR64 and GR64 registers.
1923 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg) {
1924 // SrcReg(VR128) -> DestReg(GR64)
1925 // SrcReg(VR64) -> DestReg(GR64)
1926 // SrcReg(GR64) -> DestReg(VR128)
1927 // SrcReg(GR64) -> DestReg(VR64)
1929 if (X86::GR64RegClass.contains(DestReg)) {
1930 if (X86::VR128RegClass.contains(SrcReg)) {
1931 // Copy from a VR128 register to a GR64 register.
1932 return X86::MOVPQIto64rr;
1933 } else if (X86::VR64RegClass.contains(SrcReg)) {
1934 // Copy from a VR64 register to a GR64 register.
1935 return X86::MOVSDto64rr;
1937 } else if (X86::GR64RegClass.contains(SrcReg)) {
1938 // Copy from a GR64 register to a VR128 register.
1939 if (X86::VR128RegClass.contains(DestReg))
1940 return X86::MOV64toPQIrr;
1941 // Copy from a GR64 register to a VR64 register.
1942 else if (X86::VR64RegClass.contains(DestReg))
1943 return X86::MOV64toSDrr;
1949 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
1950 MachineBasicBlock::iterator MI, DebugLoc DL,
1951 unsigned DestReg, unsigned SrcReg,
1952 bool KillSrc) const {
1953 // First deal with the normal symmetric copies.
1955 if (X86::GR64RegClass.contains(DestReg, SrcReg))
1957 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
1959 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
1961 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
1962 // Copying to or from a physical H register on x86-64 requires a NOREX
1963 // move. Otherwise use a normal move.
1964 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
1965 TM.getSubtarget<X86Subtarget>().is64Bit())
1966 Opc = X86::MOV8rr_NOREX;
1969 } else if (X86::VR128RegClass.contains(DestReg, SrcReg))
1970 Opc = X86::MOVAPSrr;
1971 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
1972 Opc = X86::MMX_MOVQ64rr;
1974 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg);
1977 BuildMI(MBB, MI, DL, get(Opc), DestReg)
1978 .addReg(SrcReg, getKillRegState(KillSrc));
1982 // Moving EFLAGS to / from another register requires a push and a pop.
1983 if (SrcReg == X86::EFLAGS) {
1984 if (X86::GR64RegClass.contains(DestReg)) {
1985 BuildMI(MBB, MI, DL, get(X86::PUSHF64));
1986 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
1988 } else if (X86::GR32RegClass.contains(DestReg)) {
1989 BuildMI(MBB, MI, DL, get(X86::PUSHF32));
1990 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
1994 if (DestReg == X86::EFLAGS) {
1995 if (X86::GR64RegClass.contains(SrcReg)) {
1996 BuildMI(MBB, MI, DL, get(X86::PUSH64r))
1997 .addReg(SrcReg, getKillRegState(KillSrc));
1998 BuildMI(MBB, MI, DL, get(X86::POPF64));
2000 } else if (X86::GR32RegClass.contains(SrcReg)) {
2001 BuildMI(MBB, MI, DL, get(X86::PUSH32r))
2002 .addReg(SrcReg, getKillRegState(KillSrc));
2003 BuildMI(MBB, MI, DL, get(X86::POPF32));
2008 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
2009 << " to " << RI.getName(DestReg) << '\n');
2010 llvm_unreachable("Cannot emit physreg copy instruction");
2013 static unsigned getLoadStoreRegOpcode(unsigned Reg,
2014 const TargetRegisterClass *RC,
2015 bool isStackAligned,
2016 const TargetMachine &TM,
2018 switch (RC->getSize()) {
2020 llvm_unreachable("Unknown spill size");
2022 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
2023 if (TM.getSubtarget<X86Subtarget>().is64Bit())
2024 // Copying to or from a physical H register on x86-64 requires a NOREX
2025 // move. Otherwise use a normal move.
2026 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
2027 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
2028 return load ? X86::MOV8rm : X86::MOV8mr;
2030 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
2031 return load ? X86::MOV16rm : X86::MOV16mr;
2033 if (X86::GR32RegClass.hasSubClassEq(RC))
2034 return load ? X86::MOV32rm : X86::MOV32mr;
2035 if (X86::FR32RegClass.hasSubClassEq(RC))
2036 return load ? X86::MOVSSrm : X86::MOVSSmr;
2037 if (X86::RFP32RegClass.hasSubClassEq(RC))
2038 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
2039 llvm_unreachable("Unknown 4-byte regclass");
2041 if (X86::GR64RegClass.hasSubClassEq(RC))
2042 return load ? X86::MOV64rm : X86::MOV64mr;
2043 if (X86::FR64RegClass.hasSubClassEq(RC))
2044 return load ? X86::MOVSDrm : X86::MOVSDmr;
2045 if (X86::VR64RegClass.hasSubClassEq(RC))
2046 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
2047 if (X86::RFP64RegClass.hasSubClassEq(RC))
2048 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
2049 llvm_unreachable("Unknown 8-byte regclass");
2051 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
2052 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
2054 assert(X86::VR128RegClass.hasSubClassEq(RC) && "Unknown 16-byte regclass");
2055 // If stack is realigned we can use aligned stores.
2057 return load ? X86::MOVAPSrm : X86::MOVAPSmr;
2059 return load ? X86::MOVUPSrm : X86::MOVUPSmr;
2063 static unsigned getStoreRegOpcode(unsigned SrcReg,
2064 const TargetRegisterClass *RC,
2065 bool isStackAligned,
2066 TargetMachine &TM) {
2067 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, TM, false);
2071 static unsigned getLoadRegOpcode(unsigned DestReg,
2072 const TargetRegisterClass *RC,
2073 bool isStackAligned,
2074 const TargetMachine &TM) {
2075 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, TM, true);
2078 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
2079 MachineBasicBlock::iterator MI,
2080 unsigned SrcReg, bool isKill, int FrameIdx,
2081 const TargetRegisterClass *RC,
2082 const TargetRegisterInfo *TRI) const {
2083 const MachineFunction &MF = *MBB.getParent();
2084 assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
2085 "Stack slot too small for store");
2086 bool isAligned = (RI.getStackAlignment() >= 16) || RI.canRealignStack(MF);
2087 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2088 DebugLoc DL = MBB.findDebugLoc(MI);
2089 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
2090 .addReg(SrcReg, getKillRegState(isKill));
2093 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
2095 SmallVectorImpl<MachineOperand> &Addr,
2096 const TargetRegisterClass *RC,
2097 MachineInstr::mmo_iterator MMOBegin,
2098 MachineInstr::mmo_iterator MMOEnd,
2099 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2100 bool isAligned = MMOBegin != MMOEnd && (*MMOBegin)->getAlignment() >= 16;
2101 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2103 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
2104 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2105 MIB.addOperand(Addr[i]);
2106 MIB.addReg(SrcReg, getKillRegState(isKill));
2107 (*MIB).setMemRefs(MMOBegin, MMOEnd);
2108 NewMIs.push_back(MIB);
2112 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
2113 MachineBasicBlock::iterator MI,
2114 unsigned DestReg, int FrameIdx,
2115 const TargetRegisterClass *RC,
2116 const TargetRegisterInfo *TRI) const {
2117 const MachineFunction &MF = *MBB.getParent();
2118 bool isAligned = (RI.getStackAlignment() >= 16) || RI.canRealignStack(MF);
2119 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2120 DebugLoc DL = MBB.findDebugLoc(MI);
2121 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
2124 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
2125 SmallVectorImpl<MachineOperand> &Addr,
2126 const TargetRegisterClass *RC,
2127 MachineInstr::mmo_iterator MMOBegin,
2128 MachineInstr::mmo_iterator MMOEnd,
2129 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2130 bool isAligned = MMOBegin != MMOEnd && (*MMOBegin)->getAlignment() >= 16;
2131 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2133 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
2134 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2135 MIB.addOperand(Addr[i]);
2136 (*MIB).setMemRefs(MMOBegin, MMOEnd);
2137 NewMIs.push_back(MIB);
2141 X86InstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
2142 int FrameIx, uint64_t Offset,
2143 const MDNode *MDPtr,
2144 DebugLoc DL) const {
2146 AM.BaseType = X86AddressMode::FrameIndexBase;
2147 AM.Base.FrameIndex = FrameIx;
2148 MachineInstrBuilder MIB = BuildMI(MF, DL, get(X86::DBG_VALUE));
2149 addFullAddress(MIB, AM).addImm(Offset).addMetadata(MDPtr);
2153 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
2154 const SmallVectorImpl<MachineOperand> &MOs,
2156 const TargetInstrInfo &TII) {
2157 // Create the base instruction with the memory operand as the first part.
2158 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2159 MI->getDebugLoc(), true);
2160 MachineInstrBuilder MIB(NewMI);
2161 unsigned NumAddrOps = MOs.size();
2162 for (unsigned i = 0; i != NumAddrOps; ++i)
2163 MIB.addOperand(MOs[i]);
2164 if (NumAddrOps < 4) // FrameIndex only
2167 // Loop over the rest of the ri operands, converting them over.
2168 unsigned NumOps = MI->getDesc().getNumOperands()-2;
2169 for (unsigned i = 0; i != NumOps; ++i) {
2170 MachineOperand &MO = MI->getOperand(i+2);
2173 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
2174 MachineOperand &MO = MI->getOperand(i);
2180 static MachineInstr *FuseInst(MachineFunction &MF,
2181 unsigned Opcode, unsigned OpNo,
2182 const SmallVectorImpl<MachineOperand> &MOs,
2183 MachineInstr *MI, const TargetInstrInfo &TII) {
2184 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2185 MI->getDebugLoc(), true);
2186 MachineInstrBuilder MIB(NewMI);
2188 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2189 MachineOperand &MO = MI->getOperand(i);
2191 assert(MO.isReg() && "Expected to fold into reg operand!");
2192 unsigned NumAddrOps = MOs.size();
2193 for (unsigned i = 0; i != NumAddrOps; ++i)
2194 MIB.addOperand(MOs[i]);
2195 if (NumAddrOps < 4) // FrameIndex only
2204 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
2205 const SmallVectorImpl<MachineOperand> &MOs,
2207 MachineFunction &MF = *MI->getParent()->getParent();
2208 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
2210 unsigned NumAddrOps = MOs.size();
2211 for (unsigned i = 0; i != NumAddrOps; ++i)
2212 MIB.addOperand(MOs[i]);
2213 if (NumAddrOps < 4) // FrameIndex only
2215 return MIB.addImm(0);
2219 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2220 MachineInstr *MI, unsigned i,
2221 const SmallVectorImpl<MachineOperand> &MOs,
2222 unsigned Size, unsigned Align) const {
2223 const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
2224 bool isTwoAddrFold = false;
2225 unsigned NumOps = MI->getDesc().getNumOperands();
2226 bool isTwoAddr = NumOps > 1 &&
2227 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2229 // FIXME: AsmPrinter doesn't know how to handle
2230 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
2231 if (MI->getOpcode() == X86::ADD32ri &&
2232 MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
2235 MachineInstr *NewMI = NULL;
2236 // Folding a memory location into the two-address part of a two-address
2237 // instruction is different than folding it other places. It requires
2238 // replacing the *two* registers with the memory location.
2239 if (isTwoAddr && NumOps >= 2 && i < 2 &&
2240 MI->getOperand(0).isReg() &&
2241 MI->getOperand(1).isReg() &&
2242 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
2243 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2244 isTwoAddrFold = true;
2245 } else if (i == 0) { // If operand 0
2246 if (MI->getOpcode() == X86::MOV64r0)
2247 NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI);
2248 else if (MI->getOpcode() == X86::MOV32r0)
2249 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
2250 else if (MI->getOpcode() == X86::MOV16r0)
2251 NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
2252 else if (MI->getOpcode() == X86::MOV8r0)
2253 NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
2257 OpcodeTablePtr = &RegOp2MemOpTable0;
2258 } else if (i == 1) {
2259 OpcodeTablePtr = &RegOp2MemOpTable1;
2260 } else if (i == 2) {
2261 OpcodeTablePtr = &RegOp2MemOpTable2;
2264 // If table selected...
2265 if (OpcodeTablePtr) {
2266 // Find the Opcode to fuse
2267 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
2268 OpcodeTablePtr->find(MI->getOpcode());
2269 if (I != OpcodeTablePtr->end()) {
2270 unsigned Opcode = I->second.first;
2271 unsigned MinAlign = I->second.second;
2272 if (Align < MinAlign)
2274 bool NarrowToMOV32rm = false;
2276 unsigned RCSize = MI->getDesc().OpInfo[i].getRegClass(&RI)->getSize();
2277 if (Size < RCSize) {
2278 // Check if it's safe to fold the load. If the size of the object is
2279 // narrower than the load width, then it's not.
2280 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
2282 // If this is a 64-bit load, but the spill slot is 32, then we can do
2283 // a 32-bit load which is implicitly zero-extended. This likely is due
2284 // to liveintervalanalysis remat'ing a load from stack slot.
2285 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
2287 Opcode = X86::MOV32rm;
2288 NarrowToMOV32rm = true;
2293 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
2295 NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
2297 if (NarrowToMOV32rm) {
2298 // If this is the special case where we use a MOV32rm to load a 32-bit
2299 // value and zero-extend the top bits. Change the destination register
2301 unsigned DstReg = NewMI->getOperand(0).getReg();
2302 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
2303 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg,
2306 NewMI->getOperand(0).setSubReg(X86::sub_32bit);
2313 if (PrintFailedFusing && !MI->isCopy())
2314 dbgs() << "We failed to fuse operand " << i << " in " << *MI;
2319 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2321 const SmallVectorImpl<unsigned> &Ops,
2322 int FrameIndex) const {
2323 // Check switch flag
2324 if (NoFusing) return NULL;
2326 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize))
2327 switch (MI->getOpcode()) {
2328 case X86::CVTSD2SSrr:
2329 case X86::Int_CVTSD2SSrr:
2330 case X86::CVTSS2SDrr:
2331 case X86::Int_CVTSS2SDrr:
2333 case X86::RCPSSr_Int:
2337 case X86::RSQRTSSr_Int:
2339 case X86::SQRTSSr_Int:
2343 const MachineFrameInfo *MFI = MF.getFrameInfo();
2344 unsigned Size = MFI->getObjectSize(FrameIndex);
2345 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
2346 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2347 unsigned NewOpc = 0;
2348 unsigned RCSize = 0;
2349 switch (MI->getOpcode()) {
2350 default: return NULL;
2351 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
2352 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
2353 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
2354 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
2356 // Check if it's safe to fold the load. If the size of the object is
2357 // narrower than the load width, then it's not.
2360 // Change to CMPXXri r, 0 first.
2361 MI->setDesc(get(NewOpc));
2362 MI->getOperand(1).ChangeToImmediate(0);
2363 } else if (Ops.size() != 1)
2366 SmallVector<MachineOperand,4> MOs;
2367 MOs.push_back(MachineOperand::CreateFI(FrameIndex));
2368 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment);
2371 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2373 const SmallVectorImpl<unsigned> &Ops,
2374 MachineInstr *LoadMI) const {
2375 // Check switch flag
2376 if (NoFusing) return NULL;
2378 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize))
2379 switch (MI->getOpcode()) {
2380 case X86::CVTSD2SSrr:
2381 case X86::Int_CVTSD2SSrr:
2382 case X86::CVTSS2SDrr:
2383 case X86::Int_CVTSS2SDrr:
2385 case X86::RCPSSr_Int:
2389 case X86::RSQRTSSr_Int:
2391 case X86::SQRTSSr_Int:
2395 // Determine the alignment of the load.
2396 unsigned Alignment = 0;
2397 if (LoadMI->hasOneMemOperand())
2398 Alignment = (*LoadMI->memoperands_begin())->getAlignment();
2400 switch (LoadMI->getOpcode()) {
2401 case X86::AVX_SET0PSY:
2402 case X86::AVX_SET0PDY:
2408 case X86::V_SETALLONES:
2409 case X86::AVX_SET0PS:
2410 case X86::AVX_SET0PD:
2411 case X86::AVX_SET0PI:
2415 case X86::VFsFLD0SD:
2419 case X86::VFsFLD0SS:
2425 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2426 unsigned NewOpc = 0;
2427 switch (MI->getOpcode()) {
2428 default: return NULL;
2429 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
2430 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
2431 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
2432 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
2434 // Change to CMPXXri r, 0 first.
2435 MI->setDesc(get(NewOpc));
2436 MI->getOperand(1).ChangeToImmediate(0);
2437 } else if (Ops.size() != 1)
2440 // Make sure the subregisters match.
2441 // Otherwise we risk changing the size of the load.
2442 if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
2445 SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
2446 switch (LoadMI->getOpcode()) {
2450 case X86::V_SETALLONES:
2451 case X86::AVX_SET0PS:
2452 case X86::AVX_SET0PD:
2453 case X86::AVX_SET0PI:
2454 case X86::AVX_SET0PSY:
2455 case X86::AVX_SET0PDY:
2457 case X86::FsFLD0SS: {
2458 // Folding a V_SET0P? or V_SETALLONES as a load, to ease register pressure.
2459 // Create a constant-pool entry and operands to load from it.
2461 // Medium and large mode can't fold loads this way.
2462 if (TM.getCodeModel() != CodeModel::Small &&
2463 TM.getCodeModel() != CodeModel::Kernel)
2466 // x86-32 PIC requires a PIC base register for constant pools.
2467 unsigned PICBase = 0;
2468 if (TM.getRelocationModel() == Reloc::PIC_) {
2469 if (TM.getSubtarget<X86Subtarget>().is64Bit())
2472 // FIXME: PICBase = getGlobalBaseReg(&MF);
2473 // This doesn't work for several reasons.
2474 // 1. GlobalBaseReg may have been spilled.
2475 // 2. It may not be live at MI.
2479 // Create a constant-pool entry.
2480 MachineConstantPool &MCP = *MF.getConstantPool();
2482 unsigned Opc = LoadMI->getOpcode();
2483 if (Opc == X86::FsFLD0SS || Opc == X86::VFsFLD0SS)
2484 Ty = Type::getFloatTy(MF.getFunction()->getContext());
2485 else if (Opc == X86::FsFLD0SD || Opc == X86::VFsFLD0SD)
2486 Ty = Type::getDoubleTy(MF.getFunction()->getContext());
2487 else if (Opc == X86::AVX_SET0PSY || Opc == X86::AVX_SET0PDY)
2488 Ty = VectorType::get(Type::getFloatTy(MF.getFunction()->getContext()), 8);
2490 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
2491 const Constant *C = LoadMI->getOpcode() == X86::V_SETALLONES ?
2492 Constant::getAllOnesValue(Ty) :
2493 Constant::getNullValue(Ty);
2494 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
2496 // Create operands to load from the constant pool entry.
2497 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
2498 MOs.push_back(MachineOperand::CreateImm(1));
2499 MOs.push_back(MachineOperand::CreateReg(0, false));
2500 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
2501 MOs.push_back(MachineOperand::CreateReg(0, false));
2505 // Folding a normal load. Just copy the load's address operands.
2506 unsigned NumOps = LoadMI->getDesc().getNumOperands();
2507 for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i)
2508 MOs.push_back(LoadMI->getOperand(i));
2512 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment);
2516 bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
2517 const SmallVectorImpl<unsigned> &Ops) const {
2518 // Check switch flag
2519 if (NoFusing) return 0;
2521 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2522 switch (MI->getOpcode()) {
2523 default: return false;
2530 // FIXME: AsmPrinter doesn't know how to handle
2531 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
2532 if (MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
2538 if (Ops.size() != 1)
2541 unsigned OpNum = Ops[0];
2542 unsigned Opc = MI->getOpcode();
2543 unsigned NumOps = MI->getDesc().getNumOperands();
2544 bool isTwoAddr = NumOps > 1 &&
2545 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2547 // Folding a memory location into the two-address part of a two-address
2548 // instruction is different than folding it other places. It requires
2549 // replacing the *two* registers with the memory location.
2550 const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
2551 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
2552 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2553 } else if (OpNum == 0) { // If operand 0
2558 case X86::MOV64r0: return true;
2561 OpcodeTablePtr = &RegOp2MemOpTable0;
2562 } else if (OpNum == 1) {
2563 OpcodeTablePtr = &RegOp2MemOpTable1;
2564 } else if (OpNum == 2) {
2565 OpcodeTablePtr = &RegOp2MemOpTable2;
2568 if (OpcodeTablePtr && OpcodeTablePtr->count(Opc))
2570 return TargetInstrInfoImpl::canFoldMemoryOperand(MI, Ops);
2573 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
2574 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
2575 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2576 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
2577 MemOp2RegOpTable.find(MI->getOpcode());
2578 if (I == MemOp2RegOpTable.end())
2580 unsigned Opc = I->second.first;
2581 unsigned Index = I->second.second & 0xf;
2582 bool FoldedLoad = I->second.second & (1 << 4);
2583 bool FoldedStore = I->second.second & (1 << 5);
2584 if (UnfoldLoad && !FoldedLoad)
2586 UnfoldLoad &= FoldedLoad;
2587 if (UnfoldStore && !FoldedStore)
2589 UnfoldStore &= FoldedStore;
2591 const TargetInstrDesc &TID = get(Opc);
2592 const TargetOperandInfo &TOI = TID.OpInfo[Index];
2593 const TargetRegisterClass *RC = TOI.getRegClass(&RI);
2594 if (!MI->hasOneMemOperand() &&
2595 RC == &X86::VR128RegClass &&
2596 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
2597 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
2598 // conservatively assume the address is unaligned. That's bad for
2601 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
2602 SmallVector<MachineOperand,2> BeforeOps;
2603 SmallVector<MachineOperand,2> AfterOps;
2604 SmallVector<MachineOperand,4> ImpOps;
2605 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2606 MachineOperand &Op = MI->getOperand(i);
2607 if (i >= Index && i < Index + X86::AddrNumOperands)
2608 AddrOps.push_back(Op);
2609 else if (Op.isReg() && Op.isImplicit())
2610 ImpOps.push_back(Op);
2612 BeforeOps.push_back(Op);
2614 AfterOps.push_back(Op);
2617 // Emit the load instruction.
2619 std::pair<MachineInstr::mmo_iterator,
2620 MachineInstr::mmo_iterator> MMOs =
2621 MF.extractLoadMemRefs(MI->memoperands_begin(),
2622 MI->memoperands_end());
2623 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
2625 // Address operands cannot be marked isKill.
2626 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
2627 MachineOperand &MO = NewMIs[0]->getOperand(i);
2629 MO.setIsKill(false);
2634 // Emit the data processing instruction.
2635 MachineInstr *DataMI = MF.CreateMachineInstr(TID, MI->getDebugLoc(), true);
2636 MachineInstrBuilder MIB(DataMI);
2639 MIB.addReg(Reg, RegState::Define);
2640 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
2641 MIB.addOperand(BeforeOps[i]);
2644 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
2645 MIB.addOperand(AfterOps[i]);
2646 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
2647 MachineOperand &MO = ImpOps[i];
2648 MIB.addReg(MO.getReg(),
2649 getDefRegState(MO.isDef()) |
2650 RegState::Implicit |
2651 getKillRegState(MO.isKill()) |
2652 getDeadRegState(MO.isDead()) |
2653 getUndefRegState(MO.isUndef()));
2655 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
2656 unsigned NewOpc = 0;
2657 switch (DataMI->getOpcode()) {
2659 case X86::CMP64ri32:
2666 MachineOperand &MO0 = DataMI->getOperand(0);
2667 MachineOperand &MO1 = DataMI->getOperand(1);
2668 if (MO1.getImm() == 0) {
2669 switch (DataMI->getOpcode()) {
2672 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
2674 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
2676 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
2677 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
2679 DataMI->setDesc(get(NewOpc));
2680 MO1.ChangeToRegister(MO0.getReg(), false);
2684 NewMIs.push_back(DataMI);
2686 // Emit the store instruction.
2688 const TargetRegisterClass *DstRC = TID.OpInfo[0].getRegClass(&RI);
2689 std::pair<MachineInstr::mmo_iterator,
2690 MachineInstr::mmo_iterator> MMOs =
2691 MF.extractStoreMemRefs(MI->memoperands_begin(),
2692 MI->memoperands_end());
2693 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
2700 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
2701 SmallVectorImpl<SDNode*> &NewNodes) const {
2702 if (!N->isMachineOpcode())
2705 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
2706 MemOp2RegOpTable.find(N->getMachineOpcode());
2707 if (I == MemOp2RegOpTable.end())
2709 unsigned Opc = I->second.first;
2710 unsigned Index = I->second.second & 0xf;
2711 bool FoldedLoad = I->second.second & (1 << 4);
2712 bool FoldedStore = I->second.second & (1 << 5);
2713 const TargetInstrDesc &TID = get(Opc);
2714 const TargetRegisterClass *RC = TID.OpInfo[Index].getRegClass(&RI);
2715 unsigned NumDefs = TID.NumDefs;
2716 std::vector<SDValue> AddrOps;
2717 std::vector<SDValue> BeforeOps;
2718 std::vector<SDValue> AfterOps;
2719 DebugLoc dl = N->getDebugLoc();
2720 unsigned NumOps = N->getNumOperands();
2721 for (unsigned i = 0; i != NumOps-1; ++i) {
2722 SDValue Op = N->getOperand(i);
2723 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
2724 AddrOps.push_back(Op);
2725 else if (i < Index-NumDefs)
2726 BeforeOps.push_back(Op);
2727 else if (i > Index-NumDefs)
2728 AfterOps.push_back(Op);
2730 SDValue Chain = N->getOperand(NumOps-1);
2731 AddrOps.push_back(Chain);
2733 // Emit the load instruction.
2735 MachineFunction &MF = DAG.getMachineFunction();
2737 EVT VT = *RC->vt_begin();
2738 std::pair<MachineInstr::mmo_iterator,
2739 MachineInstr::mmo_iterator> MMOs =
2740 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
2741 cast<MachineSDNode>(N)->memoperands_end());
2742 if (!(*MMOs.first) &&
2743 RC == &X86::VR128RegClass &&
2744 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
2745 // Do not introduce a slow unaligned load.
2747 bool isAligned = (*MMOs.first) && (*MMOs.first)->getAlignment() >= 16;
2748 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
2749 VT, MVT::Other, &AddrOps[0], AddrOps.size());
2750 NewNodes.push_back(Load);
2752 // Preserve memory reference information.
2753 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
2756 // Emit the data processing instruction.
2757 std::vector<EVT> VTs;
2758 const TargetRegisterClass *DstRC = 0;
2759 if (TID.getNumDefs() > 0) {
2760 DstRC = TID.OpInfo[0].getRegClass(&RI);
2761 VTs.push_back(*DstRC->vt_begin());
2763 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
2764 EVT VT = N->getValueType(i);
2765 if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs())
2769 BeforeOps.push_back(SDValue(Load, 0));
2770 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
2771 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, &BeforeOps[0],
2773 NewNodes.push_back(NewNode);
2775 // Emit the store instruction.
2778 AddrOps.push_back(SDValue(NewNode, 0));
2779 AddrOps.push_back(Chain);
2780 std::pair<MachineInstr::mmo_iterator,
2781 MachineInstr::mmo_iterator> MMOs =
2782 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
2783 cast<MachineSDNode>(N)->memoperands_end());
2784 if (!(*MMOs.first) &&
2785 RC == &X86::VR128RegClass &&
2786 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
2787 // Do not introduce a slow unaligned store.
2789 bool isAligned = (*MMOs.first) && (*MMOs.first)->getAlignment() >= 16;
2790 SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC,
2793 &AddrOps[0], AddrOps.size());
2794 NewNodes.push_back(Store);
2796 // Preserve memory reference information.
2797 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
2803 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
2804 bool UnfoldLoad, bool UnfoldStore,
2805 unsigned *LoadRegIndex) const {
2806 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
2807 MemOp2RegOpTable.find(Opc);
2808 if (I == MemOp2RegOpTable.end())
2810 bool FoldedLoad = I->second.second & (1 << 4);
2811 bool FoldedStore = I->second.second & (1 << 5);
2812 if (UnfoldLoad && !FoldedLoad)
2814 if (UnfoldStore && !FoldedStore)
2817 *LoadRegIndex = I->second.second & 0xf;
2818 return I->second.first;
2822 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
2823 int64_t &Offset1, int64_t &Offset2) const {
2824 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
2826 unsigned Opc1 = Load1->getMachineOpcode();
2827 unsigned Opc2 = Load2->getMachineOpcode();
2829 default: return false;
2839 case X86::MMX_MOVD64rm:
2840 case X86::MMX_MOVQ64rm:
2841 case X86::FsMOVAPSrm:
2842 case X86::FsMOVAPDrm:
2851 default: return false;
2861 case X86::MMX_MOVD64rm:
2862 case X86::MMX_MOVQ64rm:
2863 case X86::FsMOVAPSrm:
2864 case X86::FsMOVAPDrm:
2873 // Check if chain operands and base addresses match.
2874 if (Load1->getOperand(0) != Load2->getOperand(0) ||
2875 Load1->getOperand(5) != Load2->getOperand(5))
2877 // Segment operands should match as well.
2878 if (Load1->getOperand(4) != Load2->getOperand(4))
2880 // Scale should be 1, Index should be Reg0.
2881 if (Load1->getOperand(1) == Load2->getOperand(1) &&
2882 Load1->getOperand(2) == Load2->getOperand(2)) {
2883 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
2886 // Now let's examine the displacements.
2887 if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
2888 isa<ConstantSDNode>(Load2->getOperand(3))) {
2889 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
2890 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
2897 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
2898 int64_t Offset1, int64_t Offset2,
2899 unsigned NumLoads) const {
2900 assert(Offset2 > Offset1);
2901 if ((Offset2 - Offset1) / 8 > 64)
2904 unsigned Opc1 = Load1->getMachineOpcode();
2905 unsigned Opc2 = Load2->getMachineOpcode();
2907 return false; // FIXME: overly conservative?
2914 case X86::MMX_MOVD64rm:
2915 case X86::MMX_MOVQ64rm:
2919 EVT VT = Load1->getValueType(0);
2920 switch (VT.getSimpleVT().SimpleTy) {
2922 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
2923 // have 16 of them to play with.
2924 if (TM.getSubtargetImpl()->is64Bit()) {
2927 } else if (NumLoads) {
2947 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
2948 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
2949 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
2950 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
2952 Cond[0].setImm(GetOppositeBranchCondition(CC));
2957 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
2958 // FIXME: Return false for x87 stack register classes for now. We can't
2959 // allow any loads of these registers before FpGet_ST0_80.
2960 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
2961 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
2965 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or higher)
2966 /// register? e.g. r8, xmm8, xmm13, etc.
2967 bool X86InstrInfo::isX86_64ExtendedReg(unsigned RegNo) {
2970 case X86::R8: case X86::R9: case X86::R10: case X86::R11:
2971 case X86::R12: case X86::R13: case X86::R14: case X86::R15:
2972 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D:
2973 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D:
2974 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W:
2975 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W:
2976 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B:
2977 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
2978 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
2979 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
2980 case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
2981 case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
2982 case X86::CR8: case X86::CR9: case X86::CR10: case X86::CR11:
2983 case X86::CR12: case X86::CR13: case X86::CR14: case X86::CR15:
2989 /// getGlobalBaseReg - Return a virtual register initialized with the
2990 /// the global base register value. Output instructions required to
2991 /// initialize the register in the function entry block, if necessary.
2993 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
2995 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
2996 assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
2997 "X86-64 PIC uses RIP relative addressing");
2999 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
3000 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
3001 if (GlobalBaseReg != 0)
3002 return GlobalBaseReg;
3004 // Create the register. The code to initialize it is inserted
3005 // later, by the CGBR pass (below).
3006 MachineRegisterInfo &RegInfo = MF->getRegInfo();
3007 GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3008 X86FI->setGlobalBaseReg(GlobalBaseReg);
3009 return GlobalBaseReg;
3012 // These are the replaceable SSE instructions. Some of these have Int variants
3013 // that we don't include here. We don't want to replace instructions selected
3015 static const unsigned ReplaceableInstrs[][3] = {
3016 //PackedSingle PackedDouble PackedInt
3017 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
3018 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
3019 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
3020 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
3021 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
3022 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
3023 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
3024 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
3025 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
3026 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
3027 { X86::ORPSrm, X86::ORPDrm, X86::PORrm },
3028 { X86::ORPSrr, X86::ORPDrr, X86::PORrr },
3029 { X86::V_SET0PS, X86::V_SET0PD, X86::V_SET0PI },
3030 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
3031 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
3032 // AVX 128-bit support
3033 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr },
3034 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm },
3035 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr },
3036 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr },
3037 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm },
3038 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
3039 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm },
3040 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr },
3041 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm },
3042 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr },
3043 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm },
3044 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr },
3045 { X86::AVX_SET0PS, X86::AVX_SET0PD, X86::AVX_SET0PI },
3046 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm },
3047 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr },
3050 // FIXME: Some shuffle and unpack instructions have equivalents in different
3051 // domains, but they require a bit more work than just switching opcodes.
3053 static const unsigned *lookup(unsigned opcode, unsigned domain) {
3054 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
3055 if (ReplaceableInstrs[i][domain-1] == opcode)
3056 return ReplaceableInstrs[i];
3060 std::pair<uint16_t, uint16_t>
3061 X86InstrInfo::GetSSEDomain(const MachineInstr *MI) const {
3062 uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
3063 return std::make_pair(domain,
3064 domain && lookup(MI->getOpcode(), domain) ? 0xe : 0);
3067 void X86InstrInfo::SetSSEDomain(MachineInstr *MI, unsigned Domain) const {
3068 assert(Domain>0 && Domain<4 && "Invalid execution domain");
3069 uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
3070 assert(dom && "Not an SSE instruction");
3071 const unsigned *table = lookup(MI->getOpcode(), dom);
3072 assert(table && "Cannot change domain");
3073 MI->setDesc(get(table[Domain-1]));
3076 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
3077 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
3078 NopInst.setOpcode(X86::NOOP);
3081 bool X86InstrInfo::isHighLatencyDef(int opc) const {
3083 default: return false;
3085 case X86::DIVSDrm_Int:
3087 case X86::DIVSDrr_Int:
3089 case X86::DIVSSrm_Int:
3091 case X86::DIVSSrr_Int:
3093 case X86::SQRTPDm_Int:
3095 case X86::SQRTPDr_Int:
3097 case X86::SQRTPSm_Int:
3099 case X86::SQRTPSr_Int:
3101 case X86::SQRTSDm_Int:
3103 case X86::SQRTSDr_Int:
3105 case X86::SQRTSSm_Int:
3107 case X86::SQRTSSr_Int:
3113 hasHighOperandLatency(const InstrItineraryData *ItinData,
3114 const MachineRegisterInfo *MRI,
3115 const MachineInstr *DefMI, unsigned DefIdx,
3116 const MachineInstr *UseMI, unsigned UseIdx) const {
3117 return isHighLatencyDef(DefMI->getOpcode());
3121 /// CGBR - Create Global Base Reg pass. This initializes the PIC
3122 /// global base register for x86-32.
3123 struct CGBR : public MachineFunctionPass {
3125 CGBR() : MachineFunctionPass(ID) {}
3127 virtual bool runOnMachineFunction(MachineFunction &MF) {
3128 const X86TargetMachine *TM =
3129 static_cast<const X86TargetMachine *>(&MF.getTarget());
3131 assert(!TM->getSubtarget<X86Subtarget>().is64Bit() &&
3132 "X86-64 PIC uses RIP relative addressing");
3134 // Only emit a global base reg in PIC mode.
3135 if (TM->getRelocationModel() != Reloc::PIC_)
3138 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
3139 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
3141 // If we didn't need a GlobalBaseReg, don't insert code.
3142 if (GlobalBaseReg == 0)
3145 // Insert the set of GlobalBaseReg into the first MBB of the function
3146 MachineBasicBlock &FirstMBB = MF.front();
3147 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
3148 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
3149 MachineRegisterInfo &RegInfo = MF.getRegInfo();
3150 const X86InstrInfo *TII = TM->getInstrInfo();
3153 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT())
3154 PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3158 // Operand of MovePCtoStack is completely ignored by asm printer. It's
3159 // only used in JIT code emission as displacement to pc.
3160 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
3162 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
3163 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
3164 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) {
3165 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
3166 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
3167 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
3168 X86II::MO_GOT_ABSOLUTE_ADDRESS);
3174 virtual const char *getPassName() const {
3175 return "X86 PIC Global Base Reg Initialization";
3178 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
3179 AU.setPreservesCFG();
3180 MachineFunctionPass::getAnalysisUsage(AU);
3187 llvm::createGlobalBaseRegPass() { return new CGBR(); }