1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/LLVMContext.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/LiveVariables.h"
28 #include "llvm/MC/MCInst.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/MC/MCAsmInfo.h"
37 #define GET_INSTRINFO_CTOR
38 #include "X86GenInstrInfo.inc"
43 NoFusing("disable-spill-fusing",
44 cl::desc("Disable fusing of spill code into instructions"));
46 PrintFailedFusing("print-failed-fuse-candidates",
47 cl::desc("Print instructions that the allocator wants to"
48 " fuse, but the X86 backend currently can't"),
51 ReMatPICStubLoad("remat-pic-stub-load",
52 cl::desc("Re-materialize load from stub in PIC mode"),
53 cl::init(false), cl::Hidden);
56 // Select which memory operand is being unfolded.
57 // (stored in bits 0 - 7)
63 // Minimum alignment required for load/store.
64 // Used for RegOp->MemOp conversion.
65 // (stored in bits 8 - 15)
67 TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT,
68 TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT,
69 TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT,
70 TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT,
72 // Do not insert the reverse map (MemOp -> RegOp) into the table.
73 // This may be needed because there is a many -> one mapping.
74 TB_NO_REVERSE = 1 << 16,
76 // Do not insert the forward map (RegOp -> MemOp) into the table.
77 // This is needed for Native Client, which prohibits branch
78 // instructions from using a memory operand.
79 TB_NO_FORWARD = 1 << 17,
81 TB_FOLDED_LOAD = 1 << 18,
82 TB_FOLDED_STORE = 1 << 19
85 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
86 : X86GenInstrInfo((tm.getSubtarget<X86Subtarget>().is64Bit()
87 ? X86::ADJCALLSTACKDOWN64
88 : X86::ADJCALLSTACKDOWN32),
89 (tm.getSubtarget<X86Subtarget>().is64Bit()
90 ? X86::ADJCALLSTACKUP64
91 : X86::ADJCALLSTACKUP32)),
92 TM(tm), RI(tm, *this) {
94 static const unsigned OpTbl2Addr[][3] = {
95 { X86::ADC32ri, X86::ADC32mi, 0 },
96 { X86::ADC32ri8, X86::ADC32mi8, 0 },
97 { X86::ADC32rr, X86::ADC32mr, 0 },
98 { X86::ADC64ri32, X86::ADC64mi32, 0 },
99 { X86::ADC64ri8, X86::ADC64mi8, 0 },
100 { X86::ADC64rr, X86::ADC64mr, 0 },
101 { X86::ADD16ri, X86::ADD16mi, 0 },
102 { X86::ADD16ri8, X86::ADD16mi8, 0 },
103 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE },
104 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE },
105 { X86::ADD16rr, X86::ADD16mr, 0 },
106 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE },
107 { X86::ADD32ri, X86::ADD32mi, 0 },
108 { X86::ADD32ri8, X86::ADD32mi8, 0 },
109 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE },
110 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE },
111 { X86::ADD32rr, X86::ADD32mr, 0 },
112 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE },
113 { X86::ADD64ri32, X86::ADD64mi32, 0 },
114 { X86::ADD64ri8, X86::ADD64mi8, 0 },
115 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE },
116 { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE },
117 { X86::ADD64rr, X86::ADD64mr, 0 },
118 { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE },
119 { X86::ADD8ri, X86::ADD8mi, 0 },
120 { X86::ADD8rr, X86::ADD8mr, 0 },
121 { X86::AND16ri, X86::AND16mi, 0 },
122 { X86::AND16ri8, X86::AND16mi8, 0 },
123 { X86::AND16rr, X86::AND16mr, 0 },
124 { X86::AND32ri, X86::AND32mi, 0 },
125 { X86::AND32ri8, X86::AND32mi8, 0 },
126 { X86::AND32rr, X86::AND32mr, 0 },
127 { X86::AND64ri32, X86::AND64mi32, 0 },
128 { X86::AND64ri8, X86::AND64mi8, 0 },
129 { X86::AND64rr, X86::AND64mr, 0 },
130 { X86::AND8ri, X86::AND8mi, 0 },
131 { X86::AND8rr, X86::AND8mr, 0 },
132 { X86::DEC16r, X86::DEC16m, 0 },
133 { X86::DEC32r, X86::DEC32m, 0 },
134 { X86::DEC64_16r, X86::DEC64_16m, 0 },
135 { X86::DEC64_32r, X86::DEC64_32m, 0 },
136 { X86::DEC64r, X86::DEC64m, 0 },
137 { X86::DEC8r, X86::DEC8m, 0 },
138 { X86::INC16r, X86::INC16m, 0 },
139 { X86::INC32r, X86::INC32m, 0 },
140 { X86::INC64_16r, X86::INC64_16m, 0 },
141 { X86::INC64_32r, X86::INC64_32m, 0 },
142 { X86::INC64r, X86::INC64m, 0 },
143 { X86::INC8r, X86::INC8m, 0 },
144 { X86::NEG16r, X86::NEG16m, 0 },
145 { X86::NEG32r, X86::NEG32m, 0 },
146 { X86::NEG64r, X86::NEG64m, 0 },
147 { X86::NEG8r, X86::NEG8m, 0 },
148 { X86::NOT16r, X86::NOT16m, 0 },
149 { X86::NOT32r, X86::NOT32m, 0 },
150 { X86::NOT64r, X86::NOT64m, 0 },
151 { X86::NOT8r, X86::NOT8m, 0 },
152 { X86::OR16ri, X86::OR16mi, 0 },
153 { X86::OR16ri8, X86::OR16mi8, 0 },
154 { X86::OR16rr, X86::OR16mr, 0 },
155 { X86::OR32ri, X86::OR32mi, 0 },
156 { X86::OR32ri8, X86::OR32mi8, 0 },
157 { X86::OR32rr, X86::OR32mr, 0 },
158 { X86::OR64ri32, X86::OR64mi32, 0 },
159 { X86::OR64ri8, X86::OR64mi8, 0 },
160 { X86::OR64rr, X86::OR64mr, 0 },
161 { X86::OR8ri, X86::OR8mi, 0 },
162 { X86::OR8rr, X86::OR8mr, 0 },
163 { X86::ROL16r1, X86::ROL16m1, 0 },
164 { X86::ROL16rCL, X86::ROL16mCL, 0 },
165 { X86::ROL16ri, X86::ROL16mi, 0 },
166 { X86::ROL32r1, X86::ROL32m1, 0 },
167 { X86::ROL32rCL, X86::ROL32mCL, 0 },
168 { X86::ROL32ri, X86::ROL32mi, 0 },
169 { X86::ROL64r1, X86::ROL64m1, 0 },
170 { X86::ROL64rCL, X86::ROL64mCL, 0 },
171 { X86::ROL64ri, X86::ROL64mi, 0 },
172 { X86::ROL8r1, X86::ROL8m1, 0 },
173 { X86::ROL8rCL, X86::ROL8mCL, 0 },
174 { X86::ROL8ri, X86::ROL8mi, 0 },
175 { X86::ROR16r1, X86::ROR16m1, 0 },
176 { X86::ROR16rCL, X86::ROR16mCL, 0 },
177 { X86::ROR16ri, X86::ROR16mi, 0 },
178 { X86::ROR32r1, X86::ROR32m1, 0 },
179 { X86::ROR32rCL, X86::ROR32mCL, 0 },
180 { X86::ROR32ri, X86::ROR32mi, 0 },
181 { X86::ROR64r1, X86::ROR64m1, 0 },
182 { X86::ROR64rCL, X86::ROR64mCL, 0 },
183 { X86::ROR64ri, X86::ROR64mi, 0 },
184 { X86::ROR8r1, X86::ROR8m1, 0 },
185 { X86::ROR8rCL, X86::ROR8mCL, 0 },
186 { X86::ROR8ri, X86::ROR8mi, 0 },
187 { X86::SAR16r1, X86::SAR16m1, 0 },
188 { X86::SAR16rCL, X86::SAR16mCL, 0 },
189 { X86::SAR16ri, X86::SAR16mi, 0 },
190 { X86::SAR32r1, X86::SAR32m1, 0 },
191 { X86::SAR32rCL, X86::SAR32mCL, 0 },
192 { X86::SAR32ri, X86::SAR32mi, 0 },
193 { X86::SAR64r1, X86::SAR64m1, 0 },
194 { X86::SAR64rCL, X86::SAR64mCL, 0 },
195 { X86::SAR64ri, X86::SAR64mi, 0 },
196 { X86::SAR8r1, X86::SAR8m1, 0 },
197 { X86::SAR8rCL, X86::SAR8mCL, 0 },
198 { X86::SAR8ri, X86::SAR8mi, 0 },
199 { X86::SBB32ri, X86::SBB32mi, 0 },
200 { X86::SBB32ri8, X86::SBB32mi8, 0 },
201 { X86::SBB32rr, X86::SBB32mr, 0 },
202 { X86::SBB64ri32, X86::SBB64mi32, 0 },
203 { X86::SBB64ri8, X86::SBB64mi8, 0 },
204 { X86::SBB64rr, X86::SBB64mr, 0 },
205 { X86::SHL16rCL, X86::SHL16mCL, 0 },
206 { X86::SHL16ri, X86::SHL16mi, 0 },
207 { X86::SHL32rCL, X86::SHL32mCL, 0 },
208 { X86::SHL32ri, X86::SHL32mi, 0 },
209 { X86::SHL64rCL, X86::SHL64mCL, 0 },
210 { X86::SHL64ri, X86::SHL64mi, 0 },
211 { X86::SHL8rCL, X86::SHL8mCL, 0 },
212 { X86::SHL8ri, X86::SHL8mi, 0 },
213 { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 },
214 { X86::SHLD16rri8, X86::SHLD16mri8, 0 },
215 { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 },
216 { X86::SHLD32rri8, X86::SHLD32mri8, 0 },
217 { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 },
218 { X86::SHLD64rri8, X86::SHLD64mri8, 0 },
219 { X86::SHR16r1, X86::SHR16m1, 0 },
220 { X86::SHR16rCL, X86::SHR16mCL, 0 },
221 { X86::SHR16ri, X86::SHR16mi, 0 },
222 { X86::SHR32r1, X86::SHR32m1, 0 },
223 { X86::SHR32rCL, X86::SHR32mCL, 0 },
224 { X86::SHR32ri, X86::SHR32mi, 0 },
225 { X86::SHR64r1, X86::SHR64m1, 0 },
226 { X86::SHR64rCL, X86::SHR64mCL, 0 },
227 { X86::SHR64ri, X86::SHR64mi, 0 },
228 { X86::SHR8r1, X86::SHR8m1, 0 },
229 { X86::SHR8rCL, X86::SHR8mCL, 0 },
230 { X86::SHR8ri, X86::SHR8mi, 0 },
231 { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 },
232 { X86::SHRD16rri8, X86::SHRD16mri8, 0 },
233 { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 },
234 { X86::SHRD32rri8, X86::SHRD32mri8, 0 },
235 { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 },
236 { X86::SHRD64rri8, X86::SHRD64mri8, 0 },
237 { X86::SUB16ri, X86::SUB16mi, 0 },
238 { X86::SUB16ri8, X86::SUB16mi8, 0 },
239 { X86::SUB16rr, X86::SUB16mr, 0 },
240 { X86::SUB32ri, X86::SUB32mi, 0 },
241 { X86::SUB32ri8, X86::SUB32mi8, 0 },
242 { X86::SUB32rr, X86::SUB32mr, 0 },
243 { X86::SUB64ri32, X86::SUB64mi32, 0 },
244 { X86::SUB64ri8, X86::SUB64mi8, 0 },
245 { X86::SUB64rr, X86::SUB64mr, 0 },
246 { X86::SUB8ri, X86::SUB8mi, 0 },
247 { X86::SUB8rr, X86::SUB8mr, 0 },
248 { X86::XOR16ri, X86::XOR16mi, 0 },
249 { X86::XOR16ri8, X86::XOR16mi8, 0 },
250 { X86::XOR16rr, X86::XOR16mr, 0 },
251 { X86::XOR32ri, X86::XOR32mi, 0 },
252 { X86::XOR32ri8, X86::XOR32mi8, 0 },
253 { X86::XOR32rr, X86::XOR32mr, 0 },
254 { X86::XOR64ri32, X86::XOR64mi32, 0 },
255 { X86::XOR64ri8, X86::XOR64mi8, 0 },
256 { X86::XOR64rr, X86::XOR64mr, 0 },
257 { X86::XOR8ri, X86::XOR8mi, 0 },
258 { X86::XOR8rr, X86::XOR8mr, 0 }
261 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
262 unsigned RegOp = OpTbl2Addr[i][0];
263 unsigned MemOp = OpTbl2Addr[i][1];
264 unsigned Flags = OpTbl2Addr[i][2];
265 AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
267 // Index 0, folded load and store, no alignment requirement.
268 Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
271 static const unsigned OpTbl0[][3] = {
272 { X86::BT16ri8, X86::BT16mi8, TB_FOLDED_LOAD },
273 { X86::BT32ri8, X86::BT32mi8, TB_FOLDED_LOAD },
274 { X86::BT64ri8, X86::BT64mi8, TB_FOLDED_LOAD },
275 { X86::CALL32r, X86::CALL32m, TB_FOLDED_LOAD },
276 { X86::CALL64r, X86::CALL64m, TB_FOLDED_LOAD },
277 { X86::WINCALL64r, X86::WINCALL64m, TB_FOLDED_LOAD },
278 { X86::CMP16ri, X86::CMP16mi, TB_FOLDED_LOAD },
279 { X86::CMP16ri8, X86::CMP16mi8, TB_FOLDED_LOAD },
280 { X86::CMP16rr, X86::CMP16mr, TB_FOLDED_LOAD },
281 { X86::CMP32ri, X86::CMP32mi, TB_FOLDED_LOAD },
282 { X86::CMP32ri8, X86::CMP32mi8, TB_FOLDED_LOAD },
283 { X86::CMP32rr, X86::CMP32mr, TB_FOLDED_LOAD },
284 { X86::CMP64ri32, X86::CMP64mi32, TB_FOLDED_LOAD },
285 { X86::CMP64ri8, X86::CMP64mi8, TB_FOLDED_LOAD },
286 { X86::CMP64rr, X86::CMP64mr, TB_FOLDED_LOAD },
287 { X86::CMP8ri, X86::CMP8mi, TB_FOLDED_LOAD },
288 { X86::CMP8rr, X86::CMP8mr, TB_FOLDED_LOAD },
289 { X86::DIV16r, X86::DIV16m, TB_FOLDED_LOAD },
290 { X86::DIV32r, X86::DIV32m, TB_FOLDED_LOAD },
291 { X86::DIV64r, X86::DIV64m, TB_FOLDED_LOAD },
292 { X86::DIV8r, X86::DIV8m, TB_FOLDED_LOAD },
293 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
294 { X86::FsMOVAPDrr, X86::MOVSDmr, TB_FOLDED_STORE | TB_NO_REVERSE },
295 { X86::FsMOVAPSrr, X86::MOVSSmr, TB_FOLDED_STORE | TB_NO_REVERSE },
296 { X86::IDIV16r, X86::IDIV16m, TB_FOLDED_LOAD },
297 { X86::IDIV32r, X86::IDIV32m, TB_FOLDED_LOAD },
298 { X86::IDIV64r, X86::IDIV64m, TB_FOLDED_LOAD },
299 { X86::IDIV8r, X86::IDIV8m, TB_FOLDED_LOAD },
300 { X86::IMUL16r, X86::IMUL16m, TB_FOLDED_LOAD },
301 { X86::IMUL32r, X86::IMUL32m, TB_FOLDED_LOAD },
302 { X86::IMUL64r, X86::IMUL64m, TB_FOLDED_LOAD },
303 { X86::IMUL8r, X86::IMUL8m, TB_FOLDED_LOAD },
304 { X86::JMP32r, X86::JMP32m, TB_FOLDED_LOAD },
305 { X86::JMP64r, X86::JMP64m, TB_FOLDED_LOAD },
306 { X86::MOV16ri, X86::MOV16mi, TB_FOLDED_STORE },
307 { X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE },
308 { X86::MOV32ri, X86::MOV32mi, TB_FOLDED_STORE },
309 { X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE },
310 { X86::MOV64ri32, X86::MOV64mi32, TB_FOLDED_STORE },
311 { X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE },
312 { X86::MOV8ri, X86::MOV8mi, TB_FOLDED_STORE },
313 { X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE },
314 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
315 { X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
316 { X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
317 { X86::MOVDQArr, X86::MOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
318 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, TB_FOLDED_STORE },
319 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, TB_FOLDED_STORE },
320 { X86::MOVSDto64rr, X86::MOVSDto64mr, TB_FOLDED_STORE },
321 { X86::MOVSS2DIrr, X86::MOVSS2DImr, TB_FOLDED_STORE },
322 { X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE },
323 { X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE },
324 { X86::MUL16r, X86::MUL16m, TB_FOLDED_LOAD },
325 { X86::MUL32r, X86::MUL32m, TB_FOLDED_LOAD },
326 { X86::MUL64r, X86::MUL64m, TB_FOLDED_LOAD },
327 { X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD },
328 { X86::SETAEr, X86::SETAEm, TB_FOLDED_STORE },
329 { X86::SETAr, X86::SETAm, TB_FOLDED_STORE },
330 { X86::SETBEr, X86::SETBEm, TB_FOLDED_STORE },
331 { X86::SETBr, X86::SETBm, TB_FOLDED_STORE },
332 { X86::SETEr, X86::SETEm, TB_FOLDED_STORE },
333 { X86::SETGEr, X86::SETGEm, TB_FOLDED_STORE },
334 { X86::SETGr, X86::SETGm, TB_FOLDED_STORE },
335 { X86::SETLEr, X86::SETLEm, TB_FOLDED_STORE },
336 { X86::SETLr, X86::SETLm, TB_FOLDED_STORE },
337 { X86::SETNEr, X86::SETNEm, TB_FOLDED_STORE },
338 { X86::SETNOr, X86::SETNOm, TB_FOLDED_STORE },
339 { X86::SETNPr, X86::SETNPm, TB_FOLDED_STORE },
340 { X86::SETNSr, X86::SETNSm, TB_FOLDED_STORE },
341 { X86::SETOr, X86::SETOm, TB_FOLDED_STORE },
342 { X86::SETPr, X86::SETPm, TB_FOLDED_STORE },
343 { X86::SETSr, X86::SETSm, TB_FOLDED_STORE },
344 { X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD },
345 { X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD },
346 { X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD },
347 { X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD },
348 { X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD },
349 { X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD },
350 // AVX 128-bit versions of foldable instructions
351 { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
352 { X86::FsVMOVAPDrr, X86::VMOVSDmr, TB_FOLDED_STORE | TB_NO_REVERSE },
353 { X86::FsVMOVAPSrr, X86::VMOVSSmr, TB_FOLDED_STORE | TB_NO_REVERSE },
354 { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
355 { X86::VMOVAPDrr, X86::VMOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
356 { X86::VMOVAPSrr, X86::VMOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
357 { X86::VMOVDQArr, X86::VMOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
358 { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr, TB_FOLDED_STORE },
359 { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
360 { X86::VMOVSDto64rr,X86::VMOVSDto64mr, TB_FOLDED_STORE },
361 { X86::VMOVSS2DIrr, X86::VMOVSS2DImr, TB_FOLDED_STORE },
362 { X86::VMOVUPDrr, X86::VMOVUPDmr, TB_FOLDED_STORE },
363 { X86::VMOVUPSrr, X86::VMOVUPSmr, TB_FOLDED_STORE },
364 // AVX 256-bit foldable instructions
365 { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
366 { X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
367 { X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
368 { X86::VMOVDQAYrr, X86::VMOVDQAYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
369 { X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE },
370 { X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE }
373 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
374 unsigned RegOp = OpTbl0[i][0];
375 unsigned MemOp = OpTbl0[i][1];
376 unsigned Flags = OpTbl0[i][2];
377 AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
378 RegOp, MemOp, TB_INDEX_0 | Flags);
381 static const unsigned OpTbl1[][3] = {
382 { X86::CMP16rr, X86::CMP16rm, 0 },
383 { X86::CMP32rr, X86::CMP32rm, 0 },
384 { X86::CMP64rr, X86::CMP64rm, 0 },
385 { X86::CMP8rr, X86::CMP8rm, 0 },
386 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
387 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
388 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
389 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
390 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
391 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
392 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
393 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
394 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
395 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
396 { X86::FsMOVAPDrr, X86::MOVSDrm, TB_NO_REVERSE },
397 { X86::FsMOVAPSrr, X86::MOVSSrm, TB_NO_REVERSE },
398 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
399 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
400 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
401 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
402 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
403 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
404 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
405 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
406 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm, TB_ALIGN_16 },
407 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm, TB_ALIGN_16 },
408 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm, TB_ALIGN_16 },
409 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm, TB_ALIGN_16 },
410 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm, TB_ALIGN_16 },
411 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm, 0 },
412 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 },
413 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 },
414 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
415 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
416 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
417 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
418 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
419 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
420 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, TB_ALIGN_16 },
421 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, TB_ALIGN_16 },
422 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
423 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
424 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
425 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
426 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
427 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
428 { X86::MOV16rr, X86::MOV16rm, 0 },
429 { X86::MOV32rr, X86::MOV32rm, 0 },
430 { X86::MOV64rr, X86::MOV64rm, 0 },
431 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
432 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
433 { X86::MOV8rr, X86::MOV8rm, 0 },
434 { X86::MOVAPDrr, X86::MOVAPDrm, TB_ALIGN_16 },
435 { X86::MOVAPSrr, X86::MOVAPSrm, TB_ALIGN_16 },
436 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
437 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
438 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
439 { X86::MOVDQArr, X86::MOVDQArm, TB_ALIGN_16 },
440 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, TB_ALIGN_16 },
441 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16 },
442 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
443 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
444 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
445 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
446 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
447 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
448 { X86::MOVUPDrr, X86::MOVUPDrm, TB_ALIGN_16 },
449 { X86::MOVUPSrr, X86::MOVUPSrm, 0 },
450 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm, 0 },
451 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 },
452 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, TB_ALIGN_16 },
453 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
454 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
455 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
456 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
457 { X86::MOVZX64rr16, X86::MOVZX64rm16, 0 },
458 { X86::MOVZX64rr32, X86::MOVZX64rm32, 0 },
459 { X86::MOVZX64rr8, X86::MOVZX64rm8, 0 },
460 { X86::PABSBrr128, X86::PABSBrm128, TB_ALIGN_16 },
461 { X86::PABSDrr128, X86::PABSDrm128, TB_ALIGN_16 },
462 { X86::PABSWrr128, X86::PABSWrm128, TB_ALIGN_16 },
463 { X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16 },
464 { X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16 },
465 { X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16 },
466 { X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16 },
467 { X86::RCPPSr_Int, X86::RCPPSm_Int, TB_ALIGN_16 },
468 { X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16 },
469 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, TB_ALIGN_16 },
470 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
471 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
472 { X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16 },
473 { X86::SQRTPDr_Int, X86::SQRTPDm_Int, TB_ALIGN_16 },
474 { X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16 },
475 { X86::SQRTPSr_Int, X86::SQRTPSm_Int, TB_ALIGN_16 },
476 { X86::SQRTSDr, X86::SQRTSDm, 0 },
477 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
478 { X86::SQRTSSr, X86::SQRTSSm, 0 },
479 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
480 { X86::TEST16rr, X86::TEST16rm, 0 },
481 { X86::TEST32rr, X86::TEST32rm, 0 },
482 { X86::TEST64rr, X86::TEST64rm, 0 },
483 { X86::TEST8rr, X86::TEST8rm, 0 },
484 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
485 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
486 { X86::UCOMISSrr, X86::UCOMISSrm, 0 },
487 // AVX 128-bit versions of foldable instructions
488 { X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, 0 },
489 { X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, 0 },
490 { X86::Int_VCVTDQ2PDrr, X86::Int_VCVTDQ2PDrm, TB_ALIGN_16 },
491 { X86::Int_VCVTDQ2PSrr, X86::Int_VCVTDQ2PSrm, TB_ALIGN_16 },
492 { X86::Int_VCVTPD2DQrr, X86::Int_VCVTPD2DQrm, TB_ALIGN_16 },
493 { X86::Int_VCVTPD2PSrr, X86::Int_VCVTPD2PSrm, TB_ALIGN_16 },
494 { X86::Int_VCVTPS2DQrr, X86::Int_VCVTPS2DQrm, TB_ALIGN_16 },
495 { X86::Int_VCVTPS2PDrr, X86::Int_VCVTPS2PDrm, 0 },
496 { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, 0 },
497 { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, 0 },
498 { X86::FsVMOVAPDrr, X86::VMOVSDrm, TB_NO_REVERSE },
499 { X86::FsVMOVAPSrr, X86::VMOVSSrm, TB_NO_REVERSE },
500 { X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 },
501 { X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 },
502 { X86::VMOVAPDrr, X86::VMOVAPDrm, TB_ALIGN_16 },
503 { X86::VMOVAPSrr, X86::VMOVAPSrm, TB_ALIGN_16 },
504 { X86::VMOVDDUPrr, X86::VMOVDDUPrm, 0 },
505 { X86::VMOVDI2PDIrr, X86::VMOVDI2PDIrm, 0 },
506 { X86::VMOVDI2SSrr, X86::VMOVDI2SSrm, 0 },
507 { X86::VMOVDQArr, X86::VMOVDQArm, TB_ALIGN_16 },
508 { X86::VMOVSLDUPrr, X86::VMOVSLDUPrm, TB_ALIGN_16 },
509 { X86::VMOVSHDUPrr, X86::VMOVSHDUPrm, TB_ALIGN_16 },
510 { X86::VMOVUPDrr, X86::VMOVUPDrm, TB_ALIGN_16 },
511 { X86::VMOVUPSrr, X86::VMOVUPSrm, 0 },
512 { X86::VMOVZDI2PDIrr, X86::VMOVZDI2PDIrm, 0 },
513 { X86::VMOVZQI2PQIrr, X86::VMOVZQI2PQIrm, 0 },
514 { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm, TB_ALIGN_16 },
515 { X86::VPABSBrr128, X86::VPABSBrm128, TB_ALIGN_16 },
516 { X86::VPABSDrr128, X86::VPABSDrm128, TB_ALIGN_16 },
517 { X86::VPABSWrr128, X86::VPABSWrm128, TB_ALIGN_16 },
518 { X86::VPERMILPDri, X86::VPERMILPDmi, TB_ALIGN_16 },
519 { X86::VPERMILPSri, X86::VPERMILPSmi, TB_ALIGN_16 },
520 { X86::VPSHUFDri, X86::VPSHUFDmi, TB_ALIGN_16 },
521 { X86::VPSHUFHWri, X86::VPSHUFHWmi, TB_ALIGN_16 },
522 { X86::VPSHUFLWri, X86::VPSHUFLWmi, TB_ALIGN_16 },
523 { X86::VRCPPSr, X86::VRCPPSm, TB_ALIGN_16 },
524 { X86::VRCPPSr_Int, X86::VRCPPSm_Int, TB_ALIGN_16 },
525 { X86::VRSQRTPSr, X86::VRSQRTPSm, TB_ALIGN_16 },
526 { X86::VRSQRTPSr_Int, X86::VRSQRTPSm_Int, TB_ALIGN_16 },
527 { X86::VSQRTPDr, X86::VSQRTPDm, TB_ALIGN_16 },
528 { X86::VSQRTPDr_Int, X86::VSQRTPDm_Int, TB_ALIGN_16 },
529 { X86::VSQRTPSr, X86::VSQRTPSm, TB_ALIGN_16 },
530 { X86::VSQRTPSr_Int, X86::VSQRTPSm_Int, TB_ALIGN_16 },
531 { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 },
532 { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 },
533 // AVX 256-bit foldable instructions
534 { X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 },
535 { X86::VMOVAPSYrr, X86::VMOVAPSYrm, TB_ALIGN_32 },
536 { X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_32 },
537 { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 },
538 { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 },
539 { X86::VPERMILPDYri, X86::VPERMILPDYmi, TB_ALIGN_32 },
540 { X86::VPERMILPSYri, X86::VPERMILPSYmi, TB_ALIGN_32 },
541 // AVX2 foldable instructions
542 { X86::VPABSBrr256, X86::VPABSBrm256, TB_ALIGN_32 },
543 { X86::VPABSDrr256, X86::VPABSDrm256, TB_ALIGN_32 },
544 { X86::VPABSWrr256, X86::VPABSWrm256, TB_ALIGN_32 },
545 { X86::VPSHUFDYri, X86::VPSHUFDYmi, TB_ALIGN_32 },
546 { X86::VPSHUFHWYri, X86::VPSHUFHWYmi, TB_ALIGN_32 },
547 { X86::VPSHUFLWYri, X86::VPSHUFLWYmi, TB_ALIGN_32 },
548 { X86::VRCPPSYr, X86::VRCPPSYm, TB_ALIGN_32 },
549 { X86::VRCPPSYr_Int, X86::VRCPPSYm_Int, TB_ALIGN_32 },
550 { X86::VRSQRTPSYr, X86::VRSQRTPSYm, TB_ALIGN_32 },
551 { X86::VRSQRTPSYr_Int, X86::VRSQRTPSYm_Int, TB_ALIGN_32 },
552 { X86::VSQRTPDYr, X86::VSQRTPDYm, TB_ALIGN_32 },
553 { X86::VSQRTPDYr_Int, X86::VSQRTPDYm_Int, TB_ALIGN_32 },
554 { X86::VSQRTPSYr, X86::VSQRTPSYm, TB_ALIGN_32 },
555 { X86::VSQRTPSYr_Int, X86::VSQRTPSYm_Int, TB_ALIGN_32 },
558 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
559 unsigned RegOp = OpTbl1[i][0];
560 unsigned MemOp = OpTbl1[i][1];
561 unsigned Flags = OpTbl1[i][2];
562 AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
564 // Index 1, folded load
565 Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
568 static const unsigned OpTbl2[][3] = {
569 { X86::ADC32rr, X86::ADC32rm, 0 },
570 { X86::ADC64rr, X86::ADC64rm, 0 },
571 { X86::ADD16rr, X86::ADD16rm, 0 },
572 { X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE },
573 { X86::ADD32rr, X86::ADD32rm, 0 },
574 { X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE },
575 { X86::ADD64rr, X86::ADD64rm, 0 },
576 { X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE },
577 { X86::ADD8rr, X86::ADD8rm, 0 },
578 { X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 },
579 { X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 },
580 { X86::ADDSDrr, X86::ADDSDrm, 0 },
581 { X86::ADDSSrr, X86::ADDSSrm, 0 },
582 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, TB_ALIGN_16 },
583 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, TB_ALIGN_16 },
584 { X86::AND16rr, X86::AND16rm, 0 },
585 { X86::AND32rr, X86::AND32rm, 0 },
586 { X86::AND64rr, X86::AND64rm, 0 },
587 { X86::AND8rr, X86::AND8rm, 0 },
588 { X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16 },
589 { X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16 },
590 { X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16 },
591 { X86::ANDPSrr, X86::ANDPSrm, TB_ALIGN_16 },
592 { X86::BLENDPDrri, X86::BLENDPDrmi, TB_ALIGN_16 },
593 { X86::BLENDPSrri, X86::BLENDPSrmi, TB_ALIGN_16 },
594 { X86::BLENDVPDrr0, X86::BLENDVPDrm0, TB_ALIGN_16 },
595 { X86::BLENDVPSrr0, X86::BLENDVPSrm0, TB_ALIGN_16 },
596 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
597 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
598 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
599 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
600 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
601 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
602 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
603 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
604 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
605 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
606 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
607 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
608 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
609 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
610 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
611 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
612 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
613 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
614 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
615 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
616 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
617 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
618 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
619 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
620 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
621 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
622 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
623 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
624 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
625 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
626 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
627 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
628 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
629 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
630 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
631 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
632 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
633 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
634 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
635 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
636 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
637 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
638 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
639 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
640 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
641 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
642 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
643 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
644 { X86::CMPPDrri, X86::CMPPDrmi, TB_ALIGN_16 },
645 { X86::CMPPSrri, X86::CMPPSrmi, TB_ALIGN_16 },
646 { X86::CMPSDrr, X86::CMPSDrm, 0 },
647 { X86::CMPSSrr, X86::CMPSSrm, 0 },
648 { X86::DIVPDrr, X86::DIVPDrm, TB_ALIGN_16 },
649 { X86::DIVPSrr, X86::DIVPSrm, TB_ALIGN_16 },
650 { X86::DIVSDrr, X86::DIVSDrm, 0 },
651 { X86::DIVSSrr, X86::DIVSSrm, 0 },
652 { X86::FsANDNPDrr, X86::FsANDNPDrm, TB_ALIGN_16 },
653 { X86::FsANDNPSrr, X86::FsANDNPSrm, TB_ALIGN_16 },
654 { X86::FsANDPDrr, X86::FsANDPDrm, TB_ALIGN_16 },
655 { X86::FsANDPSrr, X86::FsANDPSrm, TB_ALIGN_16 },
656 { X86::FsORPDrr, X86::FsORPDrm, TB_ALIGN_16 },
657 { X86::FsORPSrr, X86::FsORPSrm, TB_ALIGN_16 },
658 { X86::FsXORPDrr, X86::FsXORPDrm, TB_ALIGN_16 },
659 { X86::FsXORPSrr, X86::FsXORPSrm, TB_ALIGN_16 },
660 { X86::HADDPDrr, X86::HADDPDrm, TB_ALIGN_16 },
661 { X86::HADDPSrr, X86::HADDPSrm, TB_ALIGN_16 },
662 { X86::HSUBPDrr, X86::HSUBPDrm, TB_ALIGN_16 },
663 { X86::HSUBPSrr, X86::HSUBPSrm, TB_ALIGN_16 },
664 { X86::IMUL16rr, X86::IMUL16rm, 0 },
665 { X86::IMUL32rr, X86::IMUL32rm, 0 },
666 { X86::IMUL64rr, X86::IMUL64rm, 0 },
667 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
668 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
669 { X86::MAXPDrr, X86::MAXPDrm, TB_ALIGN_16 },
670 { X86::MAXPDrr_Int, X86::MAXPDrm_Int, TB_ALIGN_16 },
671 { X86::MAXPSrr, X86::MAXPSrm, TB_ALIGN_16 },
672 { X86::MAXPSrr_Int, X86::MAXPSrm_Int, TB_ALIGN_16 },
673 { X86::MAXSDrr, X86::MAXSDrm, 0 },
674 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 },
675 { X86::MAXSSrr, X86::MAXSSrm, 0 },
676 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 },
677 { X86::MINPDrr, X86::MINPDrm, TB_ALIGN_16 },
678 { X86::MINPDrr_Int, X86::MINPDrm_Int, TB_ALIGN_16 },
679 { X86::MINPSrr, X86::MINPSrm, TB_ALIGN_16 },
680 { X86::MINPSrr_Int, X86::MINPSrm_Int, TB_ALIGN_16 },
681 { X86::MINSDrr, X86::MINSDrm, 0 },
682 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 },
683 { X86::MINSSrr, X86::MINSSrm, 0 },
684 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 },
685 { X86::MPSADBWrri, X86::MPSADBWrmi, TB_ALIGN_16 },
686 { X86::MULPDrr, X86::MULPDrm, TB_ALIGN_16 },
687 { X86::MULPSrr, X86::MULPSrm, TB_ALIGN_16 },
688 { X86::MULSDrr, X86::MULSDrm, 0 },
689 { X86::MULSSrr, X86::MULSSrm, 0 },
690 { X86::OR16rr, X86::OR16rm, 0 },
691 { X86::OR32rr, X86::OR32rm, 0 },
692 { X86::OR64rr, X86::OR64rm, 0 },
693 { X86::OR8rr, X86::OR8rm, 0 },
694 { X86::ORPDrr, X86::ORPDrm, TB_ALIGN_16 },
695 { X86::ORPSrr, X86::ORPSrm, TB_ALIGN_16 },
696 { X86::PACKSSDWrr, X86::PACKSSDWrm, TB_ALIGN_16 },
697 { X86::PACKSSWBrr, X86::PACKSSWBrm, TB_ALIGN_16 },
698 { X86::PACKUSDWrr, X86::PACKUSDWrm, TB_ALIGN_16 },
699 { X86::PACKUSWBrr, X86::PACKUSWBrm, TB_ALIGN_16 },
700 { X86::PADDBrr, X86::PADDBrm, TB_ALIGN_16 },
701 { X86::PADDDrr, X86::PADDDrm, TB_ALIGN_16 },
702 { X86::PADDQrr, X86::PADDQrm, TB_ALIGN_16 },
703 { X86::PADDSBrr, X86::PADDSBrm, TB_ALIGN_16 },
704 { X86::PADDSWrr, X86::PADDSWrm, TB_ALIGN_16 },
705 { X86::PADDUSBrr, X86::PADDUSBrm, TB_ALIGN_16 },
706 { X86::PADDUSWrr, X86::PADDUSWrm, TB_ALIGN_16 },
707 { X86::PADDWrr, X86::PADDWrm, TB_ALIGN_16 },
708 { X86::PALIGNR128rr, X86::PALIGNR128rm, TB_ALIGN_16 },
709 { X86::PANDNrr, X86::PANDNrm, TB_ALIGN_16 },
710 { X86::PANDrr, X86::PANDrm, TB_ALIGN_16 },
711 { X86::PAVGBrr, X86::PAVGBrm, TB_ALIGN_16 },
712 { X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16 },
713 { X86::PBLENDWrri, X86::PBLENDWrmi, TB_ALIGN_16 },
714 { X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16 },
715 { X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16 },
716 { X86::PCMPEQQrr, X86::PCMPEQQrm, TB_ALIGN_16 },
717 { X86::PCMPEQWrr, X86::PCMPEQWrm, TB_ALIGN_16 },
718 { X86::PCMPGTBrr, X86::PCMPGTBrm, TB_ALIGN_16 },
719 { X86::PCMPGTDrr, X86::PCMPGTDrm, TB_ALIGN_16 },
720 { X86::PCMPGTQrr, X86::PCMPGTQrm, TB_ALIGN_16 },
721 { X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16 },
722 { X86::PHADDDrr, X86::PHADDDrm, TB_ALIGN_16 },
723 { X86::PHADDWrr, X86::PHADDWrm, TB_ALIGN_16 },
724 { X86::PHADDSWrr128, X86::PHADDSWrm128, TB_ALIGN_16 },
725 { X86::PHSUBDrr, X86::PHSUBDrm, TB_ALIGN_16 },
726 { X86::PHSUBSWrr128, X86::PHSUBSWrm128, TB_ALIGN_16 },
727 { X86::PHSUBWrr, X86::PHSUBWrm, TB_ALIGN_16 },
728 { X86::PINSRWrri, X86::PINSRWrmi, TB_ALIGN_16 },
729 { X86::PMADDUBSWrr128, X86::PMADDUBSWrm128, TB_ALIGN_16 },
730 { X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 },
731 { X86::PMAXSWrr, X86::PMAXSWrm, TB_ALIGN_16 },
732 { X86::PMAXUBrr, X86::PMAXUBrm, TB_ALIGN_16 },
733 { X86::PMINSWrr, X86::PMINSWrm, TB_ALIGN_16 },
734 { X86::PMINUBrr, X86::PMINUBrm, TB_ALIGN_16 },
735 { X86::PMULDQrr, X86::PMULDQrm, TB_ALIGN_16 },
736 { X86::PMULHRSWrr128, X86::PMULHRSWrm128, TB_ALIGN_16 },
737 { X86::PMULHUWrr, X86::PMULHUWrm, TB_ALIGN_16 },
738 { X86::PMULHWrr, X86::PMULHWrm, TB_ALIGN_16 },
739 { X86::PMULLDrr, X86::PMULLDrm, TB_ALIGN_16 },
740 { X86::PMULLWrr, X86::PMULLWrm, TB_ALIGN_16 },
741 { X86::PMULUDQrr, X86::PMULUDQrm, TB_ALIGN_16 },
742 { X86::PORrr, X86::PORrm, TB_ALIGN_16 },
743 { X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 },
744 { X86::PSHUFBrr128, X86::PSHUFBrm128, TB_ALIGN_16 },
745 { X86::PSIGNBrr128, X86::PSIGNBrm128, TB_ALIGN_16 },
746 { X86::PSIGNWrr128, X86::PSIGNWrm128, TB_ALIGN_16 },
747 { X86::PSIGNDrr128, X86::PSIGNDrm128, TB_ALIGN_16 },
748 { X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 },
749 { X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 },
750 { X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 },
751 { X86::PSRADrr, X86::PSRADrm, TB_ALIGN_16 },
752 { X86::PSRAWrr, X86::PSRAWrm, TB_ALIGN_16 },
753 { X86::PSRLDrr, X86::PSRLDrm, TB_ALIGN_16 },
754 { X86::PSRLQrr, X86::PSRLQrm, TB_ALIGN_16 },
755 { X86::PSRLWrr, X86::PSRLWrm, TB_ALIGN_16 },
756 { X86::PSUBBrr, X86::PSUBBrm, TB_ALIGN_16 },
757 { X86::PSUBDrr, X86::PSUBDrm, TB_ALIGN_16 },
758 { X86::PSUBSBrr, X86::PSUBSBrm, TB_ALIGN_16 },
759 { X86::PSUBSWrr, X86::PSUBSWrm, TB_ALIGN_16 },
760 { X86::PSUBWrr, X86::PSUBWrm, TB_ALIGN_16 },
761 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, TB_ALIGN_16 },
762 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, TB_ALIGN_16 },
763 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, TB_ALIGN_16 },
764 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, TB_ALIGN_16 },
765 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, TB_ALIGN_16 },
766 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, TB_ALIGN_16 },
767 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, TB_ALIGN_16 },
768 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, TB_ALIGN_16 },
769 { X86::PXORrr, X86::PXORrm, TB_ALIGN_16 },
770 { X86::SBB32rr, X86::SBB32rm, 0 },
771 { X86::SBB64rr, X86::SBB64rm, 0 },
772 { X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16 },
773 { X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16 },
774 { X86::SUB16rr, X86::SUB16rm, 0 },
775 { X86::SUB32rr, X86::SUB32rm, 0 },
776 { X86::SUB64rr, X86::SUB64rm, 0 },
777 { X86::SUB8rr, X86::SUB8rm, 0 },
778 { X86::SUBPDrr, X86::SUBPDrm, TB_ALIGN_16 },
779 { X86::SUBPSrr, X86::SUBPSrm, TB_ALIGN_16 },
780 { X86::SUBSDrr, X86::SUBSDrm, 0 },
781 { X86::SUBSSrr, X86::SUBSSrm, 0 },
782 // FIXME: TEST*rr -> swapped operand of TEST*mr.
783 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, TB_ALIGN_16 },
784 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, TB_ALIGN_16 },
785 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, TB_ALIGN_16 },
786 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, TB_ALIGN_16 },
787 { X86::XOR16rr, X86::XOR16rm, 0 },
788 { X86::XOR32rr, X86::XOR32rm, 0 },
789 { X86::XOR64rr, X86::XOR64rm, 0 },
790 { X86::XOR8rr, X86::XOR8rm, 0 },
791 { X86::XORPDrr, X86::XORPDrm, TB_ALIGN_16 },
792 { X86::XORPSrr, X86::XORPSrm, TB_ALIGN_16 },
793 // AVX 128-bit versions of foldable instructions
794 { X86::VCVTSD2SSrr, X86::VCVTSD2SSrm, 0 },
795 { X86::Int_VCVTSD2SSrr, X86::Int_VCVTSD2SSrm, 0 },
796 { X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 },
797 { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 },
798 { X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 },
799 { X86::Int_VCVTSI2SDrr, X86::Int_VCVTSI2SDrm, 0 },
800 { X86::VCVTSI2SS64rr, X86::VCVTSI2SS64rm, 0 },
801 { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 },
802 { X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 },
803 { X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 },
804 { X86::VCVTSS2SDrr, X86::VCVTSS2SDrm, 0 },
805 { X86::Int_VCVTSS2SDrr, X86::Int_VCVTSS2SDrm, 0 },
806 { X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 },
807 { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm, 0 },
808 { X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 },
809 { X86::Int_VCVTTSD2SIrr, X86::Int_VCVTTSD2SIrm, 0 },
810 { X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0 },
811 { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm, 0 },
812 { X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0 },
813 { X86::Int_VCVTTSS2SIrr, X86::Int_VCVTTSS2SIrm, 0 },
814 { X86::VCVTSD2SI64rr, X86::VCVTSD2SI64rm, 0 },
815 { X86::VCVTSD2SIrr, X86::VCVTSD2SIrm, 0 },
816 { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQrm, TB_ALIGN_16 },
817 { X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, TB_ALIGN_16 },
818 { X86::VRSQRTSSr, X86::VRSQRTSSm, 0 },
819 { X86::VSQRTSDr, X86::VSQRTSDm, 0 },
820 { X86::VSQRTSSr, X86::VSQRTSSm, 0 },
821 { X86::VADDPDrr, X86::VADDPDrm, TB_ALIGN_16 },
822 { X86::VADDPSrr, X86::VADDPSrm, TB_ALIGN_16 },
823 { X86::VADDSDrr, X86::VADDSDrm, 0 },
824 { X86::VADDSSrr, X86::VADDSSrm, 0 },
825 { X86::VADDSUBPDrr, X86::VADDSUBPDrm, TB_ALIGN_16 },
826 { X86::VADDSUBPSrr, X86::VADDSUBPSrm, TB_ALIGN_16 },
827 { X86::VANDNPDrr, X86::VANDNPDrm, TB_ALIGN_16 },
828 { X86::VANDNPSrr, X86::VANDNPSrm, TB_ALIGN_16 },
829 { X86::VANDPDrr, X86::VANDPDrm, TB_ALIGN_16 },
830 { X86::VANDPSrr, X86::VANDPSrm, TB_ALIGN_16 },
831 { X86::VBLENDPDrri, X86::VBLENDPDrmi, TB_ALIGN_16 },
832 { X86::VBLENDPSrri, X86::VBLENDPSrmi, TB_ALIGN_16 },
833 { X86::VBLENDVPDrr, X86::VBLENDVPDrm, TB_ALIGN_16 },
834 { X86::VBLENDVPSrr, X86::VBLENDVPSrm, TB_ALIGN_16 },
835 { X86::VCMPPDrri, X86::VCMPPDrmi, TB_ALIGN_16 },
836 { X86::VCMPPSrri, X86::VCMPPSrmi, TB_ALIGN_16 },
837 { X86::VCMPSDrr, X86::VCMPSDrm, 0 },
838 { X86::VCMPSSrr, X86::VCMPSSrm, 0 },
839 { X86::VDIVPDrr, X86::VDIVPDrm, TB_ALIGN_16 },
840 { X86::VDIVPSrr, X86::VDIVPSrm, TB_ALIGN_16 },
841 { X86::VDIVSDrr, X86::VDIVSDrm, 0 },
842 { X86::VDIVSSrr, X86::VDIVSSrm, 0 },
843 { X86::VFsANDNPDrr, X86::VFsANDNPDrm, TB_ALIGN_16 },
844 { X86::VFsANDNPSrr, X86::VFsANDNPSrm, TB_ALIGN_16 },
845 { X86::VFsANDPDrr, X86::VFsANDPDrm, TB_ALIGN_16 },
846 { X86::VFsANDPSrr, X86::VFsANDPSrm, TB_ALIGN_16 },
847 { X86::VFsORPDrr, X86::VFsORPDrm, TB_ALIGN_16 },
848 { X86::VFsORPSrr, X86::VFsORPSrm, TB_ALIGN_16 },
849 { X86::VFsXORPDrr, X86::VFsXORPDrm, TB_ALIGN_16 },
850 { X86::VFsXORPSrr, X86::VFsXORPSrm, TB_ALIGN_16 },
851 { X86::VHADDPDrr, X86::VHADDPDrm, TB_ALIGN_16 },
852 { X86::VHADDPSrr, X86::VHADDPSrm, TB_ALIGN_16 },
853 { X86::VHSUBPDrr, X86::VHSUBPDrm, TB_ALIGN_16 },
854 { X86::VHSUBPSrr, X86::VHSUBPSrm, TB_ALIGN_16 },
855 { X86::Int_VCMPSDrr, X86::Int_VCMPSDrm, 0 },
856 { X86::Int_VCMPSSrr, X86::Int_VCMPSSrm, 0 },
857 { X86::VMAXPDrr, X86::VMAXPDrm, TB_ALIGN_16 },
858 { X86::VMAXPDrr_Int, X86::VMAXPDrm_Int, TB_ALIGN_16 },
859 { X86::VMAXPSrr, X86::VMAXPSrm, TB_ALIGN_16 },
860 { X86::VMAXPSrr_Int, X86::VMAXPSrm_Int, TB_ALIGN_16 },
861 { X86::VMAXSDrr, X86::VMAXSDrm, 0 },
862 { X86::VMAXSDrr_Int, X86::VMAXSDrm_Int, 0 },
863 { X86::VMAXSSrr, X86::VMAXSSrm, 0 },
864 { X86::VMAXSSrr_Int, X86::VMAXSSrm_Int, 0 },
865 { X86::VMINPDrr, X86::VMINPDrm, TB_ALIGN_16 },
866 { X86::VMINPDrr_Int, X86::VMINPDrm_Int, TB_ALIGN_16 },
867 { X86::VMINPSrr, X86::VMINPSrm, TB_ALIGN_16 },
868 { X86::VMINPSrr_Int, X86::VMINPSrm_Int, TB_ALIGN_16 },
869 { X86::VMINSDrr, X86::VMINSDrm, 0 },
870 { X86::VMINSDrr_Int, X86::VMINSDrm_Int, 0 },
871 { X86::VMINSSrr, X86::VMINSSrm, 0 },
872 { X86::VMINSSrr_Int, X86::VMINSSrm_Int, 0 },
873 { X86::VMPSADBWrri, X86::VMPSADBWrmi, TB_ALIGN_16 },
874 { X86::VMULPDrr, X86::VMULPDrm, TB_ALIGN_16 },
875 { X86::VMULPSrr, X86::VMULPSrm, TB_ALIGN_16 },
876 { X86::VMULSDrr, X86::VMULSDrm, 0 },
877 { X86::VMULSSrr, X86::VMULSSrm, 0 },
878 { X86::VORPDrr, X86::VORPDrm, TB_ALIGN_16 },
879 { X86::VORPSrr, X86::VORPSrm, TB_ALIGN_16 },
880 { X86::VPACKSSDWrr, X86::VPACKSSDWrm, TB_ALIGN_16 },
881 { X86::VPACKSSWBrr, X86::VPACKSSWBrm, TB_ALIGN_16 },
882 { X86::VPACKUSDWrr, X86::VPACKUSDWrm, TB_ALIGN_16 },
883 { X86::VPACKUSWBrr, X86::VPACKUSWBrm, TB_ALIGN_16 },
884 { X86::VPADDBrr, X86::VPADDBrm, TB_ALIGN_16 },
885 { X86::VPADDDrr, X86::VPADDDrm, TB_ALIGN_16 },
886 { X86::VPADDQrr, X86::VPADDQrm, TB_ALIGN_16 },
887 { X86::VPADDSBrr, X86::VPADDSBrm, TB_ALIGN_16 },
888 { X86::VPADDSWrr, X86::VPADDSWrm, TB_ALIGN_16 },
889 { X86::VPADDUSBrr, X86::VPADDUSBrm, TB_ALIGN_16 },
890 { X86::VPADDUSWrr, X86::VPADDUSWrm, TB_ALIGN_16 },
891 { X86::VPADDWrr, X86::VPADDWrm, TB_ALIGN_16 },
892 { X86::VPALIGNR128rr, X86::VPALIGNR128rm, TB_ALIGN_16 },
893 { X86::VPANDNrr, X86::VPANDNrm, TB_ALIGN_16 },
894 { X86::VPANDrr, X86::VPANDrm, TB_ALIGN_16 },
895 { X86::VPAVGBrr, X86::VPAVGBrm, TB_ALIGN_16 },
896 { X86::VPAVGWrr, X86::VPAVGWrm, TB_ALIGN_16 },
897 { X86::VPBLENDWrri, X86::VPBLENDWrmi, TB_ALIGN_16 },
898 { X86::VPCMPEQBrr, X86::VPCMPEQBrm, TB_ALIGN_16 },
899 { X86::VPCMPEQDrr, X86::VPCMPEQDrm, TB_ALIGN_16 },
900 { X86::VPCMPEQQrr, X86::VPCMPEQQrm, TB_ALIGN_16 },
901 { X86::VPCMPEQWrr, X86::VPCMPEQWrm, TB_ALIGN_16 },
902 { X86::VPCMPGTBrr, X86::VPCMPGTBrm, TB_ALIGN_16 },
903 { X86::VPCMPGTDrr, X86::VPCMPGTDrm, TB_ALIGN_16 },
904 { X86::VPCMPGTQrr, X86::VPCMPGTQrm, TB_ALIGN_16 },
905 { X86::VPCMPGTWrr, X86::VPCMPGTWrm, TB_ALIGN_16 },
906 { X86::VPHADDDrr, X86::VPHADDDrm, TB_ALIGN_16 },
907 { X86::VPHADDSWrr128, X86::VPHADDSWrm128, TB_ALIGN_16 },
908 { X86::VPHADDWrr, X86::VPHADDWrm, TB_ALIGN_16 },
909 { X86::VPHSUBDrr, X86::VPHSUBDrm, TB_ALIGN_16 },
910 { X86::VPHSUBSWrr128, X86::VPHSUBSWrm128, TB_ALIGN_16 },
911 { X86::VPHSUBWrr, X86::VPHSUBWrm, TB_ALIGN_16 },
912 { X86::VPERMILPDrr, X86::VPERMILPDrm, TB_ALIGN_16 },
913 { X86::VPERMILPSrr, X86::VPERMILPSrm, TB_ALIGN_16 },
914 { X86::VPINSRWrri, X86::VPINSRWrmi, TB_ALIGN_16 },
915 { X86::VPMADDUBSWrr128, X86::VPMADDUBSWrm128, TB_ALIGN_16 },
916 { X86::VPMADDWDrr, X86::VPMADDWDrm, TB_ALIGN_16 },
917 { X86::VPMAXSWrr, X86::VPMAXSWrm, TB_ALIGN_16 },
918 { X86::VPMAXUBrr, X86::VPMAXUBrm, TB_ALIGN_16 },
919 { X86::VPMINSWrr, X86::VPMINSWrm, TB_ALIGN_16 },
920 { X86::VPMINUBrr, X86::VPMINUBrm, TB_ALIGN_16 },
921 { X86::VPMULDQrr, X86::VPMULDQrm, TB_ALIGN_16 },
922 { X86::VPMULHRSWrr128, X86::VPMULHRSWrm128, TB_ALIGN_16 },
923 { X86::VPMULHUWrr, X86::VPMULHUWrm, TB_ALIGN_16 },
924 { X86::VPMULHWrr, X86::VPMULHWrm, TB_ALIGN_16 },
925 { X86::VPMULLDrr, X86::VPMULLDrm, TB_ALIGN_16 },
926 { X86::VPMULLWrr, X86::VPMULLWrm, TB_ALIGN_16 },
927 { X86::VPMULUDQrr, X86::VPMULUDQrm, TB_ALIGN_16 },
928 { X86::VPORrr, X86::VPORrm, TB_ALIGN_16 },
929 { X86::VPSADBWrr, X86::VPSADBWrm, TB_ALIGN_16 },
930 { X86::VPSHUFBrr128, X86::VPSHUFBrm128, TB_ALIGN_16 },
931 { X86::VPSIGNBrr128, X86::VPSIGNBrm128, TB_ALIGN_16 },
932 { X86::VPSIGNWrr128, X86::VPSIGNWrm128, TB_ALIGN_16 },
933 { X86::VPSIGNDrr128, X86::VPSIGNDrm128, TB_ALIGN_16 },
934 { X86::VPSLLDrr, X86::VPSLLDrm, TB_ALIGN_16 },
935 { X86::VPSLLQrr, X86::VPSLLQrm, TB_ALIGN_16 },
936 { X86::VPSLLWrr, X86::VPSLLWrm, TB_ALIGN_16 },
937 { X86::VPSRADrr, X86::VPSRADrm, TB_ALIGN_16 },
938 { X86::VPSRAWrr, X86::VPSRAWrm, TB_ALIGN_16 },
939 { X86::VPSRLDrr, X86::VPSRLDrm, TB_ALIGN_16 },
940 { X86::VPSRLQrr, X86::VPSRLQrm, TB_ALIGN_16 },
941 { X86::VPSRLWrr, X86::VPSRLWrm, TB_ALIGN_16 },
942 { X86::VPSUBBrr, X86::VPSUBBrm, TB_ALIGN_16 },
943 { X86::VPSUBDrr, X86::VPSUBDrm, TB_ALIGN_16 },
944 { X86::VPSUBSBrr, X86::VPSUBSBrm, TB_ALIGN_16 },
945 { X86::VPSUBSWrr, X86::VPSUBSWrm, TB_ALIGN_16 },
946 { X86::VPSUBWrr, X86::VPSUBWrm, TB_ALIGN_16 },
947 { X86::VPUNPCKHBWrr, X86::VPUNPCKHBWrm, TB_ALIGN_16 },
948 { X86::VPUNPCKHDQrr, X86::VPUNPCKHDQrm, TB_ALIGN_16 },
949 { X86::VPUNPCKHQDQrr, X86::VPUNPCKHQDQrm, TB_ALIGN_16 },
950 { X86::VPUNPCKHWDrr, X86::VPUNPCKHWDrm, TB_ALIGN_16 },
951 { X86::VPUNPCKLBWrr, X86::VPUNPCKLBWrm, TB_ALIGN_16 },
952 { X86::VPUNPCKLDQrr, X86::VPUNPCKLDQrm, TB_ALIGN_16 },
953 { X86::VPUNPCKLQDQrr, X86::VPUNPCKLQDQrm, TB_ALIGN_16 },
954 { X86::VPUNPCKLWDrr, X86::VPUNPCKLWDrm, TB_ALIGN_16 },
955 { X86::VPXORrr, X86::VPXORrm, TB_ALIGN_16 },
956 { X86::VSHUFPDrri, X86::VSHUFPDrmi, TB_ALIGN_16 },
957 { X86::VSHUFPSrri, X86::VSHUFPSrmi, TB_ALIGN_16 },
958 { X86::VSUBPDrr, X86::VSUBPDrm, TB_ALIGN_16 },
959 { X86::VSUBPSrr, X86::VSUBPSrm, TB_ALIGN_16 },
960 { X86::VSUBSDrr, X86::VSUBSDrm, 0 },
961 { X86::VSUBSSrr, X86::VSUBSSrm, 0 },
962 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrm, TB_ALIGN_16 },
963 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrm, TB_ALIGN_16 },
964 { X86::VUNPCKLPDrr, X86::VUNPCKLPDrm, TB_ALIGN_16 },
965 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrm, TB_ALIGN_16 },
966 { X86::VXORPDrr, X86::VXORPDrm, TB_ALIGN_16 },
967 { X86::VXORPSrr, X86::VXORPSrm, TB_ALIGN_16 },
968 // AVX 256-bit foldable instructions
969 { X86::VADDPDYrr, X86::VADDPDYrm, TB_ALIGN_32 },
970 { X86::VADDPSYrr, X86::VADDPSYrm, TB_ALIGN_32 },
971 { X86::VADDSUBPDYrr, X86::VADDSUBPDYrm, TB_ALIGN_32 },
972 { X86::VADDSUBPSYrr, X86::VADDSUBPSYrm, TB_ALIGN_32 },
973 { X86::VANDNPDYrr, X86::VANDNPDYrm, TB_ALIGN_32 },
974 { X86::VANDNPSYrr, X86::VANDNPSYrm, TB_ALIGN_32 },
975 { X86::VANDPDYrr, X86::VANDPDYrm, TB_ALIGN_32 },
976 { X86::VANDPSYrr, X86::VANDPSYrm, TB_ALIGN_32 },
977 { X86::VBLENDPDYrri, X86::VBLENDPDYrmi, TB_ALIGN_32 },
978 { X86::VBLENDPSYrri, X86::VBLENDPSYrmi, TB_ALIGN_32 },
979 { X86::VBLENDVPDYrr, X86::VBLENDVPDYrm, TB_ALIGN_32 },
980 { X86::VBLENDVPSYrr, X86::VBLENDVPSYrm, TB_ALIGN_32 },
981 { X86::VCMPPDYrri, X86::VCMPPDYrmi, TB_ALIGN_32 },
982 { X86::VCMPPSYrri, X86::VCMPPSYrmi, TB_ALIGN_32 },
983 { X86::VDIVPDYrr, X86::VDIVPDYrm, TB_ALIGN_32 },
984 { X86::VDIVPSYrr, X86::VDIVPSYrm, TB_ALIGN_32 },
985 { X86::VHADDPDYrr, X86::VHADDPDYrm, TB_ALIGN_32 },
986 { X86::VHADDPSYrr, X86::VHADDPSYrm, TB_ALIGN_32 },
987 { X86::VHSUBPDYrr, X86::VHSUBPDYrm, TB_ALIGN_32 },
988 { X86::VHSUBPSYrr, X86::VHSUBPSYrm, TB_ALIGN_32 },
989 { X86::VINSERTF128rr, X86::VINSERTF128rm, TB_ALIGN_32 },
990 { X86::VMAXPDYrr, X86::VMAXPDYrm, TB_ALIGN_32 },
991 { X86::VMAXPDYrr_Int, X86::VMAXPDYrm_Int, TB_ALIGN_32 },
992 { X86::VMAXPSYrr, X86::VMAXPSYrm, TB_ALIGN_32 },
993 { X86::VMAXPSYrr_Int, X86::VMAXPSYrm_Int, TB_ALIGN_32 },
994 { X86::VMINPDYrr, X86::VMINPDYrm, TB_ALIGN_32 },
995 { X86::VMINPDYrr_Int, X86::VMINPDYrm_Int, TB_ALIGN_32 },
996 { X86::VMINPSYrr, X86::VMINPSYrm, TB_ALIGN_32 },
997 { X86::VMINPSYrr_Int, X86::VMINPSYrm_Int, TB_ALIGN_32 },
998 { X86::VMULPDYrr, X86::VMULPDYrm, TB_ALIGN_32 },
999 { X86::VMULPSYrr, X86::VMULPSYrm, TB_ALIGN_32 },
1000 { X86::VORPDYrr, X86::VORPDYrm, TB_ALIGN_32 },
1001 { X86::VORPSYrr, X86::VORPSYrm, TB_ALIGN_32 },
1002 { X86::VPERM2F128rr, X86::VPERM2F128rm, TB_ALIGN_32 },
1003 { X86::VPERMILPDYrr, X86::VPERMILPDYrm, TB_ALIGN_32 },
1004 { X86::VPERMILPSYrr, X86::VPERMILPSYrm, TB_ALIGN_32 },
1005 { X86::VSHUFPDYrri, X86::VSHUFPDYrmi, TB_ALIGN_32 },
1006 { X86::VSHUFPSYrri, X86::VSHUFPSYrmi, TB_ALIGN_32 },
1007 { X86::VSUBPDYrr, X86::VSUBPDYrm, TB_ALIGN_32 },
1008 { X86::VSUBPSYrr, X86::VSUBPSYrm, TB_ALIGN_32 },
1009 { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrm, TB_ALIGN_32 },
1010 { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrm, TB_ALIGN_32 },
1011 { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrm, TB_ALIGN_32 },
1012 { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrm, TB_ALIGN_32 },
1013 { X86::VXORPDYrr, X86::VXORPDYrm, TB_ALIGN_32 },
1014 { X86::VXORPSYrr, X86::VXORPSYrm, TB_ALIGN_32 },
1015 // AVX2 foldable instructions
1016 { X86::VINSERTI128rr, X86::VINSERTI128rm, TB_ALIGN_16 },
1017 { X86::VPACKSSDWYrr, X86::VPACKSSDWYrm, TB_ALIGN_32 },
1018 { X86::VPACKSSWBYrr, X86::VPACKSSWBYrm, TB_ALIGN_32 },
1019 { X86::VPACKUSDWYrr, X86::VPACKUSDWYrm, TB_ALIGN_32 },
1020 { X86::VPACKUSWBYrr, X86::VPACKUSWBYrm, TB_ALIGN_32 },
1021 { X86::VPADDBYrr, X86::VPADDBYrm, TB_ALIGN_32 },
1022 { X86::VPADDDYrr, X86::VPADDDYrm, TB_ALIGN_32 },
1023 { X86::VPADDQYrr, X86::VPADDQYrm, TB_ALIGN_32 },
1024 { X86::VPADDSBYrr, X86::VPADDSBYrm, TB_ALIGN_32 },
1025 { X86::VPADDSWYrr, X86::VPADDSWYrm, TB_ALIGN_32 },
1026 { X86::VPADDUSBYrr, X86::VPADDUSBYrm, TB_ALIGN_32 },
1027 { X86::VPADDUSWYrr, X86::VPADDUSWYrm, TB_ALIGN_32 },
1028 { X86::VPADDWYrr, X86::VPADDWYrm, TB_ALIGN_32 },
1029 { X86::VPALIGNR256rr, X86::VPALIGNR256rm, TB_ALIGN_32 },
1030 { X86::VPANDNYrr, X86::VPANDNYrm, TB_ALIGN_32 },
1031 { X86::VPANDYrr, X86::VPANDYrm, TB_ALIGN_32 },
1032 { X86::VPAVGBYrr, X86::VPAVGBYrm, TB_ALIGN_32 },
1033 { X86::VPAVGWYrr, X86::VPAVGWYrm, TB_ALIGN_32 },
1034 { X86::VPBLENDDrri, X86::VPBLENDDrmi, TB_ALIGN_32 },
1035 { X86::VPBLENDDYrri, X86::VPBLENDDYrmi, TB_ALIGN_32 },
1036 { X86::VPBLENDWYrri, X86::VPBLENDWYrmi, TB_ALIGN_32 },
1037 { X86::VPCMPEQBYrr, X86::VPCMPEQBYrm, TB_ALIGN_32 },
1038 { X86::VPCMPEQDYrr, X86::VPCMPEQDYrm, TB_ALIGN_32 },
1039 { X86::VPCMPEQQYrr, X86::VPCMPEQQYrm, TB_ALIGN_32 },
1040 { X86::VPCMPEQWYrr, X86::VPCMPEQWYrm, TB_ALIGN_32 },
1041 { X86::VPCMPGTBYrr, X86::VPCMPGTBYrm, TB_ALIGN_32 },
1042 { X86::VPCMPGTDYrr, X86::VPCMPGTDYrm, TB_ALIGN_32 },
1043 { X86::VPCMPGTQYrr, X86::VPCMPGTQYrm, TB_ALIGN_32 },
1044 { X86::VPCMPGTWYrr, X86::VPCMPGTWYrm, TB_ALIGN_32 },
1045 { X86::VPERM2I128rr, X86::VPERM2I128rm, TB_ALIGN_32 },
1046 { X86::VPERMDYrr, X86::VPERMDYrm, TB_ALIGN_32 },
1047 { X86::VPERMPDYrr, X86::VPERMPDYrm, TB_ALIGN_32 },
1048 { X86::VPERMPSYrr, X86::VPERMPSYrm, TB_ALIGN_32 },
1049 { X86::VPERMQYrr, X86::VPERMQYrm, TB_ALIGN_32 },
1050 { X86::VPHADDDYrr, X86::VPHADDDYrm, TB_ALIGN_32 },
1051 { X86::VPHADDSWrr256, X86::VPHADDSWrm256, TB_ALIGN_32 },
1052 { X86::VPHADDWYrr, X86::VPHADDWYrm, TB_ALIGN_32 },
1053 { X86::VPHSUBDYrr, X86::VPHSUBDYrm, TB_ALIGN_32 },
1054 { X86::VPHSUBSWrr256, X86::VPHSUBSWrm256, TB_ALIGN_32 },
1055 { X86::VPHSUBWYrr, X86::VPHSUBWYrm, TB_ALIGN_32 },
1056 { X86::VPMADDUBSWrr256, X86::VPMADDUBSWrm256, TB_ALIGN_32 },
1057 { X86::VPMADDWDYrr, X86::VPMADDWDYrm, TB_ALIGN_32 },
1058 { X86::VPMAXSWYrr, X86::VPMAXSWYrm, TB_ALIGN_32 },
1059 { X86::VPMAXUBYrr, X86::VPMAXUBYrm, TB_ALIGN_32 },
1060 { X86::VPMINSWYrr, X86::VPMINSWYrm, TB_ALIGN_32 },
1061 { X86::VPMINUBYrr, X86::VPMINUBYrm, TB_ALIGN_32 },
1062 { X86::VMPSADBWYrri, X86::VMPSADBWYrmi, TB_ALIGN_32 },
1063 { X86::VPMULDQYrr, X86::VPMULDQYrm, TB_ALIGN_32 },
1064 { X86::VPMULHRSWrr256, X86::VPMULHRSWrm256, TB_ALIGN_32 },
1065 { X86::VPMULHUWYrr, X86::VPMULHUWYrm, TB_ALIGN_32 },
1066 { X86::VPMULHWYrr, X86::VPMULHWYrm, TB_ALIGN_32 },
1067 { X86::VPMULLDYrr, X86::VPMULLDYrm, TB_ALIGN_32 },
1068 { X86::VPMULLWYrr, X86::VPMULLWYrm, TB_ALIGN_32 },
1069 { X86::VPMULUDQYrr, X86::VPMULUDQYrm, TB_ALIGN_32 },
1070 { X86::VPORYrr, X86::VPORYrm, TB_ALIGN_32 },
1071 { X86::VPSADBWYrr, X86::VPSADBWYrm, TB_ALIGN_32 },
1072 { X86::VPSHUFBrr256, X86::VPSHUFBrm256, TB_ALIGN_32 },
1073 { X86::VPSIGNBrr256, X86::VPSIGNBrm256, TB_ALIGN_32 },
1074 { X86::VPSIGNWrr256, X86::VPSIGNWrm256, TB_ALIGN_32 },
1075 { X86::VPSIGNDrr256, X86::VPSIGNDrm256, TB_ALIGN_32 },
1076 { X86::VPSLLDYrr, X86::VPSLLDYrm, TB_ALIGN_16 },
1077 { X86::VPSLLQYrr, X86::VPSLLQYrm, TB_ALIGN_16 },
1078 { X86::VPSLLWYrr, X86::VPSLLWYrm, TB_ALIGN_16 },
1079 { X86::VPSLLVDrr, X86::VPSLLVDrm, TB_ALIGN_16 },
1080 { X86::VPSLLVDYrr, X86::VPSLLVDYrm, TB_ALIGN_32 },
1081 { X86::VPSLLVQrr, X86::VPSLLVQrm, TB_ALIGN_16 },
1082 { X86::VPSLLVQYrr, X86::VPSLLVQYrm, TB_ALIGN_32 },
1083 { X86::VPSRADYrr, X86::VPSRADYrm, TB_ALIGN_16 },
1084 { X86::VPSRAWYrr, X86::VPSRAWYrm, TB_ALIGN_16 },
1085 { X86::VPSRAVDrr, X86::VPSRAVDrm, TB_ALIGN_16 },
1086 { X86::VPSRAVDYrr, X86::VPSRAVDYrm, TB_ALIGN_32 },
1087 { X86::VPSRLDYrr, X86::VPSRLDYrm, TB_ALIGN_16 },
1088 { X86::VPSRLQYrr, X86::VPSRLQYrm, TB_ALIGN_16 },
1089 { X86::VPSRLWYrr, X86::VPSRLWYrm, TB_ALIGN_16 },
1090 { X86::VPSRLVDrr, X86::VPSRLVDrm, TB_ALIGN_16 },
1091 { X86::VPSRLVDYrr, X86::VPSRLVDYrm, TB_ALIGN_32 },
1092 { X86::VPSRLVQrr, X86::VPSRLVQrm, TB_ALIGN_16 },
1093 { X86::VPSRLVQYrr, X86::VPSRLVQYrm, TB_ALIGN_32 },
1094 { X86::VPSUBBYrr, X86::VPSUBBYrm, TB_ALIGN_32 },
1095 { X86::VPSUBDYrr, X86::VPSUBDYrm, TB_ALIGN_32 },
1096 { X86::VPSUBSBYrr, X86::VPSUBSBYrm, TB_ALIGN_32 },
1097 { X86::VPSUBSWYrr, X86::VPSUBSWYrm, TB_ALIGN_32 },
1098 { X86::VPSUBWYrr, X86::VPSUBWYrm, TB_ALIGN_32 },
1099 { X86::VPUNPCKHBWYrr, X86::VPUNPCKHBWYrm, TB_ALIGN_32 },
1100 { X86::VPUNPCKHDQYrr, X86::VPUNPCKHDQYrm, TB_ALIGN_32 },
1101 { X86::VPUNPCKHQDQYrr, X86::VPUNPCKHQDQYrm, TB_ALIGN_16 },
1102 { X86::VPUNPCKHWDYrr, X86::VPUNPCKHWDYrm, TB_ALIGN_32 },
1103 { X86::VPUNPCKLBWYrr, X86::VPUNPCKLBWYrm, TB_ALIGN_32 },
1104 { X86::VPUNPCKLDQYrr, X86::VPUNPCKLDQYrm, TB_ALIGN_32 },
1105 { X86::VPUNPCKLQDQYrr, X86::VPUNPCKLQDQYrm, TB_ALIGN_32 },
1106 { X86::VPUNPCKLWDYrr, X86::VPUNPCKLWDYrm, TB_ALIGN_32 },
1107 { X86::VPXORYrr, X86::VPXORYrm, TB_ALIGN_32 },
1108 // FIXME: add AVX 256-bit foldable instructions
1111 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
1112 unsigned RegOp = OpTbl2[i][0];
1113 unsigned MemOp = OpTbl2[i][1];
1114 unsigned Flags = OpTbl2[i][2];
1115 AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
1117 // Index 2, folded load
1118 Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
1123 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
1124 MemOp2RegOpTableType &M2RTable,
1125 unsigned RegOp, unsigned MemOp, unsigned Flags) {
1126 if ((Flags & TB_NO_FORWARD) == 0) {
1127 assert(!R2MTable.count(RegOp) && "Duplicate entry!");
1128 R2MTable[RegOp] = std::make_pair(MemOp, Flags);
1130 if ((Flags & TB_NO_REVERSE) == 0) {
1131 assert(!M2RTable.count(MemOp) &&
1132 "Duplicated entries in unfolding maps?");
1133 M2RTable[MemOp] = std::make_pair(RegOp, Flags);
1138 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
1139 unsigned &SrcReg, unsigned &DstReg,
1140 unsigned &SubIdx) const {
1141 switch (MI.getOpcode()) {
1143 case X86::MOVSX16rr8:
1144 case X86::MOVZX16rr8:
1145 case X86::MOVSX32rr8:
1146 case X86::MOVZX32rr8:
1147 case X86::MOVSX64rr8:
1148 case X86::MOVZX64rr8:
1149 if (!TM.getSubtarget<X86Subtarget>().is64Bit())
1150 // It's not always legal to reference the low 8-bit of the larger
1151 // register in 32-bit mode.
1153 case X86::MOVSX32rr16:
1154 case X86::MOVZX32rr16:
1155 case X86::MOVSX64rr16:
1156 case X86::MOVZX64rr16:
1157 case X86::MOVSX64rr32:
1158 case X86::MOVZX64rr32: {
1159 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
1162 SrcReg = MI.getOperand(1).getReg();
1163 DstReg = MI.getOperand(0).getReg();
1164 switch (MI.getOpcode()) {
1166 llvm_unreachable(0);
1167 case X86::MOVSX16rr8:
1168 case X86::MOVZX16rr8:
1169 case X86::MOVSX32rr8:
1170 case X86::MOVZX32rr8:
1171 case X86::MOVSX64rr8:
1172 case X86::MOVZX64rr8:
1173 SubIdx = X86::sub_8bit;
1175 case X86::MOVSX32rr16:
1176 case X86::MOVZX32rr16:
1177 case X86::MOVSX64rr16:
1178 case X86::MOVZX64rr16:
1179 SubIdx = X86::sub_16bit;
1181 case X86::MOVSX64rr32:
1182 case X86::MOVZX64rr32:
1183 SubIdx = X86::sub_32bit;
1192 /// isFrameOperand - Return true and the FrameIndex if the specified
1193 /// operand and follow operands form a reference to the stack frame.
1194 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
1195 int &FrameIndex) const {
1196 if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() &&
1197 MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() &&
1198 MI->getOperand(Op+1).getImm() == 1 &&
1199 MI->getOperand(Op+2).getReg() == 0 &&
1200 MI->getOperand(Op+3).getImm() == 0) {
1201 FrameIndex = MI->getOperand(Op).getIndex();
1207 static bool isFrameLoadOpcode(int Opcode) {
1223 case X86::VMOVAPSrm:
1224 case X86::VMOVAPDrm:
1225 case X86::VMOVDQArm:
1226 case X86::VMOVAPSYrm:
1227 case X86::VMOVAPDYrm:
1228 case X86::VMOVDQAYrm:
1229 case X86::MMX_MOVD64rm:
1230 case X86::MMX_MOVQ64rm:
1235 static bool isFrameStoreOpcode(int Opcode) {
1242 case X86::ST_FpP64m:
1250 case X86::VMOVAPSmr:
1251 case X86::VMOVAPDmr:
1252 case X86::VMOVDQAmr:
1253 case X86::VMOVAPSYmr:
1254 case X86::VMOVAPDYmr:
1255 case X86::VMOVDQAYmr:
1256 case X86::MMX_MOVD64mr:
1257 case X86::MMX_MOVQ64mr:
1258 case X86::MMX_MOVNTQmr:
1264 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1265 int &FrameIndex) const {
1266 if (isFrameLoadOpcode(MI->getOpcode()))
1267 if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
1268 return MI->getOperand(0).getReg();
1272 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1273 int &FrameIndex) const {
1274 if (isFrameLoadOpcode(MI->getOpcode())) {
1276 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
1278 // Check for post-frame index elimination operations
1279 const MachineMemOperand *Dummy;
1280 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1285 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
1286 int &FrameIndex) const {
1287 if (isFrameStoreOpcode(MI->getOpcode()))
1288 if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
1289 isFrameOperand(MI, 0, FrameIndex))
1290 return MI->getOperand(X86::AddrNumOperands).getReg();
1294 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
1295 int &FrameIndex) const {
1296 if (isFrameStoreOpcode(MI->getOpcode())) {
1298 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
1300 // Check for post-frame index elimination operations
1301 const MachineMemOperand *Dummy;
1302 return hasStoreToStackSlot(MI, Dummy, FrameIndex);
1307 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by
1309 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
1310 bool isPICBase = false;
1311 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
1312 E = MRI.def_end(); I != E; ++I) {
1313 MachineInstr *DefMI = I.getOperand().getParent();
1314 if (DefMI->getOpcode() != X86::MOVPC32r)
1316 assert(!isPICBase && "More than one PIC base?");
1323 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
1324 AliasAnalysis *AA) const {
1325 switch (MI->getOpcode()) {
1340 case X86::VMOVAPSrm:
1341 case X86::VMOVUPSrm:
1342 case X86::VMOVAPDrm:
1343 case X86::VMOVDQArm:
1344 case X86::VMOVAPSYrm:
1345 case X86::VMOVUPSYrm:
1346 case X86::VMOVAPDYrm:
1347 case X86::VMOVDQAYrm:
1348 case X86::MMX_MOVD64rm:
1349 case X86::MMX_MOVQ64rm:
1350 case X86::FsVMOVAPSrm:
1351 case X86::FsVMOVAPDrm:
1352 case X86::FsMOVAPSrm:
1353 case X86::FsMOVAPDrm: {
1354 // Loads from constant pools are trivially rematerializable.
1355 if (MI->getOperand(1).isReg() &&
1356 MI->getOperand(2).isImm() &&
1357 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
1358 MI->isInvariantLoad(AA)) {
1359 unsigned BaseReg = MI->getOperand(1).getReg();
1360 if (BaseReg == 0 || BaseReg == X86::RIP)
1362 // Allow re-materialization of PIC load.
1363 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
1365 const MachineFunction &MF = *MI->getParent()->getParent();
1366 const MachineRegisterInfo &MRI = MF.getRegInfo();
1367 bool isPICBase = false;
1368 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
1369 E = MRI.def_end(); I != E; ++I) {
1370 MachineInstr *DefMI = I.getOperand().getParent();
1371 if (DefMI->getOpcode() != X86::MOVPC32r)
1373 assert(!isPICBase && "More than one PIC base?");
1383 if (MI->getOperand(2).isImm() &&
1384 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
1385 !MI->getOperand(4).isReg()) {
1386 // lea fi#, lea GV, etc. are all rematerializable.
1387 if (!MI->getOperand(1).isReg())
1389 unsigned BaseReg = MI->getOperand(1).getReg();
1392 // Allow re-materialization of lea PICBase + x.
1393 const MachineFunction &MF = *MI->getParent()->getParent();
1394 const MachineRegisterInfo &MRI = MF.getRegInfo();
1395 return regIsPICBase(BaseReg, MRI);
1401 // All other instructions marked M_REMATERIALIZABLE are always trivially
1402 // rematerializable.
1406 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
1407 /// would clobber the EFLAGS condition register. Note the result may be
1408 /// conservative. If it cannot definitely determine the safety after visiting
1409 /// a few instructions in each direction it assumes it's not safe.
1410 static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
1411 MachineBasicBlock::iterator I) {
1412 MachineBasicBlock::iterator E = MBB.end();
1414 // For compile time consideration, if we are not able to determine the
1415 // safety after visiting 4 instructions in each direction, we will assume
1417 MachineBasicBlock::iterator Iter = I;
1418 for (unsigned i = 0; Iter != E && i < 4; ++i) {
1419 bool SeenDef = false;
1420 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1421 MachineOperand &MO = Iter->getOperand(j);
1424 if (MO.getReg() == X86::EFLAGS) {
1432 // This instruction defines EFLAGS, no need to look any further.
1435 // Skip over DBG_VALUE.
1436 while (Iter != E && Iter->isDebugValue())
1440 // It is safe to clobber EFLAGS at the end of a block of no successor has it
1443 for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(),
1444 SE = MBB.succ_end(); SI != SE; ++SI)
1445 if ((*SI)->isLiveIn(X86::EFLAGS))
1450 MachineBasicBlock::iterator B = MBB.begin();
1452 for (unsigned i = 0; i < 4; ++i) {
1453 // If we make it to the beginning of the block, it's safe to clobber
1454 // EFLAGS iff EFLAGS is not live-in.
1456 return !MBB.isLiveIn(X86::EFLAGS);
1459 // Skip over DBG_VALUE.
1460 while (Iter != B && Iter->isDebugValue())
1463 bool SawKill = false;
1464 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1465 MachineOperand &MO = Iter->getOperand(j);
1466 if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
1467 if (MO.isDef()) return MO.isDead();
1468 if (MO.isKill()) SawKill = true;
1473 // This instruction kills EFLAGS and doesn't redefine it, so
1474 // there's no need to look further.
1478 // Conservative answer.
1482 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
1483 MachineBasicBlock::iterator I,
1484 unsigned DestReg, unsigned SubIdx,
1485 const MachineInstr *Orig,
1486 const TargetRegisterInfo &TRI) const {
1487 DebugLoc DL = Orig->getDebugLoc();
1489 // MOV32r0 etc. are implemented with xor which clobbers condition code.
1490 // Re-materialize them as movri instructions to avoid side effects.
1492 unsigned Opc = Orig->getOpcode();
1498 case X86::MOV64r0: {
1499 if (!isSafeToClobberEFLAGS(MBB, I)) {
1502 case X86::MOV8r0: Opc = X86::MOV8ri; break;
1503 case X86::MOV16r0: Opc = X86::MOV16ri; break;
1504 case X86::MOV32r0: Opc = X86::MOV32ri; break;
1505 case X86::MOV64r0: Opc = X86::MOV64ri64i32; break;
1514 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1517 BuildMI(MBB, I, DL, get(Opc)).addOperand(Orig->getOperand(0)).addImm(0);
1520 MachineInstr *NewMI = prior(I);
1521 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1524 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
1525 /// is not marked dead.
1526 static bool hasLiveCondCodeDef(MachineInstr *MI) {
1527 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1528 MachineOperand &MO = MI->getOperand(i);
1529 if (MO.isReg() && MO.isDef() &&
1530 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1537 /// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
1538 /// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
1539 /// to a 32-bit superregister and then truncating back down to a 16-bit
1542 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
1543 MachineFunction::iterator &MFI,
1544 MachineBasicBlock::iterator &MBBI,
1545 LiveVariables *LV) const {
1546 MachineInstr *MI = MBBI;
1547 unsigned Dest = MI->getOperand(0).getReg();
1548 unsigned Src = MI->getOperand(1).getReg();
1549 bool isDead = MI->getOperand(0).isDead();
1550 bool isKill = MI->getOperand(1).isKill();
1552 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
1553 ? X86::LEA64_32r : X86::LEA32r;
1554 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1555 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1556 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1558 // Build and insert into an implicit UNDEF value. This is OK because
1559 // well be shifting and then extracting the lower 16-bits.
1560 // This has the potential to cause partial register stall. e.g.
1561 // movw (%rbp,%rcx,2), %dx
1562 // leal -65(%rdx), %esi
1563 // But testing has shown this *does* help performance in 64-bit mode (at
1564 // least on modern x86 machines).
1565 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1566 MachineInstr *InsMI =
1567 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
1568 .addReg(leaInReg, RegState::Define, X86::sub_16bit)
1569 .addReg(Src, getKillRegState(isKill));
1571 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
1572 get(Opc), leaOutReg);
1575 llvm_unreachable(0);
1576 case X86::SHL16ri: {
1577 unsigned ShAmt = MI->getOperand(2).getImm();
1578 MIB.addReg(0).addImm(1 << ShAmt)
1579 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
1583 case X86::INC64_16r:
1584 addRegOffset(MIB, leaInReg, true, 1);
1587 case X86::DEC64_16r:
1588 addRegOffset(MIB, leaInReg, true, -1);
1592 case X86::ADD16ri_DB:
1593 case X86::ADD16ri8_DB:
1594 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
1597 case X86::ADD16rr_DB: {
1598 unsigned Src2 = MI->getOperand(2).getReg();
1599 bool isKill2 = MI->getOperand(2).isKill();
1600 unsigned leaInReg2 = 0;
1601 MachineInstr *InsMI2 = 0;
1603 // ADD16rr %reg1028<kill>, %reg1028
1604 // just a single insert_subreg.
1605 addRegReg(MIB, leaInReg, true, leaInReg, false);
1607 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1608 // Build and insert into an implicit UNDEF value. This is OK because
1609 // well be shifting and then extracting the lower 16-bits.
1610 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
1612 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
1613 .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
1614 .addReg(Src2, getKillRegState(isKill2));
1615 addRegReg(MIB, leaInReg, true, leaInReg2, true);
1617 if (LV && isKill2 && InsMI2)
1618 LV->replaceKillInstruction(Src2, MI, InsMI2);
1623 MachineInstr *NewMI = MIB;
1624 MachineInstr *ExtMI =
1625 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
1626 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1627 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
1630 // Update live variables
1631 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
1632 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
1634 LV->replaceKillInstruction(Src, MI, InsMI);
1636 LV->replaceKillInstruction(Dest, MI, ExtMI);
1642 /// convertToThreeAddress - This method must be implemented by targets that
1643 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
1644 /// may be able to convert a two-address instruction into a true
1645 /// three-address instruction on demand. This allows the X86 target (for
1646 /// example) to convert ADD and SHL instructions into LEA instructions if they
1647 /// would require register copies due to two-addressness.
1649 /// This method returns a null pointer if the transformation cannot be
1650 /// performed, otherwise it returns the new instruction.
1653 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
1654 MachineBasicBlock::iterator &MBBI,
1655 LiveVariables *LV) const {
1656 MachineInstr *MI = MBBI;
1657 MachineFunction &MF = *MI->getParent()->getParent();
1658 // All instructions input are two-addr instructions. Get the known operands.
1659 unsigned Dest = MI->getOperand(0).getReg();
1660 unsigned Src = MI->getOperand(1).getReg();
1661 bool isDead = MI->getOperand(0).isDead();
1662 bool isKill = MI->getOperand(1).isKill();
1664 MachineInstr *NewMI = NULL;
1665 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
1666 // we have better subtarget support, enable the 16-bit LEA generation here.
1667 // 16-bit LEA is also slow on Core2.
1668 bool DisableLEA16 = true;
1669 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1671 unsigned MIOpc = MI->getOpcode();
1673 case X86::SHUFPSrri: {
1674 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
1675 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1677 unsigned B = MI->getOperand(1).getReg();
1678 unsigned C = MI->getOperand(2).getReg();
1679 if (B != C) return 0;
1680 unsigned A = MI->getOperand(0).getReg();
1681 unsigned M = MI->getOperand(3).getImm();
1682 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
1683 .addReg(A, RegState::Define | getDeadRegState(isDead))
1684 .addReg(B, getKillRegState(isKill)).addImm(M);
1687 case X86::SHUFPDrri: {
1688 assert(MI->getNumOperands() == 4 && "Unknown shufpd instruction!");
1689 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1691 unsigned B = MI->getOperand(1).getReg();
1692 unsigned C = MI->getOperand(2).getReg();
1693 if (B != C) return 0;
1694 unsigned A = MI->getOperand(0).getReg();
1695 unsigned M = MI->getOperand(3).getImm();
1697 // Convert to PSHUFD mask.
1698 M = ((M & 1) << 1) | ((M & 1) << 3) | ((M & 2) << 4) | ((M & 2) << 6)| 0x44;
1700 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
1701 .addReg(A, RegState::Define | getDeadRegState(isDead))
1702 .addReg(B, getKillRegState(isKill)).addImm(M);
1705 case X86::SHL64ri: {
1706 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1707 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1708 // the flags produced by a shift yet, so this is safe.
1709 unsigned ShAmt = MI->getOperand(2).getImm();
1710 if (ShAmt == 0 || ShAmt >= 4) return 0;
1712 // LEA can't handle RSP.
1713 if (TargetRegisterInfo::isVirtualRegister(Src) &&
1714 !MF.getRegInfo().constrainRegClass(Src, &X86::GR64_NOSPRegClass))
1717 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1718 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1719 .addReg(0).addImm(1 << ShAmt)
1720 .addReg(Src, getKillRegState(isKill))
1721 .addImm(0).addReg(0);
1724 case X86::SHL32ri: {
1725 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1726 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1727 // the flags produced by a shift yet, so this is safe.
1728 unsigned ShAmt = MI->getOperand(2).getImm();
1729 if (ShAmt == 0 || ShAmt >= 4) return 0;
1731 // LEA can't handle ESP.
1732 if (TargetRegisterInfo::isVirtualRegister(Src) &&
1733 !MF.getRegInfo().constrainRegClass(Src, &X86::GR32_NOSPRegClass))
1736 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1737 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
1738 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1739 .addReg(0).addImm(1 << ShAmt)
1740 .addReg(Src, getKillRegState(isKill)).addImm(0).addReg(0);
1743 case X86::SHL16ri: {
1744 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1745 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1746 // the flags produced by a shift yet, so this is safe.
1747 unsigned ShAmt = MI->getOperand(2).getImm();
1748 if (ShAmt == 0 || ShAmt >= 4) return 0;
1751 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1752 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1753 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1754 .addReg(0).addImm(1 << ShAmt)
1755 .addReg(Src, getKillRegState(isKill))
1756 .addImm(0).addReg(0);
1760 // The following opcodes also sets the condition code register(s). Only
1761 // convert them to equivalent lea if the condition code register def's
1763 if (hasLiveCondCodeDef(MI))
1770 case X86::INC64_32r: {
1771 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1772 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
1773 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1775 // LEA can't handle RSP.
1776 if (TargetRegisterInfo::isVirtualRegister(Src) &&
1777 !MF.getRegInfo().constrainRegClass(Src,
1778 MIOpc == X86::INC64r ? X86::GR64_NOSPRegisterClass :
1779 X86::GR32_NOSPRegisterClass))
1782 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1783 .addReg(Dest, RegState::Define |
1784 getDeadRegState(isDead)),
1789 case X86::INC64_16r:
1791 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1792 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1793 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1794 .addReg(Dest, RegState::Define |
1795 getDeadRegState(isDead)),
1800 case X86::DEC64_32r: {
1801 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1802 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1803 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1804 // LEA can't handle RSP.
1805 if (TargetRegisterInfo::isVirtualRegister(Src) &&
1806 !MF.getRegInfo().constrainRegClass(Src,
1807 MIOpc == X86::DEC64r ? X86::GR64_NOSPRegisterClass :
1808 X86::GR32_NOSPRegisterClass))
1811 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1812 .addReg(Dest, RegState::Define |
1813 getDeadRegState(isDead)),
1818 case X86::DEC64_16r:
1820 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1821 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1822 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1823 .addReg(Dest, RegState::Define |
1824 getDeadRegState(isDead)),
1828 case X86::ADD64rr_DB:
1830 case X86::ADD32rr_DB: {
1831 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1833 TargetRegisterClass *RC;
1834 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB) {
1836 RC = X86::GR64_NOSPRegisterClass;
1838 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1839 RC = X86::GR32_NOSPRegisterClass;
1843 unsigned Src2 = MI->getOperand(2).getReg();
1844 bool isKill2 = MI->getOperand(2).isKill();
1846 // LEA can't handle RSP.
1847 if (TargetRegisterInfo::isVirtualRegister(Src2) &&
1848 !MF.getRegInfo().constrainRegClass(Src2, RC))
1851 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1852 .addReg(Dest, RegState::Define |
1853 getDeadRegState(isDead)),
1854 Src, isKill, Src2, isKill2);
1856 LV->replaceKillInstruction(Src2, MI, NewMI);
1860 case X86::ADD16rr_DB: {
1862 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1863 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1864 unsigned Src2 = MI->getOperand(2).getReg();
1865 bool isKill2 = MI->getOperand(2).isKill();
1866 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1867 .addReg(Dest, RegState::Define |
1868 getDeadRegState(isDead)),
1869 Src, isKill, Src2, isKill2);
1871 LV->replaceKillInstruction(Src2, MI, NewMI);
1874 case X86::ADD64ri32:
1876 case X86::ADD64ri32_DB:
1877 case X86::ADD64ri8_DB:
1878 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1879 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1880 .addReg(Dest, RegState::Define |
1881 getDeadRegState(isDead)),
1882 Src, isKill, MI->getOperand(2).getImm());
1886 case X86::ADD32ri_DB:
1887 case X86::ADD32ri8_DB: {
1888 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1889 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1890 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1891 .addReg(Dest, RegState::Define |
1892 getDeadRegState(isDead)),
1893 Src, isKill, MI->getOperand(2).getImm());
1898 case X86::ADD16ri_DB:
1899 case X86::ADD16ri8_DB:
1901 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1902 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1903 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1904 .addReg(Dest, RegState::Define |
1905 getDeadRegState(isDead)),
1906 Src, isKill, MI->getOperand(2).getImm());
1912 if (!NewMI) return 0;
1914 if (LV) { // Update live variables
1916 LV->replaceKillInstruction(Src, MI, NewMI);
1918 LV->replaceKillInstruction(Dest, MI, NewMI);
1921 MFI->insert(MBBI, NewMI); // Insert the new inst
1925 /// commuteInstruction - We have a few instructions that must be hacked on to
1929 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1930 switch (MI->getOpcode()) {
1931 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1932 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1933 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1934 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1935 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1936 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1939 switch (MI->getOpcode()) {
1940 default: llvm_unreachable("Unreachable!");
1941 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1942 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1943 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1944 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1945 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1946 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1948 unsigned Amt = MI->getOperand(3).getImm();
1950 MachineFunction &MF = *MI->getParent()->getParent();
1951 MI = MF.CloneMachineInstr(MI);
1954 MI->setDesc(get(Opc));
1955 MI->getOperand(3).setImm(Size-Amt);
1956 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1958 case X86::CMOVB16rr:
1959 case X86::CMOVB32rr:
1960 case X86::CMOVB64rr:
1961 case X86::CMOVAE16rr:
1962 case X86::CMOVAE32rr:
1963 case X86::CMOVAE64rr:
1964 case X86::CMOVE16rr:
1965 case X86::CMOVE32rr:
1966 case X86::CMOVE64rr:
1967 case X86::CMOVNE16rr:
1968 case X86::CMOVNE32rr:
1969 case X86::CMOVNE64rr:
1970 case X86::CMOVBE16rr:
1971 case X86::CMOVBE32rr:
1972 case X86::CMOVBE64rr:
1973 case X86::CMOVA16rr:
1974 case X86::CMOVA32rr:
1975 case X86::CMOVA64rr:
1976 case X86::CMOVL16rr:
1977 case X86::CMOVL32rr:
1978 case X86::CMOVL64rr:
1979 case X86::CMOVGE16rr:
1980 case X86::CMOVGE32rr:
1981 case X86::CMOVGE64rr:
1982 case X86::CMOVLE16rr:
1983 case X86::CMOVLE32rr:
1984 case X86::CMOVLE64rr:
1985 case X86::CMOVG16rr:
1986 case X86::CMOVG32rr:
1987 case X86::CMOVG64rr:
1988 case X86::CMOVS16rr:
1989 case X86::CMOVS32rr:
1990 case X86::CMOVS64rr:
1991 case X86::CMOVNS16rr:
1992 case X86::CMOVNS32rr:
1993 case X86::CMOVNS64rr:
1994 case X86::CMOVP16rr:
1995 case X86::CMOVP32rr:
1996 case X86::CMOVP64rr:
1997 case X86::CMOVNP16rr:
1998 case X86::CMOVNP32rr:
1999 case X86::CMOVNP64rr:
2000 case X86::CMOVO16rr:
2001 case X86::CMOVO32rr:
2002 case X86::CMOVO64rr:
2003 case X86::CMOVNO16rr:
2004 case X86::CMOVNO32rr:
2005 case X86::CMOVNO64rr: {
2007 switch (MI->getOpcode()) {
2009 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
2010 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
2011 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
2012 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
2013 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
2014 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
2015 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
2016 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
2017 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
2018 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
2019 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
2020 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
2021 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
2022 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
2023 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
2024 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
2025 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
2026 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
2027 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
2028 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
2029 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
2030 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
2031 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
2032 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
2033 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
2034 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
2035 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
2036 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
2037 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
2038 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
2039 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
2040 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
2041 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
2042 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
2043 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
2044 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
2045 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
2046 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
2047 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
2048 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
2049 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
2050 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
2051 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
2052 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
2053 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
2054 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
2055 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
2056 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
2059 MachineFunction &MF = *MI->getParent()->getParent();
2060 MI = MF.CloneMachineInstr(MI);
2063 MI->setDesc(get(Opc));
2064 // Fallthrough intended.
2067 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
2071 static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
2073 default: return X86::COND_INVALID;
2074 case X86::JE_4: return X86::COND_E;
2075 case X86::JNE_4: return X86::COND_NE;
2076 case X86::JL_4: return X86::COND_L;
2077 case X86::JLE_4: return X86::COND_LE;
2078 case X86::JG_4: return X86::COND_G;
2079 case X86::JGE_4: return X86::COND_GE;
2080 case X86::JB_4: return X86::COND_B;
2081 case X86::JBE_4: return X86::COND_BE;
2082 case X86::JA_4: return X86::COND_A;
2083 case X86::JAE_4: return X86::COND_AE;
2084 case X86::JS_4: return X86::COND_S;
2085 case X86::JNS_4: return X86::COND_NS;
2086 case X86::JP_4: return X86::COND_P;
2087 case X86::JNP_4: return X86::COND_NP;
2088 case X86::JO_4: return X86::COND_O;
2089 case X86::JNO_4: return X86::COND_NO;
2093 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
2095 default: llvm_unreachable("Illegal condition code!");
2096 case X86::COND_E: return X86::JE_4;
2097 case X86::COND_NE: return X86::JNE_4;
2098 case X86::COND_L: return X86::JL_4;
2099 case X86::COND_LE: return X86::JLE_4;
2100 case X86::COND_G: return X86::JG_4;
2101 case X86::COND_GE: return X86::JGE_4;
2102 case X86::COND_B: return X86::JB_4;
2103 case X86::COND_BE: return X86::JBE_4;
2104 case X86::COND_A: return X86::JA_4;
2105 case X86::COND_AE: return X86::JAE_4;
2106 case X86::COND_S: return X86::JS_4;
2107 case X86::COND_NS: return X86::JNS_4;
2108 case X86::COND_P: return X86::JP_4;
2109 case X86::COND_NP: return X86::JNP_4;
2110 case X86::COND_O: return X86::JO_4;
2111 case X86::COND_NO: return X86::JNO_4;
2115 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
2116 /// e.g. turning COND_E to COND_NE.
2117 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2119 default: llvm_unreachable("Illegal condition code!");
2120 case X86::COND_E: return X86::COND_NE;
2121 case X86::COND_NE: return X86::COND_E;
2122 case X86::COND_L: return X86::COND_GE;
2123 case X86::COND_LE: return X86::COND_G;
2124 case X86::COND_G: return X86::COND_LE;
2125 case X86::COND_GE: return X86::COND_L;
2126 case X86::COND_B: return X86::COND_AE;
2127 case X86::COND_BE: return X86::COND_A;
2128 case X86::COND_A: return X86::COND_BE;
2129 case X86::COND_AE: return X86::COND_B;
2130 case X86::COND_S: return X86::COND_NS;
2131 case X86::COND_NS: return X86::COND_S;
2132 case X86::COND_P: return X86::COND_NP;
2133 case X86::COND_NP: return X86::COND_P;
2134 case X86::COND_O: return X86::COND_NO;
2135 case X86::COND_NO: return X86::COND_O;
2139 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
2140 if (!MI->isTerminator()) return false;
2142 // Conditional branch is a special case.
2143 if (MI->isBranch() && !MI->isBarrier())
2145 if (!MI->isPredicable())
2147 return !isPredicated(MI);
2150 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
2151 MachineBasicBlock *&TBB,
2152 MachineBasicBlock *&FBB,
2153 SmallVectorImpl<MachineOperand> &Cond,
2154 bool AllowModify) const {
2155 // Start from the bottom of the block and work up, examining the
2156 // terminator instructions.
2157 MachineBasicBlock::iterator I = MBB.end();
2158 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
2159 while (I != MBB.begin()) {
2161 if (I->isDebugValue())
2164 // Working from the bottom, when we see a non-terminator instruction, we're
2166 if (!isUnpredicatedTerminator(I))
2169 // A terminator that isn't a branch can't easily be handled by this
2174 // Handle unconditional branches.
2175 if (I->getOpcode() == X86::JMP_4) {
2179 TBB = I->getOperand(0).getMBB();
2183 // If the block has any instructions after a JMP, delete them.
2184 while (llvm::next(I) != MBB.end())
2185 llvm::next(I)->eraseFromParent();
2190 // Delete the JMP if it's equivalent to a fall-through.
2191 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
2193 I->eraseFromParent();
2195 UnCondBrIter = MBB.end();
2199 // TBB is used to indicate the unconditional destination.
2200 TBB = I->getOperand(0).getMBB();
2204 // Handle conditional branches.
2205 X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode());
2206 if (BranchCode == X86::COND_INVALID)
2207 return true; // Can't handle indirect branch.
2209 // Working from the bottom, handle the first conditional branch.
2211 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
2212 if (AllowModify && UnCondBrIter != MBB.end() &&
2213 MBB.isLayoutSuccessor(TargetBB)) {
2214 // If we can modify the code and it ends in something like:
2222 // Then we can change this to:
2229 // Which is a bit more efficient.
2230 // We conditionally jump to the fall-through block.
2231 BranchCode = GetOppositeBranchCondition(BranchCode);
2232 unsigned JNCC = GetCondBranchFromCond(BranchCode);
2233 MachineBasicBlock::iterator OldInst = I;
2235 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
2236 .addMBB(UnCondBrIter->getOperand(0).getMBB());
2237 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4))
2240 OldInst->eraseFromParent();
2241 UnCondBrIter->eraseFromParent();
2243 // Restart the analysis.
2244 UnCondBrIter = MBB.end();
2250 TBB = I->getOperand(0).getMBB();
2251 Cond.push_back(MachineOperand::CreateImm(BranchCode));
2255 // Handle subsequent conditional branches. Only handle the case where all
2256 // conditional branches branch to the same destination and their condition
2257 // opcodes fit one of the special multi-branch idioms.
2258 assert(Cond.size() == 1);
2261 // Only handle the case where all conditional branches branch to the same
2263 if (TBB != I->getOperand(0).getMBB())
2266 // If the conditions are the same, we can leave them alone.
2267 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
2268 if (OldBranchCode == BranchCode)
2271 // If they differ, see if they fit one of the known patterns. Theoretically,
2272 // we could handle more patterns here, but we shouldn't expect to see them
2273 // if instruction selection has done a reasonable job.
2274 if ((OldBranchCode == X86::COND_NP &&
2275 BranchCode == X86::COND_E) ||
2276 (OldBranchCode == X86::COND_E &&
2277 BranchCode == X86::COND_NP))
2278 BranchCode = X86::COND_NP_OR_E;
2279 else if ((OldBranchCode == X86::COND_P &&
2280 BranchCode == X86::COND_NE) ||
2281 (OldBranchCode == X86::COND_NE &&
2282 BranchCode == X86::COND_P))
2283 BranchCode = X86::COND_NE_OR_P;
2287 // Update the MachineOperand.
2288 Cond[0].setImm(BranchCode);
2294 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
2295 MachineBasicBlock::iterator I = MBB.end();
2298 while (I != MBB.begin()) {
2300 if (I->isDebugValue())
2302 if (I->getOpcode() != X86::JMP_4 &&
2303 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
2305 // Remove the branch.
2306 I->eraseFromParent();
2315 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
2316 MachineBasicBlock *FBB,
2317 const SmallVectorImpl<MachineOperand> &Cond,
2318 DebugLoc DL) const {
2319 // Shouldn't be a fall through.
2320 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
2321 assert((Cond.size() == 1 || Cond.size() == 0) &&
2322 "X86 branch conditions have one component!");
2325 // Unconditional branch?
2326 assert(!FBB && "Unconditional branch with multiple successors!");
2327 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB);
2331 // Conditional branch.
2333 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
2335 case X86::COND_NP_OR_E:
2336 // Synthesize NP_OR_E with two branches.
2337 BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB);
2339 BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB);
2342 case X86::COND_NE_OR_P:
2343 // Synthesize NE_OR_P with two branches.
2344 BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB);
2346 BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB);
2350 unsigned Opc = GetCondBranchFromCond(CC);
2351 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
2356 // Two-way Conditional branch. Insert the second branch.
2357 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB);
2363 /// isHReg - Test if the given register is a physical h register.
2364 static bool isHReg(unsigned Reg) {
2365 return X86::GR8_ABCD_HRegClass.contains(Reg);
2368 // Try and copy between VR128/VR64 and GR64 registers.
2369 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
2371 // SrcReg(VR128) -> DestReg(GR64)
2372 // SrcReg(VR64) -> DestReg(GR64)
2373 // SrcReg(GR64) -> DestReg(VR128)
2374 // SrcReg(GR64) -> DestReg(VR64)
2376 if (X86::GR64RegClass.contains(DestReg)) {
2377 if (X86::VR128RegClass.contains(SrcReg)) {
2378 // Copy from a VR128 register to a GR64 register.
2379 return HasAVX ? X86::VMOVPQIto64rr : X86::MOVPQIto64rr;
2380 } else if (X86::VR64RegClass.contains(SrcReg)) {
2381 // Copy from a VR64 register to a GR64 register.
2382 return X86::MOVSDto64rr;
2384 } else if (X86::GR64RegClass.contains(SrcReg)) {
2385 // Copy from a GR64 register to a VR128 register.
2386 if (X86::VR128RegClass.contains(DestReg))
2387 return HasAVX ? X86::VMOV64toPQIrr : X86::MOV64toPQIrr;
2388 // Copy from a GR64 register to a VR64 register.
2389 else if (X86::VR64RegClass.contains(DestReg))
2390 return X86::MOV64toSDrr;
2393 // SrcReg(FR32) -> DestReg(GR32)
2394 // SrcReg(GR32) -> DestReg(FR32)
2396 if (X86::GR32RegClass.contains(DestReg) && X86::FR32RegClass.contains(SrcReg))
2397 // Copy from a FR32 register to a GR32 register.
2398 return HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr;
2400 if (X86::FR32RegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
2401 // Copy from a GR32 register to a FR32 register.
2402 return HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr;
2407 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
2408 MachineBasicBlock::iterator MI, DebugLoc DL,
2409 unsigned DestReg, unsigned SrcReg,
2410 bool KillSrc) const {
2411 // First deal with the normal symmetric copies.
2412 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
2414 if (X86::GR64RegClass.contains(DestReg, SrcReg))
2416 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
2418 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
2420 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
2421 // Copying to or from a physical H register on x86-64 requires a NOREX
2422 // move. Otherwise use a normal move.
2423 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
2424 TM.getSubtarget<X86Subtarget>().is64Bit()) {
2425 Opc = X86::MOV8rr_NOREX;
2426 // Both operands must be encodable without an REX prefix.
2427 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
2428 "8-bit H register can not be copied outside GR8_NOREX");
2431 } else if (X86::VR128RegClass.contains(DestReg, SrcReg))
2432 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
2433 else if (X86::VR256RegClass.contains(DestReg, SrcReg))
2434 Opc = X86::VMOVAPSYrr;
2435 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
2436 Opc = X86::MMX_MOVQ64rr;
2438 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, HasAVX);
2441 BuildMI(MBB, MI, DL, get(Opc), DestReg)
2442 .addReg(SrcReg, getKillRegState(KillSrc));
2446 // Moving EFLAGS to / from another register requires a push and a pop.
2447 if (SrcReg == X86::EFLAGS) {
2448 if (X86::GR64RegClass.contains(DestReg)) {
2449 BuildMI(MBB, MI, DL, get(X86::PUSHF64));
2450 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
2452 } else if (X86::GR32RegClass.contains(DestReg)) {
2453 BuildMI(MBB, MI, DL, get(X86::PUSHF32));
2454 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
2458 if (DestReg == X86::EFLAGS) {
2459 if (X86::GR64RegClass.contains(SrcReg)) {
2460 BuildMI(MBB, MI, DL, get(X86::PUSH64r))
2461 .addReg(SrcReg, getKillRegState(KillSrc));
2462 BuildMI(MBB, MI, DL, get(X86::POPF64));
2464 } else if (X86::GR32RegClass.contains(SrcReg)) {
2465 BuildMI(MBB, MI, DL, get(X86::PUSH32r))
2466 .addReg(SrcReg, getKillRegState(KillSrc));
2467 BuildMI(MBB, MI, DL, get(X86::POPF32));
2472 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
2473 << " to " << RI.getName(DestReg) << '\n');
2474 llvm_unreachable("Cannot emit physreg copy instruction");
2477 static unsigned getLoadStoreRegOpcode(unsigned Reg,
2478 const TargetRegisterClass *RC,
2479 bool isStackAligned,
2480 const TargetMachine &TM,
2482 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
2483 switch (RC->getSize()) {
2485 llvm_unreachable("Unknown spill size");
2487 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
2488 if (TM.getSubtarget<X86Subtarget>().is64Bit())
2489 // Copying to or from a physical H register on x86-64 requires a NOREX
2490 // move. Otherwise use a normal move.
2491 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
2492 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
2493 return load ? X86::MOV8rm : X86::MOV8mr;
2495 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
2496 return load ? X86::MOV16rm : X86::MOV16mr;
2498 if (X86::GR32RegClass.hasSubClassEq(RC))
2499 return load ? X86::MOV32rm : X86::MOV32mr;
2500 if (X86::FR32RegClass.hasSubClassEq(RC))
2502 (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
2503 (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
2504 if (X86::RFP32RegClass.hasSubClassEq(RC))
2505 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
2506 llvm_unreachable("Unknown 4-byte regclass");
2508 if (X86::GR64RegClass.hasSubClassEq(RC))
2509 return load ? X86::MOV64rm : X86::MOV64mr;
2510 if (X86::FR64RegClass.hasSubClassEq(RC))
2512 (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
2513 (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
2514 if (X86::VR64RegClass.hasSubClassEq(RC))
2515 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
2516 if (X86::RFP64RegClass.hasSubClassEq(RC))
2517 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
2518 llvm_unreachable("Unknown 8-byte regclass");
2520 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
2521 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
2523 assert(X86::VR128RegClass.hasSubClassEq(RC) && "Unknown 16-byte regclass");
2524 // If stack is realigned we can use aligned stores.
2527 (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
2528 (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
2531 (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
2532 (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
2535 assert(X86::VR256RegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
2536 // If stack is realigned we can use aligned stores.
2538 return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
2540 return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
2544 static unsigned getStoreRegOpcode(unsigned SrcReg,
2545 const TargetRegisterClass *RC,
2546 bool isStackAligned,
2547 TargetMachine &TM) {
2548 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, TM, false);
2552 static unsigned getLoadRegOpcode(unsigned DestReg,
2553 const TargetRegisterClass *RC,
2554 bool isStackAligned,
2555 const TargetMachine &TM) {
2556 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, TM, true);
2559 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
2560 MachineBasicBlock::iterator MI,
2561 unsigned SrcReg, bool isKill, int FrameIdx,
2562 const TargetRegisterClass *RC,
2563 const TargetRegisterInfo *TRI) const {
2564 const MachineFunction &MF = *MBB.getParent();
2565 assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
2566 "Stack slot too small for store");
2567 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2568 bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) ||
2569 RI.canRealignStack(MF);
2570 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2571 DebugLoc DL = MBB.findDebugLoc(MI);
2572 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
2573 .addReg(SrcReg, getKillRegState(isKill));
2576 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
2578 SmallVectorImpl<MachineOperand> &Addr,
2579 const TargetRegisterClass *RC,
2580 MachineInstr::mmo_iterator MMOBegin,
2581 MachineInstr::mmo_iterator MMOEnd,
2582 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2583 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2584 bool isAligned = MMOBegin != MMOEnd &&
2585 (*MMOBegin)->getAlignment() >= Alignment;
2586 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2588 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
2589 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2590 MIB.addOperand(Addr[i]);
2591 MIB.addReg(SrcReg, getKillRegState(isKill));
2592 (*MIB).setMemRefs(MMOBegin, MMOEnd);
2593 NewMIs.push_back(MIB);
2597 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
2598 MachineBasicBlock::iterator MI,
2599 unsigned DestReg, int FrameIdx,
2600 const TargetRegisterClass *RC,
2601 const TargetRegisterInfo *TRI) const {
2602 const MachineFunction &MF = *MBB.getParent();
2603 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2604 bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) ||
2605 RI.canRealignStack(MF);
2606 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2607 DebugLoc DL = MBB.findDebugLoc(MI);
2608 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
2611 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
2612 SmallVectorImpl<MachineOperand> &Addr,
2613 const TargetRegisterClass *RC,
2614 MachineInstr::mmo_iterator MMOBegin,
2615 MachineInstr::mmo_iterator MMOEnd,
2616 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2617 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2618 bool isAligned = MMOBegin != MMOEnd &&
2619 (*MMOBegin)->getAlignment() >= Alignment;
2620 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2622 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
2623 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2624 MIB.addOperand(Addr[i]);
2625 (*MIB).setMemRefs(MMOBegin, MMOEnd);
2626 NewMIs.push_back(MIB);
2629 /// Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr
2630 /// instruction with two undef reads of the register being defined. This is
2631 /// used for mapping:
2634 /// %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
2636 static bool Expand2AddrUndef(MachineInstr *MI, const MCInstrDesc &Desc) {
2637 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
2638 unsigned Reg = MI->getOperand(0).getReg();
2641 // MachineInstr::addOperand() will insert explicit operands before any
2642 // implicit operands.
2643 MachineInstrBuilder(MI).addReg(Reg, RegState::Undef)
2644 .addReg(Reg, RegState::Undef);
2645 // But we don't trust that.
2646 assert(MI->getOperand(1).getReg() == Reg &&
2647 MI->getOperand(2).getReg() == Reg && "Misplaced operand");
2651 bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
2652 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
2653 switch (MI->getOpcode()) {
2657 return Expand2AddrUndef(MI, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
2658 case X86::TEST8ri_NOREX:
2659 MI->setDesc(get(X86::TEST8ri));
2666 X86InstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
2667 int FrameIx, uint64_t Offset,
2668 const MDNode *MDPtr,
2669 DebugLoc DL) const {
2671 AM.BaseType = X86AddressMode::FrameIndexBase;
2672 AM.Base.FrameIndex = FrameIx;
2673 MachineInstrBuilder MIB = BuildMI(MF, DL, get(X86::DBG_VALUE));
2674 addFullAddress(MIB, AM).addImm(Offset).addMetadata(MDPtr);
2678 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
2679 const SmallVectorImpl<MachineOperand> &MOs,
2681 const TargetInstrInfo &TII) {
2682 // Create the base instruction with the memory operand as the first part.
2683 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2684 MI->getDebugLoc(), true);
2685 MachineInstrBuilder MIB(NewMI);
2686 unsigned NumAddrOps = MOs.size();
2687 for (unsigned i = 0; i != NumAddrOps; ++i)
2688 MIB.addOperand(MOs[i]);
2689 if (NumAddrOps < 4) // FrameIndex only
2692 // Loop over the rest of the ri operands, converting them over.
2693 unsigned NumOps = MI->getDesc().getNumOperands()-2;
2694 for (unsigned i = 0; i != NumOps; ++i) {
2695 MachineOperand &MO = MI->getOperand(i+2);
2698 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
2699 MachineOperand &MO = MI->getOperand(i);
2705 static MachineInstr *FuseInst(MachineFunction &MF,
2706 unsigned Opcode, unsigned OpNo,
2707 const SmallVectorImpl<MachineOperand> &MOs,
2708 MachineInstr *MI, const TargetInstrInfo &TII) {
2709 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2710 MI->getDebugLoc(), true);
2711 MachineInstrBuilder MIB(NewMI);
2713 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2714 MachineOperand &MO = MI->getOperand(i);
2716 assert(MO.isReg() && "Expected to fold into reg operand!");
2717 unsigned NumAddrOps = MOs.size();
2718 for (unsigned i = 0; i != NumAddrOps; ++i)
2719 MIB.addOperand(MOs[i]);
2720 if (NumAddrOps < 4) // FrameIndex only
2729 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
2730 const SmallVectorImpl<MachineOperand> &MOs,
2732 MachineFunction &MF = *MI->getParent()->getParent();
2733 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
2735 unsigned NumAddrOps = MOs.size();
2736 for (unsigned i = 0; i != NumAddrOps; ++i)
2737 MIB.addOperand(MOs[i]);
2738 if (NumAddrOps < 4) // FrameIndex only
2740 return MIB.addImm(0);
2744 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2745 MachineInstr *MI, unsigned i,
2746 const SmallVectorImpl<MachineOperand> &MOs,
2747 unsigned Size, unsigned Align) const {
2748 const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
2749 bool isTwoAddrFold = false;
2750 unsigned NumOps = MI->getDesc().getNumOperands();
2751 bool isTwoAddr = NumOps > 1 &&
2752 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
2754 // FIXME: AsmPrinter doesn't know how to handle
2755 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
2756 if (MI->getOpcode() == X86::ADD32ri &&
2757 MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
2760 MachineInstr *NewMI = NULL;
2761 // Folding a memory location into the two-address part of a two-address
2762 // instruction is different than folding it other places. It requires
2763 // replacing the *two* registers with the memory location.
2764 if (isTwoAddr && NumOps >= 2 && i < 2 &&
2765 MI->getOperand(0).isReg() &&
2766 MI->getOperand(1).isReg() &&
2767 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
2768 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2769 isTwoAddrFold = true;
2770 } else if (i == 0) { // If operand 0
2771 if (MI->getOpcode() == X86::MOV64r0)
2772 NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI);
2773 else if (MI->getOpcode() == X86::MOV32r0)
2774 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
2775 else if (MI->getOpcode() == X86::MOV16r0)
2776 NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
2777 else if (MI->getOpcode() == X86::MOV8r0)
2778 NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
2782 OpcodeTablePtr = &RegOp2MemOpTable0;
2783 } else if (i == 1) {
2784 OpcodeTablePtr = &RegOp2MemOpTable1;
2785 } else if (i == 2) {
2786 OpcodeTablePtr = &RegOp2MemOpTable2;
2789 // If table selected...
2790 if (OpcodeTablePtr) {
2791 // Find the Opcode to fuse
2792 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
2793 OpcodeTablePtr->find(MI->getOpcode());
2794 if (I != OpcodeTablePtr->end()) {
2795 unsigned Opcode = I->second.first;
2796 unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
2797 if (Align < MinAlign)
2799 bool NarrowToMOV32rm = false;
2801 unsigned RCSize = getRegClass(MI->getDesc(), i, &RI)->getSize();
2802 if (Size < RCSize) {
2803 // Check if it's safe to fold the load. If the size of the object is
2804 // narrower than the load width, then it's not.
2805 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
2807 // If this is a 64-bit load, but the spill slot is 32, then we can do
2808 // a 32-bit load which is implicitly zero-extended. This likely is due
2809 // to liveintervalanalysis remat'ing a load from stack slot.
2810 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
2812 Opcode = X86::MOV32rm;
2813 NarrowToMOV32rm = true;
2818 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
2820 NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
2822 if (NarrowToMOV32rm) {
2823 // If this is the special case where we use a MOV32rm to load a 32-bit
2824 // value and zero-extend the top bits. Change the destination register
2826 unsigned DstReg = NewMI->getOperand(0).getReg();
2827 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
2828 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg,
2831 NewMI->getOperand(0).setSubReg(X86::sub_32bit);
2838 if (PrintFailedFusing && !MI->isCopy())
2839 dbgs() << "We failed to fuse operand " << i << " in " << *MI;
2843 /// hasPartialRegUpdate - Return true for all instructions that only update
2844 /// the first 32 or 64-bits of the destination register and leave the rest
2845 /// unmodified. This can be used to avoid folding loads if the instructions
2846 /// only update part of the destination register, and the non-updated part is
2847 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
2848 /// instructions breaks the partial register dependency and it can improve
2849 /// performance. e.g.:
2851 /// movss (%rdi), %xmm0
2852 /// cvtss2sd %xmm0, %xmm0
2855 /// cvtss2sd (%rdi), %xmm0
2857 /// FIXME: This should be turned into a TSFlags.
2859 static bool hasPartialRegUpdate(unsigned Opcode) {
2861 case X86::CVTSI2SSrr:
2862 case X86::CVTSI2SS64rr:
2863 case X86::CVTSI2SDrr:
2864 case X86::CVTSI2SD64rr:
2865 case X86::CVTSD2SSrr:
2866 case X86::Int_CVTSD2SSrr:
2867 case X86::CVTSS2SDrr:
2868 case X86::Int_CVTSS2SDrr:
2870 case X86::RCPSSr_Int:
2872 case X86::ROUNDSDr_Int:
2874 case X86::ROUNDSSr_Int:
2876 case X86::RSQRTSSr_Int:
2878 case X86::SQRTSSr_Int:
2879 // AVX encoded versions
2880 case X86::VCVTSD2SSrr:
2881 case X86::Int_VCVTSD2SSrr:
2882 case X86::VCVTSS2SDrr:
2883 case X86::Int_VCVTSS2SDrr:
2885 case X86::VROUNDSDr:
2886 case X86::VROUNDSDr_Int:
2887 case X86::VROUNDSSr:
2888 case X86::VROUNDSSr_Int:
2889 case X86::VRSQRTSSr:
2897 /// getPartialRegUpdateClearance - Inform the ExeDepsFix pass how many idle
2898 /// instructions we would like before a partial register update.
2899 unsigned X86InstrInfo::
2900 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
2901 const TargetRegisterInfo *TRI) const {
2902 if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
2905 // If MI is marked as reading Reg, the partial register update is wanted.
2906 const MachineOperand &MO = MI->getOperand(0);
2907 unsigned Reg = MO.getReg();
2908 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
2909 if (MO.readsReg() || MI->readsVirtualRegister(Reg))
2912 if (MI->readsRegister(Reg, TRI))
2916 // If any of the preceding 16 instructions are reading Reg, insert a
2917 // dependency breaking instruction. The magic number is based on a few
2918 // Nehalem experiments.
2923 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
2924 const TargetRegisterInfo *TRI) const {
2925 unsigned Reg = MI->getOperand(OpNum).getReg();
2926 if (X86::VR128RegClass.contains(Reg)) {
2927 // These instructions are all floating point domain, so xorps is the best
2929 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
2930 unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr;
2931 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg)
2932 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
2933 } else if (X86::VR256RegClass.contains(Reg)) {
2934 // Use vxorps to clear the full ymm register.
2935 // It wants to read and write the xmm sub-register.
2936 unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
2937 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg)
2938 .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef)
2939 .addReg(Reg, RegState::ImplicitDefine);
2942 MI->addRegisterKilled(Reg, TRI, true);
2945 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2947 const SmallVectorImpl<unsigned> &Ops,
2948 int FrameIndex) const {
2949 // Check switch flag
2950 if (NoFusing) return NULL;
2952 // Unless optimizing for size, don't fold to avoid partial
2953 // register update stalls
2954 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize) &&
2955 hasPartialRegUpdate(MI->getOpcode()))
2958 const MachineFrameInfo *MFI = MF.getFrameInfo();
2959 unsigned Size = MFI->getObjectSize(FrameIndex);
2960 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
2961 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2962 unsigned NewOpc = 0;
2963 unsigned RCSize = 0;
2964 switch (MI->getOpcode()) {
2965 default: return NULL;
2966 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
2967 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
2968 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
2969 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
2971 // Check if it's safe to fold the load. If the size of the object is
2972 // narrower than the load width, then it's not.
2975 // Change to CMPXXri r, 0 first.
2976 MI->setDesc(get(NewOpc));
2977 MI->getOperand(1).ChangeToImmediate(0);
2978 } else if (Ops.size() != 1)
2981 SmallVector<MachineOperand,4> MOs;
2982 MOs.push_back(MachineOperand::CreateFI(FrameIndex));
2983 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment);
2986 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2988 const SmallVectorImpl<unsigned> &Ops,
2989 MachineInstr *LoadMI) const {
2990 // Check switch flag
2991 if (NoFusing) return NULL;
2993 // Unless optimizing for size, don't fold to avoid partial
2994 // register update stalls
2995 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize) &&
2996 hasPartialRegUpdate(MI->getOpcode()))
2999 // Determine the alignment of the load.
3000 unsigned Alignment = 0;
3001 if (LoadMI->hasOneMemOperand())
3002 Alignment = (*LoadMI->memoperands_begin())->getAlignment();
3004 switch (LoadMI->getOpcode()) {
3005 case X86::AVX_SET0PSY:
3006 case X86::AVX_SET0PDY:
3007 case X86::AVX2_SETALLONES:
3008 case X86::AVX2_SET0:
3012 case X86::V_SETALLONES:
3013 case X86::AVX_SETALLONES:
3025 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
3026 unsigned NewOpc = 0;
3027 switch (MI->getOpcode()) {
3028 default: return NULL;
3029 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
3030 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
3031 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
3032 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
3034 // Change to CMPXXri r, 0 first.
3035 MI->setDesc(get(NewOpc));
3036 MI->getOperand(1).ChangeToImmediate(0);
3037 } else if (Ops.size() != 1)
3040 // Make sure the subregisters match.
3041 // Otherwise we risk changing the size of the load.
3042 if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
3045 SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
3046 switch (LoadMI->getOpcode()) {
3048 case X86::V_SETALLONES:
3049 case X86::AVX_SET0PSY:
3050 case X86::AVX_SET0PDY:
3051 case X86::AVX_SETALLONES:
3052 case X86::AVX2_SETALLONES:
3053 case X86::AVX2_SET0:
3055 case X86::FsFLD0SS: {
3056 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
3057 // Create a constant-pool entry and operands to load from it.
3059 // Medium and large mode can't fold loads this way.
3060 if (TM.getCodeModel() != CodeModel::Small &&
3061 TM.getCodeModel() != CodeModel::Kernel)
3064 // x86-32 PIC requires a PIC base register for constant pools.
3065 unsigned PICBase = 0;
3066 if (TM.getRelocationModel() == Reloc::PIC_) {
3067 if (TM.getSubtarget<X86Subtarget>().is64Bit())
3070 // FIXME: PICBase = getGlobalBaseReg(&MF);
3071 // This doesn't work for several reasons.
3072 // 1. GlobalBaseReg may have been spilled.
3073 // 2. It may not be live at MI.
3077 // Create a constant-pool entry.
3078 MachineConstantPool &MCP = *MF.getConstantPool();
3080 unsigned Opc = LoadMI->getOpcode();
3081 if (Opc == X86::FsFLD0SS)
3082 Ty = Type::getFloatTy(MF.getFunction()->getContext());
3083 else if (Opc == X86::FsFLD0SD)
3084 Ty = Type::getDoubleTy(MF.getFunction()->getContext());
3085 else if (Opc == X86::AVX_SET0PSY || Opc == X86::AVX_SET0PDY)
3086 Ty = VectorType::get(Type::getFloatTy(MF.getFunction()->getContext()), 8);
3087 else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX2_SET0)
3088 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
3090 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
3092 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX_SETALLONES ||
3093 Opc == X86::AVX2_SETALLONES);
3094 const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
3095 Constant::getNullValue(Ty);
3096 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
3098 // Create operands to load from the constant pool entry.
3099 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
3100 MOs.push_back(MachineOperand::CreateImm(1));
3101 MOs.push_back(MachineOperand::CreateReg(0, false));
3102 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
3103 MOs.push_back(MachineOperand::CreateReg(0, false));
3107 // Folding a normal load. Just copy the load's address operands.
3108 unsigned NumOps = LoadMI->getDesc().getNumOperands();
3109 for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i)
3110 MOs.push_back(LoadMI->getOperand(i));
3114 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment);
3118 bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
3119 const SmallVectorImpl<unsigned> &Ops) const {
3120 // Check switch flag
3121 if (NoFusing) return 0;
3123 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
3124 switch (MI->getOpcode()) {
3125 default: return false;
3132 // FIXME: AsmPrinter doesn't know how to handle
3133 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
3134 if (MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
3140 if (Ops.size() != 1)
3143 unsigned OpNum = Ops[0];
3144 unsigned Opc = MI->getOpcode();
3145 unsigned NumOps = MI->getDesc().getNumOperands();
3146 bool isTwoAddr = NumOps > 1 &&
3147 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
3149 // Folding a memory location into the two-address part of a two-address
3150 // instruction is different than folding it other places. It requires
3151 // replacing the *two* registers with the memory location.
3152 const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
3153 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
3154 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
3155 } else if (OpNum == 0) { // If operand 0
3160 case X86::MOV64r0: return true;
3163 OpcodeTablePtr = &RegOp2MemOpTable0;
3164 } else if (OpNum == 1) {
3165 OpcodeTablePtr = &RegOp2MemOpTable1;
3166 } else if (OpNum == 2) {
3167 OpcodeTablePtr = &RegOp2MemOpTable2;
3170 if (OpcodeTablePtr && OpcodeTablePtr->count(Opc))
3172 return TargetInstrInfoImpl::canFoldMemoryOperand(MI, Ops);
3175 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
3176 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
3177 SmallVectorImpl<MachineInstr*> &NewMIs) const {
3178 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
3179 MemOp2RegOpTable.find(MI->getOpcode());
3180 if (I == MemOp2RegOpTable.end())
3182 unsigned Opc = I->second.first;
3183 unsigned Index = I->second.second & TB_INDEX_MASK;
3184 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
3185 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
3186 if (UnfoldLoad && !FoldedLoad)
3188 UnfoldLoad &= FoldedLoad;
3189 if (UnfoldStore && !FoldedStore)
3191 UnfoldStore &= FoldedStore;
3193 const MCInstrDesc &MCID = get(Opc);
3194 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI);
3195 if (!MI->hasOneMemOperand() &&
3196 RC == &X86::VR128RegClass &&
3197 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
3198 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
3199 // conservatively assume the address is unaligned. That's bad for
3202 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
3203 SmallVector<MachineOperand,2> BeforeOps;
3204 SmallVector<MachineOperand,2> AfterOps;
3205 SmallVector<MachineOperand,4> ImpOps;
3206 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
3207 MachineOperand &Op = MI->getOperand(i);
3208 if (i >= Index && i < Index + X86::AddrNumOperands)
3209 AddrOps.push_back(Op);
3210 else if (Op.isReg() && Op.isImplicit())
3211 ImpOps.push_back(Op);
3213 BeforeOps.push_back(Op);
3215 AfterOps.push_back(Op);
3218 // Emit the load instruction.
3220 std::pair<MachineInstr::mmo_iterator,
3221 MachineInstr::mmo_iterator> MMOs =
3222 MF.extractLoadMemRefs(MI->memoperands_begin(),
3223 MI->memoperands_end());
3224 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
3226 // Address operands cannot be marked isKill.
3227 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
3228 MachineOperand &MO = NewMIs[0]->getOperand(i);
3230 MO.setIsKill(false);
3235 // Emit the data processing instruction.
3236 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true);
3237 MachineInstrBuilder MIB(DataMI);
3240 MIB.addReg(Reg, RegState::Define);
3241 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
3242 MIB.addOperand(BeforeOps[i]);
3245 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
3246 MIB.addOperand(AfterOps[i]);
3247 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
3248 MachineOperand &MO = ImpOps[i];
3249 MIB.addReg(MO.getReg(),
3250 getDefRegState(MO.isDef()) |
3251 RegState::Implicit |
3252 getKillRegState(MO.isKill()) |
3253 getDeadRegState(MO.isDead()) |
3254 getUndefRegState(MO.isUndef()));
3256 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
3257 unsigned NewOpc = 0;
3258 switch (DataMI->getOpcode()) {
3260 case X86::CMP64ri32:
3267 MachineOperand &MO0 = DataMI->getOperand(0);
3268 MachineOperand &MO1 = DataMI->getOperand(1);
3269 if (MO1.getImm() == 0) {
3270 switch (DataMI->getOpcode()) {
3273 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
3275 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
3277 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
3278 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
3280 DataMI->setDesc(get(NewOpc));
3281 MO1.ChangeToRegister(MO0.getReg(), false);
3285 NewMIs.push_back(DataMI);
3287 // Emit the store instruction.
3289 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI);
3290 std::pair<MachineInstr::mmo_iterator,
3291 MachineInstr::mmo_iterator> MMOs =
3292 MF.extractStoreMemRefs(MI->memoperands_begin(),
3293 MI->memoperands_end());
3294 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
3301 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
3302 SmallVectorImpl<SDNode*> &NewNodes) const {
3303 if (!N->isMachineOpcode())
3306 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
3307 MemOp2RegOpTable.find(N->getMachineOpcode());
3308 if (I == MemOp2RegOpTable.end())
3310 unsigned Opc = I->second.first;
3311 unsigned Index = I->second.second & TB_INDEX_MASK;
3312 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
3313 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
3314 const MCInstrDesc &MCID = get(Opc);
3315 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI);
3316 unsigned NumDefs = MCID.NumDefs;
3317 std::vector<SDValue> AddrOps;
3318 std::vector<SDValue> BeforeOps;
3319 std::vector<SDValue> AfterOps;
3320 DebugLoc dl = N->getDebugLoc();
3321 unsigned NumOps = N->getNumOperands();
3322 for (unsigned i = 0; i != NumOps-1; ++i) {
3323 SDValue Op = N->getOperand(i);
3324 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
3325 AddrOps.push_back(Op);
3326 else if (i < Index-NumDefs)
3327 BeforeOps.push_back(Op);
3328 else if (i > Index-NumDefs)
3329 AfterOps.push_back(Op);
3331 SDValue Chain = N->getOperand(NumOps-1);
3332 AddrOps.push_back(Chain);
3334 // Emit the load instruction.
3336 MachineFunction &MF = DAG.getMachineFunction();
3338 EVT VT = *RC->vt_begin();
3339 std::pair<MachineInstr::mmo_iterator,
3340 MachineInstr::mmo_iterator> MMOs =
3341 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
3342 cast<MachineSDNode>(N)->memoperands_end());
3343 if (!(*MMOs.first) &&
3344 RC == &X86::VR128RegClass &&
3345 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
3346 // Do not introduce a slow unaligned load.
3348 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
3349 bool isAligned = (*MMOs.first) &&
3350 (*MMOs.first)->getAlignment() >= Alignment;
3351 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
3352 VT, MVT::Other, &AddrOps[0], AddrOps.size());
3353 NewNodes.push_back(Load);
3355 // Preserve memory reference information.
3356 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
3359 // Emit the data processing instruction.
3360 std::vector<EVT> VTs;
3361 const TargetRegisterClass *DstRC = 0;
3362 if (MCID.getNumDefs() > 0) {
3363 DstRC = getRegClass(MCID, 0, &RI);
3364 VTs.push_back(*DstRC->vt_begin());
3366 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
3367 EVT VT = N->getValueType(i);
3368 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
3372 BeforeOps.push_back(SDValue(Load, 0));
3373 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
3374 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, &BeforeOps[0],
3376 NewNodes.push_back(NewNode);
3378 // Emit the store instruction.
3381 AddrOps.push_back(SDValue(NewNode, 0));
3382 AddrOps.push_back(Chain);
3383 std::pair<MachineInstr::mmo_iterator,
3384 MachineInstr::mmo_iterator> MMOs =
3385 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
3386 cast<MachineSDNode>(N)->memoperands_end());
3387 if (!(*MMOs.first) &&
3388 RC == &X86::VR128RegClass &&
3389 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
3390 // Do not introduce a slow unaligned store.
3392 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
3393 bool isAligned = (*MMOs.first) &&
3394 (*MMOs.first)->getAlignment() >= Alignment;
3395 SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC,
3398 &AddrOps[0], AddrOps.size());
3399 NewNodes.push_back(Store);
3401 // Preserve memory reference information.
3402 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
3408 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
3409 bool UnfoldLoad, bool UnfoldStore,
3410 unsigned *LoadRegIndex) const {
3411 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
3412 MemOp2RegOpTable.find(Opc);
3413 if (I == MemOp2RegOpTable.end())
3415 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
3416 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
3417 if (UnfoldLoad && !FoldedLoad)
3419 if (UnfoldStore && !FoldedStore)
3422 *LoadRegIndex = I->second.second & TB_INDEX_MASK;
3423 return I->second.first;
3427 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
3428 int64_t &Offset1, int64_t &Offset2) const {
3429 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
3431 unsigned Opc1 = Load1->getMachineOpcode();
3432 unsigned Opc2 = Load2->getMachineOpcode();
3434 default: return false;
3444 case X86::MMX_MOVD64rm:
3445 case X86::MMX_MOVQ64rm:
3446 case X86::FsMOVAPSrm:
3447 case X86::FsMOVAPDrm:
3453 // AVX load instructions
3456 case X86::FsVMOVAPSrm:
3457 case X86::FsVMOVAPDrm:
3458 case X86::VMOVAPSrm:
3459 case X86::VMOVUPSrm:
3460 case X86::VMOVAPDrm:
3461 case X86::VMOVDQArm:
3462 case X86::VMOVDQUrm:
3463 case X86::VMOVAPSYrm:
3464 case X86::VMOVUPSYrm:
3465 case X86::VMOVAPDYrm:
3466 case X86::VMOVDQAYrm:
3467 case X86::VMOVDQUYrm:
3471 default: return false;
3481 case X86::MMX_MOVD64rm:
3482 case X86::MMX_MOVQ64rm:
3483 case X86::FsMOVAPSrm:
3484 case X86::FsMOVAPDrm:
3490 // AVX load instructions
3493 case X86::FsVMOVAPSrm:
3494 case X86::FsVMOVAPDrm:
3495 case X86::VMOVAPSrm:
3496 case X86::VMOVUPSrm:
3497 case X86::VMOVAPDrm:
3498 case X86::VMOVDQArm:
3499 case X86::VMOVDQUrm:
3500 case X86::VMOVAPSYrm:
3501 case X86::VMOVUPSYrm:
3502 case X86::VMOVAPDYrm:
3503 case X86::VMOVDQAYrm:
3504 case X86::VMOVDQUYrm:
3508 // Check if chain operands and base addresses match.
3509 if (Load1->getOperand(0) != Load2->getOperand(0) ||
3510 Load1->getOperand(5) != Load2->getOperand(5))
3512 // Segment operands should match as well.
3513 if (Load1->getOperand(4) != Load2->getOperand(4))
3515 // Scale should be 1, Index should be Reg0.
3516 if (Load1->getOperand(1) == Load2->getOperand(1) &&
3517 Load1->getOperand(2) == Load2->getOperand(2)) {
3518 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
3521 // Now let's examine the displacements.
3522 if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
3523 isa<ConstantSDNode>(Load2->getOperand(3))) {
3524 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
3525 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
3532 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
3533 int64_t Offset1, int64_t Offset2,
3534 unsigned NumLoads) const {
3535 assert(Offset2 > Offset1);
3536 if ((Offset2 - Offset1) / 8 > 64)
3539 unsigned Opc1 = Load1->getMachineOpcode();
3540 unsigned Opc2 = Load2->getMachineOpcode();
3542 return false; // FIXME: overly conservative?
3549 case X86::MMX_MOVD64rm:
3550 case X86::MMX_MOVQ64rm:
3554 EVT VT = Load1->getValueType(0);
3555 switch (VT.getSimpleVT().SimpleTy) {
3557 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
3558 // have 16 of them to play with.
3559 if (TM.getSubtargetImpl()->is64Bit()) {
3562 } else if (NumLoads) {
3582 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
3583 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
3584 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
3585 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
3587 Cond[0].setImm(GetOppositeBranchCondition(CC));
3592 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
3593 // FIXME: Return false for x87 stack register classes for now. We can't
3594 // allow any loads of these registers before FpGet_ST0_80.
3595 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
3596 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
3599 /// getGlobalBaseReg - Return a virtual register initialized with the
3600 /// the global base register value. Output instructions required to
3601 /// initialize the register in the function entry block, if necessary.
3603 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
3605 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
3606 assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
3607 "X86-64 PIC uses RIP relative addressing");
3609 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
3610 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
3611 if (GlobalBaseReg != 0)
3612 return GlobalBaseReg;
3614 // Create the register. The code to initialize it is inserted
3615 // later, by the CGBR pass (below).
3616 MachineRegisterInfo &RegInfo = MF->getRegInfo();
3617 GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3618 X86FI->setGlobalBaseReg(GlobalBaseReg);
3619 return GlobalBaseReg;
3622 // These are the replaceable SSE instructions. Some of these have Int variants
3623 // that we don't include here. We don't want to replace instructions selected
3625 static const unsigned ReplaceableInstrs[][3] = {
3626 //PackedSingle PackedDouble PackedInt
3627 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
3628 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
3629 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
3630 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
3631 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
3632 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
3633 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
3634 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
3635 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
3636 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
3637 { X86::ORPSrm, X86::ORPDrm, X86::PORrm },
3638 { X86::ORPSrr, X86::ORPDrr, X86::PORrr },
3639 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
3640 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
3641 // AVX 128-bit support
3642 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr },
3643 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm },
3644 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr },
3645 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr },
3646 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm },
3647 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
3648 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm },
3649 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr },
3650 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm },
3651 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr },
3652 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm },
3653 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr },
3654 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm },
3655 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr },
3656 // AVX 256-bit support
3657 { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr },
3658 { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm },
3659 { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr },
3660 { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr },
3661 { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm },
3662 { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr }
3665 static const unsigned ReplaceableInstrsAVX2[][3] = {
3666 //PackedSingle PackedDouble PackedInt
3667 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm },
3668 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr },
3669 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm },
3670 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr },
3671 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm },
3672 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr },
3673 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm },
3674 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr },
3675 { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
3676 { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
3677 { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm },
3678 { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr },
3679 { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm },
3680 { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr }
3683 // FIXME: Some shuffle and unpack instructions have equivalents in different
3684 // domains, but they require a bit more work than just switching opcodes.
3686 static const unsigned *lookup(unsigned opcode, unsigned domain) {
3687 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
3688 if (ReplaceableInstrs[i][domain-1] == opcode)
3689 return ReplaceableInstrs[i];
3693 static const unsigned *lookupAVX2(unsigned opcode, unsigned domain) {
3694 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrsAVX2); i != e; ++i)
3695 if (ReplaceableInstrsAVX2[i][domain-1] == opcode)
3696 return ReplaceableInstrsAVX2[i];
3700 std::pair<uint16_t, uint16_t>
3701 X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const {
3702 uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
3703 bool hasAVX2 = TM.getSubtarget<X86Subtarget>().hasAVX2();
3704 uint16_t validDomains = 0;
3705 if (domain && lookup(MI->getOpcode(), domain))
3707 else if (domain && lookupAVX2(MI->getOpcode(), domain))
3708 validDomains = hasAVX2 ? 0xe : 0x6;
3709 return std::make_pair(domain, validDomains);
3712 void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
3713 assert(Domain>0 && Domain<4 && "Invalid execution domain");
3714 uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
3715 assert(dom && "Not an SSE instruction");
3716 const unsigned *table = lookup(MI->getOpcode(), dom);
3717 if (!table) { // try the other table
3718 assert((TM.getSubtarget<X86Subtarget>().hasAVX2() || Domain < 3) &&
3719 "256-bit vector operations only available in AVX2");
3720 table = lookupAVX2(MI->getOpcode(), dom);
3722 assert(table && "Cannot change domain");
3723 MI->setDesc(get(table[Domain-1]));
3726 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
3727 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
3728 NopInst.setOpcode(X86::NOOP);
3731 bool X86InstrInfo::isHighLatencyDef(int opc) const {
3733 default: return false;
3735 case X86::DIVSDrm_Int:
3737 case X86::DIVSDrr_Int:
3739 case X86::DIVSSrm_Int:
3741 case X86::DIVSSrr_Int:
3743 case X86::SQRTPDm_Int:
3745 case X86::SQRTPDr_Int:
3747 case X86::SQRTPSm_Int:
3749 case X86::SQRTPSr_Int:
3751 case X86::SQRTSDm_Int:
3753 case X86::SQRTSDr_Int:
3755 case X86::SQRTSSm_Int:
3757 case X86::SQRTSSr_Int:
3758 // AVX instructions with high latency
3760 case X86::VDIVSDrm_Int:
3762 case X86::VDIVSDrr_Int:
3764 case X86::VDIVSSrm_Int:
3766 case X86::VDIVSSrr_Int:
3768 case X86::VSQRTPDm_Int:
3770 case X86::VSQRTPDr_Int:
3772 case X86::VSQRTPSm_Int:
3774 case X86::VSQRTPSr_Int:
3776 case X86::VSQRTSDm_Int:
3779 case X86::VSQRTSSm_Int:
3786 hasHighOperandLatency(const InstrItineraryData *ItinData,
3787 const MachineRegisterInfo *MRI,
3788 const MachineInstr *DefMI, unsigned DefIdx,
3789 const MachineInstr *UseMI, unsigned UseIdx) const {
3790 return isHighLatencyDef(DefMI->getOpcode());
3794 /// CGBR - Create Global Base Reg pass. This initializes the PIC
3795 /// global base register for x86-32.
3796 struct CGBR : public MachineFunctionPass {
3798 CGBR() : MachineFunctionPass(ID) {}
3800 virtual bool runOnMachineFunction(MachineFunction &MF) {
3801 const X86TargetMachine *TM =
3802 static_cast<const X86TargetMachine *>(&MF.getTarget());
3804 assert(!TM->getSubtarget<X86Subtarget>().is64Bit() &&
3805 "X86-64 PIC uses RIP relative addressing");
3807 // Only emit a global base reg in PIC mode.
3808 if (TM->getRelocationModel() != Reloc::PIC_)
3811 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
3812 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
3814 // If we didn't need a GlobalBaseReg, don't insert code.
3815 if (GlobalBaseReg == 0)
3818 // Insert the set of GlobalBaseReg into the first MBB of the function
3819 MachineBasicBlock &FirstMBB = MF.front();
3820 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
3821 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
3822 MachineRegisterInfo &RegInfo = MF.getRegInfo();
3823 const X86InstrInfo *TII = TM->getInstrInfo();
3826 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT())
3827 PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3831 // Operand of MovePCtoStack is completely ignored by asm printer. It's
3832 // only used in JIT code emission as displacement to pc.
3833 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
3835 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
3836 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
3837 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) {
3838 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
3839 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
3840 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
3841 X86II::MO_GOT_ABSOLUTE_ADDRESS);
3847 virtual const char *getPassName() const {
3848 return "X86 PIC Global Base Reg Initialization";
3851 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
3852 AU.setPreservesCFG();
3853 MachineFunctionPass::getAnalysisUsage(AU);
3860 llvm::createGlobalBaseRegPass() { return new CGBR(); }
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