lib/Target/X86/X86InstrInfo.cpp

   1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the X86 implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "X86InstrInfo.h"
  15 #include "X86.h"
  16 #include "X86InstrBuilder.h"
  17 #include "X86MachineFunctionInfo.h"
  18 #include "X86Subtarget.h"
  19 #include "X86TargetMachine.h"
  20 #include "llvm/ADT/STLExtras.h"
  21 #include "llvm/CodeGen/LiveVariables.h"
  22 #include "llvm/CodeGen/MachineConstantPool.h"
  23 #include "llvm/CodeGen/MachineDominators.h"
  24 #include "llvm/CodeGen/MachineFrameInfo.h"
  25 #include "llvm/CodeGen/MachineInstrBuilder.h"
  26 #include "llvm/CodeGen/MachineModuleInfo.h"
  27 #include "llvm/CodeGen/MachineRegisterInfo.h"
  28 #include "llvm/CodeGen/StackMaps.h"
  29 #include "llvm/IR/DerivedTypes.h"
  30 #include "llvm/IR/Function.h"
  31 #include "llvm/IR/LLVMContext.h"
  32 #include "llvm/MC/MCAsmInfo.h"
  33 #include "llvm/MC/MCExpr.h"
  34 #include "llvm/MC/MCInst.h"
  35 #include "llvm/Support/CommandLine.h"
  36 #include "llvm/Support/Debug.h"
  37 #include "llvm/Support/ErrorHandling.h"
  38 #include "llvm/Support/raw_ostream.h"
  39 #include "llvm/Target/TargetOptions.h"
  40 #include <limits>
  41
  42 using namespace llvm;
  43
  44 #define DEBUG_TYPE "x86-instr-info"
  45
  46 #define GET_INSTRINFO_CTOR_DTOR
  47 #include "X86GenInstrInfo.inc"
  48
  49 static cl::opt<bool>
  50 NoFusing("disable-spill-fusing",
  51          cl::desc("Disable fusing of spill code into instructions"));
  52 static cl::opt<bool>
  53 PrintFailedFusing("print-failed-fuse-candidates",
  54                   cl::desc("Print instructions that the allocator wants to"
  55                            " fuse, but the X86 backend currently can't"),
  56                   cl::Hidden);
  57 static cl::opt<bool>
  58 ReMatPICStubLoad("remat-pic-stub-load",
  59                  cl::desc("Re-materialize load from stub in PIC mode"),
  60                  cl::init(false), cl::Hidden);
  61
  62 enum {
  63   // Select which memory operand is being unfolded.
  64   // (stored in bits 0 - 3)
  65   TB_INDEX_0    = 0,
  66   TB_INDEX_1    = 1,
  67   TB_INDEX_2    = 2,
  68   TB_INDEX_3    = 3,
  69   TB_INDEX_4    = 4,
  70   TB_INDEX_MASK = 0xf,
  71
  72   // Do not insert the reverse map (MemOp -> RegOp) into the table.
  73   // This may be needed because there is a many -> one mapping.
  74   TB_NO_REVERSE   = 1 << 4,
  75
  76   // Do not insert the forward map (RegOp -> MemOp) into the table.
  77   // This is needed for Native Client, which prohibits branch
  78   // instructions from using a memory operand.
  79   TB_NO_FORWARD   = 1 << 5,
  80
  81   TB_FOLDED_LOAD  = 1 << 6,
  82   TB_FOLDED_STORE = 1 << 7,
  83
  84   // Minimum alignment required for load/store.
  85   // Used for RegOp->MemOp conversion.
  86   // (stored in bits 8 - 15)
  87   TB_ALIGN_SHIFT = 8,
  88   TB_ALIGN_NONE  =    0 << TB_ALIGN_SHIFT,
  89   TB_ALIGN_16    =   16 << TB_ALIGN_SHIFT,
  90   TB_ALIGN_32    =   32 << TB_ALIGN_SHIFT,
  91   TB_ALIGN_64    =   64 << TB_ALIGN_SHIFT,
  92   TB_ALIGN_MASK  = 0xff << TB_ALIGN_SHIFT
  93 };
  94
  95 struct X86MemoryFoldTableEntry {
  96   uint16_t RegOp;
  97   uint16_t MemOp;
  98   uint16_t Flags;
  99 };
 100
 101 // Pin the vtable to this file.
 102 void X86InstrInfo::anchor() {}
 103
 104 X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
 105     : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
 106                                                : X86::ADJCALLSTACKDOWN32),
 107                       (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
 108                                                : X86::ADJCALLSTACKUP32),
 109                       X86::CATCHRET),
 110       Subtarget(STI), RI(STI.getTargetTriple()) {
 111
 112   static const X86MemoryFoldTableEntry MemoryFoldTable2Addr[] = {
 113     { X86::ADC32ri,     X86::ADC32mi,    0 },
 114     { X86::ADC32ri8,    X86::ADC32mi8,   0 },
 115     { X86::ADC32rr,     X86::ADC32mr,    0 },
 116     { X86::ADC64ri32,   X86::ADC64mi32,  0 },
 117     { X86::ADC64ri8,    X86::ADC64mi8,   0 },
 118     { X86::ADC64rr,     X86::ADC64mr,    0 },
 119     { X86::ADD16ri,     X86::ADD16mi,    0 },
 120     { X86::ADD16ri8,    X86::ADD16mi8,   0 },
 121     { X86::ADD16ri_DB,  X86::ADD16mi,    TB_NO_REVERSE },
 122     { X86::ADD16ri8_DB, X86::ADD16mi8,   TB_NO_REVERSE },
 123     { X86::ADD16rr,     X86::ADD16mr,    0 },
 124     { X86::ADD16rr_DB,  X86::ADD16mr,    TB_NO_REVERSE },
 125     { X86::ADD32ri,     X86::ADD32mi,    0 },
 126     { X86::ADD32ri8,    X86::ADD32mi8,   0 },
 127     { X86::ADD32ri_DB,  X86::ADD32mi,    TB_NO_REVERSE },
 128     { X86::ADD32ri8_DB, X86::ADD32mi8,   TB_NO_REVERSE },
 129     { X86::ADD32rr,     X86::ADD32mr,    0 },
 130     { X86::ADD32rr_DB,  X86::ADD32mr,    TB_NO_REVERSE },
 131     { X86::ADD64ri32,   X86::ADD64mi32,  0 },
 132     { X86::ADD64ri8,    X86::ADD64mi8,   0 },
 133     { X86::ADD64ri32_DB,X86::ADD64mi32,  TB_NO_REVERSE },
 134     { X86::ADD64ri8_DB, X86::ADD64mi8,   TB_NO_REVERSE },
 135     { X86::ADD64rr,     X86::ADD64mr,    0 },
 136     { X86::ADD64rr_DB,  X86::ADD64mr,    TB_NO_REVERSE },
 137     { X86::ADD8ri,      X86::ADD8mi,     0 },
 138     { X86::ADD8rr,      X86::ADD8mr,     0 },
 139     { X86::AND16ri,     X86::AND16mi,    0 },
 140     { X86::AND16ri8,    X86::AND16mi8,   0 },
 141     { X86::AND16rr,     X86::AND16mr,    0 },
 142     { X86::AND32ri,     X86::AND32mi,    0 },
 143     { X86::AND32ri8,    X86::AND32mi8,   0 },
 144     { X86::AND32rr,     X86::AND32mr,    0 },
 145     { X86::AND64ri32,   X86::AND64mi32,  0 },
 146     { X86::AND64ri8,    X86::AND64mi8,   0 },
 147     { X86::AND64rr,     X86::AND64mr,    0 },
 148     { X86::AND8ri,      X86::AND8mi,     0 },
 149     { X86::AND8rr,      X86::AND8mr,     0 },
 150     { X86::DEC16r,      X86::DEC16m,     0 },
 151     { X86::DEC32r,      X86::DEC32m,     0 },
 152     { X86::DEC64r,      X86::DEC64m,     0 },
 153     { X86::DEC8r,       X86::DEC8m,      0 },
 154     { X86::INC16r,      X86::INC16m,     0 },
 155     { X86::INC32r,      X86::INC32m,     0 },
 156     { X86::INC64r,      X86::INC64m,     0 },
 157     { X86::INC8r,       X86::INC8m,      0 },
 158     { X86::NEG16r,      X86::NEG16m,     0 },
 159     { X86::NEG32r,      X86::NEG32m,     0 },
 160     { X86::NEG64r,      X86::NEG64m,     0 },
 161     { X86::NEG8r,       X86::NEG8m,      0 },
 162     { X86::NOT16r,      X86::NOT16m,     0 },
 163     { X86::NOT32r,      X86::NOT32m,     0 },
 164     { X86::NOT64r,      X86::NOT64m,     0 },
 165     { X86::NOT8r,       X86::NOT8m,      0 },
 166     { X86::OR16ri,      X86::OR16mi,     0 },
 167     { X86::OR16ri8,     X86::OR16mi8,    0 },
 168     { X86::OR16rr,      X86::OR16mr,     0 },
 169     { X86::OR32ri,      X86::OR32mi,     0 },
 170     { X86::OR32ri8,     X86::OR32mi8,    0 },
 171     { X86::OR32rr,      X86::OR32mr,     0 },
 172     { X86::OR64ri32,    X86::OR64mi32,   0 },
 173     { X86::OR64ri8,     X86::OR64mi8,    0 },
 174     { X86::OR64rr,      X86::OR64mr,     0 },
 175     { X86::OR8ri,       X86::OR8mi,      0 },
 176     { X86::OR8rr,       X86::OR8mr,      0 },
 177     { X86::ROL16r1,     X86::ROL16m1,    0 },
 178     { X86::ROL16rCL,    X86::ROL16mCL,   0 },
 179     { X86::ROL16ri,     X86::ROL16mi,    0 },
 180     { X86::ROL32r1,     X86::ROL32m1,    0 },
 181     { X86::ROL32rCL,    X86::ROL32mCL,   0 },
 182     { X86::ROL32ri,     X86::ROL32mi,    0 },
 183     { X86::ROL64r1,     X86::ROL64m1,    0 },
 184     { X86::ROL64rCL,    X86::ROL64mCL,   0 },
 185     { X86::ROL64ri,     X86::ROL64mi,    0 },
 186     { X86::ROL8r1,      X86::ROL8m1,     0 },
 187     { X86::ROL8rCL,     X86::ROL8mCL,    0 },
 188     { X86::ROL8ri,      X86::ROL8mi,     0 },
 189     { X86::ROR16r1,     X86::ROR16m1,    0 },
 190     { X86::ROR16rCL,    X86::ROR16mCL,   0 },
 191     { X86::ROR16ri,     X86::ROR16mi,    0 },
 192     { X86::ROR32r1,     X86::ROR32m1,    0 },
 193     { X86::ROR32rCL,    X86::ROR32mCL,   0 },
 194     { X86::ROR32ri,     X86::ROR32mi,    0 },
 195     { X86::ROR64r1,     X86::ROR64m1,    0 },
 196     { X86::ROR64rCL,    X86::ROR64mCL,   0 },
 197     { X86::ROR64ri,     X86::ROR64mi,    0 },
 198     { X86::ROR8r1,      X86::ROR8m1,     0 },
 199     { X86::ROR8rCL,     X86::ROR8mCL,    0 },
 200     { X86::ROR8ri,      X86::ROR8mi,     0 },
 201     { X86::SAR16r1,     X86::SAR16m1,    0 },
 202     { X86::SAR16rCL,    X86::SAR16mCL,   0 },
 203     { X86::SAR16ri,     X86::SAR16mi,    0 },
 204     { X86::SAR32r1,     X86::SAR32m1,    0 },
 205     { X86::SAR32rCL,    X86::SAR32mCL,   0 },
 206     { X86::SAR32ri,     X86::SAR32mi,    0 },
 207     { X86::SAR64r1,     X86::SAR64m1,    0 },
 208     { X86::SAR64rCL,    X86::SAR64mCL,   0 },
 209     { X86::SAR64ri,     X86::SAR64mi,    0 },
 210     { X86::SAR8r1,      X86::SAR8m1,     0 },
 211     { X86::SAR8rCL,     X86::SAR8mCL,    0 },
 212     { X86::SAR8ri,      X86::SAR8mi,     0 },
 213     { X86::SBB32ri,     X86::SBB32mi,    0 },
 214     { X86::SBB32ri8,    X86::SBB32mi8,   0 },
 215     { X86::SBB32rr,     X86::SBB32mr,    0 },
 216     { X86::SBB64ri32,   X86::SBB64mi32,  0 },
 217     { X86::SBB64ri8,    X86::SBB64mi8,   0 },
 218     { X86::SBB64rr,     X86::SBB64mr,    0 },
 219     { X86::SHL16rCL,    X86::SHL16mCL,   0 },
 220     { X86::SHL16ri,     X86::SHL16mi,    0 },
 221     { X86::SHL32rCL,    X86::SHL32mCL,   0 },
 222     { X86::SHL32ri,     X86::SHL32mi,    0 },
 223     { X86::SHL64rCL,    X86::SHL64mCL,   0 },
 224     { X86::SHL64ri,     X86::SHL64mi,    0 },
 225     { X86::SHL8rCL,     X86::SHL8mCL,    0 },
 226     { X86::SHL8ri,      X86::SHL8mi,     0 },
 227     { X86::SHLD16rrCL,  X86::SHLD16mrCL, 0 },
 228     { X86::SHLD16rri8,  X86::SHLD16mri8, 0 },
 229     { X86::SHLD32rrCL,  X86::SHLD32mrCL, 0 },
 230     { X86::SHLD32rri8,  X86::SHLD32mri8, 0 },
 231     { X86::SHLD64rrCL,  X86::SHLD64mrCL, 0 },
 232     { X86::SHLD64rri8,  X86::SHLD64mri8, 0 },
 233     { X86::SHR16r1,     X86::SHR16m1,    0 },
 234     { X86::SHR16rCL,    X86::SHR16mCL,   0 },
 235     { X86::SHR16ri,     X86::SHR16mi,    0 },
 236     { X86::SHR32r1,     X86::SHR32m1,    0 },
 237     { X86::SHR32rCL,    X86::SHR32mCL,   0 },
 238     { X86::SHR32ri,     X86::SHR32mi,    0 },
 239     { X86::SHR64r1,     X86::SHR64m1,    0 },
 240     { X86::SHR64rCL,    X86::SHR64mCL,   0 },
 241     { X86::SHR64ri,     X86::SHR64mi,    0 },
 242     { X86::SHR8r1,      X86::SHR8m1,     0 },
 243     { X86::SHR8rCL,     X86::SHR8mCL,    0 },
 244     { X86::SHR8ri,      X86::SHR8mi,     0 },
 245     { X86::SHRD16rrCL,  X86::SHRD16mrCL, 0 },
 246     { X86::SHRD16rri8,  X86::SHRD16mri8, 0 },
 247     { X86::SHRD32rrCL,  X86::SHRD32mrCL, 0 },
 248     { X86::SHRD32rri8,  X86::SHRD32mri8, 0 },
 249     { X86::SHRD64rrCL,  X86::SHRD64mrCL, 0 },
 250     { X86::SHRD64rri8,  X86::SHRD64mri8, 0 },
 251     { X86::SUB16ri,     X86::SUB16mi,    0 },
 252     { X86::SUB16ri8,    X86::SUB16mi8,   0 },
 253     { X86::SUB16rr,     X86::SUB16mr,    0 },
 254     { X86::SUB32ri,     X86::SUB32mi,    0 },
 255     { X86::SUB32ri8,    X86::SUB32mi8,   0 },
 256     { X86::SUB32rr,     X86::SUB32mr,    0 },
 257     { X86::SUB64ri32,   X86::SUB64mi32,  0 },
 258     { X86::SUB64ri8,    X86::SUB64mi8,   0 },
 259     { X86::SUB64rr,     X86::SUB64mr,    0 },
 260     { X86::SUB8ri,      X86::SUB8mi,     0 },
 261     { X86::SUB8rr,      X86::SUB8mr,     0 },
 262     { X86::XOR16ri,     X86::XOR16mi,    0 },
 263     { X86::XOR16ri8,    X86::XOR16mi8,   0 },
 264     { X86::XOR16rr,     X86::XOR16mr,    0 },
 265     { X86::XOR32ri,     X86::XOR32mi,    0 },
 266     { X86::XOR32ri8,    X86::XOR32mi8,   0 },
 267     { X86::XOR32rr,     X86::XOR32mr,    0 },
 268     { X86::XOR64ri32,   X86::XOR64mi32,  0 },
 269     { X86::XOR64ri8,    X86::XOR64mi8,   0 },
 270     { X86::XOR64rr,     X86::XOR64mr,    0 },
 271     { X86::XOR8ri,      X86::XOR8mi,     0 },
 272     { X86::XOR8rr,      X86::XOR8mr,     0 }
 273   };
 274
 275   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2Addr) {
 276     AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
 277                   Entry.RegOp, Entry.MemOp,
 278                   // Index 0, folded load and store, no alignment requirement.
 279                   Entry.Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
 280   }
 281
 282   static const X86MemoryFoldTableEntry MemoryFoldTable0[] = {
 283     { X86::BT16ri8,     X86::BT16mi8,       TB_FOLDED_LOAD },
 284     { X86::BT32ri8,     X86::BT32mi8,       TB_FOLDED_LOAD },
 285     { X86::BT64ri8,     X86::BT64mi8,       TB_FOLDED_LOAD },
 286     { X86::CALL32r,     X86::CALL32m,       TB_FOLDED_LOAD },
 287     { X86::CALL64r,     X86::CALL64m,       TB_FOLDED_LOAD },
 288     { X86::CMP16ri,     X86::CMP16mi,       TB_FOLDED_LOAD },
 289     { X86::CMP16ri8,    X86::CMP16mi8,      TB_FOLDED_LOAD },
 290     { X86::CMP16rr,     X86::CMP16mr,       TB_FOLDED_LOAD },
 291     { X86::CMP32ri,     X86::CMP32mi,       TB_FOLDED_LOAD },
 292     { X86::CMP32ri8,    X86::CMP32mi8,      TB_FOLDED_LOAD },
 293     { X86::CMP32rr,     X86::CMP32mr,       TB_FOLDED_LOAD },
 294     { X86::CMP64ri32,   X86::CMP64mi32,     TB_FOLDED_LOAD },
 295     { X86::CMP64ri8,    X86::CMP64mi8,      TB_FOLDED_LOAD },
 296     { X86::CMP64rr,     X86::CMP64mr,       TB_FOLDED_LOAD },
 297     { X86::CMP8ri,      X86::CMP8mi,        TB_FOLDED_LOAD },
 298     { X86::CMP8rr,      X86::CMP8mr,        TB_FOLDED_LOAD },
 299     { X86::DIV16r,      X86::DIV16m,        TB_FOLDED_LOAD },
 300     { X86::DIV32r,      X86::DIV32m,        TB_FOLDED_LOAD },
 301     { X86::DIV64r,      X86::DIV64m,        TB_FOLDED_LOAD },
 302     { X86::DIV8r,       X86::DIV8m,         TB_FOLDED_LOAD },
 303     { X86::EXTRACTPSrr, X86::EXTRACTPSmr,   TB_FOLDED_STORE },
 304     { X86::IDIV16r,     X86::IDIV16m,       TB_FOLDED_LOAD },
 305     { X86::IDIV32r,     X86::IDIV32m,       TB_FOLDED_LOAD },
 306     { X86::IDIV64r,     X86::IDIV64m,       TB_FOLDED_LOAD },
 307     { X86::IDIV8r,      X86::IDIV8m,        TB_FOLDED_LOAD },
 308     { X86::IMUL16r,     X86::IMUL16m,       TB_FOLDED_LOAD },
 309     { X86::IMUL32r,     X86::IMUL32m,       TB_FOLDED_LOAD },
 310     { X86::IMUL64r,     X86::IMUL64m,       TB_FOLDED_LOAD },
 311     { X86::IMUL8r,      X86::IMUL8m,        TB_FOLDED_LOAD },
 312     { X86::JMP32r,      X86::JMP32m,        TB_FOLDED_LOAD },
 313     { X86::JMP64r,      X86::JMP64m,        TB_FOLDED_LOAD },
 314     { X86::MOV16ri,     X86::MOV16mi,       TB_FOLDED_STORE },
 315     { X86::MOV16rr,     X86::MOV16mr,       TB_FOLDED_STORE },
 316     { X86::MOV32ri,     X86::MOV32mi,       TB_FOLDED_STORE },
 317     { X86::MOV32rr,     X86::MOV32mr,       TB_FOLDED_STORE },
 318     { X86::MOV64ri32,   X86::MOV64mi32,     TB_FOLDED_STORE },
 319     { X86::MOV64rr,     X86::MOV64mr,       TB_FOLDED_STORE },
 320     { X86::MOV8ri,      X86::MOV8mi,        TB_FOLDED_STORE },
 321     { X86::MOV8rr,      X86::MOV8mr,        TB_FOLDED_STORE },
 322     { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
 323     { X86::MOVAPDrr,    X86::MOVAPDmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
 324     { X86::MOVAPSrr,    X86::MOVAPSmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
 325     { X86::MOVDQArr,    X86::MOVDQAmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
 326     { X86::MOVPDI2DIrr, X86::MOVPDI2DImr,   TB_FOLDED_STORE },
 327     { X86::MOVPQIto64rr,X86::MOVPQI2QImr,   TB_FOLDED_STORE },
 328     { X86::MOVSDto64rr, X86::MOVSDto64mr,   TB_FOLDED_STORE },
 329     { X86::MOVSS2DIrr,  X86::MOVSS2DImr,    TB_FOLDED_STORE },
 330     { X86::MOVUPDrr,    X86::MOVUPDmr,      TB_FOLDED_STORE },
 331     { X86::MOVUPSrr,    X86::MOVUPSmr,      TB_FOLDED_STORE },
 332     { X86::MUL16r,      X86::MUL16m,        TB_FOLDED_LOAD },
 333     { X86::MUL32r,      X86::MUL32m,        TB_FOLDED_LOAD },
 334     { X86::MUL64r,      X86::MUL64m,        TB_FOLDED_LOAD },
 335     { X86::MUL8r,       X86::MUL8m,         TB_FOLDED_LOAD },
 336     { X86::PEXTRDrr,    X86::PEXTRDmr,      TB_FOLDED_STORE },
 337     { X86::PEXTRQrr,    X86::PEXTRQmr,      TB_FOLDED_STORE },
 338     { X86::PUSH16r,     X86::PUSH16rmm,     TB_FOLDED_LOAD },
 339     { X86::PUSH32r,     X86::PUSH32rmm,     TB_FOLDED_LOAD },
 340     { X86::PUSH64r,     X86::PUSH64rmm,     TB_FOLDED_LOAD },
 341     { X86::SETAEr,      X86::SETAEm,        TB_FOLDED_STORE },
 342     { X86::SETAr,       X86::SETAm,         TB_FOLDED_STORE },
 343     { X86::SETBEr,      X86::SETBEm,        TB_FOLDED_STORE },
 344     { X86::SETBr,       X86::SETBm,         TB_FOLDED_STORE },
 345     { X86::SETEr,       X86::SETEm,         TB_FOLDED_STORE },
 346     { X86::SETGEr,      X86::SETGEm,        TB_FOLDED_STORE },
 347     { X86::SETGr,       X86::SETGm,         TB_FOLDED_STORE },
 348     { X86::SETLEr,      X86::SETLEm,        TB_FOLDED_STORE },
 349     { X86::SETLr,       X86::SETLm,         TB_FOLDED_STORE },
 350     { X86::SETNEr,      X86::SETNEm,        TB_FOLDED_STORE },
 351     { X86::SETNOr,      X86::SETNOm,        TB_FOLDED_STORE },
 352     { X86::SETNPr,      X86::SETNPm,        TB_FOLDED_STORE },
 353     { X86::SETNSr,      X86::SETNSm,        TB_FOLDED_STORE },
 354     { X86::SETOr,       X86::SETOm,         TB_FOLDED_STORE },
 355     { X86::SETPr,       X86::SETPm,         TB_FOLDED_STORE },
 356     { X86::SETSr,       X86::SETSm,         TB_FOLDED_STORE },
 357     { X86::TAILJMPr,    X86::TAILJMPm,      TB_FOLDED_LOAD },
 358     { X86::TAILJMPr64,  X86::TAILJMPm64,    TB_FOLDED_LOAD },
 359     { X86::TAILJMPr64_REX, X86::TAILJMPm64_REX, TB_FOLDED_LOAD },
 360     { X86::TEST16ri,    X86::TEST16mi,      TB_FOLDED_LOAD },
 361     { X86::TEST32ri,    X86::TEST32mi,      TB_FOLDED_LOAD },
 362     { X86::TEST64ri32,  X86::TEST64mi32,    TB_FOLDED_LOAD },
 363     { X86::TEST8ri,     X86::TEST8mi,       TB_FOLDED_LOAD },
 364
 365     // AVX 128-bit versions of foldable instructions
 366     { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr,  TB_FOLDED_STORE  },
 367     { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
 368     { X86::VMOVAPDrr,   X86::VMOVAPDmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
 369     { X86::VMOVAPSrr,   X86::VMOVAPSmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
 370     { X86::VMOVDQArr,   X86::VMOVDQAmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
 371     { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr,  TB_FOLDED_STORE },
 372     { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
 373     { X86::VMOVSDto64rr,X86::VMOVSDto64mr,  TB_FOLDED_STORE },
 374     { X86::VMOVSS2DIrr, X86::VMOVSS2DImr,   TB_FOLDED_STORE },
 375     { X86::VMOVUPDrr,   X86::VMOVUPDmr,     TB_FOLDED_STORE },
 376     { X86::VMOVUPSrr,   X86::VMOVUPSmr,     TB_FOLDED_STORE },
 377     { X86::VPEXTRDrr,   X86::VPEXTRDmr,     TB_FOLDED_STORE },
 378     { X86::VPEXTRQrr,   X86::VPEXTRQmr,     TB_FOLDED_STORE },
 379
 380     // AVX 256-bit foldable instructions
 381     { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
 382     { X86::VMOVAPDYrr,  X86::VMOVAPDYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
 383     { X86::VMOVAPSYrr,  X86::VMOVAPSYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
 384     { X86::VMOVDQAYrr,  X86::VMOVDQAYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
 385     { X86::VMOVUPDYrr,  X86::VMOVUPDYmr,    TB_FOLDED_STORE },
 386     { X86::VMOVUPSYrr,  X86::VMOVUPSYmr,    TB_FOLDED_STORE },
 387
 388     // AVX-512 foldable instructions
 389     { X86::VMOVPDI2DIZrr,   X86::VMOVPDI2DIZmr, TB_FOLDED_STORE },
 390     { X86::VMOVAPDZrr,      X86::VMOVAPDZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
 391     { X86::VMOVAPSZrr,      X86::VMOVAPSZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
 392     { X86::VMOVDQA32Zrr,    X86::VMOVDQA32Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
 393     { X86::VMOVDQA64Zrr,    X86::VMOVDQA64Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
 394     { X86::VMOVUPDZrr,      X86::VMOVUPDZmr,    TB_FOLDED_STORE },
 395     { X86::VMOVUPSZrr,      X86::VMOVUPSZmr,    TB_FOLDED_STORE },
 396     { X86::VMOVDQU8Zrr,     X86::VMOVDQU8Zmr,   TB_FOLDED_STORE },
 397     { X86::VMOVDQU16Zrr,    X86::VMOVDQU16Zmr,  TB_FOLDED_STORE },
 398     { X86::VMOVDQU32Zrr,    X86::VMOVDQU32Zmr,  TB_FOLDED_STORE },
 399     { X86::VMOVDQU64Zrr,    X86::VMOVDQU64Zmr,  TB_FOLDED_STORE },
 400
 401     // AVX-512 foldable instructions (256-bit versions)
 402     { X86::VMOVAPDZ256rr,      X86::VMOVAPDZ256mr,    TB_FOLDED_STORE | TB_ALIGN_32 },
 403     { X86::VMOVAPSZ256rr,      X86::VMOVAPSZ256mr,    TB_FOLDED_STORE | TB_ALIGN_32 },
 404     { X86::VMOVDQA32Z256rr,    X86::VMOVDQA32Z256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },
 405     { X86::VMOVDQA64Z256rr,    X86::VMOVDQA64Z256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },
 406     { X86::VMOVUPDZ256rr,      X86::VMOVUPDZ256mr,    TB_FOLDED_STORE },
 407     { X86::VMOVUPSZ256rr,      X86::VMOVUPSZ256mr,    TB_FOLDED_STORE },
 408     { X86::VMOVDQU8Z256rr,     X86::VMOVDQU8Z256mr,   TB_FOLDED_STORE },
 409     { X86::VMOVDQU16Z256rr,    X86::VMOVDQU16Z256mr,  TB_FOLDED_STORE },
 410     { X86::VMOVDQU32Z256rr,    X86::VMOVDQU32Z256mr,  TB_FOLDED_STORE },
 411     { X86::VMOVDQU64Z256rr,    X86::VMOVDQU64Z256mr,  TB_FOLDED_STORE },
 412
 413     // AVX-512 foldable instructions (128-bit versions)
 414     { X86::VMOVAPDZ128rr,      X86::VMOVAPDZ128mr,    TB_FOLDED_STORE | TB_ALIGN_16 },
 415     { X86::VMOVAPSZ128rr,      X86::VMOVAPSZ128mr,    TB_FOLDED_STORE | TB_ALIGN_16 },
 416     { X86::VMOVDQA32Z128rr,    X86::VMOVDQA32Z128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },
 417     { X86::VMOVDQA64Z128rr,    X86::VMOVDQA64Z128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },
 418     { X86::VMOVUPDZ128rr,      X86::VMOVUPDZ128mr,    TB_FOLDED_STORE },
 419     { X86::VMOVUPSZ128rr,      X86::VMOVUPSZ128mr,    TB_FOLDED_STORE },
 420     { X86::VMOVDQU8Z128rr,     X86::VMOVDQU8Z128mr,   TB_FOLDED_STORE },
 421     { X86::VMOVDQU16Z128rr,    X86::VMOVDQU16Z128mr,  TB_FOLDED_STORE },
 422     { X86::VMOVDQU32Z128rr,    X86::VMOVDQU32Z128mr,  TB_FOLDED_STORE },
 423     { X86::VMOVDQU64Z128rr,    X86::VMOVDQU64Z128mr,  TB_FOLDED_STORE },
 424
 425     // F16C foldable instructions
 426     { X86::VCVTPS2PHrr,        X86::VCVTPS2PHmr,      TB_FOLDED_STORE },
 427     { X86::VCVTPS2PHYrr,       X86::VCVTPS2PHYmr,     TB_FOLDED_STORE }
 428   };
 429
 430   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable0) {
 431     AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
 432                   Entry.RegOp, Entry.MemOp, TB_INDEX_0 | Entry.Flags);
 433   }
 434
 435   static const X86MemoryFoldTableEntry MemoryFoldTable1[] = {
 436     { X86::BSF16rr,         X86::BSF16rm,             0 },
 437     { X86::BSF32rr,         X86::BSF32rm,             0 },
 438     { X86::BSF64rr,         X86::BSF64rm,             0 },
 439     { X86::BSR16rr,         X86::BSR16rm,             0 },
 440     { X86::BSR32rr,         X86::BSR32rm,             0 },
 441     { X86::BSR64rr,         X86::BSR64rm,             0 },
 442     { X86::CMP16rr,         X86::CMP16rm,             0 },
 443     { X86::CMP32rr,         X86::CMP32rm,             0 },
 444     { X86::CMP64rr,         X86::CMP64rm,             0 },
 445     { X86::CMP8rr,          X86::CMP8rm,              0 },
 446     { X86::CVTSD2SSrr,      X86::CVTSD2SSrm,          0 },
 447     { X86::CVTSI2SD64rr,    X86::CVTSI2SD64rm,        0 },
 448     { X86::CVTSI2SDrr,      X86::CVTSI2SDrm,          0 },
 449     { X86::CVTSI2SS64rr,    X86::CVTSI2SS64rm,        0 },
 450     { X86::CVTSI2SSrr,      X86::CVTSI2SSrm,          0 },
 451     { X86::CVTSS2SDrr,      X86::CVTSS2SDrm,          0 },
 452     { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm,       0 },
 453     { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm,         0 },
 454     { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm,       0 },
 455     { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm,         0 },
 456     { X86::IMUL16rri,       X86::IMUL16rmi,           0 },
 457     { X86::IMUL16rri8,      X86::IMUL16rmi8,          0 },
 458     { X86::IMUL32rri,       X86::IMUL32rmi,           0 },
 459     { X86::IMUL32rri8,      X86::IMUL32rmi8,          0 },
 460     { X86::IMUL64rri32,     X86::IMUL64rmi32,         0 },
 461     { X86::IMUL64rri8,      X86::IMUL64rmi8,          0 },
 462     { X86::Int_COMISDrr,    X86::Int_COMISDrm,        0 },
 463     { X86::Int_COMISSrr,    X86::Int_COMISSrm,        0 },
 464     { X86::CVTSD2SI64rr,    X86::CVTSD2SI64rm,        0 },
 465     { X86::CVTSD2SIrr,      X86::CVTSD2SIrm,          0 },
 466     { X86::CVTSS2SI64rr,    X86::CVTSS2SI64rm,        0 },
 467     { X86::CVTSS2SIrr,      X86::CVTSS2SIrm,          0 },
 468     { X86::CVTDQ2PDrr,      X86::CVTDQ2PDrm,          TB_ALIGN_16 },
 469     { X86::CVTDQ2PSrr,      X86::CVTDQ2PSrm,          TB_ALIGN_16 },
 470     { X86::CVTPD2DQrr,      X86::CVTPD2DQrm,          TB_ALIGN_16 },
 471     { X86::CVTPD2PSrr,      X86::CVTPD2PSrm,          TB_ALIGN_16 },
 472     { X86::CVTPS2DQrr,      X86::CVTPS2DQrm,          TB_ALIGN_16 },
 473     { X86::CVTPS2PDrr,      X86::CVTPS2PDrm,          TB_ALIGN_16 },
 474     { X86::CVTTPD2DQrr,     X86::CVTTPD2DQrm,         TB_ALIGN_16 },
 475     { X86::CVTTPS2DQrr,     X86::CVTTPS2DQrm,         TB_ALIGN_16 },
 476     { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm,  0 },
 477     { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm,     0 },
 478     { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm,  0 },
 479     { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm,     0 },
 480     { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm,       0 },
 481     { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm,       0 },
 482     { X86::MOV16rr,         X86::MOV16rm,             0 },
 483     { X86::MOV32rr,         X86::MOV32rm,             0 },
 484     { X86::MOV64rr,         X86::MOV64rm,             0 },
 485     { X86::MOV64toPQIrr,    X86::MOVQI2PQIrm,         0 },
 486     { X86::MOV64toSDrr,     X86::MOV64toSDrm,         0 },
 487     { X86::MOV8rr,          X86::MOV8rm,              0 },
 488     { X86::MOVAPDrr,        X86::MOVAPDrm,            TB_ALIGN_16 },
 489     { X86::MOVAPSrr,        X86::MOVAPSrm,            TB_ALIGN_16 },
 490     { X86::MOVDDUPrr,       X86::MOVDDUPrm,           0 },
 491     { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm,         0 },
 492     { X86::MOVDI2SSrr,      X86::MOVDI2SSrm,          0 },
 493     { X86::MOVDQArr,        X86::MOVDQArm,            TB_ALIGN_16 },
 494     { X86::MOVSHDUPrr,      X86::MOVSHDUPrm,          TB_ALIGN_16 },
 495     { X86::MOVSLDUPrr,      X86::MOVSLDUPrm,          TB_ALIGN_16 },
 496     { X86::MOVSX16rr8,      X86::MOVSX16rm8,          0 },
 497     { X86::MOVSX32rr16,     X86::MOVSX32rm16,         0 },
 498     { X86::MOVSX32rr8,      X86::MOVSX32rm8,          0 },
 499     { X86::MOVSX64rr16,     X86::MOVSX64rm16,         0 },
 500     { X86::MOVSX64rr32,     X86::MOVSX64rm32,         0 },
 501     { X86::MOVSX64rr8,      X86::MOVSX64rm8,          0 },
 502     { X86::MOVUPDrr,        X86::MOVUPDrm,            TB_ALIGN_16 },
 503     { X86::MOVUPSrr,        X86::MOVUPSrm,            0 },
 504     { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm,     TB_ALIGN_16 },
 505     { X86::MOVZX16rr8,      X86::MOVZX16rm8,          0 },
 506     { X86::MOVZX32rr16,     X86::MOVZX32rm16,         0 },
 507     { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8,   0 },
 508     { X86::MOVZX32rr8,      X86::MOVZX32rm8,          0 },
 509     { X86::PABSBrr128,      X86::PABSBrm128,          TB_ALIGN_16 },
 510     { X86::PABSDrr128,      X86::PABSDrm128,          TB_ALIGN_16 },
 511     { X86::PABSWrr128,      X86::PABSWrm128,          TB_ALIGN_16 },
 512     { X86::PCMPESTRIrr,     X86::PCMPESTRIrm,         TB_ALIGN_16 },
 513     { X86::PCMPESTRM128rr,  X86::PCMPESTRM128rm,      TB_ALIGN_16 },
 514     { X86::PCMPISTRIrr,     X86::PCMPISTRIrm,         TB_ALIGN_16 },
 515     { X86::PCMPISTRM128rr,  X86::PCMPISTRM128rm,      TB_ALIGN_16 },
 516     { X86::PHMINPOSUWrr128, X86::PHMINPOSUWrm128,     TB_ALIGN_16 },
 517     { X86::PMOVSXBDrr,      X86::PMOVSXBDrm,          TB_ALIGN_16 },
 518     { X86::PMOVSXBQrr,      X86::PMOVSXBQrm,          TB_ALIGN_16 },
 519     { X86::PMOVSXBWrr,      X86::PMOVSXBWrm,          TB_ALIGN_16 },
 520     { X86::PMOVSXDQrr,      X86::PMOVSXDQrm,          TB_ALIGN_16 },
 521     { X86::PMOVSXWDrr,      X86::PMOVSXWDrm,          TB_ALIGN_16 },
 522     { X86::PMOVSXWQrr,      X86::PMOVSXWQrm,          TB_ALIGN_16 },
 523     { X86::PMOVZXBDrr,      X86::PMOVZXBDrm,          TB_ALIGN_16 },
 524     { X86::PMOVZXBQrr,      X86::PMOVZXBQrm,          TB_ALIGN_16 },
 525     { X86::PMOVZXBWrr,      X86::PMOVZXBWrm,          TB_ALIGN_16 },
 526     { X86::PMOVZXDQrr,      X86::PMOVZXDQrm,          TB_ALIGN_16 },
 527     { X86::PMOVZXWDrr,      X86::PMOVZXWDrm,          TB_ALIGN_16 },
 528     { X86::PMOVZXWQrr,      X86::PMOVZXWQrm,          TB_ALIGN_16 },
 529     { X86::PSHUFDri,        X86::PSHUFDmi,            TB_ALIGN_16 },
 530     { X86::PSHUFHWri,       X86::PSHUFHWmi,           TB_ALIGN_16 },
 531     { X86::PSHUFLWri,       X86::PSHUFLWmi,           TB_ALIGN_16 },
 532     { X86::PTESTrr,         X86::PTESTrm,             TB_ALIGN_16 },
 533     { X86::RCPPSr,          X86::RCPPSm,              TB_ALIGN_16 },
 534     { X86::RCPSSr,          X86::RCPSSm,              0 },
 535     { X86::RCPSSr_Int,      X86::RCPSSm_Int,          0 },
 536     { X86::ROUNDPDr,        X86::ROUNDPDm,            TB_ALIGN_16 },
 537     { X86::ROUNDPSr,        X86::ROUNDPSm,            TB_ALIGN_16 },
 538     { X86::RSQRTPSr,        X86::RSQRTPSm,            TB_ALIGN_16 },
 539     { X86::RSQRTSSr,        X86::RSQRTSSm,            0 },
 540     { X86::RSQRTSSr_Int,    X86::RSQRTSSm_Int,        0 },
 541     { X86::SQRTPDr,         X86::SQRTPDm,             TB_ALIGN_16 },
 542     { X86::SQRTPSr,         X86::SQRTPSm,             TB_ALIGN_16 },
 543     { X86::SQRTSDr,         X86::SQRTSDm,             0 },
 544     { X86::SQRTSDr_Int,     X86::SQRTSDm_Int,         0 },
 545     { X86::SQRTSSr,         X86::SQRTSSm,             0 },
 546     { X86::SQRTSSr_Int,     X86::SQRTSSm_Int,         0 },
 547     { X86::TEST16rr,        X86::TEST16rm,            0 },
 548     { X86::TEST32rr,        X86::TEST32rm,            0 },
 549     { X86::TEST64rr,        X86::TEST64rm,            0 },
 550     { X86::TEST8rr,         X86::TEST8rm,             0 },
 551     // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
 552     { X86::UCOMISDrr,       X86::UCOMISDrm,           0 },
 553     { X86::UCOMISSrr,       X86::UCOMISSrm,           0 },
 554
 555     // MMX version of foldable instructions
 556     { X86::MMX_CVTPD2PIirr,   X86::MMX_CVTPD2PIirm,   0 },
 557     { X86::MMX_CVTPI2PDirr,   X86::MMX_CVTPI2PDirm,   0 },
 558     { X86::MMX_CVTPS2PIirr,   X86::MMX_CVTPS2PIirm,   0 },
 559     { X86::MMX_CVTTPD2PIirr,  X86::MMX_CVTTPD2PIirm,  0 },
 560     { X86::MMX_CVTTPS2PIirr,  X86::MMX_CVTTPS2PIirm,  0 },
 561     { X86::MMX_MOVD64to64rr,  X86::MMX_MOVQ64rm,      0 },
 562     { X86::MMX_PABSBrr64,     X86::MMX_PABSBrm64,     0 },
 563     { X86::MMX_PABSDrr64,     X86::MMX_PABSDrm64,     0 },
 564     { X86::MMX_PABSWrr64,     X86::MMX_PABSWrm64,     0 },
 565     { X86::MMX_PSHUFWri,      X86::MMX_PSHUFWmi,      0 },
 566
 567     // 3DNow! version of foldable instructions
 568     { X86::PF2IDrr,         X86::PF2IDrm,             0 },
 569     { X86::PF2IWrr,         X86::PF2IWrm,             0 },
 570     { X86::PFRCPrr,         X86::PFRCPrm,             0 },
 571     { X86::PFRSQRTrr,       X86::PFRSQRTrm,           0 },
 572     { X86::PI2FDrr,         X86::PI2FDrm,             0 },
 573     { X86::PI2FWrr,         X86::PI2FWrm,             0 },
 574     { X86::PSWAPDrr,        X86::PSWAPDrm,            0 },
 575
 576     // AVX 128-bit versions of foldable instructions
 577     { X86::Int_VCOMISDrr,   X86::Int_VCOMISDrm,       0 },
 578     { X86::Int_VCOMISSrr,   X86::Int_VCOMISSrm,       0 },
 579     { X86::Int_VUCOMISDrr,  X86::Int_VUCOMISDrm,      0 },
 580     { X86::Int_VUCOMISSrr,  X86::Int_VUCOMISSrm,      0 },
 581     { X86::VCVTTSD2SI64rr,  X86::VCVTTSD2SI64rm,      0 },
 582     { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
 583     { X86::VCVTTSD2SIrr,    X86::VCVTTSD2SIrm,        0 },
 584     { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm,    0 },
 585     { X86::VCVTTSS2SI64rr,  X86::VCVTTSS2SI64rm,      0 },
 586     { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
 587     { X86::VCVTTSS2SIrr,    X86::VCVTTSS2SIrm,        0 },
 588     { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm,    0 },
 589     { X86::VCVTSD2SI64rr,   X86::VCVTSD2SI64rm,       0 },
 590     { X86::VCVTSD2SIrr,     X86::VCVTSD2SIrm,         0 },
 591     { X86::VCVTSS2SI64rr,   X86::VCVTSS2SI64rm,       0 },
 592     { X86::VCVTSS2SIrr,     X86::VCVTSS2SIrm,         0 },
 593     { X86::VCVTDQ2PDrr,     X86::VCVTDQ2PDrm,         0 },
 594     { X86::VCVTDQ2PSrr,     X86::VCVTDQ2PSrm,         0 },
 595     { X86::VCVTPD2DQrr,     X86::VCVTPD2DQXrm,        0 },
 596     { X86::VCVTPD2PSrr,     X86::VCVTPD2PSXrm,        0 },
 597     { X86::VCVTPS2DQrr,     X86::VCVTPS2DQrm,         0 },
 598     { X86::VCVTPS2PDrr,     X86::VCVTPS2PDrm,         0 },
 599     { X86::VCVTTPD2DQrr,    X86::VCVTTPD2DQXrm,       0 },
 600     { X86::VCVTTPS2DQrr,    X86::VCVTTPS2DQrm,        0 },
 601     { X86::VMOV64toPQIrr,   X86::VMOVQI2PQIrm,        0 },
 602     { X86::VMOV64toSDrr,    X86::VMOV64toSDrm,        0 },
 603     { X86::VMOVAPDrr,       X86::VMOVAPDrm,           TB_ALIGN_16 },
 604     { X86::VMOVAPSrr,       X86::VMOVAPSrm,           TB_ALIGN_16 },
 605     { X86::VMOVDDUPrr,      X86::VMOVDDUPrm,          0 },
 606     { X86::VMOVDI2PDIrr,    X86::VMOVDI2PDIrm,        0 },
 607     { X86::VMOVDI2SSrr,     X86::VMOVDI2SSrm,         0 },
 608     { X86::VMOVDQArr,       X86::VMOVDQArm,           TB_ALIGN_16 },
 609     { X86::VMOVSLDUPrr,     X86::VMOVSLDUPrm,         0 },
 610     { X86::VMOVSHDUPrr,     X86::VMOVSHDUPrm,         0 },
 611     { X86::VMOVUPDrr,       X86::VMOVUPDrm,           0 },
 612     { X86::VMOVUPSrr,       X86::VMOVUPSrm,           0 },
 613     { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm,    TB_ALIGN_16 },
 614     { X86::VPABSBrr128,     X86::VPABSBrm128,         0 },
 615     { X86::VPABSDrr128,     X86::VPABSDrm128,         0 },
 616     { X86::VPABSWrr128,     X86::VPABSWrm128,         0 },
 617     { X86::VPCMPESTRIrr,    X86::VPCMPESTRIrm,        0 },
 618     { X86::VPCMPESTRM128rr, X86::VPCMPESTRM128rm,     0 },
 619     { X86::VPCMPISTRIrr,    X86::VPCMPISTRIrm,        0 },
 620     { X86::VPCMPISTRM128rr, X86::VPCMPISTRM128rm,     0 },
 621     { X86::VPHMINPOSUWrr128, X86::VPHMINPOSUWrm128,   0 },
 622     { X86::VPERMILPDri,     X86::VPERMILPDmi,         0 },
 623     { X86::VPERMILPSri,     X86::VPERMILPSmi,         0 },
 624     { X86::VPMOVSXBDrr,     X86::VPMOVSXBDrm,         0 },
 625     { X86::VPMOVSXBQrr,     X86::VPMOVSXBQrm,         0 },
 626     { X86::VPMOVSXBWrr,     X86::VPMOVSXBWrm,         0 },
 627     { X86::VPMOVSXDQrr,     X86::VPMOVSXDQrm,         0 },
 628     { X86::VPMOVSXWDrr,     X86::VPMOVSXWDrm,         0 },
 629     { X86::VPMOVSXWQrr,     X86::VPMOVSXWQrm,         0 },
 630     { X86::VPMOVZXBDrr,     X86::VPMOVZXBDrm,         0 },
 631     { X86::VPMOVZXBQrr,     X86::VPMOVZXBQrm,         0 },
 632     { X86::VPMOVZXBWrr,     X86::VPMOVZXBWrm,         0 },
 633     { X86::VPMOVZXDQrr,     X86::VPMOVZXDQrm,         0 },
 634     { X86::VPMOVZXWDrr,     X86::VPMOVZXWDrm,         0 },
 635     { X86::VPMOVZXWQrr,     X86::VPMOVZXWQrm,         0 },
 636     { X86::VPSHUFDri,       X86::VPSHUFDmi,           0 },
 637     { X86::VPSHUFHWri,      X86::VPSHUFHWmi,          0 },
 638     { X86::VPSHUFLWri,      X86::VPSHUFLWmi,          0 },
 639     { X86::VPTESTrr,        X86::VPTESTrm,            0 },
 640     { X86::VRCPPSr,         X86::VRCPPSm,             0 },
 641     { X86::VROUNDPDr,       X86::VROUNDPDm,           0 },
 642     { X86::VROUNDPSr,       X86::VROUNDPSm,           0 },
 643     { X86::VRSQRTPSr,       X86::VRSQRTPSm,           0 },
 644     { X86::VSQRTPDr,        X86::VSQRTPDm,            0 },
 645     { X86::VSQRTPSr,        X86::VSQRTPSm,            0 },
 646     { X86::VTESTPDrr,       X86::VTESTPDrm,           0 },
 647     { X86::VTESTPSrr,       X86::VTESTPSrm,           0 },
 648     { X86::VUCOMISDrr,      X86::VUCOMISDrm,          0 },
 649     { X86::VUCOMISSrr,      X86::VUCOMISSrm,          0 },
 650
 651     // AVX 256-bit foldable instructions
 652     { X86::VCVTDQ2PDYrr,    X86::VCVTDQ2PDYrm,        0 },
 653     { X86::VCVTDQ2PSYrr,    X86::VCVTDQ2PSYrm,        0 },
 654     { X86::VCVTPD2DQYrr,    X86::VCVTPD2DQYrm,        0 },
 655     { X86::VCVTPD2PSYrr,    X86::VCVTPD2PSYrm,        0 },
 656     { X86::VCVTPS2DQYrr,    X86::VCVTPS2DQYrm,        0 },
 657     { X86::VCVTPS2PDYrr,    X86::VCVTPS2PDYrm,        0 },
 658     { X86::VCVTTPD2DQYrr,   X86::VCVTTPD2DQYrm,       0 },
 659     { X86::VCVTTPS2DQYrr,   X86::VCVTTPS2DQYrm,       0 },
 660     { X86::VMOVAPDYrr,      X86::VMOVAPDYrm,          TB_ALIGN_32 },
 661     { X86::VMOVAPSYrr,      X86::VMOVAPSYrm,          TB_ALIGN_32 },
 662     { X86::VMOVDDUPYrr,     X86::VMOVDDUPYrm,         0 },
 663     { X86::VMOVDQAYrr,      X86::VMOVDQAYrm,          TB_ALIGN_32 },
 664     { X86::VMOVSLDUPYrr,    X86::VMOVSLDUPYrm,        0 },
 665     { X86::VMOVSHDUPYrr,    X86::VMOVSHDUPYrm,        0 },
 666     { X86::VMOVUPDYrr,      X86::VMOVUPDYrm,          0 },
 667     { X86::VMOVUPSYrr,      X86::VMOVUPSYrm,          0 },
 668     { X86::VPERMILPDYri,    X86::VPERMILPDYmi,        0 },
 669     { X86::VPERMILPSYri,    X86::VPERMILPSYmi,        0 },
 670     { X86::VPTESTYrr,       X86::VPTESTYrm,           0 },
 671     { X86::VRCPPSYr,        X86::VRCPPSYm,            0 },
 672     { X86::VROUNDYPDr,      X86::VROUNDYPDm,          0 },
 673     { X86::VROUNDYPSr,      X86::VROUNDYPSm,          0 },
 674     { X86::VRSQRTPSYr,      X86::VRSQRTPSYm,          0 },
 675     { X86::VSQRTPDYr,       X86::VSQRTPDYm,           0 },
 676     { X86::VSQRTPSYr,       X86::VSQRTPSYm,           0 },
 677     { X86::VTESTPDYrr,      X86::VTESTPDYrm,          0 },
 678     { X86::VTESTPSYrr,      X86::VTESTPSYrm,          0 },
 679
 680     // AVX2 foldable instructions
 681
 682     // VBROADCASTS{SD}rr register instructions were an AVX2 addition while the
 683     // VBROADCASTS{SD}rm memory instructions were available from AVX1.
 684     // TB_NO_REVERSE prevents unfolding from introducing an illegal instruction
 685     // on AVX1 targets. The VPBROADCAST instructions are all AVX2 instructions
 686     // so they don't need an equivalent limitation.
 687     { X86::VBROADCASTSSrr,  X86::VBROADCASTSSrm,      TB_NO_REVERSE },
 688     { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm,     TB_NO_REVERSE },
 689     { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm,     TB_NO_REVERSE },
 690     { X86::VPABSBrr256,     X86::VPABSBrm256,         0 },
 691     { X86::VPABSDrr256,     X86::VPABSDrm256,         0 },
 692     { X86::VPABSWrr256,     X86::VPABSWrm256,         0 },
 693     { X86::VPBROADCASTBrr,  X86::VPBROADCASTBrm,      0 },
 694     { X86::VPBROADCASTBYrr, X86::VPBROADCASTBYrm,     0 },
 695     { X86::VPBROADCASTDrr,  X86::VPBROADCASTDrm,      0 },
 696     { X86::VPBROADCASTDYrr, X86::VPBROADCASTDYrm,     0 },
 697     { X86::VPBROADCASTQrr,  X86::VPBROADCASTQrm,      0 },
 698     { X86::VPBROADCASTQYrr, X86::VPBROADCASTQYrm,     0 },
 699     { X86::VPBROADCASTWrr,  X86::VPBROADCASTWrm,      0 },
 700     { X86::VPBROADCASTWYrr, X86::VPBROADCASTWYrm,     0 },
 701     { X86::VPERMPDYri,      X86::VPERMPDYmi,          0 },
 702     { X86::VPERMQYri,       X86::VPERMQYmi,           0 },
 703     { X86::VPMOVSXBDYrr,    X86::VPMOVSXBDYrm,        0 },
 704     { X86::VPMOVSXBQYrr,    X86::VPMOVSXBQYrm,        0 },
 705     { X86::VPMOVSXBWYrr,    X86::VPMOVSXBWYrm,        0 },
 706     { X86::VPMOVSXDQYrr,    X86::VPMOVSXDQYrm,        0 },
 707     { X86::VPMOVSXWDYrr,    X86::VPMOVSXWDYrm,        0 },
 708     { X86::VPMOVSXWQYrr,    X86::VPMOVSXWQYrm,        0 },
 709     { X86::VPMOVZXBDYrr,    X86::VPMOVZXBDYrm,        0 },
 710     { X86::VPMOVZXBQYrr,    X86::VPMOVZXBQYrm,        0 },
 711     { X86::VPMOVZXBWYrr,    X86::VPMOVZXBWYrm,        0 },
 712     { X86::VPMOVZXDQYrr,    X86::VPMOVZXDQYrm,        0 },
 713     { X86::VPMOVZXWDYrr,    X86::VPMOVZXWDYrm,        0 },
 714     { X86::VPMOVZXWQYrr,    X86::VPMOVZXWQYrm,        0 },
 715     { X86::VPSHUFDYri,      X86::VPSHUFDYmi,          0 },
 716     { X86::VPSHUFHWYri,     X86::VPSHUFHWYmi,         0 },
 717     { X86::VPSHUFLWYri,     X86::VPSHUFLWYmi,         0 },
 718
 719     // XOP foldable instructions
 720     { X86::VFRCZPDrr,          X86::VFRCZPDrm,        0 },
 721     { X86::VFRCZPDrrY,         X86::VFRCZPDrmY,       0 },
 722     { X86::VFRCZPSrr,          X86::VFRCZPSrm,        0 },
 723     { X86::VFRCZPSrrY,         X86::VFRCZPSrmY,       0 },
 724     { X86::VFRCZSDrr,          X86::VFRCZSDrm,        0 },
 725     { X86::VFRCZSSrr,          X86::VFRCZSSrm,        0 },
 726     { X86::VPHADDBDrr,         X86::VPHADDBDrm,       0 },
 727     { X86::VPHADDBQrr,         X86::VPHADDBQrm,       0 },
 728     { X86::VPHADDBWrr,         X86::VPHADDBWrm,       0 },
 729     { X86::VPHADDDQrr,         X86::VPHADDDQrm,       0 },
 730     { X86::VPHADDWDrr,         X86::VPHADDWDrm,       0 },
 731     { X86::VPHADDWQrr,         X86::VPHADDWQrm,       0 },
 732     { X86::VPHADDUBDrr,        X86::VPHADDUBDrm,      0 },
 733     { X86::VPHADDUBQrr,        X86::VPHADDUBQrm,      0 },
 734     { X86::VPHADDUBWrr,        X86::VPHADDUBWrm,      0 },
 735     { X86::VPHADDUDQrr,        X86::VPHADDUDQrm,      0 },
 736     { X86::VPHADDUWDrr,        X86::VPHADDUWDrm,      0 },
 737     { X86::VPHADDUWQrr,        X86::VPHADDUWQrm,      0 },
 738     { X86::VPHSUBBWrr,         X86::VPHSUBBWrm,       0 },
 739     { X86::VPHSUBDQrr,         X86::VPHSUBDQrm,       0 },
 740     { X86::VPHSUBWDrr,         X86::VPHSUBWDrm,       0 },
 741     { X86::VPROTBri,           X86::VPROTBmi,         0 },
 742     { X86::VPROTBrr,           X86::VPROTBmr,         0 },
 743     { X86::VPROTDri,           X86::VPROTDmi,         0 },
 744     { X86::VPROTDrr,           X86::VPROTDmr,         0 },
 745     { X86::VPROTQri,           X86::VPROTQmi,         0 },
 746     { X86::VPROTQrr,           X86::VPROTQmr,         0 },
 747     { X86::VPROTWri,           X86::VPROTWmi,         0 },
 748     { X86::VPROTWrr,           X86::VPROTWmr,         0 },
 749     { X86::VPSHABrr,           X86::VPSHABmr,         0 },
 750     { X86::VPSHADrr,           X86::VPSHADmr,         0 },
 751     { X86::VPSHAQrr,           X86::VPSHAQmr,         0 },
 752     { X86::VPSHAWrr,           X86::VPSHAWmr,         0 },
 753     { X86::VPSHLBrr,           X86::VPSHLBmr,         0 },
 754     { X86::VPSHLDrr,           X86::VPSHLDmr,         0 },
 755     { X86::VPSHLQrr,           X86::VPSHLQmr,         0 },
 756     { X86::VPSHLWrr,           X86::VPSHLWmr,         0 },
 757
 758     // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
 759     { X86::BEXTR32rr,       X86::BEXTR32rm,           0 },
 760     { X86::BEXTR64rr,       X86::BEXTR64rm,           0 },
 761     { X86::BEXTRI32ri,      X86::BEXTRI32mi,          0 },
 762     { X86::BEXTRI64ri,      X86::BEXTRI64mi,          0 },
 763     { X86::BLCFILL32rr,     X86::BLCFILL32rm,         0 },
 764     { X86::BLCFILL64rr,     X86::BLCFILL64rm,         0 },
 765     { X86::BLCI32rr,        X86::BLCI32rm,            0 },
 766     { X86::BLCI64rr,        X86::BLCI64rm,            0 },
 767     { X86::BLCIC32rr,       X86::BLCIC32rm,           0 },
 768     { X86::BLCIC64rr,       X86::BLCIC64rm,           0 },
 769     { X86::BLCMSK32rr,      X86::BLCMSK32rm,          0 },
 770     { X86::BLCMSK64rr,      X86::BLCMSK64rm,          0 },
 771     { X86::BLCS32rr,        X86::BLCS32rm,            0 },
 772     { X86::BLCS64rr,        X86::BLCS64rm,            0 },
 773     { X86::BLSFILL32rr,     X86::BLSFILL32rm,         0 },
 774     { X86::BLSFILL64rr,     X86::BLSFILL64rm,         0 },
 775     { X86::BLSI32rr,        X86::BLSI32rm,            0 },
 776     { X86::BLSI64rr,        X86::BLSI64rm,            0 },
 777     { X86::BLSIC32rr,       X86::BLSIC32rm,           0 },
 778     { X86::BLSIC64rr,       X86::BLSIC64rm,           0 },
 779     { X86::BLSMSK32rr,      X86::BLSMSK32rm,          0 },
 780     { X86::BLSMSK64rr,      X86::BLSMSK64rm,          0 },
 781     { X86::BLSR32rr,        X86::BLSR32rm,            0 },
 782     { X86::BLSR64rr,        X86::BLSR64rm,            0 },
 783     { X86::BZHI32rr,        X86::BZHI32rm,            0 },
 784     { X86::BZHI64rr,        X86::BZHI64rm,            0 },
 785     { X86::LZCNT16rr,       X86::LZCNT16rm,           0 },
 786     { X86::LZCNT32rr,       X86::LZCNT32rm,           0 },
 787     { X86::LZCNT64rr,       X86::LZCNT64rm,           0 },
 788     { X86::POPCNT16rr,      X86::POPCNT16rm,          0 },
 789     { X86::POPCNT32rr,      X86::POPCNT32rm,          0 },
 790     { X86::POPCNT64rr,      X86::POPCNT64rm,          0 },
 791     { X86::RORX32ri,        X86::RORX32mi,            0 },
 792     { X86::RORX64ri,        X86::RORX64mi,            0 },
 793     { X86::SARX32rr,        X86::SARX32rm,            0 },
 794     { X86::SARX64rr,        X86::SARX64rm,            0 },
 795     { X86::SHRX32rr,        X86::SHRX32rm,            0 },
 796     { X86::SHRX64rr,        X86::SHRX64rm,            0 },
 797     { X86::SHLX32rr,        X86::SHLX32rm,            0 },
 798     { X86::SHLX64rr,        X86::SHLX64rm,            0 },
 799     { X86::T1MSKC32rr,      X86::T1MSKC32rm,          0 },
 800     { X86::T1MSKC64rr,      X86::T1MSKC64rm,          0 },
 801     { X86::TZCNT16rr,       X86::TZCNT16rm,           0 },
 802     { X86::TZCNT32rr,       X86::TZCNT32rm,           0 },
 803     { X86::TZCNT64rr,       X86::TZCNT64rm,           0 },
 804     { X86::TZMSK32rr,       X86::TZMSK32rm,           0 },
 805     { X86::TZMSK64rr,       X86::TZMSK64rm,           0 },
 806
 807     // AVX-512 foldable instructions
 808     { X86::VMOV64toPQIZrr,  X86::VMOVQI2PQIZrm,       0 },
 809     { X86::VMOVDI2SSZrr,    X86::VMOVDI2SSZrm,        0 },
 810     { X86::VMOVAPDZrr,      X86::VMOVAPDZrm,          TB_ALIGN_64 },
 811     { X86::VMOVAPSZrr,      X86::VMOVAPSZrm,          TB_ALIGN_64 },
 812     { X86::VMOVDQA32Zrr,    X86::VMOVDQA32Zrm,        TB_ALIGN_64 },
 813     { X86::VMOVDQA64Zrr,    X86::VMOVDQA64Zrm,        TB_ALIGN_64 },
 814     { X86::VMOVDQU8Zrr,     X86::VMOVDQU8Zrm,         0 },
 815     { X86::VMOVDQU16Zrr,    X86::VMOVDQU16Zrm,        0 },
 816     { X86::VMOVDQU32Zrr,    X86::VMOVDQU32Zrm,        0 },
 817     { X86::VMOVDQU64Zrr,    X86::VMOVDQU64Zrm,        0 },
 818     { X86::VMOVUPDZrr,      X86::VMOVUPDZrm,          0 },
 819     { X86::VMOVUPSZrr,      X86::VMOVUPSZrm,          0 },
 820     { X86::VPABSDZrr,       X86::VPABSDZrm,           0 },
 821     { X86::VPABSQZrr,       X86::VPABSQZrm,           0 },
 822     { X86::VBROADCASTSSZr,  X86::VBROADCASTSSZm,      TB_NO_REVERSE },
 823     { X86::VBROADCASTSDZr,  X86::VBROADCASTSDZm,      TB_NO_REVERSE },
 824
 825     // AVX-512 foldable instructions (256-bit versions)
 826     { X86::VMOVAPDZ256rr,      X86::VMOVAPDZ256rm,          TB_ALIGN_32 },
 827     { X86::VMOVAPSZ256rr,      X86::VMOVAPSZ256rm,          TB_ALIGN_32 },
 828     { X86::VMOVDQA32Z256rr,    X86::VMOVDQA32Z256rm,        TB_ALIGN_32 },
 829     { X86::VMOVDQA64Z256rr,    X86::VMOVDQA64Z256rm,        TB_ALIGN_32 },
 830     { X86::VMOVDQU8Z256rr,     X86::VMOVDQU8Z256rm,         0 },
 831     { X86::VMOVDQU16Z256rr,    X86::VMOVDQU16Z256rm,        0 },
 832     { X86::VMOVDQU32Z256rr,    X86::VMOVDQU32Z256rm,        0 },
 833     { X86::VMOVDQU64Z256rr,    X86::VMOVDQU64Z256rm,        0 },
 834     { X86::VMOVUPDZ256rr,      X86::VMOVUPDZ256rm,          0 },
 835     { X86::VMOVUPSZ256rr,      X86::VMOVUPSZ256rm,          0 },
 836     { X86::VBROADCASTSSZ256r,  X86::VBROADCASTSSZ256m,      TB_NO_REVERSE },
 837     { X86::VBROADCASTSDZ256r,  X86::VBROADCASTSDZ256m,      TB_NO_REVERSE },
 838
 839     // AVX-512 foldable instructions (256-bit versions)
 840     { X86::VMOVAPDZ128rr,      X86::VMOVAPDZ128rm,          TB_ALIGN_16 },
 841     { X86::VMOVAPSZ128rr,      X86::VMOVAPSZ128rm,          TB_ALIGN_16 },
 842     { X86::VMOVDQA32Z128rr,    X86::VMOVDQA32Z128rm,        TB_ALIGN_16 },
 843     { X86::VMOVDQA64Z128rr,    X86::VMOVDQA64Z128rm,        TB_ALIGN_16 },
 844     { X86::VMOVDQU8Z128rr,     X86::VMOVDQU8Z128rm,         0 },
 845     { X86::VMOVDQU16Z128rr,    X86::VMOVDQU16Z128rm,        0 },
 846     { X86::VMOVDQU32Z128rr,    X86::VMOVDQU32Z128rm,        0 },
 847     { X86::VMOVDQU64Z128rr,    X86::VMOVDQU64Z128rm,        0 },
 848     { X86::VMOVUPDZ128rr,      X86::VMOVUPDZ128rm,          0 },
 849     { X86::VMOVUPSZ128rr,      X86::VMOVUPSZ128rm,          0 },
 850     { X86::VBROADCASTSSZ128r,  X86::VBROADCASTSSZ128m,      TB_NO_REVERSE },
 851
 852     // F16C foldable instructions
 853     { X86::VCVTPH2PSrr,        X86::VCVTPH2PSrm,            0 },
 854     { X86::VCVTPH2PSYrr,       X86::VCVTPH2PSYrm,           0 },
 855
 856     // AES foldable instructions
 857     { X86::AESIMCrr,              X86::AESIMCrm,              TB_ALIGN_16 },
 858     { X86::AESKEYGENASSIST128rr,  X86::AESKEYGENASSIST128rm,  TB_ALIGN_16 },
 859     { X86::VAESIMCrr,             X86::VAESIMCrm,             0 },
 860     { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, 0 }
 861   };
 862
 863   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable1) {
 864     AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
 865                   Entry.RegOp, Entry.MemOp,
 866                   // Index 1, folded load
 867                   Entry.Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
 868   }
 869
 870   static const X86MemoryFoldTableEntry MemoryFoldTable2[] = {
 871     { X86::ADC32rr,         X86::ADC32rm,       0 },
 872     { X86::ADC64rr,         X86::ADC64rm,       0 },
 873     { X86::ADD16rr,         X86::ADD16rm,       0 },
 874     { X86::ADD16rr_DB,      X86::ADD16rm,       TB_NO_REVERSE },
 875     { X86::ADD32rr,         X86::ADD32rm,       0 },
 876     { X86::ADD32rr_DB,      X86::ADD32rm,       TB_NO_REVERSE },
 877     { X86::ADD64rr,         X86::ADD64rm,       0 },
 878     { X86::ADD64rr_DB,      X86::ADD64rm,       TB_NO_REVERSE },
 879     { X86::ADD8rr,          X86::ADD8rm,        0 },
 880     { X86::ADDPDrr,         X86::ADDPDrm,       TB_ALIGN_16 },
 881     { X86::ADDPSrr,         X86::ADDPSrm,       TB_ALIGN_16 },
 882     { X86::ADDSDrr,         X86::ADDSDrm,       0 },
 883     { X86::ADDSDrr_Int,     X86::ADDSDrm_Int,   0 },
 884     { X86::ADDSSrr,         X86::ADDSSrm,       0 },
 885     { X86::ADDSSrr_Int,     X86::ADDSSrm_Int,   0 },
 886     { X86::ADDSUBPDrr,      X86::ADDSUBPDrm,    TB_ALIGN_16 },
 887     { X86::ADDSUBPSrr,      X86::ADDSUBPSrm,    TB_ALIGN_16 },
 888     { X86::AND16rr,         X86::AND16rm,       0 },
 889     { X86::AND32rr,         X86::AND32rm,       0 },
 890     { X86::AND64rr,         X86::AND64rm,       0 },
 891     { X86::AND8rr,          X86::AND8rm,        0 },
 892     { X86::ANDNPDrr,        X86::ANDNPDrm,      TB_ALIGN_16 },
 893     { X86::ANDNPSrr,        X86::ANDNPSrm,      TB_ALIGN_16 },
 894     { X86::ANDPDrr,         X86::ANDPDrm,       TB_ALIGN_16 },
 895     { X86::ANDPSrr,         X86::ANDPSrm,       TB_ALIGN_16 },
 896     { X86::BLENDPDrri,      X86::BLENDPDrmi,    TB_ALIGN_16 },
 897     { X86::BLENDPSrri,      X86::BLENDPSrmi,    TB_ALIGN_16 },
 898     { X86::BLENDVPDrr0,     X86::BLENDVPDrm0,   TB_ALIGN_16 },
 899     { X86::BLENDVPSrr0,     X86::BLENDVPSrm0,   TB_ALIGN_16 },
 900     { X86::CMOVA16rr,       X86::CMOVA16rm,     0 },
 901     { X86::CMOVA32rr,       X86::CMOVA32rm,     0 },
 902     { X86::CMOVA64rr,       X86::CMOVA64rm,     0 },
 903     { X86::CMOVAE16rr,      X86::CMOVAE16rm,    0 },
 904     { X86::CMOVAE32rr,      X86::CMOVAE32rm,    0 },
 905     { X86::CMOVAE64rr,      X86::CMOVAE64rm,    0 },
 906     { X86::CMOVB16rr,       X86::CMOVB16rm,     0 },
 907     { X86::CMOVB32rr,       X86::CMOVB32rm,     0 },
 908     { X86::CMOVB64rr,       X86::CMOVB64rm,     0 },
 909     { X86::CMOVBE16rr,      X86::CMOVBE16rm,    0 },
 910     { X86::CMOVBE32rr,      X86::CMOVBE32rm,    0 },
 911     { X86::CMOVBE64rr,      X86::CMOVBE64rm,    0 },
 912     { X86::CMOVE16rr,       X86::CMOVE16rm,     0 },
 913     { X86::CMOVE32rr,       X86::CMOVE32rm,     0 },
 914     { X86::CMOVE64rr,       X86::CMOVE64rm,     0 },
 915     { X86::CMOVG16rr,       X86::CMOVG16rm,     0 },
 916     { X86::CMOVG32rr,       X86::CMOVG32rm,     0 },
 917     { X86::CMOVG64rr,       X86::CMOVG64rm,     0 },
 918     { X86::CMOVGE16rr,      X86::CMOVGE16rm,    0 },
 919     { X86::CMOVGE32rr,      X86::CMOVGE32rm,    0 },
 920     { X86::CMOVGE64rr,      X86::CMOVGE64rm,    0 },
 921     { X86::CMOVL16rr,       X86::CMOVL16rm,     0 },
 922     { X86::CMOVL32rr,       X86::CMOVL32rm,     0 },
 923     { X86::CMOVL64rr,       X86::CMOVL64rm,     0 },
 924     { X86::CMOVLE16rr,      X86::CMOVLE16rm,    0 },
 925     { X86::CMOVLE32rr,      X86::CMOVLE32rm,    0 },
 926     { X86::CMOVLE64rr,      X86::CMOVLE64rm,    0 },
 927     { X86::CMOVNE16rr,      X86::CMOVNE16rm,    0 },
 928     { X86::CMOVNE32rr,      X86::CMOVNE32rm,    0 },
 929     { X86::CMOVNE64rr,      X86::CMOVNE64rm,    0 },
 930     { X86::CMOVNO16rr,      X86::CMOVNO16rm,    0 },
 931     { X86::CMOVNO32rr,      X86::CMOVNO32rm,    0 },
 932     { X86::CMOVNO64rr,      X86::CMOVNO64rm,    0 },
 933     { X86::CMOVNP16rr,      X86::CMOVNP16rm,    0 },
 934     { X86::CMOVNP32rr,      X86::CMOVNP32rm,    0 },
 935     { X86::CMOVNP64rr,      X86::CMOVNP64rm,    0 },
 936     { X86::CMOVNS16rr,      X86::CMOVNS16rm,    0 },
 937     { X86::CMOVNS32rr,      X86::CMOVNS32rm,    0 },
 938     { X86::CMOVNS64rr,      X86::CMOVNS64rm,    0 },
 939     { X86::CMOVO16rr,       X86::CMOVO16rm,     0 },
 940     { X86::CMOVO32rr,       X86::CMOVO32rm,     0 },
 941     { X86::CMOVO64rr,       X86::CMOVO64rm,     0 },
 942     { X86::CMOVP16rr,       X86::CMOVP16rm,     0 },
 943     { X86::CMOVP32rr,       X86::CMOVP32rm,     0 },
 944     { X86::CMOVP64rr,       X86::CMOVP64rm,     0 },
 945     { X86::CMOVS16rr,       X86::CMOVS16rm,     0 },
 946     { X86::CMOVS32rr,       X86::CMOVS32rm,     0 },
 947     { X86::CMOVS64rr,       X86::CMOVS64rm,     0 },
 948     { X86::CMPPDrri,        X86::CMPPDrmi,      TB_ALIGN_16 },
 949     { X86::CMPPSrri,        X86::CMPPSrmi,      TB_ALIGN_16 },
 950     { X86::CMPSDrr,         X86::CMPSDrm,       0 },
 951     { X86::CMPSSrr,         X86::CMPSSrm,       0 },
 952     { X86::CRC32r32r32,     X86::CRC32r32m32,   0 },
 953     { X86::CRC32r64r64,     X86::CRC32r64m64,   0 },
 954     { X86::DIVPDrr,         X86::DIVPDrm,       TB_ALIGN_16 },
 955     { X86::DIVPSrr,         X86::DIVPSrm,       TB_ALIGN_16 },
 956     { X86::DIVSDrr,         X86::DIVSDrm,       0 },
 957     { X86::DIVSDrr_Int,     X86::DIVSDrm_Int,   0 },
 958     { X86::DIVSSrr,         X86::DIVSSrm,       0 },
 959     { X86::DIVSSrr_Int,     X86::DIVSSrm_Int,   0 },
 960     { X86::DPPDrri,         X86::DPPDrmi,       TB_ALIGN_16 },
 961     { X86::DPPSrri,         X86::DPPSrmi,       TB_ALIGN_16 },
 962
 963     // Do not fold Fs* scalar logical op loads because there are no scalar
 964     // load variants for these instructions. When folded, the load is required
 965     // to be 128-bits, so the load size would not match.
 966
 967     { X86::FvANDNPDrr,      X86::FvANDNPDrm,    TB_ALIGN_16 },
 968     { X86::FvANDNPSrr,      X86::FvANDNPSrm,    TB_ALIGN_16 },
 969     { X86::FvANDPDrr,       X86::FvANDPDrm,     TB_ALIGN_16 },
 970     { X86::FvANDPSrr,       X86::FvANDPSrm,     TB_ALIGN_16 },
 971     { X86::FvORPDrr,        X86::FvORPDrm,      TB_ALIGN_16 },
 972     { X86::FvORPSrr,        X86::FvORPSrm,      TB_ALIGN_16 },
 973     { X86::FvXORPDrr,       X86::FvXORPDrm,     TB_ALIGN_16 },
 974     { X86::FvXORPSrr,       X86::FvXORPSrm,     TB_ALIGN_16 },
 975     { X86::HADDPDrr,        X86::HADDPDrm,      TB_ALIGN_16 },
 976     { X86::HADDPSrr,        X86::HADDPSrm,      TB_ALIGN_16 },
 977     { X86::HSUBPDrr,        X86::HSUBPDrm,      TB_ALIGN_16 },
 978     { X86::HSUBPSrr,        X86::HSUBPSrm,      TB_ALIGN_16 },
 979     { X86::IMUL16rr,        X86::IMUL16rm,      0 },
 980     { X86::IMUL32rr,        X86::IMUL32rm,      0 },
 981     { X86::IMUL64rr,        X86::IMUL64rm,      0 },
 982     { X86::Int_CMPSDrr,     X86::Int_CMPSDrm,   0 },
 983     { X86::Int_CMPSSrr,     X86::Int_CMPSSrm,   0 },
 984     { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm,      0 },
 985     { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm,    0 },
 986     { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm,      0 },
 987     { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm,    0 },
 988     { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm,      0 },
 989     { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm,      0 },
 990     { X86::MAXPDrr,         X86::MAXPDrm,       TB_ALIGN_16 },
 991     { X86::MAXPSrr,         X86::MAXPSrm,       TB_ALIGN_16 },
 992     { X86::MAXSDrr,         X86::MAXSDrm,       0 },
 993     { X86::MAXSDrr_Int,     X86::MAXSDrm_Int,   0 },
 994     { X86::MAXSSrr,         X86::MAXSSrm,       0 },
 995     { X86::MAXSSrr_Int,     X86::MAXSSrm_Int,   0 },
 996     { X86::MINPDrr,         X86::MINPDrm,       TB_ALIGN_16 },
 997     { X86::MINPSrr,         X86::MINPSrm,       TB_ALIGN_16 },
 998     { X86::MINSDrr,         X86::MINSDrm,       0 },
 999     { X86::MINSDrr_Int,     X86::MINSDrm_Int,   0 },
1000     { X86::MINSSrr,         X86::MINSSrm,       0 },
1001     { X86::MINSSrr_Int,     X86::MINSSrm_Int,   0 },
1002     { X86::MPSADBWrri,      X86::MPSADBWrmi,    TB_ALIGN_16 },
1003     { X86::MULPDrr,         X86::MULPDrm,       TB_ALIGN_16 },
1004     { X86::MULPSrr,         X86::MULPSrm,       TB_ALIGN_16 },
1005     { X86::MULSDrr,         X86::MULSDrm,       0 },
1006     { X86::MULSDrr_Int,     X86::MULSDrm_Int,   0 },
1007     { X86::MULSSrr,         X86::MULSSrm,       0 },
1008     { X86::MULSSrr_Int,     X86::MULSSrm_Int,   0 },
1009     { X86::OR16rr,          X86::OR16rm,        0 },
1010     { X86::OR32rr,          X86::OR32rm,        0 },
1011     { X86::OR64rr,          X86::OR64rm,        0 },
1012     { X86::OR8rr,           X86::OR8rm,         0 },
1013     { X86::ORPDrr,          X86::ORPDrm,        TB_ALIGN_16 },
1014     { X86::ORPSrr,          X86::ORPSrm,        TB_ALIGN_16 },
1015     { X86::PACKSSDWrr,      X86::PACKSSDWrm,    TB_ALIGN_16 },
1016     { X86::PACKSSWBrr,      X86::PACKSSWBrm,    TB_ALIGN_16 },
1017     { X86::PACKUSDWrr,      X86::PACKUSDWrm,    TB_ALIGN_16 },
1018     { X86::PACKUSWBrr,      X86::PACKUSWBrm,    TB_ALIGN_16 },
1019     { X86::PADDBrr,         X86::PADDBrm,       TB_ALIGN_16 },
1020     { X86::PADDDrr,         X86::PADDDrm,       TB_ALIGN_16 },
1021     { X86::PADDQrr,         X86::PADDQrm,       TB_ALIGN_16 },
1022     { X86::PADDSBrr,        X86::PADDSBrm,      TB_ALIGN_16 },
1023     { X86::PADDSWrr,        X86::PADDSWrm,      TB_ALIGN_16 },
1024     { X86::PADDUSBrr,       X86::PADDUSBrm,     TB_ALIGN_16 },
1025     { X86::PADDUSWrr,       X86::PADDUSWrm,     TB_ALIGN_16 },
1026     { X86::PADDWrr,         X86::PADDWrm,       TB_ALIGN_16 },
1027     { X86::PALIGNR128rr,    X86::PALIGNR128rm,  TB_ALIGN_16 },
1028     { X86::PANDNrr,         X86::PANDNrm,       TB_ALIGN_16 },
1029     { X86::PANDrr,          X86::PANDrm,        TB_ALIGN_16 },
1030     { X86::PAVGBrr,         X86::PAVGBrm,       TB_ALIGN_16 },
1031     { X86::PAVGWrr,         X86::PAVGWrm,       TB_ALIGN_16 },
1032     { X86::PBLENDVBrr0,     X86::PBLENDVBrm0,   TB_ALIGN_16 },
1033     { X86::PBLENDWrri,      X86::PBLENDWrmi,    TB_ALIGN_16 },
1034     { X86::PCLMULQDQrr,     X86::PCLMULQDQrm,   TB_ALIGN_16 },
1035     { X86::PCMPEQBrr,       X86::PCMPEQBrm,     TB_ALIGN_16 },
1036     { X86::PCMPEQDrr,       X86::PCMPEQDrm,     TB_ALIGN_16 },
1037     { X86::PCMPEQQrr,       X86::PCMPEQQrm,     TB_ALIGN_16 },
1038     { X86::PCMPEQWrr,       X86::PCMPEQWrm,     TB_ALIGN_16 },
1039     { X86::PCMPGTBrr,       X86::PCMPGTBrm,     TB_ALIGN_16 },
1040     { X86::PCMPGTDrr,       X86::PCMPGTDrm,     TB_ALIGN_16 },
1041     { X86::PCMPGTQrr,       X86::PCMPGTQrm,     TB_ALIGN_16 },
1042     { X86::PCMPGTWrr,       X86::PCMPGTWrm,     TB_ALIGN_16 },
1043     { X86::PHADDDrr,        X86::PHADDDrm,      TB_ALIGN_16 },
1044     { X86::PHADDWrr,        X86::PHADDWrm,      TB_ALIGN_16 },
1045     { X86::PHADDSWrr128,    X86::PHADDSWrm128,  TB_ALIGN_16 },
1046     { X86::PHSUBDrr,        X86::PHSUBDrm,      TB_ALIGN_16 },
1047     { X86::PHSUBSWrr128,    X86::PHSUBSWrm128,  TB_ALIGN_16 },
1048     { X86::PHSUBWrr,        X86::PHSUBWrm,      TB_ALIGN_16 },
1049     { X86::PINSRBrr,        X86::PINSRBrm,      0 },
1050     { X86::PINSRDrr,        X86::PINSRDrm,      0 },
1051     { X86::PINSRQrr,        X86::PINSRQrm,      0 },
1052     { X86::PINSRWrri,       X86::PINSRWrmi,     0 },
1053     { X86::PMADDUBSWrr128,  X86::PMADDUBSWrm128, TB_ALIGN_16 },
1054     { X86::PMADDWDrr,       X86::PMADDWDrm,     TB_ALIGN_16 },
1055     { X86::PMAXSWrr,        X86::PMAXSWrm,      TB_ALIGN_16 },
1056     { X86::PMAXUBrr,        X86::PMAXUBrm,      TB_ALIGN_16 },
1057     { X86::PMINSWrr,        X86::PMINSWrm,      TB_ALIGN_16 },
1058     { X86::PMINUBrr,        X86::PMINUBrm,      TB_ALIGN_16 },
1059     { X86::PMINSBrr,        X86::PMINSBrm,      TB_ALIGN_16 },
1060     { X86::PMINSDrr,        X86::PMINSDrm,      TB_ALIGN_16 },
1061     { X86::PMINUDrr,        X86::PMINUDrm,      TB_ALIGN_16 },
1062     { X86::PMINUWrr,        X86::PMINUWrm,      TB_ALIGN_16 },
1063     { X86::PMAXSBrr,        X86::PMAXSBrm,      TB_ALIGN_16 },
1064     { X86::PMAXSDrr,        X86::PMAXSDrm,      TB_ALIGN_16 },
1065     { X86::PMAXUDrr,        X86::PMAXUDrm,      TB_ALIGN_16 },
1066     { X86::PMAXUWrr,        X86::PMAXUWrm,      TB_ALIGN_16 },
1067     { X86::PMULDQrr,        X86::PMULDQrm,      TB_ALIGN_16 },
1068     { X86::PMULHRSWrr128,   X86::PMULHRSWrm128, TB_ALIGN_16 },
1069     { X86::PMULHUWrr,       X86::PMULHUWrm,     TB_ALIGN_16 },
1070     { X86::PMULHWrr,        X86::PMULHWrm,      TB_ALIGN_16 },
1071     { X86::PMULLDrr,        X86::PMULLDrm,      TB_ALIGN_16 },
1072     { X86::PMULLWrr,        X86::PMULLWrm,      TB_ALIGN_16 },
1073     { X86::PMULUDQrr,       X86::PMULUDQrm,     TB_ALIGN_16 },
1074     { X86::PORrr,           X86::PORrm,         TB_ALIGN_16 },
1075     { X86::PSADBWrr,        X86::PSADBWrm,      TB_ALIGN_16 },
1076     { X86::PSHUFBrr,        X86::PSHUFBrm,      TB_ALIGN_16 },
1077     { X86::PSIGNBrr,        X86::PSIGNBrm,      TB_ALIGN_16 },
1078     { X86::PSIGNWrr,        X86::PSIGNWrm,      TB_ALIGN_16 },
1079     { X86::PSIGNDrr,        X86::PSIGNDrm,      TB_ALIGN_16 },
1080     { X86::PSLLDrr,         X86::PSLLDrm,       TB_ALIGN_16 },
1081     { X86::PSLLQrr,         X86::PSLLQrm,       TB_ALIGN_16 },
1082     { X86::PSLLWrr,         X86::PSLLWrm,       TB_ALIGN_16 },
1083     { X86::PSRADrr,         X86::PSRADrm,       TB_ALIGN_16 },
1084     { X86::PSRAWrr,         X86::PSRAWrm,       TB_ALIGN_16 },
1085     { X86::PSRLDrr,         X86::PSRLDrm,       TB_ALIGN_16 },
1086     { X86::PSRLQrr,         X86::PSRLQrm,       TB_ALIGN_16 },
1087     { X86::PSRLWrr,         X86::PSRLWrm,       TB_ALIGN_16 },
1088     { X86::PSUBBrr,         X86::PSUBBrm,       TB_ALIGN_16 },
1089     { X86::PSUBDrr,         X86::PSUBDrm,       TB_ALIGN_16 },
1090     { X86::PSUBQrr,         X86::PSUBQrm,       TB_ALIGN_16 },
1091     { X86::PSUBSBrr,        X86::PSUBSBrm,      TB_ALIGN_16 },
1092     { X86::PSUBSWrr,        X86::PSUBSWrm,      TB_ALIGN_16 },
1093     { X86::PSUBUSBrr,       X86::PSUBUSBrm,     TB_ALIGN_16 },
1094     { X86::PSUBUSWrr,       X86::PSUBUSWrm,     TB_ALIGN_16 },
1095     { X86::PSUBWrr,         X86::PSUBWrm,       TB_ALIGN_16 },
1096     { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm,   TB_ALIGN_16 },
1097     { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm,   TB_ALIGN_16 },
1098     { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm,  TB_ALIGN_16 },
1099     { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm,   TB_ALIGN_16 },
1100     { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm,   TB_ALIGN_16 },
1101     { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm,   TB_ALIGN_16 },
1102     { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm,  TB_ALIGN_16 },
1103     { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm,   TB_ALIGN_16 },
1104     { X86::PXORrr,          X86::PXORrm,        TB_ALIGN_16 },
1105     { X86::ROUNDSDr,        X86::ROUNDSDm,      0 },
1106     { X86::ROUNDSSr,        X86::ROUNDSSm,      0 },
1107     { X86::SBB32rr,         X86::SBB32rm,       0 },
1108     { X86::SBB64rr,         X86::SBB64rm,       0 },
1109     { X86::SHUFPDrri,       X86::SHUFPDrmi,     TB_ALIGN_16 },
1110     { X86::SHUFPSrri,       X86::SHUFPSrmi,     TB_ALIGN_16 },
1111     { X86::SUB16rr,         X86::SUB16rm,       0 },
1112     { X86::SUB32rr,         X86::SUB32rm,       0 },
1113     { X86::SUB64rr,         X86::SUB64rm,       0 },
1114     { X86::SUB8rr,          X86::SUB8rm,        0 },
1115     { X86::SUBPDrr,         X86::SUBPDrm,       TB_ALIGN_16 },
1116     { X86::SUBPSrr,         X86::SUBPSrm,       TB_ALIGN_16 },
1117     { X86::SUBSDrr,         X86::SUBSDrm,       0 },
1118     { X86::SUBSDrr_Int,     X86::SUBSDrm_Int,   0 },
1119     { X86::SUBSSrr,         X86::SUBSSrm,       0 },
1120     { X86::SUBSSrr_Int,     X86::SUBSSrm_Int,   0 },
1121     // FIXME: TEST*rr -> swapped operand of TEST*mr.
1122     { X86::UNPCKHPDrr,      X86::UNPCKHPDrm,    TB_ALIGN_16 },
1123     { X86::UNPCKHPSrr,      X86::UNPCKHPSrm,    TB_ALIGN_16 },
1124     { X86::UNPCKLPDrr,      X86::UNPCKLPDrm,    TB_ALIGN_16 },
1125     { X86::UNPCKLPSrr,      X86::UNPCKLPSrm,    TB_ALIGN_16 },
1126     { X86::XOR16rr,         X86::XOR16rm,       0 },
1127     { X86::XOR32rr,         X86::XOR32rm,       0 },
1128     { X86::XOR64rr,         X86::XOR64rm,       0 },
1129     { X86::XOR8rr,          X86::XOR8rm,        0 },
1130     { X86::XORPDrr,         X86::XORPDrm,       TB_ALIGN_16 },
1131     { X86::XORPSrr,         X86::XORPSrm,       TB_ALIGN_16 },
1132
1133     // MMX version of foldable instructions
1134     { X86::MMX_CVTPI2PSirr,   X86::MMX_CVTPI2PSirm,   0 },
1135     { X86::MMX_PACKSSDWirr,   X86::MMX_PACKSSDWirm,   0 },
1136     { X86::MMX_PACKSSWBirr,   X86::MMX_PACKSSWBirm,   0 },
1137     { X86::MMX_PACKUSWBirr,   X86::MMX_PACKUSWBirm,   0 },
1138     { X86::MMX_PADDBirr,      X86::MMX_PADDBirm,      0 },
1139     { X86::MMX_PADDDirr,      X86::MMX_PADDDirm,      0 },
1140     { X86::MMX_PADDQirr,      X86::MMX_PADDQirm,      0 },
1141     { X86::MMX_PADDSBirr,     X86::MMX_PADDSBirm,     0 },
1142     { X86::MMX_PADDSWirr,     X86::MMX_PADDSWirm,     0 },
1143     { X86::MMX_PADDUSBirr,    X86::MMX_PADDUSBirm,    0 },
1144     { X86::MMX_PADDUSWirr,    X86::MMX_PADDUSWirm,    0 },
1145     { X86::MMX_PADDWirr,      X86::MMX_PADDWirm,      0 },
1146     { X86::MMX_PALIGNR64irr,  X86::MMX_PALIGNR64irm,  0 },
1147     { X86::MMX_PANDNirr,      X86::MMX_PANDNirm,      0 },
1148     { X86::MMX_PANDirr,       X86::MMX_PANDirm,       0 },
1149     { X86::MMX_PAVGBirr,      X86::MMX_PAVGBirm,      0 },
1150     { X86::MMX_PAVGWirr,      X86::MMX_PAVGWirm,      0 },
1151     { X86::MMX_PCMPEQBirr,    X86::MMX_PCMPEQBirm,    0 },
1152     { X86::MMX_PCMPEQDirr,    X86::MMX_PCMPEQDirm,    0 },
1153     { X86::MMX_PCMPEQWirr,    X86::MMX_PCMPEQWirm,    0 },
1154     { X86::MMX_PCMPGTBirr,    X86::MMX_PCMPGTBirm,    0 },
1155     { X86::MMX_PCMPGTDirr,    X86::MMX_PCMPGTDirm,    0 },
1156     { X86::MMX_PCMPGTWirr,    X86::MMX_PCMPGTWirm,    0 },
1157     { X86::MMX_PHADDSWrr64,   X86::MMX_PHADDSWrm64,   0 },
1158     { X86::MMX_PHADDWrr64,    X86::MMX_PHADDWrm64,    0 },
1159     { X86::MMX_PHADDrr64,     X86::MMX_PHADDrm64,     0 },
1160     { X86::MMX_PHSUBDrr64,    X86::MMX_PHSUBDrm64,    0 },
1161     { X86::MMX_PHSUBSWrr64,   X86::MMX_PHSUBSWrm64,   0 },
1162     { X86::MMX_PHSUBWrr64,    X86::MMX_PHSUBWrm64,    0 },
1163     { X86::MMX_PINSRWirri,    X86::MMX_PINSRWirmi,    0 },
1164     { X86::MMX_PMADDUBSWrr64, X86::MMX_PMADDUBSWrm64, 0 },
1165     { X86::MMX_PMADDWDirr,    X86::MMX_PMADDWDirm,    0 },
1166     { X86::MMX_PMAXSWirr,     X86::MMX_PMAXSWirm,     0 },
1167     { X86::MMX_PMAXUBirr,     X86::MMX_PMAXUBirm,     0 },
1168     { X86::MMX_PMINSWirr,     X86::MMX_PMINSWirm,     0 },
1169     { X86::MMX_PMINUBirr,     X86::MMX_PMINUBirm,     0 },
1170     { X86::MMX_PMULHRSWrr64,  X86::MMX_PMULHRSWrm64,  0 },
1171     { X86::MMX_PMULHUWirr,    X86::MMX_PMULHUWirm,    0 },
1172     { X86::MMX_PMULHWirr,     X86::MMX_PMULHWirm,     0 },
1173     { X86::MMX_PMULLWirr,     X86::MMX_PMULLWirm,     0 },
1174     { X86::MMX_PMULUDQirr,    X86::MMX_PMULUDQirm,    0 },
1175     { X86::MMX_PORirr,        X86::MMX_PORirm,        0 },
1176     { X86::MMX_PSADBWirr,     X86::MMX_PSADBWirm,     0 },
1177     { X86::MMX_PSHUFBrr64,    X86::MMX_PSHUFBrm64,    0 },
1178     { X86::MMX_PSIGNBrr64,    X86::MMX_PSIGNBrm64,    0 },
1179     { X86::MMX_PSIGNDrr64,    X86::MMX_PSIGNDrm64,    0 },
1180     { X86::MMX_PSIGNWrr64,    X86::MMX_PSIGNWrm64,    0 },
1181     { X86::MMX_PSLLDrr,       X86::MMX_PSLLDrm,       0 },
1182     { X86::MMX_PSLLQrr,       X86::MMX_PSLLQrm,       0 },
1183     { X86::MMX_PSLLWrr,       X86::MMX_PSLLWrm,       0 },
1184     { X86::MMX_PSRADrr,       X86::MMX_PSRADrm,       0 },
1185     { X86::MMX_PSRAWrr,       X86::MMX_PSRAWrm,       0 },
1186     { X86::MMX_PSRLDrr,       X86::MMX_PSRLDrm,       0 },
1187     { X86::MMX_PSRLQrr,       X86::MMX_PSRLQrm,       0 },
1188     { X86::MMX_PSRLWrr,       X86::MMX_PSRLWrm,       0 },
1189     { X86::MMX_PSUBBirr,      X86::MMX_PSUBBirm,      0 },
1190     { X86::MMX_PSUBDirr,      X86::MMX_PSUBDirm,      0 },
1191     { X86::MMX_PSUBQirr,      X86::MMX_PSUBQirm,      0 },
1192     { X86::MMX_PSUBSBirr,     X86::MMX_PSUBSBirm,     0 },
1193     { X86::MMX_PSUBSWirr,     X86::MMX_PSUBSWirm,     0 },
1194     { X86::MMX_PSUBUSBirr,    X86::MMX_PSUBUSBirm,    0 },
1195     { X86::MMX_PSUBUSWirr,    X86::MMX_PSUBUSWirm,    0 },
1196     { X86::MMX_PSUBWirr,      X86::MMX_PSUBWirm,      0 },
1197     { X86::MMX_PUNPCKHBWirr,  X86::MMX_PUNPCKHBWirm,  0 },
1198     { X86::MMX_PUNPCKHDQirr,  X86::MMX_PUNPCKHDQirm,  0 },
1199     { X86::MMX_PUNPCKHWDirr,  X86::MMX_PUNPCKHWDirm,  0 },
1200     { X86::MMX_PUNPCKLBWirr,  X86::MMX_PUNPCKLBWirm,  0 },
1201     { X86::MMX_PUNPCKLDQirr,  X86::MMX_PUNPCKLDQirm,  0 },
1202     { X86::MMX_PUNPCKLWDirr,  X86::MMX_PUNPCKLWDirm,  0 },
1203     { X86::MMX_PXORirr,       X86::MMX_PXORirm,       0 },
1204
1205     // 3DNow! version of foldable instructions
1206     { X86::PAVGUSBrr,         X86::PAVGUSBrm,         0 },
1207     { X86::PFACCrr,           X86::PFACCrm,           0 },
1208     { X86::PFADDrr,           X86::PFADDrm,           0 },
1209     { X86::PFCMPEQrr,         X86::PFCMPEQrm,         0 },
1210     { X86::PFCMPGErr,         X86::PFCMPGErm,         0 },
1211     { X86::PFCMPGTrr,         X86::PFCMPGTrm,         0 },
1212     { X86::PFMAXrr,           X86::PFMAXrm,           0 },
1213     { X86::PFMINrr,           X86::PFMINrm,           0 },
1214     { X86::PFMULrr,           X86::PFMULrm,           0 },
1215     { X86::PFNACCrr,          X86::PFNACCrm,          0 },
1216     { X86::PFPNACCrr,         X86::PFPNACCrm,         0 },
1217     { X86::PFRCPIT1rr,        X86::PFRCPIT1rm,        0 },
1218     { X86::PFRCPIT2rr,        X86::PFRCPIT2rm,        0 },
1219     { X86::PFRSQIT1rr,        X86::PFRSQIT1rm,        0 },
1220     { X86::PFSUBrr,           X86::PFSUBrm,           0 },
1221     { X86::PFSUBRrr,          X86::PFSUBRrm,          0 },
1222     { X86::PMULHRWrr,         X86::PMULHRWrm,         0 },
1223
1224     // AVX 128-bit versions of foldable instructions
1225     { X86::VCVTSD2SSrr,       X86::VCVTSD2SSrm,        0 },
1226     { X86::Int_VCVTSD2SSrr,   X86::Int_VCVTSD2SSrm,    0 },
1227     { X86::VCVTSI2SD64rr,     X86::VCVTSI2SD64rm,      0 },
1228     { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm,  0 },
1229     { X86::VCVTSI2SDrr,       X86::VCVTSI2SDrm,        0 },
1230     { X86::Int_VCVTSI2SDrr,   X86::Int_VCVTSI2SDrm,    0 },
1231     { X86::VCVTSI2SS64rr,     X86::VCVTSI2SS64rm,      0 },
1232     { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm,  0 },
1233     { X86::VCVTSI2SSrr,       X86::VCVTSI2SSrm,        0 },
1234     { X86::Int_VCVTSI2SSrr,   X86::Int_VCVTSI2SSrm,    0 },
1235     { X86::VCVTSS2SDrr,       X86::VCVTSS2SDrm,        0 },
1236     { X86::Int_VCVTSS2SDrr,   X86::Int_VCVTSS2SDrm,    0 },
1237     { X86::VRCPSSr,           X86::VRCPSSm,            0 },
1238     { X86::VRCPSSr_Int,       X86::VRCPSSm_Int,        0 },
1239     { X86::VRSQRTSSr,         X86::VRSQRTSSm,          0 },
1240     { X86::VRSQRTSSr_Int,     X86::VRSQRTSSm_Int,      0 },
1241     { X86::VSQRTSDr,          X86::VSQRTSDm,           0 },
1242     { X86::VSQRTSDr_Int,      X86::VSQRTSDm_Int,       0 },
1243     { X86::VSQRTSSr,          X86::VSQRTSSm,           0 },
1244     { X86::VSQRTSSr_Int,      X86::VSQRTSSm_Int,       0 },
1245     { X86::VADDPDrr,          X86::VADDPDrm,           0 },
1246     { X86::VADDPSrr,          X86::VADDPSrm,           0 },
1247     { X86::VADDSDrr,          X86::VADDSDrm,           0 },
1248     { X86::VADDSDrr_Int,      X86::VADDSDrm_Int,       0 },
1249     { X86::VADDSSrr,          X86::VADDSSrm,           0 },
1250     { X86::VADDSSrr_Int,      X86::VADDSSrm_Int,       0 },
1251     { X86::VADDSUBPDrr,       X86::VADDSUBPDrm,        0 },
1252     { X86::VADDSUBPSrr,       X86::VADDSUBPSrm,        0 },
1253     { X86::VANDNPDrr,         X86::VANDNPDrm,          0 },
1254     { X86::VANDNPSrr,         X86::VANDNPSrm,          0 },
1255     { X86::VANDPDrr,          X86::VANDPDrm,           0 },
1256     { X86::VANDPSrr,          X86::VANDPSrm,           0 },
1257     { X86::VBLENDPDrri,       X86::VBLENDPDrmi,        0 },
1258     { X86::VBLENDPSrri,       X86::VBLENDPSrmi,        0 },
1259     { X86::VBLENDVPDrr,       X86::VBLENDVPDrm,        0 },
1260     { X86::VBLENDVPSrr,       X86::VBLENDVPSrm,        0 },
1261     { X86::VCMPPDrri,         X86::VCMPPDrmi,          0 },
1262     { X86::VCMPPSrri,         X86::VCMPPSrmi,          0 },
1263     { X86::VCMPSDrr,          X86::VCMPSDrm,           0 },
1264     { X86::VCMPSSrr,          X86::VCMPSSrm,           0 },
1265     { X86::VDIVPDrr,          X86::VDIVPDrm,           0 },
1266     { X86::VDIVPSrr,          X86::VDIVPSrm,           0 },
1267     { X86::VDIVSDrr,          X86::VDIVSDrm,           0 },
1268     { X86::VDIVSDrr_Int,      X86::VDIVSDrm_Int,       0 },
1269     { X86::VDIVSSrr,          X86::VDIVSSrm,           0 },
1270     { X86::VDIVSSrr_Int,      X86::VDIVSSrm_Int,       0 },
1271     { X86::VDPPDrri,          X86::VDPPDrmi,           0 },
1272     { X86::VDPPSrri,          X86::VDPPSrmi,           0 },
1273     // Do not fold VFs* loads because there are no scalar load variants for
1274     // these instructions. When folded, the load is required to be 128-bits, so
1275     // the load size would not match.
1276     { X86::VFvANDNPDrr,       X86::VFvANDNPDrm,        0 },
1277     { X86::VFvANDNPSrr,       X86::VFvANDNPSrm,        0 },
1278     { X86::VFvANDPDrr,        X86::VFvANDPDrm,         0 },
1279     { X86::VFvANDPSrr,        X86::VFvANDPSrm,         0 },
1280     { X86::VFvORPDrr,         X86::VFvORPDrm,          0 },
1281     { X86::VFvORPSrr,         X86::VFvORPSrm,          0 },
1282     { X86::VFvXORPDrr,        X86::VFvXORPDrm,         0 },
1283     { X86::VFvXORPSrr,        X86::VFvXORPSrm,         0 },
1284     { X86::VHADDPDrr,         X86::VHADDPDrm,          0 },
1285     { X86::VHADDPSrr,         X86::VHADDPSrm,          0 },
1286     { X86::VHSUBPDrr,         X86::VHSUBPDrm,          0 },
1287     { X86::VHSUBPSrr,         X86::VHSUBPSrm,          0 },
1288     { X86::Int_VCMPSDrr,      X86::Int_VCMPSDrm,       0 },
1289     { X86::Int_VCMPSSrr,      X86::Int_VCMPSSrm,       0 },
1290     { X86::VMAXPDrr,          X86::VMAXPDrm,           0 },
1291     { X86::VMAXPSrr,          X86::VMAXPSrm,           0 },
1292     { X86::VMAXSDrr,          X86::VMAXSDrm,           0 },
1293     { X86::VMAXSDrr_Int,      X86::VMAXSDrm_Int,       0 },
1294     { X86::VMAXSSrr,          X86::VMAXSSrm,           0 },
1295     { X86::VMAXSSrr_Int,      X86::VMAXSSrm_Int,       0 },
1296     { X86::VMINPDrr,          X86::VMINPDrm,           0 },
1297     { X86::VMINPSrr,          X86::VMINPSrm,           0 },
1298     { X86::VMINSDrr,          X86::VMINSDrm,           0 },
1299     { X86::VMINSDrr_Int,      X86::VMINSDrm_Int,       0 },
1300     { X86::VMINSSrr,          X86::VMINSSrm,           0 },
1301     { X86::VMINSSrr_Int,      X86::VMINSSrm_Int,       0 },
1302     { X86::VMPSADBWrri,       X86::VMPSADBWrmi,        0 },
1303     { X86::VMULPDrr,          X86::VMULPDrm,           0 },
1304     { X86::VMULPSrr,          X86::VMULPSrm,           0 },
1305     { X86::VMULSDrr,          X86::VMULSDrm,           0 },
1306     { X86::VMULSDrr_Int,      X86::VMULSDrm_Int,       0 },
1307     { X86::VMULSSrr,          X86::VMULSSrm,           0 },
1308     { X86::VMULSSrr_Int,      X86::VMULSSrm_Int,       0 },
1309     { X86::VORPDrr,           X86::VORPDrm,            0 },
1310     { X86::VORPSrr,           X86::VORPSrm,            0 },
1311     { X86::VPACKSSDWrr,       X86::VPACKSSDWrm,        0 },
1312     { X86::VPACKSSWBrr,       X86::VPACKSSWBrm,        0 },
1313     { X86::VPACKUSDWrr,       X86::VPACKUSDWrm,        0 },
1314     { X86::VPACKUSWBrr,       X86::VPACKUSWBrm,        0 },
1315     { X86::VPADDBrr,          X86::VPADDBrm,           0 },
1316     { X86::VPADDDrr,          X86::VPADDDrm,           0 },
1317     { X86::VPADDQrr,          X86::VPADDQrm,           0 },
1318     { X86::VPADDSBrr,         X86::VPADDSBrm,          0 },
1319     { X86::VPADDSWrr,         X86::VPADDSWrm,          0 },
1320     { X86::VPADDUSBrr,        X86::VPADDUSBrm,         0 },
1321     { X86::VPADDUSWrr,        X86::VPADDUSWrm,         0 },
1322     { X86::VPADDWrr,          X86::VPADDWrm,           0 },
1323     { X86::VPALIGNR128rr,     X86::VPALIGNR128rm,      0 },
1324     { X86::VPANDNrr,          X86::VPANDNrm,           0 },
1325     { X86::VPANDrr,           X86::VPANDrm,            0 },
1326     { X86::VPAVGBrr,          X86::VPAVGBrm,           0 },
1327     { X86::VPAVGWrr,          X86::VPAVGWrm,           0 },
1328     { X86::VPBLENDVBrr,       X86::VPBLENDVBrm,        0 },
1329     { X86::VPBLENDWrri,       X86::VPBLENDWrmi,        0 },
1330     { X86::VPCLMULQDQrr,      X86::VPCLMULQDQrm,       0 },
1331     { X86::VPCMPEQBrr,        X86::VPCMPEQBrm,         0 },
1332     { X86::VPCMPEQDrr,        X86::VPCMPEQDrm,         0 },
1333     { X86::VPCMPEQQrr,        X86::VPCMPEQQrm,         0 },
1334     { X86::VPCMPEQWrr,        X86::VPCMPEQWrm,         0 },
1335     { X86::VPCMPGTBrr,        X86::VPCMPGTBrm,         0 },
1336     { X86::VPCMPGTDrr,        X86::VPCMPGTDrm,         0 },
1337     { X86::VPCMPGTQrr,        X86::VPCMPGTQrm,         0 },
1338     { X86::VPCMPGTWrr,        X86::VPCMPGTWrm,         0 },
1339     { X86::VPHADDDrr,         X86::VPHADDDrm,          0 },
1340     { X86::VPHADDSWrr128,     X86::VPHADDSWrm128,      0 },
1341     { X86::VPHADDWrr,         X86::VPHADDWrm,          0 },
1342     { X86::VPHSUBDrr,         X86::VPHSUBDrm,          0 },
1343     { X86::VPHSUBSWrr128,     X86::VPHSUBSWrm128,      0 },
1344     { X86::VPHSUBWrr,         X86::VPHSUBWrm,          0 },
1345     { X86::VPERMILPDrr,       X86::VPERMILPDrm,        0 },
1346     { X86::VPERMILPSrr,       X86::VPERMILPSrm,        0 },
1347     { X86::VPINSRBrr,         X86::VPINSRBrm,          0 },
1348     { X86::VPINSRDrr,         X86::VPINSRDrm,          0 },
1349     { X86::VPINSRQrr,         X86::VPINSRQrm,          0 },
1350     { X86::VPINSRWrri,        X86::VPINSRWrmi,         0 },
1351     { X86::VPMADDUBSWrr128,   X86::VPMADDUBSWrm128,    0 },
1352     { X86::VPMADDWDrr,        X86::VPMADDWDrm,         0 },
1353     { X86::VPMAXSWrr,         X86::VPMAXSWrm,          0 },
1354     { X86::VPMAXUBrr,         X86::VPMAXUBrm,          0 },
1355     { X86::VPMINSWrr,         X86::VPMINSWrm,          0 },
1356     { X86::VPMINUBrr,         X86::VPMINUBrm,          0 },
1357     { X86::VPMINSBrr,         X86::VPMINSBrm,          0 },
1358     { X86::VPMINSDrr,         X86::VPMINSDrm,          0 },
1359     { X86::VPMINUDrr,         X86::VPMINUDrm,          0 },
1360     { X86::VPMINUWrr,         X86::VPMINUWrm,          0 },
1361     { X86::VPMAXSBrr,         X86::VPMAXSBrm,          0 },
1362     { X86::VPMAXSDrr,         X86::VPMAXSDrm,          0 },
1363     { X86::VPMAXUDrr,         X86::VPMAXUDrm,          0 },
1364     { X86::VPMAXUWrr,         X86::VPMAXUWrm,          0 },
1365     { X86::VPMULDQrr,         X86::VPMULDQrm,          0 },
1366     { X86::VPMULHRSWrr128,    X86::VPMULHRSWrm128,     0 },
1367     { X86::VPMULHUWrr,        X86::VPMULHUWrm,         0 },
1368     { X86::VPMULHWrr,         X86::VPMULHWrm,          0 },
1369     { X86::VPMULLDrr,         X86::VPMULLDrm,          0 },
1370     { X86::VPMULLWrr,         X86::VPMULLWrm,          0 },
1371     { X86::VPMULUDQrr,        X86::VPMULUDQrm,         0 },
1372     { X86::VPORrr,            X86::VPORrm,             0 },
1373     { X86::VPSADBWrr,         X86::VPSADBWrm,          0 },
1374     { X86::VPSHUFBrr,         X86::VPSHUFBrm,          0 },
1375     { X86::VPSIGNBrr,         X86::VPSIGNBrm,          0 },
1376     { X86::VPSIGNWrr,         X86::VPSIGNWrm,          0 },
1377     { X86::VPSIGNDrr,         X86::VPSIGNDrm,          0 },
1378     { X86::VPSLLDrr,          X86::VPSLLDrm,           0 },
1379     { X86::VPSLLQrr,          X86::VPSLLQrm,           0 },
1380     { X86::VPSLLWrr,          X86::VPSLLWrm,           0 },
1381     { X86::VPSRADrr,          X86::VPSRADrm,           0 },
1382     { X86::VPSRAWrr,          X86::VPSRAWrm,           0 },
1383     { X86::VPSRLDrr,          X86::VPSRLDrm,           0 },
1384     { X86::VPSRLQrr,          X86::VPSRLQrm,           0 },
1385     { X86::VPSRLWrr,          X86::VPSRLWrm,           0 },
1386     { X86::VPSUBBrr,          X86::VPSUBBrm,           0 },
1387     { X86::VPSUBDrr,          X86::VPSUBDrm,           0 },
1388     { X86::VPSUBQrr,          X86::VPSUBQrm,           0 },
1389     { X86::VPSUBSBrr,         X86::VPSUBSBrm,          0 },
1390     { X86::VPSUBSWrr,         X86::VPSUBSWrm,          0 },
1391     { X86::VPSUBUSBrr,        X86::VPSUBUSBrm,         0 },
1392     { X86::VPSUBUSWrr,        X86::VPSUBUSWrm,         0 },
1393     { X86::VPSUBWrr,          X86::VPSUBWrm,           0 },
1394     { X86::VPUNPCKHBWrr,      X86::VPUNPCKHBWrm,       0 },
1395     { X86::VPUNPCKHDQrr,      X86::VPUNPCKHDQrm,       0 },
1396     { X86::VPUNPCKHQDQrr,     X86::VPUNPCKHQDQrm,      0 },
1397     { X86::VPUNPCKHWDrr,      X86::VPUNPCKHWDrm,       0 },
1398     { X86::VPUNPCKLBWrr,      X86::VPUNPCKLBWrm,       0 },
1399     { X86::VPUNPCKLDQrr,      X86::VPUNPCKLDQrm,       0 },
1400     { X86::VPUNPCKLQDQrr,     X86::VPUNPCKLQDQrm,      0 },
1401     { X86::VPUNPCKLWDrr,      X86::VPUNPCKLWDrm,       0 },
1402     { X86::VPXORrr,           X86::VPXORrm,            0 },
1403     { X86::VROUNDSDr,         X86::VROUNDSDm,          0 },
1404     { X86::VROUNDSSr,         X86::VROUNDSSm,          0 },
1405     { X86::VSHUFPDrri,        X86::VSHUFPDrmi,         0 },
1406     { X86::VSHUFPSrri,        X86::VSHUFPSrmi,         0 },
1407     { X86::VSUBPDrr,          X86::VSUBPDrm,           0 },
1408     { X86::VSUBPSrr,          X86::VSUBPSrm,           0 },
1409     { X86::VSUBSDrr,          X86::VSUBSDrm,           0 },
1410     { X86::VSUBSDrr_Int,      X86::VSUBSDrm_Int,       0 },
1411     { X86::VSUBSSrr,          X86::VSUBSSrm,           0 },
1412     { X86::VSUBSSrr_Int,      X86::VSUBSSrm_Int,       0 },
1413     { X86::VUNPCKHPDrr,       X86::VUNPCKHPDrm,        0 },
1414     { X86::VUNPCKHPSrr,       X86::VUNPCKHPSrm,        0 },
1415     { X86::VUNPCKLPDrr,       X86::VUNPCKLPDrm,        0 },
1416     { X86::VUNPCKLPSrr,       X86::VUNPCKLPSrm,        0 },
1417     { X86::VXORPDrr,          X86::VXORPDrm,           0 },
1418     { X86::VXORPSrr,          X86::VXORPSrm,           0 },
1419
1420     // AVX 256-bit foldable instructions
1421     { X86::VADDPDYrr,         X86::VADDPDYrm,          0 },
1422     { X86::VADDPSYrr,         X86::VADDPSYrm,          0 },
1423     { X86::VADDSUBPDYrr,      X86::VADDSUBPDYrm,       0 },
1424     { X86::VADDSUBPSYrr,      X86::VADDSUBPSYrm,       0 },
1425     { X86::VANDNPDYrr,        X86::VANDNPDYrm,         0 },
1426     { X86::VANDNPSYrr,        X86::VANDNPSYrm,         0 },
1427     { X86::VANDPDYrr,         X86::VANDPDYrm,          0 },
1428     { X86::VANDPSYrr,         X86::VANDPSYrm,          0 },
1429     { X86::VBLENDPDYrri,      X86::VBLENDPDYrmi,       0 },
1430     { X86::VBLENDPSYrri,      X86::VBLENDPSYrmi,       0 },
1431     { X86::VBLENDVPDYrr,      X86::VBLENDVPDYrm,       0 },
1432     { X86::VBLENDVPSYrr,      X86::VBLENDVPSYrm,       0 },
1433     { X86::VCMPPDYrri,        X86::VCMPPDYrmi,         0 },
1434     { X86::VCMPPSYrri,        X86::VCMPPSYrmi,         0 },
1435     { X86::VDIVPDYrr,         X86::VDIVPDYrm,          0 },
1436     { X86::VDIVPSYrr,         X86::VDIVPSYrm,          0 },
1437     { X86::VDPPSYrri,         X86::VDPPSYrmi,          0 },
1438     { X86::VHADDPDYrr,        X86::VHADDPDYrm,         0 },
1439     { X86::VHADDPSYrr,        X86::VHADDPSYrm,         0 },
1440     { X86::VHSUBPDYrr,        X86::VHSUBPDYrm,         0 },
1441     { X86::VHSUBPSYrr,        X86::VHSUBPSYrm,         0 },
1442     { X86::VINSERTF128rr,     X86::VINSERTF128rm,      0 },
1443     { X86::VMAXPDYrr,         X86::VMAXPDYrm,          0 },
1444     { X86::VMAXPSYrr,         X86::VMAXPSYrm,          0 },
1445     { X86::VMINPDYrr,         X86::VMINPDYrm,          0 },
1446     { X86::VMINPSYrr,         X86::VMINPSYrm,          0 },
1447     { X86::VMULPDYrr,         X86::VMULPDYrm,          0 },
1448     { X86::VMULPSYrr,         X86::VMULPSYrm,          0 },
1449     { X86::VORPDYrr,          X86::VORPDYrm,           0 },
1450     { X86::VORPSYrr,          X86::VORPSYrm,           0 },
1451     { X86::VPERM2F128rr,      X86::VPERM2F128rm,       0 },
1452     { X86::VPERMILPDYrr,      X86::VPERMILPDYrm,       0 },
1453     { X86::VPERMILPSYrr,      X86::VPERMILPSYrm,       0 },
1454     { X86::VSHUFPDYrri,       X86::VSHUFPDYrmi,        0 },
1455     { X86::VSHUFPSYrri,       X86::VSHUFPSYrmi,        0 },
1456     { X86::VSUBPDYrr,         X86::VSUBPDYrm,          0 },
1457     { X86::VSUBPSYrr,         X86::VSUBPSYrm,          0 },
1458     { X86::VUNPCKHPDYrr,      X86::VUNPCKHPDYrm,       0 },
1459     { X86::VUNPCKHPSYrr,      X86::VUNPCKHPSYrm,       0 },
1460     { X86::VUNPCKLPDYrr,      X86::VUNPCKLPDYrm,       0 },
1461     { X86::VUNPCKLPSYrr,      X86::VUNPCKLPSYrm,       0 },
1462     { X86::VXORPDYrr,         X86::VXORPDYrm,          0 },
1463     { X86::VXORPSYrr,         X86::VXORPSYrm,          0 },
1464
1465     // AVX2 foldable instructions
1466     { X86::VINSERTI128rr,     X86::VINSERTI128rm,      0 },
1467     { X86::VPACKSSDWYrr,      X86::VPACKSSDWYrm,       0 },
1468     { X86::VPACKSSWBYrr,      X86::VPACKSSWBYrm,       0 },
1469     { X86::VPACKUSDWYrr,      X86::VPACKUSDWYrm,       0 },
1470     { X86::VPACKUSWBYrr,      X86::VPACKUSWBYrm,       0 },
1471     { X86::VPADDBYrr,         X86::VPADDBYrm,          0 },
1472     { X86::VPADDDYrr,         X86::VPADDDYrm,          0 },
1473     { X86::VPADDQYrr,         X86::VPADDQYrm,          0 },
1474     { X86::VPADDSBYrr,        X86::VPADDSBYrm,         0 },
1475     { X86::VPADDSWYrr,        X86::VPADDSWYrm,         0 },
1476     { X86::VPADDUSBYrr,       X86::VPADDUSBYrm,        0 },
1477     { X86::VPADDUSWYrr,       X86::VPADDUSWYrm,        0 },
1478     { X86::VPADDWYrr,         X86::VPADDWYrm,          0 },
1479     { X86::VPALIGNR256rr,     X86::VPALIGNR256rm,      0 },
1480     { X86::VPANDNYrr,         X86::VPANDNYrm,          0 },
1481     { X86::VPANDYrr,          X86::VPANDYrm,           0 },
1482     { X86::VPAVGBYrr,         X86::VPAVGBYrm,          0 },
1483     { X86::VPAVGWYrr,         X86::VPAVGWYrm,          0 },
1484     { X86::VPBLENDDrri,       X86::VPBLENDDrmi,        0 },
1485     { X86::VPBLENDDYrri,      X86::VPBLENDDYrmi,       0 },
1486     { X86::VPBLENDVBYrr,      X86::VPBLENDVBYrm,       0 },
1487     { X86::VPBLENDWYrri,      X86::VPBLENDWYrmi,       0 },
1488     { X86::VPCMPEQBYrr,       X86::VPCMPEQBYrm,        0 },
1489     { X86::VPCMPEQDYrr,       X86::VPCMPEQDYrm,        0 },
1490     { X86::VPCMPEQQYrr,       X86::VPCMPEQQYrm,        0 },
1491     { X86::VPCMPEQWYrr,       X86::VPCMPEQWYrm,        0 },
1492     { X86::VPCMPGTBYrr,       X86::VPCMPGTBYrm,        0 },
1493     { X86::VPCMPGTDYrr,       X86::VPCMPGTDYrm,        0 },
1494     { X86::VPCMPGTQYrr,       X86::VPCMPGTQYrm,        0 },
1495     { X86::VPCMPGTWYrr,       X86::VPCMPGTWYrm,        0 },
1496     { X86::VPERM2I128rr,      X86::VPERM2I128rm,       0 },
1497     { X86::VPERMDYrr,         X86::VPERMDYrm,          0 },
1498     { X86::VPERMPSYrr,        X86::VPERMPSYrm,         0 },
1499     { X86::VPHADDDYrr,        X86::VPHADDDYrm,         0 },
1500     { X86::VPHADDSWrr256,     X86::VPHADDSWrm256,      0 },
1501     { X86::VPHADDWYrr,        X86::VPHADDWYrm,         0 },
1502     { X86::VPHSUBDYrr,        X86::VPHSUBDYrm,         0 },
1503     { X86::VPHSUBSWrr256,     X86::VPHSUBSWrm256,      0 },
1504     { X86::VPHSUBWYrr,        X86::VPHSUBWYrm,         0 },
1505     { X86::VPMADDUBSWrr256,   X86::VPMADDUBSWrm256,    0 },
1506     { X86::VPMADDWDYrr,       X86::VPMADDWDYrm,        0 },
1507     { X86::VPMAXSWYrr,        X86::VPMAXSWYrm,         0 },
1508     { X86::VPMAXUBYrr,        X86::VPMAXUBYrm,         0 },
1509     { X86::VPMINSWYrr,        X86::VPMINSWYrm,         0 },
1510     { X86::VPMINUBYrr,        X86::VPMINUBYrm,         0 },
1511     { X86::VPMINSBYrr,        X86::VPMINSBYrm,         0 },
1512     { X86::VPMINSDYrr,        X86::VPMINSDYrm,         0 },
1513     { X86::VPMINUDYrr,        X86::VPMINUDYrm,         0 },
1514     { X86::VPMINUWYrr,        X86::VPMINUWYrm,         0 },
1515     { X86::VPMAXSBYrr,        X86::VPMAXSBYrm,         0 },
1516     { X86::VPMAXSDYrr,        X86::VPMAXSDYrm,         0 },
1517     { X86::VPMAXUDYrr,        X86::VPMAXUDYrm,         0 },
1518     { X86::VPMAXUWYrr,        X86::VPMAXUWYrm,         0 },
1519     { X86::VMPSADBWYrri,      X86::VMPSADBWYrmi,       0 },
1520     { X86::VPMULDQYrr,        X86::VPMULDQYrm,         0 },
1521     { X86::VPMULHRSWrr256,    X86::VPMULHRSWrm256,     0 },
1522     { X86::VPMULHUWYrr,       X86::VPMULHUWYrm,        0 },
1523     { X86::VPMULHWYrr,        X86::VPMULHWYrm,         0 },
1524     { X86::VPMULLDYrr,        X86::VPMULLDYrm,         0 },
1525     { X86::VPMULLWYrr,        X86::VPMULLWYrm,         0 },
1526     { X86::VPMULUDQYrr,       X86::VPMULUDQYrm,        0 },
1527     { X86::VPORYrr,           X86::VPORYrm,            0 },
1528     { X86::VPSADBWYrr,        X86::VPSADBWYrm,         0 },
1529     { X86::VPSHUFBYrr,        X86::VPSHUFBYrm,         0 },
1530     { X86::VPSIGNBYrr,        X86::VPSIGNBYrm,         0 },
1531     { X86::VPSIGNWYrr,        X86::VPSIGNWYrm,         0 },
1532     { X86::VPSIGNDYrr,        X86::VPSIGNDYrm,         0 },
1533     { X86::VPSLLDYrr,         X86::VPSLLDYrm,          0 },
1534     { X86::VPSLLQYrr,         X86::VPSLLQYrm,          0 },
1535     { X86::VPSLLWYrr,         X86::VPSLLWYrm,          0 },
1536     { X86::VPSLLVDrr,         X86::VPSLLVDrm,          0 },
1537     { X86::VPSLLVDYrr,        X86::VPSLLVDYrm,         0 },
1538     { X86::VPSLLVQrr,         X86::VPSLLVQrm,          0 },
1539     { X86::VPSLLVQYrr,        X86::VPSLLVQYrm,         0 },
1540     { X86::VPSRADYrr,         X86::VPSRADYrm,          0 },
1541     { X86::VPSRAWYrr,         X86::VPSRAWYrm,          0 },
1542     { X86::VPSRAVDrr,         X86::VPSRAVDrm,          0 },
1543     { X86::VPSRAVDYrr,        X86::VPSRAVDYrm,         0 },
1544     { X86::VPSRLDYrr,         X86::VPSRLDYrm,          0 },
1545     { X86::VPSRLQYrr,         X86::VPSRLQYrm,          0 },
1546     { X86::VPSRLWYrr,         X86::VPSRLWYrm,          0 },
1547     { X86::VPSRLVDrr,         X86::VPSRLVDrm,          0 },
1548     { X86::VPSRLVDYrr,        X86::VPSRLVDYrm,         0 },
1549     { X86::VPSRLVQrr,         X86::VPSRLVQrm,          0 },
1550     { X86::VPSRLVQYrr,        X86::VPSRLVQYrm,         0 },
1551     { X86::VPSUBBYrr,         X86::VPSUBBYrm,          0 },
1552     { X86::VPSUBDYrr,         X86::VPSUBDYrm,          0 },
1553     { X86::VPSUBQYrr,         X86::VPSUBQYrm,          0 },
1554     { X86::VPSUBSBYrr,        X86::VPSUBSBYrm,         0 },
1555     { X86::VPSUBSWYrr,        X86::VPSUBSWYrm,         0 },
1556     { X86::VPSUBUSBYrr,       X86::VPSUBUSBYrm,        0 },
1557     { X86::VPSUBUSWYrr,       X86::VPSUBUSWYrm,        0 },
1558     { X86::VPSUBWYrr,         X86::VPSUBWYrm,          0 },
1559     { X86::VPUNPCKHBWYrr,     X86::VPUNPCKHBWYrm,      0 },
1560     { X86::VPUNPCKHDQYrr,     X86::VPUNPCKHDQYrm,      0 },
1561     { X86::VPUNPCKHQDQYrr,    X86::VPUNPCKHQDQYrm,     0 },
1562     { X86::VPUNPCKHWDYrr,     X86::VPUNPCKHWDYrm,      0 },
1563     { X86::VPUNPCKLBWYrr,     X86::VPUNPCKLBWYrm,      0 },
1564     { X86::VPUNPCKLDQYrr,     X86::VPUNPCKLDQYrm,      0 },
1565     { X86::VPUNPCKLQDQYrr,    X86::VPUNPCKLQDQYrm,     0 },
1566     { X86::VPUNPCKLWDYrr,     X86::VPUNPCKLWDYrm,      0 },
1567     { X86::VPXORYrr,          X86::VPXORYrm,           0 },
1568
1569     // FMA4 foldable patterns
1570     { X86::VFMADDSS4rr,       X86::VFMADDSS4mr,        TB_ALIGN_NONE },
1571     { X86::VFMADDSD4rr,       X86::VFMADDSD4mr,        TB_ALIGN_NONE },
1572     { X86::VFMADDPS4rr,       X86::VFMADDPS4mr,        TB_ALIGN_NONE },
1573     { X86::VFMADDPD4rr,       X86::VFMADDPD4mr,        TB_ALIGN_NONE },
1574     { X86::VFMADDPS4rrY,      X86::VFMADDPS4mrY,       TB_ALIGN_NONE },
1575     { X86::VFMADDPD4rrY,      X86::VFMADDPD4mrY,       TB_ALIGN_NONE },
1576     { X86::VFNMADDSS4rr,      X86::VFNMADDSS4mr,       TB_ALIGN_NONE },
1577     { X86::VFNMADDSD4rr,      X86::VFNMADDSD4mr,       TB_ALIGN_NONE },
1578     { X86::VFNMADDPS4rr,      X86::VFNMADDPS4mr,       TB_ALIGN_NONE },
1579     { X86::VFNMADDPD4rr,      X86::VFNMADDPD4mr,       TB_ALIGN_NONE },
1580     { X86::VFNMADDPS4rrY,     X86::VFNMADDPS4mrY,      TB_ALIGN_NONE },
1581     { X86::VFNMADDPD4rrY,     X86::VFNMADDPD4mrY,      TB_ALIGN_NONE },
1582     { X86::VFMSUBSS4rr,       X86::VFMSUBSS4mr,        TB_ALIGN_NONE },
1583     { X86::VFMSUBSD4rr,       X86::VFMSUBSD4mr,        TB_ALIGN_NONE },
1584     { X86::VFMSUBPS4rr,       X86::VFMSUBPS4mr,        TB_ALIGN_NONE },
1585     { X86::VFMSUBPD4rr,       X86::VFMSUBPD4mr,        TB_ALIGN_NONE },
1586     { X86::VFMSUBPS4rrY,      X86::VFMSUBPS4mrY,       TB_ALIGN_NONE },
1587     { X86::VFMSUBPD4rrY,      X86::VFMSUBPD4mrY,       TB_ALIGN_NONE },
1588     { X86::VFNMSUBSS4rr,      X86::VFNMSUBSS4mr,       TB_ALIGN_NONE },
1589     { X86::VFNMSUBSD4rr,      X86::VFNMSUBSD4mr,       TB_ALIGN_NONE },
1590     { X86::VFNMSUBPS4rr,      X86::VFNMSUBPS4mr,       TB_ALIGN_NONE },
1591     { X86::VFNMSUBPD4rr,      X86::VFNMSUBPD4mr,       TB_ALIGN_NONE },
1592     { X86::VFNMSUBPS4rrY,     X86::VFNMSUBPS4mrY,      TB_ALIGN_NONE },
1593     { X86::VFNMSUBPD4rrY,     X86::VFNMSUBPD4mrY,      TB_ALIGN_NONE },
1594     { X86::VFMADDSUBPS4rr,    X86::VFMADDSUBPS4mr,     TB_ALIGN_NONE },
1595     { X86::VFMADDSUBPD4rr,    X86::VFMADDSUBPD4mr,     TB_ALIGN_NONE },
1596     { X86::VFMADDSUBPS4rrY,   X86::VFMADDSUBPS4mrY,    TB_ALIGN_NONE },
1597     { X86::VFMADDSUBPD4rrY,   X86::VFMADDSUBPD4mrY,    TB_ALIGN_NONE },
1598     { X86::VFMSUBADDPS4rr,    X86::VFMSUBADDPS4mr,     TB_ALIGN_NONE },
1599     { X86::VFMSUBADDPD4rr,    X86::VFMSUBADDPD4mr,     TB_ALIGN_NONE },
1600     { X86::VFMSUBADDPS4rrY,   X86::VFMSUBADDPS4mrY,    TB_ALIGN_NONE },
1601     { X86::VFMSUBADDPD4rrY,   X86::VFMSUBADDPD4mrY,    TB_ALIGN_NONE },
1602
1603     // XOP foldable instructions
1604     { X86::VPCMOVrr,          X86::VPCMOVmr,            0 },
1605     { X86::VPCMOVrrY,         X86::VPCMOVmrY,           0 },
1606     { X86::VPCOMBri,          X86::VPCOMBmi,            0 },
1607     { X86::VPCOMDri,          X86::VPCOMDmi,            0 },
1608     { X86::VPCOMQri,          X86::VPCOMQmi,            0 },
1609     { X86::VPCOMWri,          X86::VPCOMWmi,            0 },
1610     { X86::VPCOMUBri,         X86::VPCOMUBmi,           0 },
1611     { X86::VPCOMUDri,         X86::VPCOMUDmi,           0 },
1612     { X86::VPCOMUQri,         X86::VPCOMUQmi,           0 },
1613     { X86::VPCOMUWri,         X86::VPCOMUWmi,           0 },
1614     { X86::VPERMIL2PDrr,      X86::VPERMIL2PDmr,        0 },
1615     { X86::VPERMIL2PDrrY,     X86::VPERMIL2PDmrY,       0 },
1616     { X86::VPERMIL2PSrr,      X86::VPERMIL2PSmr,        0 },
1617     { X86::VPERMIL2PSrrY,     X86::VPERMIL2PSmrY,       0 },
1618     { X86::VPMACSDDrr,        X86::VPMACSDDrm,          0 },
1619     { X86::VPMACSDQHrr,       X86::VPMACSDQHrm,         0 },
1620     { X86::VPMACSDQLrr,       X86::VPMACSDQLrm,         0 },
1621     { X86::VPMACSSDDrr,       X86::VPMACSSDDrm,         0 },
1622     { X86::VPMACSSDQHrr,      X86::VPMACSSDQHrm,        0 },
1623     { X86::VPMACSSDQLrr,      X86::VPMACSSDQLrm,        0 },
1624     { X86::VPMACSSWDrr,       X86::VPMACSSWDrm,         0 },
1625     { X86::VPMACSSWWrr,       X86::VPMACSSWWrm,         0 },
1626     { X86::VPMACSWDrr,        X86::VPMACSWDrm,          0 },
1627     { X86::VPMACSWWrr,        X86::VPMACSWWrm,          0 },
1628     { X86::VPMADCSSWDrr,      X86::VPMADCSSWDrm,        0 },
1629     { X86::VPMADCSWDrr,       X86::VPMADCSWDrm,         0 },
1630     { X86::VPPERMrr,          X86::VPPERMmr,            0 },
1631     { X86::VPROTBrr,          X86::VPROTBrm,            0 },
1632     { X86::VPROTDrr,          X86::VPROTDrm,            0 },
1633     { X86::VPROTQrr,          X86::VPROTQrm,            0 },
1634     { X86::VPROTWrr,          X86::VPROTWrm,            0 },
1635     { X86::VPSHABrr,          X86::VPSHABrm,            0 },
1636     { X86::VPSHADrr,          X86::VPSHADrm,            0 },
1637     { X86::VPSHAQrr,          X86::VPSHAQrm,            0 },
1638     { X86::VPSHAWrr,          X86::VPSHAWrm,            0 },
1639     { X86::VPSHLBrr,          X86::VPSHLBrm,            0 },
1640     { X86::VPSHLDrr,          X86::VPSHLDrm,            0 },
1641     { X86::VPSHLQrr,          X86::VPSHLQrm,            0 },
1642     { X86::VPSHLWrr,          X86::VPSHLWrm,            0 },
1643
1644     // BMI/BMI2 foldable instructions
1645     { X86::ANDN32rr,          X86::ANDN32rm,            0 },
1646     { X86::ANDN64rr,          X86::ANDN64rm,            0 },
1647     { X86::MULX32rr,          X86::MULX32rm,            0 },
1648     { X86::MULX64rr,          X86::MULX64rm,            0 },
1649     { X86::PDEP32rr,          X86::PDEP32rm,            0 },
1650     { X86::PDEP64rr,          X86::PDEP64rm,            0 },
1651     { X86::PEXT32rr,          X86::PEXT32rm,            0 },
1652     { X86::PEXT64rr,          X86::PEXT64rm,            0 },
1653
1654     // ADX foldable instructions
1655     { X86::ADCX32rr,          X86::ADCX32rm,            0 },
1656     { X86::ADCX64rr,          X86::ADCX64rm,            0 },
1657     { X86::ADOX32rr,          X86::ADOX32rm,            0 },
1658     { X86::ADOX64rr,          X86::ADOX64rm,            0 },
1659
1660     // AVX-512 foldable instructions
1661     { X86::VADDPSZrr,         X86::VADDPSZrm,           0 },
1662     { X86::VADDPDZrr,         X86::VADDPDZrm,           0 },
1663     { X86::VSUBPSZrr,         X86::VSUBPSZrm,           0 },
1664     { X86::VSUBPDZrr,         X86::VSUBPDZrm,           0 },
1665     { X86::VMULPSZrr,         X86::VMULPSZrm,           0 },
1666     { X86::VMULPDZrr,         X86::VMULPDZrm,           0 },
1667     { X86::VDIVPSZrr,         X86::VDIVPSZrm,           0 },
1668     { X86::VDIVPDZrr,         X86::VDIVPDZrm,           0 },
1669     { X86::VMINPSZrr,         X86::VMINPSZrm,           0 },
1670     { X86::VMINPDZrr,         X86::VMINPDZrm,           0 },
1671     { X86::VMAXPSZrr,         X86::VMAXPSZrm,           0 },
1672     { X86::VMAXPDZrr,         X86::VMAXPDZrm,           0 },
1673     { X86::VPADDDZrr,         X86::VPADDDZrm,           0 },
1674     { X86::VPADDQZrr,         X86::VPADDQZrm,           0 },
1675     { X86::VPERMPDZri,        X86::VPERMPDZmi,          0 },
1676     { X86::VPERMPSZrr,        X86::VPERMPSZrm,          0 },
1677     { X86::VPMAXSDZrr,        X86::VPMAXSDZrm,          0 },
1678     { X86::VPMAXSQZrr,        X86::VPMAXSQZrm,          0 },
1679     { X86::VPMAXUDZrr,        X86::VPMAXUDZrm,          0 },
1680     { X86::VPMAXUQZrr,        X86::VPMAXUQZrm,          0 },
1681     { X86::VPMINSDZrr,        X86::VPMINSDZrm,          0 },
1682     { X86::VPMINSQZrr,        X86::VPMINSQZrm,          0 },
1683     { X86::VPMINUDZrr,        X86::VPMINUDZrm,          0 },
1684     { X86::VPMINUQZrr,        X86::VPMINUQZrm,          0 },
1685     { X86::VPMULDQZrr,        X86::VPMULDQZrm,          0 },
1686     { X86::VPSLLVDZrr,        X86::VPSLLVDZrm,          0 },
1687     { X86::VPSLLVQZrr,        X86::VPSLLVQZrm,          0 },
1688     { X86::VPSRAVDZrr,        X86::VPSRAVDZrm,          0 },
1689     { X86::VPSRLVDZrr,        X86::VPSRLVDZrm,          0 },
1690     { X86::VPSRLVQZrr,        X86::VPSRLVQZrm,          0 },
1691     { X86::VPSUBDZrr,         X86::VPSUBDZrm,           0 },
1692     { X86::VPSUBQZrr,         X86::VPSUBQZrm,           0 },
1693     { X86::VSHUFPDZrri,       X86::VSHUFPDZrmi,         0 },
1694     { X86::VSHUFPSZrri,       X86::VSHUFPSZrmi,         0 },
1695     { X86::VALIGNQZrri,       X86::VALIGNQZrmi,         0 },
1696     { X86::VALIGNDZrri,       X86::VALIGNDZrmi,         0 },
1697     { X86::VPMULUDQZrr,       X86::VPMULUDQZrm,         0 },
1698     { X86::VBROADCASTSSZrkz,  X86::VBROADCASTSSZmkz,    TB_NO_REVERSE },
1699     { X86::VBROADCASTSDZrkz,  X86::VBROADCASTSDZmkz,    TB_NO_REVERSE },
1700
1701     // AVX-512{F,VL} foldable instructions
1702     { X86::VBROADCASTSSZ256rkz,  X86::VBROADCASTSSZ256mkz,      TB_NO_REVERSE },
1703     { X86::VBROADCASTSDZ256rkz,  X86::VBROADCASTSDZ256mkz,      TB_NO_REVERSE },
1704     { X86::VBROADCASTSSZ128rkz,  X86::VBROADCASTSSZ128mkz,      TB_NO_REVERSE },
1705
1706     // AVX-512{F,VL} foldable instructions
1707     { X86::VADDPDZ128rr,      X86::VADDPDZ128rm,        0 },
1708     { X86::VADDPDZ256rr,      X86::VADDPDZ256rm,        0 },
1709     { X86::VADDPSZ128rr,      X86::VADDPSZ128rm,        0 },
1710     { X86::VADDPSZ256rr,      X86::VADDPSZ256rm,        0 },
1711
1712     // AES foldable instructions
1713     { X86::AESDECLASTrr,      X86::AESDECLASTrm,        TB_ALIGN_16 },
1714     { X86::AESDECrr,          X86::AESDECrm,            TB_ALIGN_16 },
1715     { X86::AESENCLASTrr,      X86::AESENCLASTrm,        TB_ALIGN_16 },
1716     { X86::AESENCrr,          X86::AESENCrm,            TB_ALIGN_16 },
1717     { X86::VAESDECLASTrr,     X86::VAESDECLASTrm,       0 },
1718     { X86::VAESDECrr,         X86::VAESDECrm,           0 },
1719     { X86::VAESENCLASTrr,     X86::VAESENCLASTrm,       0 },
1720     { X86::VAESENCrr,         X86::VAESENCrm,           0 },
1721
1722     // SHA foldable instructions
1723     { X86::SHA1MSG1rr,        X86::SHA1MSG1rm,          TB_ALIGN_16 },
1724     { X86::SHA1MSG2rr,        X86::SHA1MSG2rm,          TB_ALIGN_16 },
1725     { X86::SHA1NEXTErr,       X86::SHA1NEXTErm,         TB_ALIGN_16 },
1726     { X86::SHA1RNDS4rri,      X86::SHA1RNDS4rmi,        TB_ALIGN_16 },
1727     { X86::SHA256MSG1rr,      X86::SHA256MSG1rm,        TB_ALIGN_16 },
1728     { X86::SHA256MSG2rr,      X86::SHA256MSG2rm,        TB_ALIGN_16 },
1729     { X86::SHA256RNDS2rr,     X86::SHA256RNDS2rm,       TB_ALIGN_16 }
1730   };
1731
1732   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2) {
1733     AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
1734                   Entry.RegOp, Entry.MemOp,
1735                   // Index 2, folded load
1736                   Entry.Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
1737   }
1738
1739   static const X86MemoryFoldTableEntry MemoryFoldTable3[] = {
1740     // FMA foldable instructions
1741     { X86::VFMADDSSr231r,         X86::VFMADDSSr231m,         TB_ALIGN_NONE },
1742     { X86::VFMADDSSr231r_Int,     X86::VFMADDSSr231m_Int,     TB_ALIGN_NONE },
1743     { X86::VFMADDSDr231r,         X86::VFMADDSDr231m,         TB_ALIGN_NONE },
1744     { X86::VFMADDSDr231r_Int,     X86::VFMADDSDr231m_Int,     TB_ALIGN_NONE },
1745     { X86::VFMADDSSr132r,         X86::VFMADDSSr132m,         TB_ALIGN_NONE },
1746     { X86::VFMADDSSr132r_Int,     X86::VFMADDSSr132m_Int,     TB_ALIGN_NONE },
1747     { X86::VFMADDSDr132r,         X86::VFMADDSDr132m,         TB_ALIGN_NONE },
1748     { X86::VFMADDSDr132r_Int,     X86::VFMADDSDr132m_Int,     TB_ALIGN_NONE },
1749     { X86::VFMADDSSr213r,         X86::VFMADDSSr213m,         TB_ALIGN_NONE },
1750     { X86::VFMADDSSr213r_Int,     X86::VFMADDSSr213m_Int,     TB_ALIGN_NONE },
1751     { X86::VFMADDSDr213r,         X86::VFMADDSDr213m,         TB_ALIGN_NONE },
1752     { X86::VFMADDSDr213r_Int,     X86::VFMADDSDr213m_Int,     TB_ALIGN_NONE },
1753
1754     { X86::VFMADDPSr231r,         X86::VFMADDPSr231m,         TB_ALIGN_NONE },
1755     { X86::VFMADDPDr231r,         X86::VFMADDPDr231m,         TB_ALIGN_NONE },
1756     { X86::VFMADDPSr132r,         X86::VFMADDPSr132m,         TB_ALIGN_NONE },
1757     { X86::VFMADDPDr132r,         X86::VFMADDPDr132m,         TB_ALIGN_NONE },
1758     { X86::VFMADDPSr213r,         X86::VFMADDPSr213m,         TB_ALIGN_NONE },
1759     { X86::VFMADDPDr213r,         X86::VFMADDPDr213m,         TB_ALIGN_NONE },
1760     { X86::VFMADDPSr231rY,        X86::VFMADDPSr231mY,        TB_ALIGN_NONE },
1761     { X86::VFMADDPDr231rY,        X86::VFMADDPDr231mY,        TB_ALIGN_NONE },
1762     { X86::VFMADDPSr132rY,        X86::VFMADDPSr132mY,        TB_ALIGN_NONE },
1763     { X86::VFMADDPDr132rY,        X86::VFMADDPDr132mY,        TB_ALIGN_NONE },
1764     { X86::VFMADDPSr213rY,        X86::VFMADDPSr213mY,        TB_ALIGN_NONE },
1765     { X86::VFMADDPDr213rY,        X86::VFMADDPDr213mY,        TB_ALIGN_NONE },
1766
1767     { X86::VFNMADDSSr231r,        X86::VFNMADDSSr231m,        TB_ALIGN_NONE },
1768     { X86::VFNMADDSSr231r_Int,    X86::VFNMADDSSr231m_Int,    TB_ALIGN_NONE },
1769     { X86::VFNMADDSDr231r,        X86::VFNMADDSDr231m,        TB_ALIGN_NONE },
1770     { X86::VFNMADDSDr231r_Int,    X86::VFNMADDSDr231m_Int,    TB_ALIGN_NONE },
1771     { X86::VFNMADDSSr132r,        X86::VFNMADDSSr132m,        TB_ALIGN_NONE },
1772     { X86::VFNMADDSSr132r_Int,    X86::VFNMADDSSr132m_Int,    TB_ALIGN_NONE },
1773     { X86::VFNMADDSDr132r,        X86::VFNMADDSDr132m,        TB_ALIGN_NONE },
1774     { X86::VFNMADDSDr132r_Int,    X86::VFNMADDSDr132m_Int,    TB_ALIGN_NONE },
1775     { X86::VFNMADDSSr213r,        X86::VFNMADDSSr213m,        TB_ALIGN_NONE },
1776     { X86::VFNMADDSSr213r_Int,    X86::VFNMADDSSr213m_Int,    TB_ALIGN_NONE },
1777     { X86::VFNMADDSDr213r,        X86::VFNMADDSDr213m,        TB_ALIGN_NONE },
1778     { X86::VFNMADDSDr213r_Int,    X86::VFNMADDSDr213m_Int,    TB_ALIGN_NONE },
1779
1780     { X86::VFNMADDPSr231r,        X86::VFNMADDPSr231m,        TB_ALIGN_NONE },
1781     { X86::VFNMADDPDr231r,        X86::VFNMADDPDr231m,        TB_ALIGN_NONE },
1782     { X86::VFNMADDPSr132r,        X86::VFNMADDPSr132m,        TB_ALIGN_NONE },
1783     { X86::VFNMADDPDr132r,        X86::VFNMADDPDr132m,        TB_ALIGN_NONE },
1784     { X86::VFNMADDPSr213r,        X86::VFNMADDPSr213m,        TB_ALIGN_NONE },
1785     { X86::VFNMADDPDr213r,        X86::VFNMADDPDr213m,        TB_ALIGN_NONE },
1786     { X86::VFNMADDPSr231rY,       X86::VFNMADDPSr231mY,       TB_ALIGN_NONE },
1787     { X86::VFNMADDPDr231rY,       X86::VFNMADDPDr231mY,       TB_ALIGN_NONE },
1788     { X86::VFNMADDPSr132rY,       X86::VFNMADDPSr132mY,       TB_ALIGN_NONE },
1789     { X86::VFNMADDPDr132rY,       X86::VFNMADDPDr132mY,       TB_ALIGN_NONE },
1790     { X86::VFNMADDPSr213rY,       X86::VFNMADDPSr213mY,       TB_ALIGN_NONE },
1791     { X86::VFNMADDPDr213rY,       X86::VFNMADDPDr213mY,       TB_ALIGN_NONE },
1792
1793     { X86::VFMSUBSSr231r,         X86::VFMSUBSSr231m,         TB_ALIGN_NONE },
1794     { X86::VFMSUBSSr231r_Int,     X86::VFMSUBSSr231m_Int,     TB_ALIGN_NONE },
1795     { X86::VFMSUBSDr231r,         X86::VFMSUBSDr231m,         TB_ALIGN_NONE },
1796     { X86::VFMSUBSDr231r_Int,     X86::VFMSUBSDr231m_Int,     TB_ALIGN_NONE },
1797     { X86::VFMSUBSSr132r,         X86::VFMSUBSSr132m,         TB_ALIGN_NONE },
1798     { X86::VFMSUBSSr132r_Int,     X86::VFMSUBSSr132m_Int,     TB_ALIGN_NONE },
1799     { X86::VFMSUBSDr132r,         X86::VFMSUBSDr132m,         TB_ALIGN_NONE },
1800     { X86::VFMSUBSDr132r_Int,     X86::VFMSUBSDr132m_Int,     TB_ALIGN_NONE },
1801     { X86::VFMSUBSSr213r,         X86::VFMSUBSSr213m,         TB_ALIGN_NONE },
1802     { X86::VFMSUBSSr213r_Int,     X86::VFMSUBSSr213m_Int,     TB_ALIGN_NONE },
1803     { X86::VFMSUBSDr213r,         X86::VFMSUBSDr213m,         TB_ALIGN_NONE },
1804     { X86::VFMSUBSDr213r_Int,     X86::VFMSUBSDr213m_Int,     TB_ALIGN_NONE },
1805
1806     { X86::VFMSUBPSr231r,         X86::VFMSUBPSr231m,         TB_ALIGN_NONE },
1807     { X86::VFMSUBPDr231r,         X86::VFMSUBPDr231m,         TB_ALIGN_NONE },
1808     { X86::VFMSUBPSr132r,         X86::VFMSUBPSr132m,         TB_ALIGN_NONE },
1809     { X86::VFMSUBPDr132r,         X86::VFMSUBPDr132m,         TB_ALIGN_NONE },
1810     { X86::VFMSUBPSr213r,         X86::VFMSUBPSr213m,         TB_ALIGN_NONE },
1811     { X86::VFMSUBPDr213r,         X86::VFMSUBPDr213m,         TB_ALIGN_NONE },
1812     { X86::VFMSUBPSr231rY,        X86::VFMSUBPSr231mY,        TB_ALIGN_NONE },
1813     { X86::VFMSUBPDr231rY,        X86::VFMSUBPDr231mY,        TB_ALIGN_NONE },
1814     { X86::VFMSUBPSr132rY,        X86::VFMSUBPSr132mY,        TB_ALIGN_NONE },
1815     { X86::VFMSUBPDr132rY,        X86::VFMSUBPDr132mY,        TB_ALIGN_NONE },
1816     { X86::VFMSUBPSr213rY,        X86::VFMSUBPSr213mY,        TB_ALIGN_NONE },
1817     { X86::VFMSUBPDr213rY,        X86::VFMSUBPDr213mY,        TB_ALIGN_NONE },
1818
1819     { X86::VFNMSUBSSr231r,        X86::VFNMSUBSSr231m,        TB_ALIGN_NONE },
1820     { X86::VFNMSUBSSr231r_Int,    X86::VFNMSUBSSr231m_Int,    TB_ALIGN_NONE },
1821     { X86::VFNMSUBSDr231r,        X86::VFNMSUBSDr231m,        TB_ALIGN_NONE },
1822     { X86::VFNMSUBSDr231r_Int,    X86::VFNMSUBSDr231m_Int,    TB_ALIGN_NONE },
1823     { X86::VFNMSUBSSr132r,        X86::VFNMSUBSSr132m,        TB_ALIGN_NONE },
1824     { X86::VFNMSUBSSr132r_Int,    X86::VFNMSUBSSr132m_Int,    TB_ALIGN_NONE },
1825     { X86::VFNMSUBSDr132r,        X86::VFNMSUBSDr132m,        TB_ALIGN_NONE },
1826     { X86::VFNMSUBSDr132r_Int,    X86::VFNMSUBSDr132m_Int,    TB_ALIGN_NONE },
1827     { X86::VFNMSUBSSr213r,        X86::VFNMSUBSSr213m,        TB_ALIGN_NONE },
1828     { X86::VFNMSUBSSr213r_Int,    X86::VFNMSUBSSr213m_Int,    TB_ALIGN_NONE },
1829     { X86::VFNMSUBSDr213r,        X86::VFNMSUBSDr213m,        TB_ALIGN_NONE },
1830     { X86::VFNMSUBSDr213r_Int,    X86::VFNMSUBSDr213m_Int,    TB_ALIGN_NONE },
1831
1832     { X86::VFNMSUBPSr231r,        X86::VFNMSUBPSr231m,        TB_ALIGN_NONE },
1833     { X86::VFNMSUBPDr231r,        X86::VFNMSUBPDr231m,        TB_ALIGN_NONE },
1834     { X86::VFNMSUBPSr132r,        X86::VFNMSUBPSr132m,        TB_ALIGN_NONE },
1835     { X86::VFNMSUBPDr132r,        X86::VFNMSUBPDr132m,        TB_ALIGN_NONE },
1836     { X86::VFNMSUBPSr213r,        X86::VFNMSUBPSr213m,        TB_ALIGN_NONE },
1837     { X86::VFNMSUBPDr213r,        X86::VFNMSUBPDr213m,        TB_ALIGN_NONE },
1838     { X86::VFNMSUBPSr231rY,       X86::VFNMSUBPSr231mY,       TB_ALIGN_NONE },
1839     { X86::VFNMSUBPDr231rY,       X86::VFNMSUBPDr231mY,       TB_ALIGN_NONE },
1840     { X86::VFNMSUBPSr132rY,       X86::VFNMSUBPSr132mY,       TB_ALIGN_NONE },
1841     { X86::VFNMSUBPDr132rY,       X86::VFNMSUBPDr132mY,       TB_ALIGN_NONE },
1842     { X86::VFNMSUBPSr213rY,       X86::VFNMSUBPSr213mY,       TB_ALIGN_NONE },
1843     { X86::VFNMSUBPDr213rY,       X86::VFNMSUBPDr213mY,       TB_ALIGN_NONE },
1844
1845     { X86::VFMADDSUBPSr231r,      X86::VFMADDSUBPSr231m,      TB_ALIGN_NONE },
1846     { X86::VFMADDSUBPDr231r,      X86::VFMADDSUBPDr231m,      TB_ALIGN_NONE },
1847     { X86::VFMADDSUBPSr132r,      X86::VFMADDSUBPSr132m,      TB_ALIGN_NONE },
1848     { X86::VFMADDSUBPDr132r,      X86::VFMADDSUBPDr132m,      TB_ALIGN_NONE },
1849     { X86::VFMADDSUBPSr213r,      X86::VFMADDSUBPSr213m,      TB_ALIGN_NONE },
1850     { X86::VFMADDSUBPDr213r,      X86::VFMADDSUBPDr213m,      TB_ALIGN_NONE },
1851     { X86::VFMADDSUBPSr231rY,     X86::VFMADDSUBPSr231mY,     TB_ALIGN_NONE },
1852     { X86::VFMADDSUBPDr231rY,     X86::VFMADDSUBPDr231mY,     TB_ALIGN_NONE },
1853     { X86::VFMADDSUBPSr132rY,     X86::VFMADDSUBPSr132mY,     TB_ALIGN_NONE },
1854     { X86::VFMADDSUBPDr132rY,     X86::VFMADDSUBPDr132mY,     TB_ALIGN_NONE },
1855     { X86::VFMADDSUBPSr213rY,     X86::VFMADDSUBPSr213mY,     TB_ALIGN_NONE },
1856     { X86::VFMADDSUBPDr213rY,     X86::VFMADDSUBPDr213mY,     TB_ALIGN_NONE },
1857
1858     { X86::VFMSUBADDPSr231r,      X86::VFMSUBADDPSr231m,      TB_ALIGN_NONE },
1859     { X86::VFMSUBADDPDr231r,      X86::VFMSUBADDPDr231m,      TB_ALIGN_NONE },
1860     { X86::VFMSUBADDPSr132r,      X86::VFMSUBADDPSr132m,      TB_ALIGN_NONE },
1861     { X86::VFMSUBADDPDr132r,      X86::VFMSUBADDPDr132m,      TB_ALIGN_NONE },
1862     { X86::VFMSUBADDPSr213r,      X86::VFMSUBADDPSr213m,      TB_ALIGN_NONE },
1863     { X86::VFMSUBADDPDr213r,      X86::VFMSUBADDPDr213m,      TB_ALIGN_NONE },
1864     { X86::VFMSUBADDPSr231rY,     X86::VFMSUBADDPSr231mY,     TB_ALIGN_NONE },
1865     { X86::VFMSUBADDPDr231rY,     X86::VFMSUBADDPDr231mY,     TB_ALIGN_NONE },
1866     { X86::VFMSUBADDPSr132rY,     X86::VFMSUBADDPSr132mY,     TB_ALIGN_NONE },
1867     { X86::VFMSUBADDPDr132rY,     X86::VFMSUBADDPDr132mY,     TB_ALIGN_NONE },
1868     { X86::VFMSUBADDPSr213rY,     X86::VFMSUBADDPSr213mY,     TB_ALIGN_NONE },
1869     { X86::VFMSUBADDPDr213rY,     X86::VFMSUBADDPDr213mY,     TB_ALIGN_NONE },
1870
1871     // FMA4 foldable patterns
1872     { X86::VFMADDSS4rr,           X86::VFMADDSS4rm,           TB_ALIGN_NONE },
1873     { X86::VFMADDSD4rr,           X86::VFMADDSD4rm,           TB_ALIGN_NONE },
1874     { X86::VFMADDPS4rr,           X86::VFMADDPS4rm,           TB_ALIGN_NONE },
1875     { X86::VFMADDPD4rr,           X86::VFMADDPD4rm,           TB_ALIGN_NONE },
1876     { X86::VFMADDPS4rrY,          X86::VFMADDPS4rmY,          TB_ALIGN_NONE },
1877     { X86::VFMADDPD4rrY,          X86::VFMADDPD4rmY,          TB_ALIGN_NONE },
1878     { X86::VFNMADDSS4rr,          X86::VFNMADDSS4rm,          TB_ALIGN_NONE },
1879     { X86::VFNMADDSD4rr,          X86::VFNMADDSD4rm,          TB_ALIGN_NONE },
1880     { X86::VFNMADDPS4rr,          X86::VFNMADDPS4rm,          TB_ALIGN_NONE },
1881     { X86::VFNMADDPD4rr,          X86::VFNMADDPD4rm,          TB_ALIGN_NONE },
1882     { X86::VFNMADDPS4rrY,         X86::VFNMADDPS4rmY,         TB_ALIGN_NONE },
1883     { X86::VFNMADDPD4rrY,         X86::VFNMADDPD4rmY,         TB_ALIGN_NONE },
1884     { X86::VFMSUBSS4rr,           X86::VFMSUBSS4rm,           TB_ALIGN_NONE },
1885     { X86::VFMSUBSD4rr,           X86::VFMSUBSD4rm,           TB_ALIGN_NONE },
1886     { X86::VFMSUBPS4rr,           X86::VFMSUBPS4rm,           TB_ALIGN_NONE },
1887     { X86::VFMSUBPD4rr,           X86::VFMSUBPD4rm,           TB_ALIGN_NONE },
1888     { X86::VFMSUBPS4rrY,          X86::VFMSUBPS4rmY,          TB_ALIGN_NONE },
1889     { X86::VFMSUBPD4rrY,          X86::VFMSUBPD4rmY,          TB_ALIGN_NONE },
1890     { X86::VFNMSUBSS4rr,          X86::VFNMSUBSS4rm,          TB_ALIGN_NONE },
1891     { X86::VFNMSUBSD4rr,          X86::VFNMSUBSD4rm,          TB_ALIGN_NONE },
1892     { X86::VFNMSUBPS4rr,          X86::VFNMSUBPS4rm,          TB_ALIGN_NONE },
1893     { X86::VFNMSUBPD4rr,          X86::VFNMSUBPD4rm,          TB_ALIGN_NONE },
1894     { X86::VFNMSUBPS4rrY,         X86::VFNMSUBPS4rmY,         TB_ALIGN_NONE },
1895     { X86::VFNMSUBPD4rrY,         X86::VFNMSUBPD4rmY,         TB_ALIGN_NONE },
1896     { X86::VFMADDSUBPS4rr,        X86::VFMADDSUBPS4rm,        TB_ALIGN_NONE },
1897     { X86::VFMADDSUBPD4rr,        X86::VFMADDSUBPD4rm,        TB_ALIGN_NONE },
1898     { X86::VFMADDSUBPS4rrY,       X86::VFMADDSUBPS4rmY,       TB_ALIGN_NONE },
1899     { X86::VFMADDSUBPD4rrY,       X86::VFMADDSUBPD4rmY,       TB_ALIGN_NONE },
1900     { X86::VFMSUBADDPS4rr,        X86::VFMSUBADDPS4rm,        TB_ALIGN_NONE },
1901     { X86::VFMSUBADDPD4rr,        X86::VFMSUBADDPD4rm,        TB_ALIGN_NONE },
1902     { X86::VFMSUBADDPS4rrY,       X86::VFMSUBADDPS4rmY,       TB_ALIGN_NONE },
1903     { X86::VFMSUBADDPD4rrY,       X86::VFMSUBADDPD4rmY,       TB_ALIGN_NONE },
1904
1905     // XOP foldable instructions
1906     { X86::VPCMOVrr,              X86::VPCMOVrm,              0 },
1907     { X86::VPCMOVrrY,             X86::VPCMOVrmY,             0 },
1908     { X86::VPERMIL2PDrr,          X86::VPERMIL2PDrm,          0 },
1909     { X86::VPERMIL2PDrrY,         X86::VPERMIL2PDrmY,         0 },
1910     { X86::VPERMIL2PSrr,          X86::VPERMIL2PSrm,          0 },
1911     { X86::VPERMIL2PSrrY,         X86::VPERMIL2PSrmY,         0 },
1912     { X86::VPPERMrr,              X86::VPPERMrm,              0 },
1913
1914     // AVX-512 VPERMI instructions with 3 source operands.
1915     { X86::VPERMI2Drr,            X86::VPERMI2Drm,            0 },
1916     { X86::VPERMI2Qrr,            X86::VPERMI2Qrm,            0 },
1917     { X86::VPERMI2PSrr,           X86::VPERMI2PSrm,           0 },
1918     { X86::VPERMI2PDrr,           X86::VPERMI2PDrm,           0 },
1919     { X86::VBLENDMPDZrr,          X86::VBLENDMPDZrm,          0 },
1920     { X86::VBLENDMPSZrr,          X86::VBLENDMPSZrm,          0 },
1921     { X86::VPBLENDMDZrr,          X86::VPBLENDMDZrm,          0 },
1922     { X86::VPBLENDMQZrr,          X86::VPBLENDMQZrm,          0 },
1923     { X86::VBROADCASTSSZrk,       X86::VBROADCASTSSZmk,       TB_NO_REVERSE },
1924     { X86::VBROADCASTSDZrk,       X86::VBROADCASTSDZmk,       TB_NO_REVERSE },
1925     { X86::VBROADCASTSSZ256rk,    X86::VBROADCASTSSZ256mk,    TB_NO_REVERSE },
1926     { X86::VBROADCASTSDZ256rk,    X86::VBROADCASTSDZ256mk,    TB_NO_REVERSE },
1927     { X86::VBROADCASTSSZ128rk,    X86::VBROADCASTSSZ128mk,    TB_NO_REVERSE },
1928      // AVX-512 arithmetic instructions
1929     { X86::VADDPSZrrkz,           X86::VADDPSZrmkz,           0 },
1930     { X86::VADDPDZrrkz,           X86::VADDPDZrmkz,           0 },
1931     { X86::VSUBPSZrrkz,           X86::VSUBPSZrmkz,           0 },
1932     { X86::VSUBPDZrrkz,           X86::VSUBPDZrmkz,           0 },
1933     { X86::VMULPSZrrkz,           X86::VMULPSZrmkz,           0 },
1934     { X86::VMULPDZrrkz,           X86::VMULPDZrmkz,           0 },
1935     { X86::VDIVPSZrrkz,           X86::VDIVPSZrmkz,           0 },
1936     { X86::VDIVPDZrrkz,           X86::VDIVPDZrmkz,           0 },
1937     { X86::VMINPSZrrkz,           X86::VMINPSZrmkz,           0 },
1938     { X86::VMINPDZrrkz,           X86::VMINPDZrmkz,           0 },
1939     { X86::VMAXPSZrrkz,           X86::VMAXPSZrmkz,           0 },
1940     { X86::VMAXPDZrrkz,           X86::VMAXPDZrmkz,           0 },
1941     // AVX-512{F,VL} arithmetic instructions 256-bit
1942     { X86::VADDPSZ256rrkz,        X86::VADDPSZ256rmkz,        0 },
1943     { X86::VADDPDZ256rrkz,        X86::VADDPDZ256rmkz,        0 },
1944     { X86::VSUBPSZ256rrkz,        X86::VSUBPSZ256rmkz,        0 },
1945     { X86::VSUBPDZ256rrkz,        X86::VSUBPDZ256rmkz,        0 },
1946     { X86::VMULPSZ256rrkz,        X86::VMULPSZ256rmkz,        0 },
1947     { X86::VMULPDZ256rrkz,        X86::VMULPDZ256rmkz,        0 },
1948     { X86::VDIVPSZ256rrkz,        X86::VDIVPSZ256rmkz,        0 },
1949     { X86::VDIVPDZ256rrkz,        X86::VDIVPDZ256rmkz,        0 },
1950     { X86::VMINPSZ256rrkz,        X86::VMINPSZ256rmkz,        0 },
1951     { X86::VMINPDZ256rrkz,        X86::VMINPDZ256rmkz,        0 },
1952     { X86::VMAXPSZ256rrkz,        X86::VMAXPSZ256rmkz,        0 },
1953     { X86::VMAXPDZ256rrkz,        X86::VMAXPDZ256rmkz,        0 },
1954     // AVX-512{F,VL} arithmetic instructions 128-bit
1955     { X86::VADDPSZ128rrkz,        X86::VADDPSZ128rmkz,        0 },
1956     { X86::VADDPDZ128rrkz,        X86::VADDPDZ128rmkz,        0 },
1957     { X86::VSUBPSZ128rrkz,        X86::VSUBPSZ128rmkz,        0 },
1958     { X86::VSUBPDZ128rrkz,        X86::VSUBPDZ128rmkz,        0 },
1959     { X86::VMULPSZ128rrkz,        X86::VMULPSZ128rmkz,        0 },
1960     { X86::VMULPDZ128rrkz,        X86::VMULPDZ128rmkz,        0 },
1961     { X86::VDIVPSZ128rrkz,        X86::VDIVPSZ128rmkz,        0 },
1962     { X86::VDIVPDZ128rrkz,        X86::VDIVPDZ128rmkz,        0 },
1963     { X86::VMINPSZ128rrkz,        X86::VMINPSZ128rmkz,        0 },
1964     { X86::VMINPDZ128rrkz,        X86::VMINPDZ128rmkz,        0 },
1965     { X86::VMAXPSZ128rrkz,        X86::VMAXPSZ128rmkz,        0 },
1966     { X86::VMAXPDZ128rrkz,        X86::VMAXPDZ128rmkz,        0 }
1967   };
1968
1969   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable3) {
1970     AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
1971                   Entry.RegOp, Entry.MemOp,
1972                   // Index 3, folded load
1973                   Entry.Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
1974   }
1975
1976   static const X86MemoryFoldTableEntry MemoryFoldTable4[] = {
1977      // AVX-512 foldable instructions
1978     { X86::VADDPSZrrk,         X86::VADDPSZrmk,           0 },
1979     { X86::VADDPDZrrk,         X86::VADDPDZrmk,           0 },
1980     { X86::VSUBPSZrrk,         X86::VSUBPSZrmk,           0 },
1981     { X86::VSUBPDZrrk,         X86::VSUBPDZrmk,           0 },
1982     { X86::VMULPSZrrk,         X86::VMULPSZrmk,           0 },
1983     { X86::VMULPDZrrk,         X86::VMULPDZrmk,           0 },
1984     { X86::VDIVPSZrrk,         X86::VDIVPSZrmk,           0 },
1985     { X86::VDIVPDZrrk,         X86::VDIVPDZrmk,           0 },
1986     { X86::VMINPSZrrk,         X86::VMINPSZrmk,           0 },
1987     { X86::VMINPDZrrk,         X86::VMINPDZrmk,           0 },
1988     { X86::VMAXPSZrrk,         X86::VMAXPSZrmk,           0 },
1989     { X86::VMAXPDZrrk,         X86::VMAXPDZrmk,           0 },
1990     // AVX-512{F,VL} foldable instructions 256-bit
1991     { X86::VADDPSZ256rrk,      X86::VADDPSZ256rmk,        0 },
1992     { X86::VADDPDZ256rrk,      X86::VADDPDZ256rmk,        0 },
1993     { X86::VSUBPSZ256rrk,      X86::VSUBPSZ256rmk,        0 },
1994     { X86::VSUBPDZ256rrk,      X86::VSUBPDZ256rmk,        0 },
1995     { X86::VMULPSZ256rrk,      X86::VMULPSZ256rmk,        0 },
1996     { X86::VMULPDZ256rrk,      X86::VMULPDZ256rmk,        0 },
1997     { X86::VDIVPSZ256rrk,      X86::VDIVPSZ256rmk,        0 },
1998     { X86::VDIVPDZ256rrk,      X86::VDIVPDZ256rmk,        0 },
1999     { X86::VMINPSZ256rrk,      X86::VMINPSZ256rmk,        0 },
2000     { X86::VMINPDZ256rrk,      X86::VMINPDZ256rmk,        0 },
2001     { X86::VMAXPSZ256rrk,      X86::VMAXPSZ256rmk,        0 },
2002     { X86::VMAXPDZ256rrk,      X86::VMAXPDZ256rmk,        0 },
2003     // AVX-512{F,VL} foldable instructions 128-bit
2004     { X86::VADDPSZ128rrk,      X86::VADDPSZ128rmk,        0 },
2005     { X86::VADDPDZ128rrk,      X86::VADDPDZ128rmk,        0 },
2006     { X86::VSUBPSZ128rrk,      X86::VSUBPSZ128rmk,        0 },
2007     { X86::VSUBPDZ128rrk,      X86::VSUBPDZ128rmk,        0 },
2008     { X86::VMULPSZ128rrk,      X86::VMULPSZ128rmk,        0 },
2009     { X86::VMULPDZ128rrk,      X86::VMULPDZ128rmk,        0 },
2010     { X86::VDIVPSZ128rrk,      X86::VDIVPSZ128rmk,        0 },
2011     { X86::VDIVPDZ128rrk,      X86::VDIVPDZ128rmk,        0 },
2012     { X86::VMINPSZ128rrk,      X86::VMINPSZ128rmk,        0 },
2013     { X86::VMINPDZ128rrk,      X86::VMINPDZ128rmk,        0 },
2014     { X86::VMAXPSZ128rrk,      X86::VMAXPSZ128rmk,        0 },
2015     { X86::VMAXPDZ128rrk,      X86::VMAXPDZ128rmk,        0 }
2016   };
2017
2018   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable4) {
2019     AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
2020                   Entry.RegOp, Entry.MemOp,
2021                   // Index 4, folded load
2022                   Entry.Flags | TB_INDEX_4 | TB_FOLDED_LOAD);
2023   }
2024 }
2025
2026 void
2027 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
2028                             MemOp2RegOpTableType &M2RTable,
2029                             unsigned RegOp, unsigned MemOp, unsigned Flags) {
2030     if ((Flags & TB_NO_FORWARD) == 0) {
2031       assert(!R2MTable.count(RegOp) && "Duplicate entry!");
2032       R2MTable[RegOp] = std::make_pair(MemOp, Flags);
2033     }
2034     if ((Flags & TB_NO_REVERSE) == 0) {
2035       assert(!M2RTable.count(MemOp) &&
2036            "Duplicated entries in unfolding maps?");
2037       M2RTable[MemOp] = std::make_pair(RegOp, Flags);
2038     }
2039 }
2040
2041 bool
2042 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
2043                                     unsigned &SrcReg, unsigned &DstReg,
2044                                     unsigned &SubIdx) const {
2045   switch (MI.getOpcode()) {
2046   default: break;
2047   case X86::MOVSX16rr8:
2048   case X86::MOVZX16rr8:
2049   case X86::MOVSX32rr8:
2050   case X86::MOVZX32rr8:
2051   case X86::MOVSX64rr8:
2052     if (!Subtarget.is64Bit())
2053       // It's not always legal to reference the low 8-bit of the larger
2054       // register in 32-bit mode.
2055       return false;
2056   case X86::MOVSX32rr16:
2057   case X86::MOVZX32rr16:
2058   case X86::MOVSX64rr16:
2059   case X86::MOVSX64rr32: {
2060     if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
2061       // Be conservative.
2062       return false;
2063     SrcReg = MI.getOperand(1).getReg();
2064     DstReg = MI.getOperand(0).getReg();
2065     switch (MI.getOpcode()) {
2066     default: llvm_unreachable("Unreachable!");
2067     case X86::MOVSX16rr8:
2068     case X86::MOVZX16rr8:
2069     case X86::MOVSX32rr8:
2070     case X86::MOVZX32rr8:
2071     case X86::MOVSX64rr8:
2072       SubIdx = X86::sub_8bit;
2073       break;
2074     case X86::MOVSX32rr16:
2075     case X86::MOVZX32rr16:
2076     case X86::MOVSX64rr16:
2077       SubIdx = X86::sub_16bit;
2078       break;
2079     case X86::MOVSX64rr32:
2080       SubIdx = X86::sub_32bit;
2081       break;
2082     }
2083     return true;
2084   }
2085   }
2086   return false;
2087 }
2088
2089 int X86InstrInfo::getSPAdjust(const MachineInstr *MI) const {
2090   const MachineFunction *MF = MI->getParent()->getParent();
2091   const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
2092
2093   if (MI->getOpcode() == getCallFrameSetupOpcode() ||
2094       MI->getOpcode() == getCallFrameDestroyOpcode()) {
2095     unsigned StackAlign = TFI->getStackAlignment();
2096     int SPAdj = (MI->getOperand(0).getImm() + StackAlign - 1) / StackAlign *
2097                  StackAlign;
2098
2099     SPAdj -= MI->getOperand(1).getImm();
2100
2101     if (MI->getOpcode() == getCallFrameSetupOpcode())
2102       return SPAdj;
2103     else
2104       return -SPAdj;
2105   }
2106
2107   // To know whether a call adjusts the stack, we need information
2108   // that is bound to the following ADJCALLSTACKUP pseudo.
2109   // Look for the next ADJCALLSTACKUP that follows the call.
2110   if (MI->isCall()) {
2111     const MachineBasicBlock* MBB = MI->getParent();
2112     auto I = ++MachineBasicBlock::const_iterator(MI);
2113     for (auto E = MBB->end(); I != E; ++I) {
2114       if (I->getOpcode() == getCallFrameDestroyOpcode() ||
2115           I->isCall())
2116         break;
2117     }
2118
2119     // If we could not find a frame destroy opcode, then it has already
2120     // been simplified, so we don't care.
2121     if (I->getOpcode() != getCallFrameDestroyOpcode())
2122       return 0;
2123
2124     return -(I->getOperand(1).getImm());
2125   }
2126
2127   // Currently handle only PUSHes we can reasonably expect to see
2128   // in call sequences
2129   switch (MI->getOpcode()) {
2130   default:
2131     return 0;
2132   case X86::PUSH32i8:
2133   case X86::PUSH32r:
2134   case X86::PUSH32rmm:
2135   case X86::PUSH32rmr:
2136   case X86::PUSHi32:
2137     return 4;
2138   }
2139 }
2140
2141 /// Return true and the FrameIndex if the specified
2142 /// operand and follow operands form a reference to the stack frame.
2143 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
2144                                   int &FrameIndex) const {
2145   if (MI->getOperand(Op+X86::AddrBaseReg).isFI() &&
2146       MI->getOperand(Op+X86::AddrScaleAmt).isImm() &&
2147       MI->getOperand(Op+X86::AddrIndexReg).isReg() &&
2148       MI->getOperand(Op+X86::AddrDisp).isImm() &&
2149       MI->getOperand(Op+X86::AddrScaleAmt).getImm() == 1 &&
2150       MI->getOperand(Op+X86::AddrIndexReg).getReg() == 0 &&
2151       MI->getOperand(Op+X86::AddrDisp).getImm() == 0) {
2152     FrameIndex = MI->getOperand(Op+X86::AddrBaseReg).getIndex();
2153     return true;
2154   }
2155   return false;
2156 }
2157
2158 static bool isFrameLoadOpcode(int Opcode) {
2159   switch (Opcode) {
2160   default:
2161     return false;
2162   case X86::MOV8rm:
2163   case X86::MOV16rm:
2164   case X86::MOV32rm:
2165   case X86::MOV64rm:
2166   case X86::LD_Fp64m:
2167   case X86::MOVSSrm:
2168   case X86::MOVSDrm:
2169   case X86::MOVAPSrm:
2170   case X86::MOVAPDrm:
2171   case X86::MOVDQArm:
2172   case X86::VMOVSSrm:
2173   case X86::VMOVSDrm:
2174   case X86::VMOVAPSrm:
2175   case X86::VMOVAPDrm:
2176   case X86::VMOVDQArm:
2177   case X86::VMOVUPSYrm:
2178   case X86::VMOVAPSYrm:
2179   case X86::VMOVUPDYrm:
2180   case X86::VMOVAPDYrm:
2181   case X86::VMOVDQUYrm:
2182   case X86::VMOVDQAYrm:
2183   case X86::MMX_MOVD64rm:
2184   case X86::MMX_MOVQ64rm:
2185   case X86::VMOVAPSZrm:
2186   case X86::VMOVUPSZrm:
2187     return true;
2188   }
2189 }
2190
2191 static bool isFrameStoreOpcode(int Opcode) {
2192   switch (Opcode) {
2193   default: break;
2194   case X86::MOV8mr:
2195   case X86::MOV16mr:
2196   case X86::MOV32mr:
2197   case X86::MOV64mr:
2198   case X86::ST_FpP64m:
2199   case X86::MOVSSmr:
2200   case X86::MOVSDmr:
2201   case X86::MOVAPSmr:
2202   case X86::MOVAPDmr:
2203   case X86::MOVDQAmr:
2204   case X86::VMOVSSmr:
2205   case X86::VMOVSDmr:
2206   case X86::VMOVAPSmr:
2207   case X86::VMOVAPDmr:
2208   case X86::VMOVDQAmr:
2209   case X86::VMOVUPSYmr:
2210   case X86::VMOVAPSYmr:
2211   case X86::VMOVUPDYmr:
2212   case X86::VMOVAPDYmr:
2213   case X86::VMOVDQUYmr:
2214   case X86::VMOVDQAYmr:
2215   case X86::VMOVUPSZmr:
2216   case X86::VMOVAPSZmr:
2217   case X86::MMX_MOVD64mr:
2218   case X86::MMX_MOVQ64mr:
2219   case X86::MMX_MOVNTQmr:
2220     return true;
2221   }
2222   return false;
2223 }
2224
2225 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
2226                                            int &FrameIndex) const {
2227   if (isFrameLoadOpcode(MI->getOpcode()))
2228     if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
2229       return MI->getOperand(0).getReg();
2230   return 0;
2231 }
2232
2233 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
2234                                                  int &FrameIndex) const {
2235   if (isFrameLoadOpcode(MI->getOpcode())) {
2236     unsigned Reg;
2237     if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
2238       return Reg;
2239     // Check for post-frame index elimination operations
2240     const MachineMemOperand *Dummy;
2241     return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
2242   }
2243   return 0;
2244 }
2245
2246 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
2247                                           int &FrameIndex) const {
2248   if (isFrameStoreOpcode(MI->getOpcode()))
2249     if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
2250         isFrameOperand(MI, 0, FrameIndex))
2251       return MI->getOperand(X86::AddrNumOperands).getReg();
2252   return 0;
2253 }
2254
2255 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
2256                                                 int &FrameIndex) const {
2257   if (isFrameStoreOpcode(MI->getOpcode())) {
2258     unsigned Reg;
2259     if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
2260       return Reg;
2261     // Check for post-frame index elimination operations
2262     const MachineMemOperand *Dummy;
2263     return hasStoreToStackSlot(MI, Dummy, FrameIndex);
2264   }
2265   return 0;
2266 }
2267
2268 /// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
2269 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
2270   // Don't waste compile time scanning use-def chains of physregs.
2271   if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
2272     return false;
2273   bool isPICBase = false;
2274   for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
2275          E = MRI.def_instr_end(); I != E; ++I) {
2276     MachineInstr *DefMI = &*I;
2277     if (DefMI->getOpcode() != X86::MOVPC32r)
2278       return false;
2279     assert(!isPICBase && "More than one PIC base?");
2280     isPICBase = true;
2281   }
2282   return isPICBase;
2283 }
2284
2285 bool
2286 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
2287                                                 AliasAnalysis *AA) const {
2288   switch (MI->getOpcode()) {
2289   default: break;
2290   case X86::MOV8rm:
2291   case X86::MOV16rm:
2292   case X86::MOV32rm:
2293   case X86::MOV64rm:
2294   case X86::LD_Fp64m:
2295   case X86::MOVSSrm:
2296   case X86::MOVSDrm:
2297   case X86::MOVAPSrm:
2298   case X86::MOVUPSrm:
2299   case X86::MOVAPDrm:
2300   case X86::MOVDQArm:
2301   case X86::MOVDQUrm:
2302   case X86::VMOVSSrm:
2303   case X86::VMOVSDrm:
2304   case X86::VMOVAPSrm:
2305   case X86::VMOVUPSrm:
2306   case X86::VMOVAPDrm:
2307   case X86::VMOVDQArm:
2308   case X86::VMOVDQUrm:
2309   case X86::VMOVAPSYrm:
2310   case X86::VMOVUPSYrm:
2311   case X86::VMOVAPDYrm:
2312   case X86::VMOVDQAYrm:
2313   case X86::VMOVDQUYrm:
2314   case X86::MMX_MOVD64rm:
2315   case X86::MMX_MOVQ64rm:
2316   case X86::FsVMOVAPSrm:
2317   case X86::FsVMOVAPDrm:
2318   case X86::FsMOVAPSrm:
2319   case X86::FsMOVAPDrm:
2320   // AVX-512
2321   case X86::VMOVAPDZ128rm:
2322   case X86::VMOVAPDZ256rm:
2323   case X86::VMOVAPDZrm:
2324   case X86::VMOVAPSZ128rm:
2325   case X86::VMOVAPSZ256rm:
2326   case X86::VMOVAPSZrm:
2327   case X86::VMOVDQA32Z128rm:
2328   case X86::VMOVDQA32Z256rm:
2329   case X86::VMOVDQA32Zrm:
2330   case X86::VMOVDQA64Z128rm:
2331   case X86::VMOVDQA64Z256rm:
2332   case X86::VMOVDQA64Zrm:
2333   case X86::VMOVDQU16Z128rm:
2334   case X86::VMOVDQU16Z256rm:
2335   case X86::VMOVDQU16Zrm:
2336   case X86::VMOVDQU32Z128rm:
2337   case X86::VMOVDQU32Z256rm:
2338   case X86::VMOVDQU32Zrm:
2339   case X86::VMOVDQU64Z128rm:
2340   case X86::VMOVDQU64Z256rm:
2341   case X86::VMOVDQU64Zrm:
2342   case X86::VMOVDQU8Z128rm:
2343   case X86::VMOVDQU8Z256rm:
2344   case X86::VMOVDQU8Zrm:
2345   case X86::VMOVUPSZ128rm:
2346   case X86::VMOVUPSZ256rm:
2347   case X86::VMOVUPSZrm: {
2348     // Loads from constant pools are trivially rematerializable.
2349     if (MI->getOperand(1+X86::AddrBaseReg).isReg() &&
2350         MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
2351         MI->getOperand(1+X86::AddrIndexReg).isReg() &&
2352         MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
2353         MI->isInvariantLoad(AA)) {
2354       unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
2355       if (BaseReg == 0 || BaseReg == X86::RIP)
2356         return true;
2357       // Allow re-materialization of PIC load.
2358       if (!ReMatPICStubLoad && MI->getOperand(1+X86::AddrDisp).isGlobal())
2359         return false;
2360       const MachineFunction &MF = *MI->getParent()->getParent();
2361       const MachineRegisterInfo &MRI = MF.getRegInfo();
2362       return regIsPICBase(BaseReg, MRI);
2363     }
2364     return false;
2365   }
2366
2367   case X86::LEA32r:
2368   case X86::LEA64r: {
2369     if (MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
2370         MI->getOperand(1+X86::AddrIndexReg).isReg() &&
2371         MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
2372         !MI->getOperand(1+X86::AddrDisp).isReg()) {
2373       // lea fi#, lea GV, etc. are all rematerializable.
2374       if (!MI->getOperand(1+X86::AddrBaseReg).isReg())
2375         return true;
2376       unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
2377       if (BaseReg == 0)
2378         return true;
2379       // Allow re-materialization of lea PICBase + x.
2380       const MachineFunction &MF = *MI->getParent()->getParent();
2381       const MachineRegisterInfo &MRI = MF.getRegInfo();
2382       return regIsPICBase(BaseReg, MRI);
2383     }
2384     return false;
2385   }
2386   }
2387
2388   // All other instructions marked M_REMATERIALIZABLE are always trivially
2389   // rematerializable.
2390   return true;
2391 }
2392
2393 bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
2394                                          MachineBasicBlock::iterator I) const {
2395   MachineBasicBlock::iterator E = MBB.end();
2396
2397   // For compile time consideration, if we are not able to determine the
2398   // safety after visiting 4 instructions in each direction, we will assume
2399   // it's not safe.
2400   MachineBasicBlock::iterator Iter = I;
2401   for (unsigned i = 0; Iter != E && i < 4; ++i) {
2402     bool SeenDef = false;
2403     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2404       MachineOperand &MO = Iter->getOperand(j);
2405       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2406         SeenDef = true;
2407       if (!MO.isReg())
2408         continue;
2409       if (MO.getReg() == X86::EFLAGS) {
2410         if (MO.isUse())
2411           return false;
2412         SeenDef = true;
2413       }
2414     }
2415
2416     if (SeenDef)
2417       // This instruction defines EFLAGS, no need to look any further.
2418       return true;
2419     ++Iter;
2420     // Skip over DBG_VALUE.
2421     while (Iter != E && Iter->isDebugValue())
2422       ++Iter;
2423   }
2424
2425   // It is safe to clobber EFLAGS at the end of a block of no successor has it
2426   // live in.
2427   if (Iter == E) {
2428     for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(),
2429            SE = MBB.succ_end(); SI != SE; ++SI)
2430       if ((*SI)->isLiveIn(X86::EFLAGS))
2431         return false;
2432     return true;
2433   }
2434
2435   MachineBasicBlock::iterator B = MBB.begin();
2436   Iter = I;
2437   for (unsigned i = 0; i < 4; ++i) {
2438     // If we make it to the beginning of the block, it's safe to clobber
2439     // EFLAGS iff EFLAGS is not live-in.
2440     if (Iter == B)
2441       return !MBB.isLiveIn(X86::EFLAGS);
2442
2443     --Iter;
2444     // Skip over DBG_VALUE.
2445     while (Iter != B && Iter->isDebugValue())
2446       --Iter;
2447
2448     bool SawKill = false;
2449     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2450       MachineOperand &MO = Iter->getOperand(j);
2451       // A register mask may clobber EFLAGS, but we should still look for a
2452       // live EFLAGS def.
2453       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2454         SawKill = true;
2455       if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
2456         if (MO.isDef()) return MO.isDead();
2457         if (MO.isKill()) SawKill = true;
2458       }
2459     }
2460
2461     if (SawKill)
2462       // This instruction kills EFLAGS and doesn't redefine it, so
2463       // there's no need to look further.
2464       return true;
2465   }
2466
2467   // Conservative answer.
2468   return false;
2469 }
2470
2471 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
2472                                  MachineBasicBlock::iterator I,
2473                                  unsigned DestReg, unsigned SubIdx,
2474                                  const MachineInstr *Orig,
2475                                  const TargetRegisterInfo &TRI) const {
2476   bool ClobbersEFLAGS = false;
2477   for (const MachineOperand &MO : Orig->operands()) {
2478     if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
2479       ClobbersEFLAGS = true;
2480       break;
2481     }
2482   }
2483
2484   if (ClobbersEFLAGS && !isSafeToClobberEFLAGS(MBB, I)) {
2485     // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
2486     // effects.
2487     int Value;
2488     switch (Orig->getOpcode()) {
2489     case X86::MOV32r0:  Value = 0; break;
2490     case X86::MOV32r1:  Value = 1; break;
2491     case X86::MOV32r_1: Value = -1; break;
2492     default:
2493       llvm_unreachable("Unexpected instruction!");
2494     }
2495
2496     DebugLoc DL = Orig->getDebugLoc();
2497     BuildMI(MBB, I, DL, get(X86::MOV32ri)).addOperand(Orig->getOperand(0))
2498       .addImm(Value);
2499   } else {
2500     MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
2501     MBB.insert(I, MI);
2502   }
2503
2504   MachineInstr *NewMI = std::prev(I);
2505   NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
2506 }
2507
2508 /// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
2509 bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr *MI) const {
2510   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2511     MachineOperand &MO = MI->getOperand(i);
2512     if (MO.isReg() && MO.isDef() &&
2513         MO.getReg() == X86::EFLAGS && !MO.isDead()) {
2514       return true;
2515     }
2516   }
2517   return false;
2518 }
2519
2520 /// Check whether the shift count for a machine operand is non-zero.
2521 inline static unsigned getTruncatedShiftCount(MachineInstr *MI,
2522                                               unsigned ShiftAmtOperandIdx) {
2523   // The shift count is six bits with the REX.W prefix and five bits without.
2524   unsigned ShiftCountMask = (MI->getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
2525   unsigned Imm = MI->getOperand(ShiftAmtOperandIdx).getImm();
2526   return Imm & ShiftCountMask;
2527 }
2528
2529 /// Check whether the given shift count is appropriate
2530 /// can be represented by a LEA instruction.
2531 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
2532   // Left shift instructions can be transformed into load-effective-address
2533   // instructions if we can encode them appropriately.
2534   // A LEA instruction utilizes a SIB byte to encode its scale factor.
2535   // The SIB.scale field is two bits wide which means that we can encode any
2536   // shift amount less than 4.
2537   return ShAmt < 4 && ShAmt > 0;
2538 }
2539
2540 bool X86InstrInfo::classifyLEAReg(MachineInstr *MI, const MachineOperand &Src,
2541                                   unsigned Opc, bool AllowSP,
2542                                   unsigned &NewSrc, bool &isKill, bool &isUndef,
2543                                   MachineOperand &ImplicitOp) const {
2544   MachineFunction &MF = *MI->getParent()->getParent();
2545   const TargetRegisterClass *RC;
2546   if (AllowSP) {
2547     RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
2548   } else {
2549     RC = Opc != X86::LEA32r ?
2550       &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
2551   }
2552   unsigned SrcReg = Src.getReg();
2553
2554   // For both LEA64 and LEA32 the register already has essentially the right
2555   // type (32-bit or 64-bit) we may just need to forbid SP.
2556   if (Opc != X86::LEA64_32r) {
2557     NewSrc = SrcReg;
2558     isKill = Src.isKill();
2559     isUndef = Src.isUndef();
2560
2561     if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
2562         !MF.getRegInfo().constrainRegClass(NewSrc, RC))
2563       return false;
2564
2565     return true;
2566   }
2567
2568   // This is for an LEA64_32r and incoming registers are 32-bit. One way or
2569   // another we need to add 64-bit registers to the final MI.
2570   if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
2571     ImplicitOp = Src;
2572     ImplicitOp.setImplicit();
2573
2574     NewSrc = getX86SubSuperRegister(Src.getReg(), MVT::i64);
2575     MachineBasicBlock::LivenessQueryResult LQR =
2576       MI->getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI);
2577
2578     switch (LQR) {
2579     case MachineBasicBlock::LQR_Unknown:
2580       // We can't give sane liveness flags to the instruction, abandon LEA
2581       // formation.
2582       return false;
2583     case MachineBasicBlock::LQR_Live:
2584       isKill = MI->killsRegister(SrcReg);
2585       isUndef = false;
2586       break;
2587     default:
2588       // The physreg itself is dead, so we have to use it as an <undef>.
2589       isKill = false;
2590       isUndef = true;
2591       break;
2592     }
2593   } else {
2594     // Virtual register of the wrong class, we have to create a temporary 64-bit
2595     // vreg to feed into the LEA.
2596     NewSrc = MF.getRegInfo().createVirtualRegister(RC);
2597     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
2598             get(TargetOpcode::COPY))
2599       .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
2600         .addOperand(Src);
2601
2602     // Which is obviously going to be dead after we're done with it.
2603     isKill = true;
2604     isUndef = false;
2605   }
2606
2607   // We've set all the parameters without issue.
2608   return true;
2609 }
2610
2611 /// Helper for convertToThreeAddress when 16-bit LEA is disabled, use 32-bit
2612 /// LEA to form 3-address code by promoting to a 32-bit superregister and then
2613 /// truncating back down to a 16-bit subregister.
2614 MachineInstr *
2615 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
2616                                            MachineFunction::iterator &MFI,
2617                                            MachineBasicBlock::iterator &MBBI,
2618                                            LiveVariables *LV) const {
2619   MachineInstr *MI = MBBI;
2620   unsigned Dest = MI->getOperand(0).getReg();
2621   unsigned Src = MI->getOperand(1).getReg();
2622   bool isDead = MI->getOperand(0).isDead();
2623   bool isKill = MI->getOperand(1).isKill();
2624
2625   MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
2626   unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
2627   unsigned Opc, leaInReg;
2628   if (Subtarget.is64Bit()) {
2629     Opc = X86::LEA64_32r;
2630     leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2631   } else {
2632     Opc = X86::LEA32r;
2633     leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2634   }
2635
2636   // Build and insert into an implicit UNDEF value. This is OK because
2637   // well be shifting and then extracting the lower 16-bits.
2638   // This has the potential to cause partial register stall. e.g.
2639   //   movw    (%rbp,%rcx,2), %dx
2640   //   leal    -65(%rdx), %esi
2641   // But testing has shown this *does* help performance in 64-bit mode (at
2642   // least on modern x86 machines).
2643   BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
2644   MachineInstr *InsMI =
2645     BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2646     .addReg(leaInReg, RegState::Define, X86::sub_16bit)
2647     .addReg(Src, getKillRegState(isKill));
2648
2649   MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
2650                                     get(Opc), leaOutReg);
2651   switch (MIOpc) {
2652   default: llvm_unreachable("Unreachable!");
2653   case X86::SHL16ri: {
2654     unsigned ShAmt = MI->getOperand(2).getImm();
2655     MIB.addReg(0).addImm(1 << ShAmt)
2656        .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
2657     break;
2658   }
2659   case X86::INC16r:
2660     addRegOffset(MIB, leaInReg, true, 1);
2661     break;
2662   case X86::DEC16r:
2663     addRegOffset(MIB, leaInReg, true, -1);
2664     break;
2665   case X86::ADD16ri:
2666   case X86::ADD16ri8:
2667   case X86::ADD16ri_DB:
2668   case X86::ADD16ri8_DB:
2669     addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
2670     break;
2671   case X86::ADD16rr:
2672   case X86::ADD16rr_DB: {
2673     unsigned Src2 = MI->getOperand(2).getReg();
2674     bool isKill2 = MI->getOperand(2).isKill();
2675     unsigned leaInReg2 = 0;
2676     MachineInstr *InsMI2 = nullptr;
2677     if (Src == Src2) {
2678       // ADD16rr %reg1028<kill>, %reg1028
2679       // just a single insert_subreg.
2680       addRegReg(MIB, leaInReg, true, leaInReg, false);
2681     } else {
2682       if (Subtarget.is64Bit())
2683         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2684       else
2685         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2686       // Build and insert into an implicit UNDEF value. This is OK because
2687       // well be shifting and then extracting the lower 16-bits.
2688       BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
2689       InsMI2 =
2690         BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
2691         .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
2692         .addReg(Src2, getKillRegState(isKill2));
2693       addRegReg(MIB, leaInReg, true, leaInReg2, true);
2694     }
2695     if (LV && isKill2 && InsMI2)
2696       LV->replaceKillInstruction(Src2, MI, InsMI2);
2697     break;
2698   }
2699   }
2700
2701   MachineInstr *NewMI = MIB;
2702   MachineInstr *ExtMI =
2703     BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2704     .addReg(Dest, RegState::Define | getDeadRegState(isDead))
2705     .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
2706
2707   if (LV) {
2708     // Update live variables
2709     LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
2710     LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
2711     if (isKill)
2712       LV->replaceKillInstruction(Src, MI, InsMI);
2713     if (isDead)
2714       LV->replaceKillInstruction(Dest, MI, ExtMI);
2715   }
2716
2717   return ExtMI;
2718 }
2719
2720 /// This method must be implemented by targets that
2721 /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
2722 /// may be able to convert a two-address instruction into a true
2723 /// three-address instruction on demand.  This allows the X86 target (for
2724 /// example) to convert ADD and SHL instructions into LEA instructions if they
2725 /// would require register copies due to two-addressness.
2726 ///
2727 /// This method returns a null pointer if the transformation cannot be
2728 /// performed, otherwise it returns the new instruction.
2729 ///
2730 MachineInstr *
2731 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
2732                                     MachineBasicBlock::iterator &MBBI,
2733                                     LiveVariables *LV) const {
2734   MachineInstr *MI = MBBI;
2735
2736   // The following opcodes also sets the condition code register(s). Only
2737   // convert them to equivalent lea if the condition code register def's
2738   // are dead!
2739   if (hasLiveCondCodeDef(MI))
2740     return nullptr;
2741
2742   MachineFunction &MF = *MI->getParent()->getParent();
2743   // All instructions input are two-addr instructions.  Get the known operands.
2744   const MachineOperand &Dest = MI->getOperand(0);
2745   const MachineOperand &Src = MI->getOperand(1);
2746
2747   MachineInstr *NewMI = nullptr;
2748   // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's.  When
2749   // we have better subtarget support, enable the 16-bit LEA generation here.
2750   // 16-bit LEA is also slow on Core2.
2751   bool DisableLEA16 = true;
2752   bool is64Bit = Subtarget.is64Bit();
2753
2754   unsigned MIOpc = MI->getOpcode();
2755   switch (MIOpc) {
2756   default: return nullptr;
2757   case X86::SHL64ri: {
2758     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2759     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2760     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2761
2762     // LEA can't handle RSP.
2763     if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
2764         !MF.getRegInfo().constrainRegClass(Src.getReg(),
2765                                            &X86::GR64_NOSPRegClass))
2766       return nullptr;
2767
2768     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2769       .addOperand(Dest)
2770       .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
2771     break;
2772   }
2773   case X86::SHL32ri: {
2774     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2775     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2776     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2777
2778     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2779
2780     // LEA can't handle ESP.
2781     bool isKill, isUndef;
2782     unsigned SrcReg;
2783     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2784     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2785                         SrcReg, isKill, isUndef, ImplicitOp))
2786       return nullptr;
2787
2788     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2789       .addOperand(Dest)
2790       .addReg(0).addImm(1 << ShAmt)
2791       .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
2792       .addImm(0).addReg(0);
2793     if (ImplicitOp.getReg() != 0)
2794       MIB.addOperand(ImplicitOp);
2795     NewMI = MIB;
2796
2797     break;
2798   }
2799   case X86::SHL16ri: {
2800     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2801     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2802     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2803
2804     if (DisableLEA16)
2805       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : nullptr;
2806     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2807       .addOperand(Dest)
2808       .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
2809     break;
2810   }
2811   case X86::INC64r:
2812   case X86::INC32r: {
2813     assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2814     unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
2815       : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2816     bool isKill, isUndef;
2817     unsigned SrcReg;
2818     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2819     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2820                         SrcReg, isKill, isUndef, ImplicitOp))
2821       return nullptr;
2822
2823     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2824         .addOperand(Dest)
2825         .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef));
2826     if (ImplicitOp.getReg() != 0)
2827       MIB.addOperand(ImplicitOp);
2828
2829     NewMI = addOffset(MIB, 1);
2830     break;
2831   }
2832   case X86::INC16r:
2833     if (DisableLEA16)
2834       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2835                      : nullptr;
2836     assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2837     NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2838                       .addOperand(Dest).addOperand(Src), 1);
2839     break;
2840   case X86::DEC64r:
2841   case X86::DEC32r: {
2842     assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2843     unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
2844       : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2845
2846     bool isKill, isUndef;
2847     unsigned SrcReg;
2848     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2849     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2850                         SrcReg, isKill, isUndef, ImplicitOp))
2851       return nullptr;
2852
2853     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2854         .addOperand(Dest)
2855         .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2856     if (ImplicitOp.getReg() != 0)
2857       MIB.addOperand(ImplicitOp);
2858
2859     NewMI = addOffset(MIB, -1);
2860
2861     break;
2862   }
2863   case X86::DEC16r:
2864     if (DisableLEA16)
2865       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2866                      : nullptr;
2867     assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2868     NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2869                       .addOperand(Dest).addOperand(Src), -1);
2870     break;
2871   case X86::ADD64rr:
2872   case X86::ADD64rr_DB:
2873   case X86::ADD32rr:
2874   case X86::ADD32rr_DB: {
2875     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2876     unsigned Opc;
2877     if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
2878       Opc = X86::LEA64r;
2879     else
2880       Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2881
2882     bool isKill, isUndef;
2883     unsigned SrcReg;
2884     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2885     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2886                         SrcReg, isKill, isUndef, ImplicitOp))
2887       return nullptr;
2888
2889     const MachineOperand &Src2 = MI->getOperand(2);
2890     bool isKill2, isUndef2;
2891     unsigned SrcReg2;
2892     MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
2893     if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
2894                         SrcReg2, isKill2, isUndef2, ImplicitOp2))
2895       return nullptr;
2896
2897     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2898       .addOperand(Dest);
2899     if (ImplicitOp.getReg() != 0)
2900       MIB.addOperand(ImplicitOp);
2901     if (ImplicitOp2.getReg() != 0)
2902       MIB.addOperand(ImplicitOp2);
2903
2904     NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
2905
2906     // Preserve undefness of the operands.
2907     NewMI->getOperand(1).setIsUndef(isUndef);
2908     NewMI->getOperand(3).setIsUndef(isUndef2);
2909
2910     if (LV && Src2.isKill())
2911       LV->replaceKillInstruction(SrcReg2, MI, NewMI);
2912     break;
2913   }
2914   case X86::ADD16rr:
2915   case X86::ADD16rr_DB: {
2916     if (DisableLEA16)
2917       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2918                      : nullptr;
2919     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2920     unsigned Src2 = MI->getOperand(2).getReg();
2921     bool isKill2 = MI->getOperand(2).isKill();
2922     NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2923                       .addOperand(Dest),
2924                       Src.getReg(), Src.isKill(), Src2, isKill2);
2925
2926     // Preserve undefness of the operands.
2927     bool isUndef = MI->getOperand(1).isUndef();
2928     bool isUndef2 = MI->getOperand(2).isUndef();
2929     NewMI->getOperand(1).setIsUndef(isUndef);
2930     NewMI->getOperand(3).setIsUndef(isUndef2);
2931
2932     if (LV && isKill2)
2933       LV->replaceKillInstruction(Src2, MI, NewMI);
2934     break;
2935   }
2936   case X86::ADD64ri32:
2937   case X86::ADD64ri8:
2938   case X86::ADD64ri32_DB:
2939   case X86::ADD64ri8_DB:
2940     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2941     NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2942                       .addOperand(Dest).addOperand(Src),
2943                       MI->getOperand(2).getImm());
2944     break;
2945   case X86::ADD32ri:
2946   case X86::ADD32ri8:
2947   case X86::ADD32ri_DB:
2948   case X86::ADD32ri8_DB: {
2949     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2950     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2951
2952     bool isKill, isUndef;
2953     unsigned SrcReg;
2954     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2955     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2956                         SrcReg, isKill, isUndef, ImplicitOp))
2957       return nullptr;
2958
2959     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2960         .addOperand(Dest)
2961         .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2962     if (ImplicitOp.getReg() != 0)
2963       MIB.addOperand(ImplicitOp);
2964
2965     NewMI = addOffset(MIB, MI->getOperand(2).getImm());
2966     break;
2967   }
2968   case X86::ADD16ri:
2969   case X86::ADD16ri8:
2970   case X86::ADD16ri_DB:
2971   case X86::ADD16ri8_DB:
2972     if (DisableLEA16)
2973       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2974                      : nullptr;
2975     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2976     NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2977                       .addOperand(Dest).addOperand(Src),
2978                       MI->getOperand(2).getImm());
2979     break;
2980   }
2981
2982   if (!NewMI) return nullptr;
2983
2984   if (LV) {  // Update live variables
2985     if (Src.isKill())
2986       LV->replaceKillInstruction(Src.getReg(), MI, NewMI);
2987     if (Dest.isDead())
2988       LV->replaceKillInstruction(Dest.getReg(), MI, NewMI);
2989   }
2990
2991   MFI->insert(MBBI, NewMI);          // Insert the new inst
2992   return NewMI;
2993 }
2994
2995 /// Returns true if the given instruction opcode is FMA3.
2996 /// Otherwise, returns false.
2997 /// The second parameter is optional and is used as the second return from
2998 /// the function. It is set to true if the given instruction has FMA3 opcode
2999 /// that is used for lowering of scalar FMA intrinsics, and it is set to false
3000 /// otherwise.
3001 static bool isFMA3(unsigned Opcode, bool *IsIntrinsic = nullptr) {
3002   if (IsIntrinsic)
3003     *IsIntrinsic = false;
3004
3005   switch (Opcode) {
3006     case X86::VFMADDSDr132r:      case X86::VFMADDSDr132m:
3007     case X86::VFMADDSSr132r:      case X86::VFMADDSSr132m:
3008     case X86::VFMSUBSDr132r:      case X86::VFMSUBSDr132m:
3009     case X86::VFMSUBSSr132r:      case X86::VFMSUBSSr132m:
3010     case X86::VFNMADDSDr132r:     case X86::VFNMADDSDr132m:
3011     case X86::VFNMADDSSr132r:     case X86::VFNMADDSSr132m:
3012     case X86::VFNMSUBSDr132r:     case X86::VFNMSUBSDr132m:
3013     case X86::VFNMSUBSSr132r:     case X86::VFNMSUBSSr132m:
3014
3