1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "X86GenInstrInfo.inc"
20 X86InstrInfo::X86InstrInfo()
21 : TargetInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0]), 0) {
25 // createNOPinstr - returns the target's implementation of NOP, which is
26 // usually a pseudo-instruction, implemented by a degenerate version of
27 // another instruction, e.g. X86: `xchg ax, ax'; SparcV9: `sethi r0, r0, r0'
29 MachineInstr* X86InstrInfo::createNOPinstr() const {
30 return BuildMI(X86::XCHGrr16, 2).addReg(X86::AX, MOTy::UseAndDef)
31 .addReg(X86::AX, MOTy::UseAndDef);
35 /// isNOPinstr - not having a special NOP opcode, we need to know if a given
36 /// instruction is interpreted as an `official' NOP instr, i.e., there may be
37 /// more than one way to `do nothing' but only one canonical way to slack off.
39 bool X86InstrInfo::isNOPinstr(const MachineInstr &MI) const {
40 // Make sure the instruction is EXACTLY `xchg ax, ax'
41 if (MI.getOpcode() == X86::XCHGrr16) {
42 const MachineOperand &op0 = MI.getOperand(0), &op1 = MI.getOperand(1);
43 if (op0.isMachineRegister() && op0.getMachineRegNum() == X86::AX &&
44 op1.isMachineRegister() && op1.getMachineRegNum() == X86::AX) {
48 // FIXME: there are several NOOP instructions, we should check for them here.