lib/Target/X86/X86InstrFragmentsSIMD.td

   1 //===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file provides pattern fragments useful for SIMD instructions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 // MMX specific DAG Nodes.
  16 //===----------------------------------------------------------------------===//
  17
  18 // Low word of MMX to GPR.
  19 def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1,
  20                             [SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>;
  21 // GPR to low word of MMX.
  22 def MMX_X86movw2d : SDNode<"X86ISD::MMX_MOVW2D", SDTypeProfile<1, 1,
  23                             [SDTCisVT<0, x86mmx>, SDTCisVT<1, i32>]>>;
  24
  25 //===----------------------------------------------------------------------===//
  26 // MMX Pattern Fragments
  27 //===----------------------------------------------------------------------===//
  28
  29 def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
  30 def load_mvmmx : PatFrag<(ops node:$ptr),
  31                          (x86mmx (MMX_X86movw2d (load node:$ptr)))>;
  32 def bc_mmx  : PatFrag<(ops node:$in), (x86mmx  (bitconvert node:$in))>;
  33
  34 //===----------------------------------------------------------------------===//
  35 // SSE specific DAG Nodes.
  36 //===----------------------------------------------------------------------===//
  37
  38 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
  39                                        SDTCisFP<1>, SDTCisVT<3, i8>,
  40                                        SDTCisVec<1>]>;
  41
  42 def X86fmin    : SDNode<"X86ISD::FMIN",      SDTFPBinOp>;
  43 def X86fmax    : SDNode<"X86ISD::FMAX",      SDTFPBinOp>;
  44
  45 // Commutative and Associative FMIN and FMAX.
  46 def X86fminc    : SDNode<"X86ISD::FMINC", SDTFPBinOp,
  47     [SDNPCommutative, SDNPAssociative]>;
  48 def X86fmaxc    : SDNode<"X86ISD::FMAXC", SDTFPBinOp,
  49     [SDNPCommutative, SDNPAssociative]>;
  50
  51 def X86fand    : SDNode<"X86ISD::FAND",      SDTFPBinOp,
  52                         [SDNPCommutative, SDNPAssociative]>;
  53 def X86for     : SDNode<"X86ISD::FOR",       SDTFPBinOp,
  54                         [SDNPCommutative, SDNPAssociative]>;
  55 def X86fxor    : SDNode<"X86ISD::FXOR",      SDTFPBinOp,
  56                         [SDNPCommutative, SDNPAssociative]>;
  57 def X86fandn   : SDNode<"X86ISD::FANDN",     SDTFPBinOp,
  58                         [SDNPCommutative, SDNPAssociative]>;
  59 def X86frsqrt  : SDNode<"X86ISD::FRSQRT",    SDTFPUnaryOp>;
  60 def X86frcp    : SDNode<"X86ISD::FRCP",      SDTFPUnaryOp>;
  61 def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
  62 def X86fhadd   : SDNode<"X86ISD::FHADD",     SDTFPBinOp>;
  63 def X86fhsub   : SDNode<"X86ISD::FHSUB",     SDTFPBinOp>;
  64 def X86hadd    : SDNode<"X86ISD::HADD",      SDTIntBinOp>;
  65 def X86hsub    : SDNode<"X86ISD::HSUB",      SDTIntBinOp>;
  66 def X86comi    : SDNode<"X86ISD::COMI",      SDTX86CmpTest>;
  67 def X86ucomi   : SDNode<"X86ISD::UCOMI",     SDTX86CmpTest>;
  68 def X86cmps    : SDNode<"X86ISD::FSETCC",     SDTX86Cmps>;
  69 //def X86cmpsd   : SDNode<"X86ISD::FSETCCsd",    SDTX86Cmpsd>;
  70 def X86cvtdq2pd: SDNode<"X86ISD::CVTDQ2PD",
  71                  SDTypeProfile<1, 1, [SDTCisVT<0, v2f64>,
  72                                       SDTCisVT<1, v4i32>]>>;
  73 def X86cvtudq2pd: SDNode<"X86ISD::CVTUDQ2PD",
  74                  SDTypeProfile<1, 1, [SDTCisVT<0, v2f64>,
  75                                       SDTCisVT<1, v4i32>]>>;
  76 def X86pshufb  : SDNode<"X86ISD::PSHUFB",
  77                  SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
  78                                       SDTCisSameAs<0,2>]>>;
  79 def X86psadbw  : SDNode<"X86ISD::PSADBW",
  80                  SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
  81                                       SDTCisSameAs<0,2>]>>;
  82 def X86dbpsadbw : SDNode<"X86ISD::DBPSADBW",
  83                   SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>,
  84                                        SDTCisSameAs<1,2>, SDTCisInt<3>]>>;
  85 def X86andnp   : SDNode<"X86ISD::ANDNP",
  86                  SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
  87                                       SDTCisSameAs<0,2>]>>;
  88 def X86psign   : SDNode<"X86ISD::PSIGN",
  89                  SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
  90                                       SDTCisSameAs<0,2>]>>;
  91 def X86pextrb  : SDNode<"X86ISD::PEXTRB",
  92                  SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
  93 def X86pextrw  : SDNode<"X86ISD::PEXTRW",
  94                  SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
  95 def X86pinsrb  : SDNode<"X86ISD::PINSRB",
  96                  SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
  97                                       SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
  98 def X86pinsrw  : SDNode<"X86ISD::PINSRW",
  99                  SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
 100                                       SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
 101 def X86insertps : SDNode<"X86ISD::INSERTPS",
 102                  SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
 103                                       SDTCisVT<2, v4f32>, SDTCisVT<3, i8>]>>;
 104 def X86vzmovl  : SDNode<"X86ISD::VZEXT_MOVL",
 105                  SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
 106
 107 def X86vzload  : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
 108                         [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 109
 110 def X86vzext   : SDNode<"X86ISD::VZEXT",
 111                          SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 112                                               SDTCisInt<0>, SDTCisInt<1>,
 113                                               SDTCisOpSmallerThanOp<1, 0>]>>;
 114
 115 def X86vsext   : SDNode<"X86ISD::VSEXT",
 116                          SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 117                                               SDTCisInt<0>, SDTCisInt<1>,
 118                                               SDTCisOpSmallerThanOp<1, 0>]>>;
 119
 120 def SDTVtrunc    : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 121                                        SDTCisInt<0>, SDTCisInt<1>,
 122                                        SDTCisOpSmallerThanOp<0, 1>]>;
 123
 124 def X86vtrunc    : SDNode<"X86ISD::VTRUNC",   SDTVtrunc>;
 125 def X86vtruncs   : SDNode<"X86ISD::VTRUNCS",  SDTVtrunc>;
 126 def X86vtruncus  : SDNode<"X86ISD::VTRUNCUS", SDTVtrunc>;
 127
 128 def X86trunc    : SDNode<"X86ISD::TRUNC",
 129                          SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>,
 130                                               SDTCisOpSmallerThanOp<0, 1>]>>;
 131 def X86vfpext  : SDNode<"X86ISD::VFPEXT",
 132                         SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 133                                              SDTCisFP<0>, SDTCisFP<1>,
 134                                              SDTCisOpSmallerThanOp<1, 0>]>>;
 135 def X86vfpround: SDNode<"X86ISD::VFPROUND",
 136                         SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 137                                              SDTCisFP<0>, SDTCisFP<1>,
 138                                              SDTCisOpSmallerThanOp<0, 1>]>>;
 139
 140 def X86fround: SDNode<"X86ISD::VFPROUND",
 141                         SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
 142                                              SDTCVecEltisVT<0, f32>,
 143                                              SDTCVecEltisVT<1, f64>,
 144                                              SDTCVecEltisVT<2, f64>,
 145                                              SDTCisOpSmallerThanOp<0, 1>]>>;
 146 def X86froundRnd: SDNode<"X86ISD::VFPROUND",
 147                         SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
 148                                              SDTCVecEltisVT<0, f32>,
 149                                              SDTCVecEltisVT<1, f64>,
 150                                              SDTCVecEltisVT<2, f64>,
 151                                              SDTCisOpSmallerThanOp<0, 1>,
 152                                              SDTCisInt<3>]>>;
 153
 154 def X86fpext  : SDNode<"X86ISD::VFPEXT",
 155                         SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
 156                                              SDTCVecEltisVT<0, f64>,
 157                                              SDTCVecEltisVT<1, f32>,
 158                                              SDTCVecEltisVT<2, f32>,
 159                                              SDTCisOpSmallerThanOp<1, 0>]>>;
 160
 161 def X86fpextRnd  : SDNode<"X86ISD::VFPEXT",
 162                         SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
 163                                              SDTCVecEltisVT<0, f64>,
 164                                              SDTCVecEltisVT<1, f32>,
 165                                              SDTCVecEltisVT<2, f32>,
 166                                              SDTCisOpSmallerThanOp<1, 0>,
 167                                              SDTCisInt<3>]>>;
 168
 169 def X86vshldq  : SDNode<"X86ISD::VSHLDQ",    SDTIntShiftOp>;
 170 def X86vshrdq  : SDNode<"X86ISD::VSRLDQ",    SDTIntShiftOp>;
 171 def X86cmpp    : SDNode<"X86ISD::CMPP",      SDTX86VFCMP>;
 172 def X86pcmpeq  : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
 173 def X86pcmpgt  : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
 174
 175 def X86IntCmpMask : SDTypeProfile<1, 2,
 176     [SDTCisVec<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>]>;
 177 def X86pcmpeqm  : SDNode<"X86ISD::PCMPEQM", X86IntCmpMask, [SDNPCommutative]>;
 178 def X86pcmpgtm  : SDNode<"X86ISD::PCMPGTM", X86IntCmpMask>;
 179
 180 def X86CmpMaskCC :
 181       SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
 182                        SDTCisVec<1>, SDTCisSameAs<2, 1>,
 183                        SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>]>;
 184 def X86CmpMaskCCRound :
 185       SDTypeProfile<1, 4, [SDTCisVec<0>,SDTCVecEltisVT<0, i1>,
 186                        SDTCisVec<1>, SDTCisSameAs<2, 1>,
 187                        SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>,
 188                        SDTCisInt<4>]>;
 189 def X86CmpMaskCCScalar :
 190       SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
 191
 192 def X86cmpm    : SDNode<"X86ISD::CMPM",     X86CmpMaskCC>;
 193 def X86cmpmRnd : SDNode<"X86ISD::CMPM_RND", X86CmpMaskCCRound>;
 194 def X86cmpmu   : SDNode<"X86ISD::CMPMU",    X86CmpMaskCC>;
 195 def X86cmpms   : SDNode<"X86ISD::FSETCC",   X86CmpMaskCCScalar>;
 196
 197 def X86vshl    : SDNode<"X86ISD::VSHL",
 198                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 199                                       SDTCisVec<2>]>>;
 200 def X86vsrl    : SDNode<"X86ISD::VSRL",
 201                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 202                                       SDTCisVec<2>]>>;
 203 def X86vsra    : SDNode<"X86ISD::VSRA",
 204                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 205                                       SDTCisVec<2>]>>;
 206
 207 def X86vshli   : SDNode<"X86ISD::VSHLI", SDTIntShiftOp>;
 208 def X86vsrli   : SDNode<"X86ISD::VSRLI", SDTIntShiftOp>;
 209 def X86vsrai   : SDNode<"X86ISD::VSRAI", SDTIntShiftOp>;
 210
 211 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
 212                                           SDTCisVec<1>,
 213                                           SDTCisSameAs<2, 1>]>;
 214 def X86addus   : SDNode<"X86ISD::ADDUS", SDTIntBinOp>;
 215 def X86subus   : SDNode<"X86ISD::SUBUS", SDTIntBinOp>;
 216 def X86adds    : SDNode<"X86ISD::ADDS", SDTIntBinOp>;
 217 def X86subs    : SDNode<"X86ISD::SUBS", SDTIntBinOp>;
 218 def X86mulhrs  : SDNode<"X86ISD::MULHRS" , SDTIntBinOp>;
 219 def X86avg     : SDNode<"X86ISD::AVG" , SDTIntBinOp>;
 220 def X86ptest   : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
 221 def X86testp   : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
 222 def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>;
 223 def X86ktest   : SDNode<"X86ISD::KTEST", SDTX86CmpPTest>;
 224 def X86testm   : SDNode<"X86ISD::TESTM", SDTypeProfile<1, 2, [SDTCisVec<0>,
 225                                           SDTCisVec<1>, SDTCisSameAs<2, 1>,
 226                                           SDTCVecEltisVT<0, i1>,
 227                                           SDTCisSameNumEltsAs<0, 1>]>>;
 228 def X86testnm  : SDNode<"X86ISD::TESTNM", SDTypeProfile<1, 2, [SDTCisVec<0>,
 229                                           SDTCisVec<1>, SDTCisSameAs<2, 1>,
 230                                           SDTCVecEltisVT<0, i1>,
 231                                           SDTCisSameNumEltsAs<0, 1>]>>;
 232 def X86select  : SDNode<"X86ISD::SELECT"     , SDTSelect>;
 233
 234 def X86pmuludq : SDNode<"X86ISD::PMULUDQ",
 235                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 236                                       SDTCisSameAs<1,2>]>>;
 237 def X86pmuldq  : SDNode<"X86ISD::PMULDQ",
 238                          SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 239                                        SDTCisSameAs<1,2>]>>;
 240
 241 def X86extrqi : SDNode<"X86ISD::EXTRQI",
 242                   SDTypeProfile<1, 3, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
 243                                        SDTCisVT<2, i8>, SDTCisVT<3, i8>]>>;
 244 def X86insertqi : SDNode<"X86ISD::INSERTQI",
 245                     SDTypeProfile<1, 4, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
 246                                          SDTCisSameAs<1,2>, SDTCisVT<3, i8>,
 247                                          SDTCisVT<4, i8>]>>;
 248
 249 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
 250 // translated into one of the target nodes below during lowering.
 251 // Note: this is a work in progress...
 252 def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
 253 def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 254                                 SDTCisSameAs<0,2>]>;
 255 def SDTShuff3Op : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 256                                 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>;
 257
 258 def SDTShuff2OpM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 259                                         SDTCisVec<2>]>;
 260 def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
 261                                  SDTCisSameAs<0,1>, SDTCisInt<2>]>;
 262 def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 263                                  SDTCisSameAs<0,2>, SDTCisInt<3>]>;
 264 def SDTFPBinOpImmRound: SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 265                              SDTCisSameAs<0,2>, SDTCisInt<3>, SDTCisInt<4>]>;
 266 def SDTFPUnaryOpImmRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 267                               SDTCisInt<2>, SDTCisInt<3>]>;
 268
 269 def SDTVBroadcast  : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
 270 def SDTVBroadcastm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>]>;
 271
 272 def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 273                              SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>;
 274
 275 def SDTFPBinOpRound : SDTypeProfile<1, 3, [      // fadd_round, fmul_round, etc.
 276   SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>, SDTCisInt<3>]>;
 277
 278 def SDTFPUnaryOpRound : SDTypeProfile<1, 2, [      // fsqrt_round, fgetexp_round, etc.
 279   SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]>;
 280
 281 def SDTFma : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
 282                            SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
 283 def SDTFmaRound : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
 284                            SDTCisSameAs<1,2>, SDTCisSameAs<1,3>, SDTCisInt<4>]>;
 285 def STDFp1SrcRm : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>,
 286                            SDTCisVec<0>, SDTCisInt<2>]>;
 287 def STDFp2SrcRm : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
 288                            SDTCisVec<0>, SDTCisInt<3>]>;
 289 def STDFp3SrcRm : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
 290                            SDTCisVec<0>, SDTCisInt<3>, SDTCisInt<4>]>;
 291
 292 def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>;
 293 def X86VAlign  : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>;
 294
 295 def X86Abs      : SDNode<"X86ISD::ABS", SDTIntUnaryOp>;
 296 def X86Conflict : SDNode<"X86ISD::CONFLICT", SDTIntUnaryOp>;
 297
 298 def X86PShufd  : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
 299 def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
 300 def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
 301
 302 def X86Shufp   : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>;
 303 def X86Shuf128 : SDNode<"X86ISD::SHUF128", SDTShuff3OpI>;
 304
 305 def X86Movddup  : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
 306 def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
 307 def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
 308
 309 def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>;
 310 def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>;
 311
 312 def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>;
 313 def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>;
 314 def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;
 315
 316 def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
 317 def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
 318
 319 def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<2, 1>]>;
 320 def X86Packss : SDNode<"X86ISD::PACKSS", SDTPack>;
 321 def X86Packus : SDNode<"X86ISD::PACKUS", SDTPack>;
 322
 323 def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
 324 def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
 325
 326 def X86vpmaddubsw  : SDNode<"X86ISD::VPMADDUBSW" , SDTPack>;
 327 def X86vpmaddwd    : SDNode<"X86ISD::VPMADDWD"   , SDTPack>;
 328
 329 def X86VPermilpv  : SDNode<"X86ISD::VPERMILPV", SDTShuff2OpM>;
 330 def X86VPermilpi  : SDNode<"X86ISD::VPERMILPI", SDTShuff2OpI>;
 331 def X86VPermv     : SDNode<"X86ISD::VPERMV",    SDTShuff2Op>;
 332 def X86VPermi     : SDNode<"X86ISD::VPERMI",    SDTShuff2OpI>;
 333 def X86VPermv3    : SDNode<"X86ISD::VPERMV3",   SDTShuff3Op>;
 334 def X86VPermiv3   : SDNode<"X86ISD::VPERMIV3",  SDTShuff3Op>;
 335
 336 def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
 337
 338 def X86VFixupimm   : SDNode<"X86ISD::VFIXUPIMM", SDTFPBinOpImmRound>;
 339 def X86VRange      : SDNode<"X86ISD::VRANGE",    SDTFPBinOpImmRound>;
 340 def X86VReduce     : SDNode<"X86ISD::VREDUCE",   SDTFPUnaryOpImmRound>;
 341 def X86VRndScale   : SDNode<"X86ISD::VRNDSCALE", SDTFPUnaryOpImmRound>;
 342 def X86VGetMant    : SDNode<"X86ISD::VGETMANT",  SDTFPUnaryOpImmRound>;
 343 def X86Vfpclass    : SDNode<"X86ISD::VFPCLASS",
 344                        SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
 345                                             SDTCisVec<1>, SDTCisInt<2>]>, []>;
 346
 347 def X86SubVBroadcast : SDNode<"X86ISD::SUBV_BROADCAST",
 348                     SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 349                                          SDTCisSubVecOfVec<1, 0>]>, []>;
 350 def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
 351 def X86Vinsert   : SDNode<"X86ISD::VINSERT",  SDTypeProfile<1, 3,
 352                               [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
 353 def X86Vextract   : SDNode<"X86ISD::VEXTRACT",  SDTypeProfile<1, 2,
 354                               [SDTCisVec<1>, SDTCisPtrTy<2>]>, []>;
 355
 356 def X86Blendi    : SDNode<"X86ISD::BLENDI",   SDTBlend>;
 357
 358 def X86Addsub    : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>;
 359
 360 def X86faddRnd   : SDNode<"X86ISD::FADD_RND",  SDTFPBinOpRound>;
 361 def X86fsubRnd   : SDNode<"X86ISD::FSUB_RND",  SDTFPBinOpRound>;
 362 def X86fmulRnd   : SDNode<"X86ISD::FMUL_RND",  SDTFPBinOpRound>;
 363 def X86fdivRnd   : SDNode<"X86ISD::FDIV_RND",  SDTFPBinOpRound>;
 364 def X86fmaxRnd   : SDNode<"X86ISD::FMAX_RND",       SDTFPBinOpRound>;
 365 def X86scalef    : SDNode<"X86ISD::SCALEF",         SDTFPBinOpRound>;
 366 def X86fminRnd   : SDNode<"X86ISD::FMIN_RND",       SDTFPBinOpRound>;
 367 def X86fsqrtRnd     : SDNode<"X86ISD::FSQRT_RND",   SDTFPUnaryOpRound>;
 368 def X86fsqrtRnds    : SDNode<"X86ISD::FSQRT_RND",   STDFp2SrcRm>;
 369 def X86fgetexpRnd   : SDNode<"X86ISD::FGETEXP_RND", SDTFPUnaryOpRound>;
 370 def X86fgetexpRnds  : SDNode<"X86ISD::FGETEXP_RND", STDFp2SrcRm>;
 371
 372 def X86Fmadd     : SDNode<"X86ISD::FMADD",     SDTFma>;
 373 def X86Fnmadd    : SDNode<"X86ISD::FNMADD",    SDTFma>;
 374 def X86Fmsub     : SDNode<"X86ISD::FMSUB",     SDTFma>;
 375 def X86Fnmsub    : SDNode<"X86ISD::FNMSUB",    SDTFma>;
 376 def X86Fmaddsub  : SDNode<"X86ISD::FMADDSUB",  SDTFma>;
 377 def X86Fmsubadd  : SDNode<"X86ISD::FMSUBADD",  SDTFma>;
 378
 379 def X86FmaddRnd     : SDNode<"X86ISD::FMADD_RND",     SDTFmaRound>;
 380 def X86FnmaddRnd    : SDNode<"X86ISD::FNMADD_RND",    SDTFmaRound>;
 381 def X86FmsubRnd     : SDNode<"X86ISD::FMSUB_RND",     SDTFmaRound>;
 382 def X86FnmsubRnd    : SDNode<"X86ISD::FNMSUB_RND",    SDTFmaRound>;
 383 def X86FmaddsubRnd  : SDNode<"X86ISD::FMADDSUB_RND",  SDTFmaRound>;
 384 def X86FmsubaddRnd  : SDNode<"X86ISD::FMSUBADD_RND",  SDTFmaRound>;
 385
 386 def X86rsqrt28   : SDNode<"X86ISD::RSQRT28",  STDFp1SrcRm>;
 387 def X86rcp28     : SDNode<"X86ISD::RCP28",    STDFp1SrcRm>;
 388 def X86exp2      : SDNode<"X86ISD::EXP2",     STDFp1SrcRm>;
 389
 390 def X86rsqrt28s  : SDNode<"X86ISD::RSQRT28",   STDFp2SrcRm>;
 391 def X86rcp28s    : SDNode<"X86ISD::RCP28",     STDFp2SrcRm>;
 392 def X86RndScales : SDNode<"X86ISD::VRNDSCALE", STDFp3SrcRm>;
 393 def X86Reduces   : SDNode<"X86ISD::VREDUCE",   STDFp3SrcRm>;
 394 def X86GetMants  : SDNode<"X86ISD::VGETMANT",  STDFp3SrcRm>;
 395
 396 def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
 397                                          SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>,
 398                                          SDTCisVT<4, i8>]>;
 399 def SDT_PCMPESTRI : SDTypeProfile<2, 5, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
 400                                          SDTCisVT<2, v16i8>, SDTCisVT<3, i32>,
 401                                          SDTCisVT<4, v16i8>, SDTCisVT<5, i32>,
 402                                          SDTCisVT<6, i8>]>;
 403
 404 def X86pcmpistri : SDNode<"X86ISD::PCMPISTRI", SDT_PCMPISTRI>;
 405 def X86pcmpestri : SDNode<"X86ISD::PCMPESTRI", SDT_PCMPESTRI>;
 406
 407 def X86compress: SDNode<"X86ISD::COMPRESS", SDTypeProfile<1, 1,
 408                               [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
 409 def X86expand  : SDNode<"X86ISD::EXPAND", SDTypeProfile<1, 1,
 410                               [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
 411
 412 def SDTintToFPRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>,
 413                                SDTCisSameAs<0,1>, SDTCisInt<2>, SDTCisInt<3>]>;
 414
 415 def SDTDoubleToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 416                                          SDTCisInt<0>, SDTCVecEltisVT<1, f64>]>;
 417 def SDTFloatToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 418                                          SDTCisInt<0>, SDTCVecEltisVT<1, f32>]>;
 419
 420 def SDTDoubleToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 421                                          SDTCisInt<0>, SDTCVecEltisVT<1, f64>]>;
 422 def SDTSDoubleToIntRnd: SDTypeProfile<1, 2, [SDTCisInt<0>,SDTCisFP<1>,
 423                                              SDTCVecEltisVT<1, f64>, SDTCisInt<2>]>;
 424 def SDTFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 425                                          SDTCisInt<0>, SDTCVecEltisVT<1, f32>]>;
 426 def SDTSFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisFP<1>,
 427                                             SDTCVecEltisVT<1, f32>, SDTCisInt<2>]>;
 428 def SDTVintToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 429                                            SDTCisFP<0>, SDTCVecEltisVT<1, i32>,
 430                                            SDTCisInt<2>]>;
 431 def SDTVlongToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 432                                            SDTCisFP<0>, SDTCVecEltisVT<1, i64>,
 433                                            SDTCisInt<2>]>;
 434
 435 def SDTVFPToIntRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 436                                            SDTCisFP<1>, SDTCVecEltisVT<0, i32>,
 437                                            SDTCisInt<2>]>;
 438 def SDTVFPToLongRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 439                                            SDTCisFP<1>, SDTCVecEltisVT<0, i64>,
 440                                            SDTCisInt<2>]>;
 441
 442 // Scalar
 443 def X86SintToFpRnd  : SDNode<"X86ISD::SINT_TO_FP_RND",  SDTintToFPRound>;
 444 def X86UintToFpRnd  : SDNode<"X86ISD::UINT_TO_FP_RND",  SDTintToFPRound>;
 445
 446 def X86cvttss2IntRnd      : SDNode<"X86ISD::FP_TO_SINT_RND",  SDTSFloatToIntRnd>;
 447 def X86cvttss2UIntRnd     : SDNode<"X86ISD::FP_TO_UINT_RND",  SDTSFloatToIntRnd>;
 448 def X86cvttsd2IntRnd      : SDNode<"X86ISD::FP_TO_SINT_RND",  SDTSDoubleToIntRnd>;
 449 def X86cvttsd2UIntRnd     : SDNode<"X86ISD::FP_TO_UINT_RND",  SDTSDoubleToIntRnd>;
 450 // Vector with rounding mode
 451
 452 // cvtt fp-to-int staff
 453 def X86VFpToSintRnd   : SDNode<"ISD::FP_TO_SINT",  SDTVFPToIntRound>;
 454 def X86VFpToUintRnd   : SDNode<"ISD::FP_TO_UINT",  SDTVFPToIntRound>;
 455 def X86VFpToSlongRnd  : SDNode<"ISD::FP_TO_SINT",  SDTVFPToLongRound>;
 456 def X86VFpToUlongRnd  : SDNode<"ISD::FP_TO_UINT",  SDTVFPToLongRound>;
 457
 458 def X86VSintToFpRnd   : SDNode<"ISD::SINT_TO_FP",  SDTVintToFPRound>;
 459 def X86VUintToFpRnd   : SDNode<"ISD::UINT_TO_FP",  SDTVintToFPRound>;
 460 def X86VSlongToFpRnd  : SDNode<"ISD::SINT_TO_FP",  SDTVlongToFPRound>;
 461 def X86VUlongToFpRnd  : SDNode<"ISD::UINT_TO_FP",  SDTVlongToFPRound>;
 462
 463 // cvt fp-to-int staff
 464 def X86cvtps2IntRnd      : SDNode<"X86ISD::FP_TO_SINT_RND",  SDTFloatToIntRnd>;
 465 def X86cvtps2UIntRnd     : SDNode<"X86ISD::FP_TO_UINT_RND",  SDTFloatToIntRnd>;
 466 def X86cvtpd2IntRnd      : SDNode<"X86ISD::FP_TO_SINT_RND",  SDTDoubleToIntRnd>;
 467 def X86cvtpd2UIntRnd     : SDNode<"X86ISD::FP_TO_UINT_RND",  SDTDoubleToIntRnd>;
 468
 469 // Vector without rounding mode
 470 def X86cvtps2Int      : SDNode<"X86ISD::FP_TO_SINT_RND",  SDTFloatToInt>;
 471 def X86cvtps2UInt     : SDNode<"X86ISD::FP_TO_UINT_RND",  SDTFloatToInt>;
 472 def X86cvtpd2Int      : SDNode<"X86ISD::FP_TO_SINT_RND",  SDTDoubleToInt>;
 473 def X86cvtpd2UInt     : SDNode<"X86ISD::FP_TO_UINT_RND",  SDTDoubleToInt>;
 474
 475 def X86vfpextRnd  : SDNode<"X86ISD::VFPEXT",
 476                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 477                                              SDTCisFP<0>, SDTCisFP<1>,
 478                                              SDTCisOpSmallerThanOp<1, 0>,
 479                                              SDTCisInt<2>]>>;
 480 def X86vfproundRnd: SDNode<"X86ISD::VFPROUND",
 481                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 482                                              SDTCisFP<0>, SDTCisFP<1>,
 483                                              SDTCVecEltisVT<0, f32>,
 484                                              SDTCVecEltisVT<1, f64>,
 485                                              SDTCisInt<2>]>>;
 486
 487 //===----------------------------------------------------------------------===//
 488 // SSE Complex Patterns
 489 //===----------------------------------------------------------------------===//
 490
 491 // These are 'extloads' from a scalar to the low element of a vector, zeroing
 492 // the top elements.  These are used for the SSE 'ss' and 'sd' instruction
 493 // forms.
 494 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
 495                                   [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
 496                                    SDNPWantRoot]>;
 497 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
 498                                   [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
 499                                    SDNPWantRoot]>;
 500
 501 def ssmem : Operand<v4f32> {
 502   let PrintMethod = "printf32mem";
 503   let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
 504   let ParserMatchClass = X86Mem32AsmOperand;
 505   let OperandType = "OPERAND_MEMORY";
 506 }
 507 def sdmem : Operand<v2f64> {
 508   let PrintMethod = "printf64mem";
 509   let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
 510   let ParserMatchClass = X86Mem64AsmOperand;
 511   let OperandType = "OPERAND_MEMORY";
 512 }
 513
 514 //===----------------------------------------------------------------------===//
 515 // SSE pattern fragments
 516 //===----------------------------------------------------------------------===//
 517
 518 // 128-bit load pattern fragments
 519 // NOTE: all 128-bit integer vector loads are promoted to v2i64
 520 def loadv4f32    : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
 521 def loadv2f64    : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
 522 def loadv2i64    : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
 523
 524 // 256-bit load pattern fragments
 525 // NOTE: all 256-bit integer vector loads are promoted to v4i64
 526 def loadv8f32    : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
 527 def loadv4f64    : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
 528 def loadv4i64    : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
 529
 530 // 512-bit load pattern fragments
 531 def loadv16f32   : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>;
 532 def loadv8f64    : PatFrag<(ops node:$ptr), (v8f64 (load node:$ptr))>;
 533 def loadv64i8    : PatFrag<(ops node:$ptr), (v64i8 (load node:$ptr))>;
 534 def loadv32i16   : PatFrag<(ops node:$ptr), (v32i16 (load node:$ptr))>;
 535 def loadv16i32   : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>;
 536 def loadv8i64    : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>;
 537
 538 // 128-/256-/512-bit extload pattern fragments
 539 def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>;
 540 def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>;
 541 def extloadv8f32 : PatFrag<(ops node:$ptr), (v8f64 (extloadvf32 node:$ptr))>;
 542
 543 // These are needed to match a scalar load that is used in a vector-only
 544 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
 545 // The memory operand is required to be a 128-bit load, so it must be converted
 546 // from a vector to a scalar.
 547 def loadf32_128 : PatFrag<(ops node:$ptr),
 548   (f32 (vector_extract (loadv4f32 node:$ptr), (iPTR 0)))>;
 549 def loadf64_128 : PatFrag<(ops node:$ptr),
 550   (f64 (vector_extract (loadv2f64 node:$ptr), (iPTR 0)))>;
 551
 552 // Like 'store', but always requires 128-bit vector alignment.
 553 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
 554                            (store node:$val, node:$ptr), [{
 555   return cast<StoreSDNode>(N)->getAlignment() >= 16;
 556 }]>;
 557
 558 // Like 'store', but always requires 256-bit vector alignment.
 559 def alignedstore256 : PatFrag<(ops node:$val, node:$ptr),
 560                               (store node:$val, node:$ptr), [{
 561   return cast<StoreSDNode>(N)->getAlignment() >= 32;
 562 }]>;
 563
 564 // Like 'store', but always requires 512-bit vector alignment.
 565 def alignedstore512 : PatFrag<(ops node:$val, node:$ptr),
 566                               (store node:$val, node:$ptr), [{
 567   return cast<StoreSDNode>(N)->getAlignment() >= 64;
 568 }]>;
 569
 570 // Like 'load', but always requires 128-bit vector alignment.
 571 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 572   return cast<LoadSDNode>(N)->getAlignment() >= 16;
 573 }]>;
 574
 575 // Like 'X86vzload', but always requires 128-bit vector alignment.
 576 def alignedX86vzload : PatFrag<(ops node:$ptr), (X86vzload node:$ptr), [{
 577   return cast<MemSDNode>(N)->getAlignment() >= 16;
 578 }]>;
 579
 580 // Like 'load', but always requires 256-bit vector alignment.
 581 def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 582   return cast<LoadSDNode>(N)->getAlignment() >= 32;
 583 }]>;
 584
 585 // Like 'load', but always requires 512-bit vector alignment.
 586 def alignedload512 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 587   return cast<LoadSDNode>(N)->getAlignment() >= 64;
 588 }]>;
 589
 590 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
 591                                (f32 (alignedload node:$ptr))>;
 592 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
 593                                (f64 (alignedload node:$ptr))>;
 594
 595 // 128-bit aligned load pattern fragments
 596 // NOTE: all 128-bit integer vector loads are promoted to v2i64
 597 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
 598                                (v4f32 (alignedload node:$ptr))>;
 599 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
 600                                (v2f64 (alignedload node:$ptr))>;
 601 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
 602                                (v2i64 (alignedload node:$ptr))>;
 603
 604 // 256-bit aligned load pattern fragments
 605 // NOTE: all 256-bit integer vector loads are promoted to v4i64
 606 def alignedloadv8f32 : PatFrag<(ops node:$ptr),
 607                                (v8f32 (alignedload256 node:$ptr))>;
 608 def alignedloadv4f64 : PatFrag<(ops node:$ptr),
 609                                (v4f64 (alignedload256 node:$ptr))>;
 610 def alignedloadv4i64 : PatFrag<(ops node:$ptr),
 611                                (v4i64 (alignedload256 node:$ptr))>;
 612
 613 // 512-bit aligned load pattern fragments
 614 def alignedloadv16f32 : PatFrag<(ops node:$ptr),
 615                                 (v16f32 (alignedload512 node:$ptr))>;
 616 def alignedloadv16i32 : PatFrag<(ops node:$ptr),
 617                                 (v16i32 (alignedload512 node:$ptr))>;
 618 def alignedloadv8f64  : PatFrag<(ops node:$ptr),
 619                                 (v8f64  (alignedload512 node:$ptr))>;
 620 def alignedloadv8i64  : PatFrag<(ops node:$ptr),
 621                                 (v8i64  (alignedload512 node:$ptr))>;
 622
 623 // Like 'load', but uses special alignment checks suitable for use in
 624 // memory operands in most SSE instructions, which are required to
 625 // be naturally aligned on some targets but not on others.  If the subtarget
 626 // allows unaligned accesses, match any load, though this may require
 627 // setting a feature bit in the processor (on startup, for example).
 628 // Opteron 10h and later implement such a feature.
 629 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 630   return    Subtarget->hasSSEUnalignedMem()
 631          || cast<LoadSDNode>(N)->getAlignment() >= 16;
 632 }]>;
 633
 634 def memopfsf32 : PatFrag<(ops node:$ptr), (f32   (memop node:$ptr))>;
 635 def memopfsf64 : PatFrag<(ops node:$ptr), (f64   (memop node:$ptr))>;
 636
 637 // 128-bit memop pattern fragments
 638 // NOTE: all 128-bit integer vector loads are promoted to v2i64
 639 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
 640 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
 641 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
 642
 643 // These are needed to match a scalar memop that is used in a vector-only
 644 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
 645 // The memory operand is required to be a 128-bit load, so it must be converted
 646 // from a vector to a scalar.
 647 def memopfsf32_128 : PatFrag<(ops node:$ptr),
 648   (f32 (vector_extract (memopv4f32 node:$ptr), (iPTR 0)))>;
 649 def memopfsf64_128 : PatFrag<(ops node:$ptr),
 650   (f64 (vector_extract (memopv2f64 node:$ptr), (iPTR 0)))>;
 651
 652
 653 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
 654 // 16-byte boundary.
 655 // FIXME: 8 byte alignment for mmx reads is not required
 656 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 657   return cast<LoadSDNode>(N)->getAlignment() >= 8;
 658 }]>;
 659
 660 def memopmmx  : PatFrag<(ops node:$ptr), (x86mmx  (memop64 node:$ptr))>;
 661
 662 def mgatherv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 663   (masked_gather node:$src1, node:$src2, node:$src3) , [{
 664   if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
 665     return (Mgt->getIndex().getValueType() == MVT::v4i32 ||
 666             Mgt->getBasePtr().getValueType() == MVT::v4i32);
 667   return false;
 668 }]>;
 669
 670 def mgatherv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 671   (masked_gather node:$src1, node:$src2, node:$src3) , [{
 672   if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
 673     return (Mgt->getIndex().getValueType() == MVT::v8i32 ||
 674             Mgt->getBasePtr().getValueType() == MVT::v8i32);
 675   return false;
 676 }]>;
 677
 678 def mgatherv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 679   (masked_gather node:$src1, node:$src2, node:$src3) , [{
 680   if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
 681     return (Mgt->getIndex().getValueType() == MVT::v2i64 ||
 682             Mgt->getBasePtr().getValueType() == MVT::v2i64);
 683   return false;
 684 }]>;
 685 def mgatherv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 686   (masked_gather node:$src1, node:$src2, node:$src3) , [{
 687   if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
 688     return (Mgt->getIndex().getValueType() == MVT::v4i64 ||
 689             Mgt->getBasePtr().getValueType() == MVT::v4i64);
 690   return false;
 691 }]>;
 692 def mgatherv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 693   (masked_gather node:$src1, node:$src2, node:$src3) , [{
 694   if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
 695     return (Mgt->getIndex().getValueType() == MVT::v8i64 ||
 696             Mgt->getBasePtr().getValueType() == MVT::v8i64);
 697   return false;
 698 }]>;
 699 def mgatherv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 700   (masked_gather node:$src1, node:$src2, node:$src3) , [{
 701   if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
 702     return (Mgt->getIndex().getValueType() == MVT::v16i32 ||
 703             Mgt->getBasePtr().getValueType() == MVT::v16i32);
 704   return false;
 705 }]>;
 706
 707 def mscatterv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 708   (masked_scatter node:$src1, node:$src2, node:$src3) , [{
 709   if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
 710     return (Sc->getIndex().getValueType() == MVT::v2i64 ||
 711             Sc->getBasePtr().getValueType() == MVT::v2i64);
 712   return false;
 713 }]>;
 714
 715 def mscatterv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 716   (masked_scatter node:$src1, node:$src2, node:$src3) , [{
 717   if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
 718     return (Sc->getIndex().getValueType() == MVT::v4i32 ||
 719             Sc->getBasePtr().getValueType() == MVT::v4i32);
 720   return false;
 721 }]>;
 722
 723 def mscatterv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 724   (masked_scatter node:$src1, node:$src2, node:$src3) , [{
 725   if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
 726     return (Sc->getIndex().getValueType() == MVT::v4i64 ||
 727             Sc->getBasePtr().getValueType() == MVT::v4i64);
 728   return false;
 729 }]>;
 730
 731 def mscatterv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 732   (masked_scatter node:$src1, node:$src2, node:$src3) , [{
 733   if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
 734     return (Sc->getIndex().getValueType() == MVT::v8i32 ||
 735             Sc->getBasePtr().getValueType() == MVT::v8i32);
 736   return false;
 737 }]>;
 738
 739 def mscatterv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 740   (masked_scatter node:$src1, node:$src2, node:$src3) , [{
 741   if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
 742     return (Sc->getIndex().getValueType() == MVT::v8i64 ||
 743             Sc->getBasePtr().getValueType() == MVT::v8i64);
 744   return false;
 745 }]>;
 746 def mscatterv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 747   (masked_scatter node:$src1, node:$src2, node:$src3) , [{
 748   if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
 749     return (Sc->getIndex().getValueType() == MVT::v16i32 ||
 750             Sc->getBasePtr().getValueType() == MVT::v16i32);
 751   return false;
 752 }]>;
 753
 754 // 128-bit bitconvert pattern fragments
 755 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
 756 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
 757 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
 758 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
 759 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
 760 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
 761
 762 // 256-bit bitconvert pattern fragments
 763 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
 764 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
 765 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
 766 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
 767 def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>;
 768
 769 // 512-bit bitconvert pattern fragments
 770 def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
 771 def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
 772 def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>;
 773 def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>;
 774
 775 def vzmovl_v2i64 : PatFrag<(ops node:$src),
 776                            (bitconvert (v2i64 (X86vzmovl
 777                              (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
 778 def vzmovl_v4i32 : PatFrag<(ops node:$src),
 779                            (bitconvert (v4i32 (X86vzmovl
 780                              (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
 781
 782 def vzload_v2i64 : PatFrag<(ops node:$src),
 783                            (bitconvert (v2i64 (X86vzload node:$src)))>;
 784
 785
 786 def fp32imm0 : PatLeaf<(f32 fpimm), [{
 787   return N->isExactlyValue(+0.0);
 788 }]>;
 789
 790 def I8Imm : SDNodeXForm<imm, [{
 791   // Transformation function: get the low 8 bits.
 792   return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
 793 }]>;
 794
 795 def FROUND_NO_EXC : ImmLeaf<i32, [{ return Imm == 8; }]>;
 796 def FROUND_CURRENT : ImmLeaf<i32, [{
 797   return Imm == X86::STATIC_ROUNDING::CUR_DIRECTION;
 798 }]>;
 799
 800 // BYTE_imm - Transform bit immediates into byte immediates.
 801 def BYTE_imm  : SDNodeXForm<imm, [{
 802   // Transformation function: imm >> 3
 803   return getI32Imm(N->getZExtValue() >> 3, SDLoc(N));
 804 }]>;
 805
 806 // EXTRACT_get_vextract128_imm xform function: convert extract_subvector index
 807 // to VEXTRACTF128/VEXTRACTI128 imm.
 808 def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{
 809   return getI8Imm(X86::getExtractVEXTRACT128Immediate(N), SDLoc(N));
 810 }]>;
 811
 812 // INSERT_get_vinsert128_imm xform function: convert insert_subvector index to
 813 // VINSERTF128/VINSERTI128 imm.
 814 def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{
 815   return getI8Imm(X86::getInsertVINSERT128Immediate(N), SDLoc(N));
 816 }]>;
 817
 818 // EXTRACT_get_vextract256_imm xform function: convert extract_subvector index
 819 // to VEXTRACTF64x4 imm.
 820 def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{
 821   return getI8Imm(X86::getExtractVEXTRACT256Immediate(N), SDLoc(N));
 822 }]>;
 823
 824 // INSERT_get_vinsert256_imm xform function: convert insert_subvector index to
 825 // VINSERTF64x4 imm.
 826 def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{
 827   return getI8Imm(X86::getInsertVINSERT256Immediate(N), SDLoc(N));
 828 }]>;
 829
 830 def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index),
 831                                    (extract_subvector node:$bigvec,
 832                                                       node:$index), [{
 833   return X86::isVEXTRACT128Index(N);
 834 }], EXTRACT_get_vextract128_imm>;
 835
 836 def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
 837                                       node:$index),
 838                                  (insert_subvector node:$bigvec, node:$smallvec,
 839                                                    node:$index), [{
 840   return X86::isVINSERT128Index(N);
 841 }], INSERT_get_vinsert128_imm>;
 842
 843
 844 def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index),
 845                                    (extract_subvector node:$bigvec,
 846                                                       node:$index), [{
 847   return X86::isVEXTRACT256Index(N);
 848 }], EXTRACT_get_vextract256_imm>;
 849
 850 def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
 851                                       node:$index),
 852                                  (insert_subvector node:$bigvec, node:$smallvec,
 853                                                    node:$index), [{
 854   return X86::isVINSERT256Index(N);
 855 }], INSERT_get_vinsert256_imm>;
 856
 857 def masked_load_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 858                          (masked_load node:$src1, node:$src2, node:$src3), [{
 859   if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
 860     return Load->getAlignment() >= 16;
 861   return false;
 862 }]>;
 863
 864 def masked_load_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 865                          (masked_load node:$src1, node:$src2, node:$src3), [{
 866   if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
 867     return Load->getAlignment() >= 32;
 868   return false;
 869 }]>;
 870
 871 def masked_load_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 872                          (masked_load node:$src1, node:$src2, node:$src3), [{
 873   if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
 874     return Load->getAlignment() >= 64;
 875   return false;
 876 }]>;
 877
 878 def masked_load_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 879                          (masked_load node:$src1, node:$src2, node:$src3), [{
 880   return isa<MaskedLoadSDNode>(N);
 881 }]>;
 882
 883 // masked store fragments.
 884 // X86mstore can't be implemented in core DAG files because some targets
 885 // doesn't support vector type ( llvm-tblgen will fail)
 886 def X86mstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 887                         (masked_store node:$src1, node:$src2, node:$src3), [{
 888   return !cast<MaskedStoreSDNode>(N)->isTruncatingStore();
 889 }]>;
 890
 891 def masked_store_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 892                          (X86mstore node:$src1, node:$src2, node:$src3), [{
 893   if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
 894     return Store->getAlignment() >= 16;
 895   return false;
 896 }]>;
 897
 898 def masked_store_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 899                          (X86mstore node:$src1, node:$src2, node:$src3), [{
 900   if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
 901     return Store->getAlignment() >= 32;
 902   return false;
 903 }]>;
 904
 905 def masked_store_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 906                          (X86mstore node:$src1, node:$src2, node:$src3), [{
 907   if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
 908     return Store->getAlignment() >= 64;
 909   return false;
 910 }]>;
 911
 912 def masked_store_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 913                          (X86mstore node:$src1, node:$src2, node:$src3), [{
 914   return isa<MaskedStoreSDNode>(N);
 915 }]>;
 916
 917 // masked truncstore fragments
 918 // X86mtruncstore can't be implemented in core DAG files because some targets
 919 // doesn't support vector type ( llvm-tblgen will fail)
 920 def X86mtruncstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 921                              (masked_store node:$src1, node:$src2, node:$src3), [{
 922     return cast<MaskedStoreSDNode>(N)->isTruncatingStore();
 923 }]>;
 924 def masked_truncstorevi8 :
 925   PatFrag<(ops node:$src1, node:$src2, node:$src3),
 926           (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
 927   return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
 928 }]>;
 929 def masked_truncstorevi16 :
 930   PatFrag<(ops node:$src1, node:$src2, node:$src3),
 931           (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
 932   return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
 933 }]>;
 934 def masked_truncstorevi32 :
 935   PatFrag<(ops node:$src1, node:$src2, node:$src3),
 936           (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
 937   return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
 938 }]>;