1 //===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides pattern fragments useful for SIMD instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // MMX Pattern Fragments
16 //===----------------------------------------------------------------------===//
18 def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
19 def bc_mmx : PatFrag<(ops node:$in), (x86mmx (bitconvert node:$in))>;
21 //===----------------------------------------------------------------------===//
22 // SSE specific DAG Nodes.
23 //===----------------------------------------------------------------------===//
25 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
26 SDTCisFP<0>, SDTCisInt<2> ]>;
27 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
28 SDTCisFP<1>, SDTCisVT<3, i8>]>;
30 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
31 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
33 // Commutative and Associative FMIN and FMAX.
34 def X86fminc : SDNode<"X86ISD::FMINC", SDTFPBinOp,
35 [SDNPCommutative, SDNPAssociative]>;
36 def X86fmaxc : SDNode<"X86ISD::FMAXC", SDTFPBinOp,
37 [SDNPCommutative, SDNPAssociative]>;
39 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
40 [SDNPCommutative, SDNPAssociative]>;
41 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
42 [SDNPCommutative, SDNPAssociative]>;
43 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
44 [SDNPCommutative, SDNPAssociative]>;
45 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
46 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
47 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
48 def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
49 def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>;
50 def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>;
51 def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>;
52 def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>;
53 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
54 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
55 def X86cmpss : SDNode<"X86ISD::FSETCCss", SDTX86Cmpss>;
56 def X86cmpsd : SDNode<"X86ISD::FSETCCsd", SDTX86Cmpsd>;
57 def X86pshufb : SDNode<"X86ISD::PSHUFB",
58 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
60 def X86andnp : SDNode<"X86ISD::ANDNP",
61 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
63 def X86psign : SDNode<"X86ISD::PSIGN",
64 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
66 def X86pextrb : SDNode<"X86ISD::PEXTRB",
67 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
68 def X86pextrw : SDNode<"X86ISD::PEXTRW",
69 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
70 def X86pinsrb : SDNode<"X86ISD::PINSRB",
71 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
72 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
73 def X86pinsrw : SDNode<"X86ISD::PINSRW",
74 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
75 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
76 def X86insrtps : SDNode<"X86ISD::INSERTPS",
77 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
78 SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>;
79 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
80 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
82 def X86vzmovly : SDNode<"X86ISD::VZEXT_MOVL",
83 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
84 SDTCisOpSmallerThanOp<1, 0> ]>>;
86 def X86vsmovl : SDNode<"X86ISD::VSEXT_MOVL",
88 [SDTCisVec<0>, SDTCisInt<1>, SDTCisInt<0>]>>;
90 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
91 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
93 def X86vzext : SDNode<"X86ISD::VZEXT",
94 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
95 SDTCisInt<0>, SDTCisInt<1>]>>;
97 def X86vsext : SDNode<"X86ISD::VSEXT",
98 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
99 SDTCisInt<0>, SDTCisInt<1>]>>;
101 def X86vfpext : SDNode<"X86ISD::VFPEXT",
102 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
103 SDTCisFP<0>, SDTCisFP<1>]>>;
104 def X86vfpround: SDNode<"X86ISD::VFPROUND",
105 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
106 SDTCisFP<0>, SDTCisFP<1>]>>;
108 def X86vshldq : SDNode<"X86ISD::VSHLDQ", SDTIntShiftOp>;
109 def X86vshrdq : SDNode<"X86ISD::VSRLDQ", SDTIntShiftOp>;
110 def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP>;
111 def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
112 def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
114 def X86vshl : SDNode<"X86ISD::VSHL",
115 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
117 def X86vsrl : SDNode<"X86ISD::VSRL",
118 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
120 def X86vsra : SDNode<"X86ISD::VSRA",
121 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
124 def X86vshli : SDNode<"X86ISD::VSHLI", SDTIntShiftOp>;
125 def X86vsrli : SDNode<"X86ISD::VSRLI", SDTIntShiftOp>;
126 def X86vsrai : SDNode<"X86ISD::VSRAI", SDTIntShiftOp>;
128 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
130 SDTCisSameAs<2, 1>]>;
131 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
132 def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
134 def X86pmuludq : SDNode<"X86ISD::PMULUDQ",
135 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
136 SDTCisSameAs<1,2>]>>;
138 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
139 // translated into one of the target nodes below during lowering.
140 // Note: this is a work in progress...
141 def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
142 def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
145 def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
146 SDTCisSameAs<0,1>, SDTCisInt<2>]>;
147 def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
148 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
150 def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
151 def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
152 SDTCisSameAs<1,2>, SDTCisVT<3, i32>]>;
154 def SDTFma : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
155 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
157 def X86PAlign : SDNode<"X86ISD::PALIGN", SDTShuff3OpI>;
159 def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
160 def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
161 def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
163 def X86Shufp : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>;
165 def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
166 def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
167 def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
169 def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>;
170 def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>;
172 def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>;
173 def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>;
174 def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;
176 def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
177 def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
179 def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
180 def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
182 def X86VPermilp : SDNode<"X86ISD::VPERMILP", SDTShuff2OpI>;
183 def X86VPermv : SDNode<"X86ISD::VPERMV", SDTShuff2Op>;
184 def X86VPermi : SDNode<"X86ISD::VPERMI", SDTShuff2OpI>;
186 def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
188 def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
190 def X86Blendpw : SDNode<"X86ISD::BLENDPW", SDTBlend>;
191 def X86Blendps : SDNode<"X86ISD::BLENDPS", SDTBlend>;
192 def X86Blendpd : SDNode<"X86ISD::BLENDPD", SDTBlend>;
193 def X86Fmadd : SDNode<"X86ISD::FMADD", SDTFma>;
194 def X86Fnmadd : SDNode<"X86ISD::FNMADD", SDTFma>;
195 def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFma>;
196 def X86Fnmsub : SDNode<"X86ISD::FNMSUB", SDTFma>;
197 def X86Fmaddsub : SDNode<"X86ISD::FMADDSUB", SDTFma>;
198 def X86Fmsubadd : SDNode<"X86ISD::FMSUBADD", SDTFma>;
200 def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
201 SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>,
203 def SDT_PCMPESTRI : SDTypeProfile<2, 5, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
204 SDTCisVT<2, v16i8>, SDTCisVT<3, i32>,
205 SDTCisVT<4, v16i8>, SDTCisVT<5, i32>,
208 def X86pcmpistri : SDNode<"X86ISD::PCMPISTRI", SDT_PCMPISTRI>;
209 def X86pcmpestri : SDNode<"X86ISD::PCMPESTRI", SDT_PCMPESTRI>;
211 //===----------------------------------------------------------------------===//
212 // SSE Complex Patterns
213 //===----------------------------------------------------------------------===//
215 // These are 'extloads' from a scalar to the low element of a vector, zeroing
216 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
218 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
219 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
221 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
222 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
225 def ssmem : Operand<v4f32> {
226 let PrintMethod = "printf32mem";
227 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
228 let ParserMatchClass = X86MemAsmOperand;
229 let OperandType = "OPERAND_MEMORY";
231 def sdmem : Operand<v2f64> {
232 let PrintMethod = "printf64mem";
233 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
234 let ParserMatchClass = X86MemAsmOperand;
235 let OperandType = "OPERAND_MEMORY";
238 //===----------------------------------------------------------------------===//
239 // SSE pattern fragments
240 //===----------------------------------------------------------------------===//
242 // 128-bit load pattern fragments
243 // NOTE: all 128-bit integer vector loads are promoted to v2i64
244 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
245 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
246 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
248 // 256-bit load pattern fragments
249 // NOTE: all 256-bit integer vector loads are promoted to v4i64
250 def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
251 def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
252 def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
254 // 128-/256-bit extload pattern fragments
255 def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>;
256 def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>;
258 // Like 'store', but always requires 128-bit vector alignment.
259 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
260 (store node:$val, node:$ptr), [{
261 return cast<StoreSDNode>(N)->getAlignment() >= 16;
264 // Like 'store', but always requires 256-bit vector alignment.
265 def alignedstore256 : PatFrag<(ops node:$val, node:$ptr),
266 (store node:$val, node:$ptr), [{
267 return cast<StoreSDNode>(N)->getAlignment() >= 32;
270 // Like 'load', but always requires 128-bit vector alignment.
271 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
272 return cast<LoadSDNode>(N)->getAlignment() >= 16;
275 // Like 'X86vzload', but always requires 128-bit vector alignment.
276 def alignedX86vzload : PatFrag<(ops node:$ptr), (X86vzload node:$ptr), [{
277 return cast<MemSDNode>(N)->getAlignment() >= 16;
280 // Like 'load', but always requires 256-bit vector alignment.
281 def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
282 return cast<LoadSDNode>(N)->getAlignment() >= 32;
285 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
286 (f32 (alignedload node:$ptr))>;
287 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
288 (f64 (alignedload node:$ptr))>;
290 // 128-bit aligned load pattern fragments
291 // NOTE: all 128-bit integer vector loads are promoted to v2i64
292 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
293 (v4f32 (alignedload node:$ptr))>;
294 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
295 (v2f64 (alignedload node:$ptr))>;
296 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
297 (v2i64 (alignedload node:$ptr))>;
299 // 256-bit aligned load pattern fragments
300 // NOTE: all 256-bit integer vector loads are promoted to v4i64
301 def alignedloadv8f32 : PatFrag<(ops node:$ptr),
302 (v8f32 (alignedload256 node:$ptr))>;
303 def alignedloadv4f64 : PatFrag<(ops node:$ptr),
304 (v4f64 (alignedload256 node:$ptr))>;
305 def alignedloadv4i64 : PatFrag<(ops node:$ptr),
306 (v4i64 (alignedload256 node:$ptr))>;
308 // Like 'load', but uses special alignment checks suitable for use in
309 // memory operands in most SSE instructions, which are required to
310 // be naturally aligned on some targets but not on others. If the subtarget
311 // allows unaligned accesses, match any load, though this may require
312 // setting a feature bit in the processor (on startup, for example).
313 // Opteron 10h and later implement such a feature.
314 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
315 return Subtarget->hasVectorUAMem()
316 || cast<LoadSDNode>(N)->getAlignment() >= 16;
319 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
320 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
322 // 128-bit memop pattern fragments
323 // NOTE: all 128-bit integer vector loads are promoted to v2i64
324 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
325 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
326 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
328 // 256-bit memop pattern fragments
329 // NOTE: all 256-bit integer vector loads are promoted to v4i64
330 def memopv8f32 : PatFrag<(ops node:$ptr), (v8f32 (memop node:$ptr))>;
331 def memopv4f64 : PatFrag<(ops node:$ptr), (v4f64 (memop node:$ptr))>;
332 def memopv4i64 : PatFrag<(ops node:$ptr), (v4i64 (memop node:$ptr))>;
334 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
336 // FIXME: 8 byte alignment for mmx reads is not required
337 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
338 return cast<LoadSDNode>(N)->getAlignment() >= 8;
341 def memopmmx : PatFrag<(ops node:$ptr), (x86mmx (memop64 node:$ptr))>;
344 // Like 'store', but requires the non-temporal bit to be set
345 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
346 (st node:$val, node:$ptr), [{
347 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
348 return ST->isNonTemporal();
352 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
353 (st node:$val, node:$ptr), [{
354 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
355 return ST->isNonTemporal() && !ST->isTruncatingStore() &&
356 ST->getAddressingMode() == ISD::UNINDEXED &&
357 ST->getAlignment() >= 16;
361 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
362 (st node:$val, node:$ptr), [{
363 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
364 return ST->isNonTemporal() &&
365 ST->getAlignment() < 16;
369 // 128-bit bitconvert pattern fragments
370 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
371 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
372 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
373 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
374 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
375 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
377 // 256-bit bitconvert pattern fragments
378 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
379 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
380 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
381 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
383 def vzmovl_v2i64 : PatFrag<(ops node:$src),
384 (bitconvert (v2i64 (X86vzmovl
385 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
386 def vzmovl_v4i32 : PatFrag<(ops node:$src),
387 (bitconvert (v4i32 (X86vzmovl
388 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
390 def vzload_v2i64 : PatFrag<(ops node:$src),
391 (bitconvert (v2i64 (X86vzload node:$src)))>;
394 def fp32imm0 : PatLeaf<(f32 fpimm), [{
395 return N->isExactlyValue(+0.0);
398 // BYTE_imm - Transform bit immediates into byte immediates.
399 def BYTE_imm : SDNodeXForm<imm, [{
400 // Transformation function: imm >> 3
401 return getI32Imm(N->getZExtValue() >> 3);
404 // EXTRACT_get_vextractf128_imm xform function: convert extract_subvector index
405 // to VEXTRACTF128 imm.
406 def EXTRACT_get_vextractf128_imm : SDNodeXForm<extract_subvector, [{
407 return getI8Imm(X86::getExtractVEXTRACTF128Immediate(N));
410 // INSERT_get_vinsertf128_imm xform function: convert insert_subvector index to
412 def INSERT_get_vinsertf128_imm : SDNodeXForm<insert_subvector, [{
413 return getI8Imm(X86::getInsertVINSERTF128Immediate(N));
416 def vextractf128_extract : PatFrag<(ops node:$bigvec, node:$index),
417 (extract_subvector node:$bigvec,
419 return X86::isVEXTRACTF128Index(N);
420 }], EXTRACT_get_vextractf128_imm>;
422 def vinsertf128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
424 (insert_subvector node:$bigvec, node:$smallvec,
426 return X86::isVINSERTF128Index(N);
427 }], INSERT_get_vinsertf128_imm>;