lib/Target/X86/X86InstrFragmentsSIMD.td

   1 //===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file provides pattern fragments useful for SIMD instructions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 // MMX specific DAG Nodes.
  16 //===----------------------------------------------------------------------===//
  17
  18 // Low word of MMX to GPR.
  19 def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1,
  20                             [SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>;
  21 // GPR to low word of MMX.
  22 def MMX_X86movw2d : SDNode<"X86ISD::MMX_MOVW2D", SDTypeProfile<1, 1,
  23                             [SDTCisVT<0, x86mmx>, SDTCisVT<1, i32>]>>;
  24
  25 //===----------------------------------------------------------------------===//
  26 // MMX Pattern Fragments
  27 //===----------------------------------------------------------------------===//
  28
  29 def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
  30 def load_mvmmx : PatFrag<(ops node:$ptr),
  31                          (x86mmx (MMX_X86movw2d (load node:$ptr)))>;
  32 def bc_mmx  : PatFrag<(ops node:$in), (x86mmx  (bitconvert node:$in))>;
  33
  34 //===----------------------------------------------------------------------===//
  35 // SSE specific DAG Nodes.
  36 //===----------------------------------------------------------------------===//
  37
  38 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
  39                                        SDTCisFP<1>, SDTCisVT<3, i8>,
  40                                        SDTCisVec<1>]>;
  41
  42 def X86fmin    : SDNode<"X86ISD::FMIN",      SDTFPBinOp>;
  43 def X86fmax    : SDNode<"X86ISD::FMAX",      SDTFPBinOp>;
  44
  45 // Commutative and Associative FMIN and FMAX.
  46 def X86fminc    : SDNode<"X86ISD::FMINC", SDTFPBinOp,
  47     [SDNPCommutative, SDNPAssociative]>;
  48 def X86fmaxc    : SDNode<"X86ISD::FMAXC", SDTFPBinOp,
  49     [SDNPCommutative, SDNPAssociative]>;
  50
  51 def X86fand    : SDNode<"X86ISD::FAND",      SDTFPBinOp,
  52                         [SDNPCommutative, SDNPAssociative]>;
  53 def X86for     : SDNode<"X86ISD::FOR",       SDTFPBinOp,
  54                         [SDNPCommutative, SDNPAssociative]>;
  55 def X86fxor    : SDNode<"X86ISD::FXOR",      SDTFPBinOp,
  56                         [SDNPCommutative, SDNPAssociative]>;
  57 def X86fandn   : SDNode<"X86ISD::FANDN",     SDTFPBinOp,
  58                         [SDNPCommutative, SDNPAssociative]>;
  59 def X86frsqrt  : SDNode<"X86ISD::FRSQRT",    SDTFPUnaryOp>;
  60 def X86frcp    : SDNode<"X86ISD::FRCP",      SDTFPUnaryOp>;
  61 def X86frsqrt14s: SDNode<"X86ISD::FRSQRT",  SDTFPBinOp>;
  62 def X86frcp14s : SDNode<"X86ISD::FRCP",    SDTFPBinOp>;
  63 def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
  64 def X86fhadd   : SDNode<"X86ISD::FHADD",     SDTFPBinOp>;
  65 def X86fhsub   : SDNode<"X86ISD::FHSUB",     SDTFPBinOp>;
  66 def X86hadd    : SDNode<"X86ISD::HADD",      SDTIntBinOp>;
  67 def X86hsub    : SDNode<"X86ISD::HSUB",      SDTIntBinOp>;
  68 def X86comi    : SDNode<"X86ISD::COMI",      SDTX86CmpTest>;
  69 def X86ucomi   : SDNode<"X86ISD::UCOMI",     SDTX86CmpTest>;
  70 def X86cmps    : SDNode<"X86ISD::FSETCC",     SDTX86Cmps>;
  71 //def X86cmpsd   : SDNode<"X86ISD::FSETCCsd",    SDTX86Cmpsd>;
  72 def X86cvtdq2pd: SDNode<"X86ISD::CVTDQ2PD",
  73                  SDTypeProfile<1, 1, [SDTCisVT<0, v2f64>,
  74                                       SDTCisVT<1, v4i32>]>>;
  75 def X86cvtudq2pd: SDNode<"X86ISD::CVTUDQ2PD",
  76                  SDTypeProfile<1, 1, [SDTCisVT<0, v2f64>,
  77                                       SDTCisVT<1, v4i32>]>>;
  78 def X86pshufb  : SDNode<"X86ISD::PSHUFB",
  79                  SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
  80                                       SDTCisSameAs<0,2>]>>;
  81 def X86psadbw  : SDNode<"X86ISD::PSADBW",
  82                  SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>,
  83                                       SDTCVecEltisVT<1, i8>,
  84                                       SDTCisSameSizeAs<0,1>,
  85                                       SDTCisSameAs<1,2>]>>;
  86 def X86dbpsadbw : SDNode<"X86ISD::DBPSADBW",
  87                   SDTypeProfile<1, 3, [SDTCVecEltisVT<0, i16>,
  88                                        SDTCVecEltisVT<1, i8>,
  89                                        SDTCisSameSizeAs<0,1>,
  90                                        SDTCisSameAs<1,2>, SDTCisInt<3>]>>;
  91 def X86andnp   : SDNode<"X86ISD::ANDNP",
  92                  SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
  93                                       SDTCisSameAs<0,2>]>>;
  94 def X86psign   : SDNode<"X86ISD::PSIGN",
  95                  SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
  96                                       SDTCisSameAs<0,2>]>>;
  97 def X86pextrb  : SDNode<"X86ISD::PEXTRB",
  98                  SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
  99 def X86pextrw  : SDNode<"X86ISD::PEXTRW",
 100                  SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
 101 def X86pinsrb  : SDNode<"X86ISD::PINSRB",
 102                  SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
 103                                       SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
 104 def X86pinsrw  : SDNode<"X86ISD::PINSRW",
 105                  SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
 106                                       SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
 107 def X86insertps : SDNode<"X86ISD::INSERTPS",
 108                  SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
 109                                       SDTCisVT<2, v4f32>, SDTCisVT<3, i8>]>>;
 110 def X86vzmovl  : SDNode<"X86ISD::VZEXT_MOVL",
 111                  SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
 112
 113 def X86vzload  : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
 114                         [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 115
 116 def X86vzext   : SDNode<"X86ISD::VZEXT",
 117                          SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 118                                               SDTCisInt<0>, SDTCisInt<1>,
 119                                               SDTCisOpSmallerThanOp<1, 0>]>>;
 120
 121 def X86vsext   : SDNode<"X86ISD::VSEXT",
 122                          SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 123                                               SDTCisInt<0>, SDTCisInt<1>,
 124                                               SDTCisOpSmallerThanOp<1, 0>]>>;
 125
 126 def SDTVtrunc    : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 127                                        SDTCisInt<0>, SDTCisInt<1>,
 128                                        SDTCisOpSmallerThanOp<0, 1>]>;
 129
 130 def X86vtrunc    : SDNode<"X86ISD::VTRUNC",   SDTVtrunc>;
 131 def X86vtruncs   : SDNode<"X86ISD::VTRUNCS",  SDTVtrunc>;
 132 def X86vtruncus  : SDNode<"X86ISD::VTRUNCUS", SDTVtrunc>;
 133
 134 def X86trunc    : SDNode<"X86ISD::TRUNC",
 135                          SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>,
 136                                               SDTCisOpSmallerThanOp<0, 1>]>>;
 137 def X86vfpext  : SDNode<"X86ISD::VFPEXT",
 138                         SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 139                                              SDTCisFP<0>, SDTCisFP<1>,
 140                                              SDTCisOpSmallerThanOp<1, 0>]>>;
 141 def X86vfpround: SDNode<"X86ISD::VFPROUND",
 142                         SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 143                                              SDTCisFP<0>, SDTCisFP<1>,
 144                                              SDTCisOpSmallerThanOp<0, 1>]>>;
 145
 146 def X86fround: SDNode<"X86ISD::VFPROUND",
 147                         SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
 148                                              SDTCVecEltisVT<0, f32>,
 149                                              SDTCVecEltisVT<1, f64>,
 150                                              SDTCVecEltisVT<2, f64>,
 151                                              SDTCisOpSmallerThanOp<0, 1>]>>;
 152 def X86froundRnd: SDNode<"X86ISD::VFPROUND",
 153                         SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
 154                                              SDTCVecEltisVT<0, f32>,
 155                                              SDTCVecEltisVT<1, f64>,
 156                                              SDTCVecEltisVT<2, f64>,
 157                                              SDTCisOpSmallerThanOp<0, 1>,
 158                                              SDTCisInt<3>]>>;
 159
 160 def X86fpext  : SDNode<"X86ISD::VFPEXT",
 161                         SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
 162                                              SDTCVecEltisVT<0, f64>,
 163                                              SDTCVecEltisVT<1, f32>,
 164                                              SDTCVecEltisVT<2, f32>,
 165                                              SDTCisOpSmallerThanOp<1, 0>]>>;
 166
 167 def X86fpextRnd  : SDNode<"X86ISD::VFPEXT",
 168                         SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
 169                                              SDTCVecEltisVT<0, f64>,
 170                                              SDTCVecEltisVT<1, f32>,
 171                                              SDTCVecEltisVT<2, f32>,
 172                                              SDTCisOpSmallerThanOp<1, 0>,
 173                                              SDTCisInt<3>]>>;
 174
 175 def X86vshldq  : SDNode<"X86ISD::VSHLDQ",    SDTIntShiftOp>;
 176 def X86vshrdq  : SDNode<"X86ISD::VSRLDQ",    SDTIntShiftOp>;
 177 def X86cmpp    : SDNode<"X86ISD::CMPP",      SDTX86VFCMP>;
 178 def X86pcmpeq  : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
 179 def X86pcmpgt  : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
 180
 181 def X86IntCmpMask : SDTypeProfile<1, 2,
 182     [SDTCisVec<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>]>;
 183 def X86pcmpeqm  : SDNode<"X86ISD::PCMPEQM", X86IntCmpMask, [SDNPCommutative]>;
 184 def X86pcmpgtm  : SDNode<"X86ISD::PCMPGTM", X86IntCmpMask>;
 185
 186 def X86CmpMaskCC :
 187       SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
 188                        SDTCisVec<1>, SDTCisSameAs<2, 1>,
 189                        SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>]>;
 190 def X86CmpMaskCCRound :
 191       SDTypeProfile<1, 4, [SDTCisVec<0>,SDTCVecEltisVT<0, i1>,
 192                        SDTCisVec<1>, SDTCisSameAs<2, 1>,
 193                        SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>,
 194                        SDTCisInt<4>]>;
 195 def X86CmpMaskCCScalar :
 196       SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
 197
 198 def X86CmpMaskCCScalarRound :
 199       SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>,
 200                            SDTCisInt<4>]>;
 201
 202 def X86cmpm     : SDNode<"X86ISD::CMPM",     X86CmpMaskCC>;
 203 def X86cmpmRnd  : SDNode<"X86ISD::CMPM_RND", X86CmpMaskCCRound>;
 204 def X86cmpmu    : SDNode<"X86ISD::CMPMU",    X86CmpMaskCC>;
 205 def X86cmpms    : SDNode<"X86ISD::FSETCC",   X86CmpMaskCCScalar>;
 206 def X86cmpmsRnd : SDNode<"X86ISD::FSETCC",   X86CmpMaskCCScalarRound>;
 207
 208 def X86vshl    : SDNode<"X86ISD::VSHL",
 209                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 210                                       SDTCisVec<2>]>>;
 211 def X86vsrl    : SDNode<"X86ISD::VSRL",
 212                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 213                                       SDTCisVec<2>]>>;
 214 def X86vsra    : SDNode<"X86ISD::VSRA",
 215                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 216                                       SDTCisVec<2>]>>;
 217
 218 def X86vshli   : SDNode<"X86ISD::VSHLI", SDTIntShiftOp>;
 219 def X86vsrli   : SDNode<"X86ISD::VSRLI", SDTIntShiftOp>;
 220 def X86vsrai   : SDNode<"X86ISD::VSRAI", SDTIntShiftOp>;
 221
 222 def X86vprot   : SDNode<"X86ISD::VPROT",
 223                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 224                                       SDTCisVec<2>]>>;
 225 def X86vproti  : SDNode<"X86ISD::VPROTI",
 226                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 227                                       SDTCisVT<2, i8>]>>;
 228
 229 def X86vpshl   : SDNode<"X86ISD::VPSHL",
 230                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 231                                       SDTCisVec<2>]>>;
 232 def X86vpsha   : SDNode<"X86ISD::VPSHA",
 233                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 234                                       SDTCisVec<2>]>>;
 235
 236 def X86vpcom   : SDNode<"X86ISD::VPCOM",
 237                         SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 238                                       SDTCisVec<2>, SDTCisVT<3, i8>]>>;
 239 def X86vpcomu  : SDNode<"X86ISD::VPCOMU",
 240                         SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 241                                       SDTCisVec<2>, SDTCisVT<3, i8>]>>;
 242
 243 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
 244                                           SDTCisVec<1>,
 245                                           SDTCisSameAs<2, 1>]>;
 246 def X86addus   : SDNode<"X86ISD::ADDUS", SDTIntBinOp>;
 247 def X86subus   : SDNode<"X86ISD::SUBUS", SDTIntBinOp>;
 248 def X86adds    : SDNode<"X86ISD::ADDS", SDTIntBinOp>;
 249 def X86subs    : SDNode<"X86ISD::SUBS", SDTIntBinOp>;
 250 def X86mulhrs  : SDNode<"X86ISD::MULHRS" , SDTIntBinOp>;
 251 def X86avg     : SDNode<"X86ISD::AVG" , SDTIntBinOp>;
 252 def X86ptest   : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
 253 def X86testp   : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
 254 def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>;
 255 def X86ktest   : SDNode<"X86ISD::KTEST", SDTX86CmpPTest>;
 256 def X86testm   : SDNode<"X86ISD::TESTM", SDTypeProfile<1, 2, [SDTCisVec<0>,
 257                                           SDTCisVec<1>, SDTCisSameAs<2, 1>,
 258                                           SDTCVecEltisVT<0, i1>,
 259                                           SDTCisSameNumEltsAs<0, 1>]>>;
 260 def X86testnm  : SDNode<"X86ISD::TESTNM", SDTypeProfile<1, 2, [SDTCisVec<0>,
 261                                           SDTCisVec<1>, SDTCisSameAs<2, 1>,
 262                                           SDTCVecEltisVT<0, i1>,
 263                                           SDTCisSameNumEltsAs<0, 1>]>>;
 264 def X86select  : SDNode<"X86ISD::SELECT"     , SDTSelect>;
 265
 266 def X86pmuludq : SDNode<"X86ISD::PMULUDQ",
 267                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 268                                       SDTCisSameAs<1,2>]>>;
 269 def X86pmuldq  : SDNode<"X86ISD::PMULDQ",
 270                          SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 271                                        SDTCisSameAs<1,2>]>>;
 272
 273 def X86extrqi : SDNode<"X86ISD::EXTRQI",
 274                   SDTypeProfile<1, 3, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
 275                                        SDTCisVT<2, i8>, SDTCisVT<3, i8>]>>;
 276 def X86insertqi : SDNode<"X86ISD::INSERTQI",
 277                     SDTypeProfile<1, 4, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
 278                                          SDTCisSameAs<1,2>, SDTCisVT<3, i8>,
 279                                          SDTCisVT<4, i8>]>>;
 280
 281 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
 282 // translated into one of the target nodes below during lowering.
 283 // Note: this is a work in progress...
 284 def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
 285 def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 286                                 SDTCisSameAs<0,2>]>;
 287 def SDTShuff3Op : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 288                                 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>;
 289
 290 def SDTShuff2OpM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 291                                         SDTCisVec<2>]>;
 292 def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
 293                                  SDTCisSameAs<0,1>, SDTCisInt<2>]>;
 294 def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 295                                  SDTCisSameAs<0,2>, SDTCisInt<3>]>;
 296 def SDTFPBinOpImmRound: SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 297                              SDTCisSameAs<0,2>, SDTCisInt<3>, SDTCisInt<4>]>;
 298 def SDTFPUnaryOpImmRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 299                               SDTCisInt<2>, SDTCisInt<3>]>;
 300
 301 def SDTVBroadcast  : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
 302 def SDTVBroadcastm : SDTypeProfile<1, 1, [SDTCisVec<0>,
 303                                           SDTCisInt<0>, SDTCisInt<1>]>;
 304
 305 def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 306                              SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>;
 307
 308 def SDTTernlog  : SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 309                                 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>,
 310                                 SDTCisInt<4>]>;
 311
 312 def SDTFPBinOpRound : SDTypeProfile<1, 3, [      // fadd_round, fmul_round, etc.
 313   SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>, SDTCisInt<3>]>;
 314
 315 def SDTFPUnaryOpRound : SDTypeProfile<1, 2, [      // fsqrt_round, fgetexp_round, etc.
 316   SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]>;
 317
 318 def SDTFma : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
 319                            SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
 320 def SDTFmaRound : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
 321                            SDTCisSameAs<1,2>, SDTCisSameAs<1,3>, SDTCisInt<4>]>;
 322 def STDFp1SrcRm : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>,
 323                            SDTCisVec<0>, SDTCisInt<2>]>;
 324 def STDFp2SrcRm : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
 325                            SDTCisVec<0>, SDTCisInt<3>]>;
 326 def STDFp3SrcRm : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
 327                            SDTCisVec<0>, SDTCisInt<3>, SDTCisInt<4>]>;
 328
 329 def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>;
 330 def X86VAlign  : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>;
 331
 332 def X86Abs      : SDNode<"X86ISD::ABS", SDTIntUnaryOp>;
 333 def X86Conflict : SDNode<"X86ISD::CONFLICT", SDTIntUnaryOp>;
 334
 335 def X86PShufd  : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
 336 def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
 337 def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
 338
 339 def X86Shufp   : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>;
 340 def X86Shuf128 : SDNode<"X86ISD::SHUF128", SDTShuff3OpI>;
 341
 342 def X86Movddup  : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
 343 def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
 344 def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
 345
 346 def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>;
 347 def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>;
 348
 349 def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>;
 350 def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>;
 351 def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;
 352
 353 def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
 354 def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
 355
 356 def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<2, 1>]>;
 357 def X86Packss : SDNode<"X86ISD::PACKSS", SDTPack>;
 358 def X86Packus : SDNode<"X86ISD::PACKUS", SDTPack>;
 359
 360 def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
 361 def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
 362
 363 def X86vpmaddubsw  : SDNode<"X86ISD::VPMADDUBSW" , SDTPack>;
 364 def X86vpmaddwd    : SDNode<"X86ISD::VPMADDWD"   , SDTPack>;
 365
 366 def X86VPermilpv  : SDNode<"X86ISD::VPERMILPV", SDTShuff2OpM>;
 367 def X86VPermilpi  : SDNode<"X86ISD::VPERMILPI", SDTShuff2OpI>;
 368 def X86VPermv     : SDNode<"X86ISD::VPERMV",    SDTShuff2Op>;
 369 def X86VPermi     : SDNode<"X86ISD::VPERMI",    SDTShuff2OpI>;
 370 def X86VPermt2Fp   : SDNode<"X86ISD::VPERMV3",
 371                     SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>,
 372                                          SDTCisSameAs<0,1>, SDTCisInt<2>,
 373                                          SDTCisVec<2>, SDTCisSameNumEltsAs<0, 2>,
 374                                          SDTCisSameAs<0,3>]>, []>;
 375 def X86VPermt2Int  : SDNode<"X86ISD::VPERMV3",
 376                     SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisInt<0>,
 377                                          SDTCisSameAs<0,1>, SDTCisSameAs<0,2>,
 378                                          SDTCisSameAs<0,3>]>, []>;
 379
 380 def X86VPermi2X   : SDNode<"X86ISD::VPERMIV3", SDTShuff3Op>;
 381 def X86vpternlog  : SDNode<"X86ISD::VPTERNLOG", SDTTernlog>;
 382
 383 def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
 384
 385 def X86VFixupimm   : SDNode<"X86ISD::VFIXUPIMM", SDTFPBinOpImmRound>;
 386 def X86VRange      : SDNode<"X86ISD::VRANGE",    SDTFPBinOpImmRound>;
 387 def X86VReduce     : SDNode<"X86ISD::VREDUCE",   SDTFPUnaryOpImmRound>;
 388 def X86VRndScale   : SDNode<"X86ISD::VRNDSCALE", SDTFPUnaryOpImmRound>;
 389 def X86VGetMant    : SDNode<"X86ISD::VGETMANT",  SDTFPUnaryOpImmRound>;
 390 def X86Vfpclass    : SDNode<"X86ISD::VFPCLASS",
 391                        SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
 392                                             SDTCisVec<1>, SDTCisInt<2>]>, []>;
 393 def X86Vfpclasss   : SDNode<"X86ISD::VFPCLASS", SDTypeProfile<1, 2, [SDTCisInt<0>,
 394                               SDTCisFP<1>, SDTCisInt<2>]>,[]>;
 395
 396 def X86SubVBroadcast : SDNode<"X86ISD::SUBV_BROADCAST",
 397                     SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 398                                          SDTCisSubVecOfVec<1, 0>]>, []>;
 399 // SDTCisSubVecOfVec restriction cannot be applied for 128 bit version of VBROADCASTI32x2.
 400 def X86SubV32x2Broadcast : SDNode<"X86ISD::SUBV_BROADCAST",
 401                     SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>]>, []>;
 402
 403 def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
 404 def X86VBroadcastm : SDNode<"X86ISD::VBROADCASTM", SDTVBroadcastm>;
 405 def X86Vinsert   : SDNode<"X86ISD::VINSERT",  SDTypeProfile<1, 3,
 406                               [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
 407 def X86Vextract   : SDNode<"X86ISD::VEXTRACT",  SDTypeProfile<1, 2,
 408                               [SDTCisVec<1>, SDTCisPtrTy<2>]>, []>;
 409
 410 def X86Blendi    : SDNode<"X86ISD::BLENDI",   SDTBlend>;
 411
 412 def X86Addsub    : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>;
 413
 414 def X86faddRnd   : SDNode<"X86ISD::FADD_RND",  SDTFPBinOpRound>;
 415 def X86fsubRnd   : SDNode<"X86ISD::FSUB_RND",  SDTFPBinOpRound>;
 416 def X86fmulRnd   : SDNode<"X86ISD::FMUL_RND",  SDTFPBinOpRound>;
 417 def X86fdivRnd   : SDNode<"X86ISD::FDIV_RND",  SDTFPBinOpRound>;
 418 def X86fmaxRnd   : SDNode<"X86ISD::FMAX_RND",       SDTFPBinOpRound>;
 419 def X86scalef    : SDNode<"X86ISD::SCALEF",         SDTFPBinOpRound>;
 420 def X86fminRnd   : SDNode<"X86ISD::FMIN_RND",       SDTFPBinOpRound>;
 421 def X86fsqrtRnd     : SDNode<"X86ISD::FSQRT_RND",   SDTFPUnaryOpRound>;
 422 def X86fsqrtRnds    : SDNode<"X86ISD::FSQRT_RND",   STDFp2SrcRm>;
 423 def X86fgetexpRnd   : SDNode<"X86ISD::FGETEXP_RND", SDTFPUnaryOpRound>;
 424 def X86fgetexpRnds  : SDNode<"X86ISD::FGETEXP_RND", STDFp2SrcRm>;
 425
 426 def X86Fmadd     : SDNode<"X86ISD::FMADD",     SDTFma>;
 427 def X86Fnmadd    : SDNode<"X86ISD::FNMADD",    SDTFma>;
 428 def X86Fmsub     : SDNode<"X86ISD::FMSUB",     SDTFma>;
 429 def X86Fnmsub    : SDNode<"X86ISD::FNMSUB",    SDTFma>;
 430 def X86Fmaddsub  : SDNode<"X86ISD::FMADDSUB",  SDTFma>;
 431 def X86Fmsubadd  : SDNode<"X86ISD::FMSUBADD",  SDTFma>;
 432
 433 def X86FmaddRnd     : SDNode<"X86ISD::FMADD_RND",     SDTFmaRound>;
 434 def X86FnmaddRnd    : SDNode<"X86ISD::FNMADD_RND",    SDTFmaRound>;
 435 def X86FmsubRnd     : SDNode<"X86ISD::FMSUB_RND",     SDTFmaRound>;
 436 def X86FnmsubRnd    : SDNode<"X86ISD::FNMSUB_RND",    SDTFmaRound>;
 437 def X86FmaddsubRnd  : SDNode<"X86ISD::FMADDSUB_RND",  SDTFmaRound>;
 438 def X86FmsubaddRnd  : SDNode<"X86ISD::FMSUBADD_RND",  SDTFmaRound>;
 439
 440 def X86rsqrt28   : SDNode<"X86ISD::RSQRT28",  STDFp1SrcRm>;
 441 def X86rcp28     : SDNode<"X86ISD::RCP28",    STDFp1SrcRm>;
 442 def X86exp2      : SDNode<"X86ISD::EXP2",     STDFp1SrcRm>;
 443
 444 def X86rsqrt28s  : SDNode<"X86ISD::RSQRT28",   STDFp2SrcRm>;
 445 def X86rcp28s    : SDNode<"X86ISD::RCP28",     STDFp2SrcRm>;
 446 def X86RndScales : SDNode<"X86ISD::VRNDSCALE", STDFp3SrcRm>;
 447 def X86Reduces   : SDNode<"X86ISD::VREDUCE",   STDFp3SrcRm>;
 448 def X86GetMants  : SDNode<"X86ISD::VGETMANT",  STDFp3SrcRm>;
 449
 450 def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
 451                                          SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>,
 452                                          SDTCisVT<4, i8>]>;
 453 def SDT_PCMPESTRI : SDTypeProfile<2, 5, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
 454                                          SDTCisVT<2, v16i8>, SDTCisVT<3, i32>,
 455                                          SDTCisVT<4, v16i8>, SDTCisVT<5, i32>,
 456                                          SDTCisVT<6, i8>]>;
 457
 458 def X86pcmpistri : SDNode<"X86ISD::PCMPISTRI", SDT_PCMPISTRI>;
 459 def X86pcmpestri : SDNode<"X86ISD::PCMPESTRI", SDT_PCMPESTRI>;
 460
 461 def X86compress: SDNode<"X86ISD::COMPRESS", SDTypeProfile<1, 1,
 462                               [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
 463 def X86expand  : SDNode<"X86ISD::EXPAND", SDTypeProfile<1, 1,
 464                               [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
 465
 466 def SDTintToFPRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>,
 467                                SDTCisSameAs<0,1>, SDTCisInt<2>, SDTCisInt<3>]>;
 468
 469 def SDTDoubleToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 470                                          SDTCisInt<0>, SDTCVecEltisVT<1, f64>]>;
 471 def SDTFloatToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 472                                          SDTCisInt<0>, SDTCVecEltisVT<1, f32>]>;
 473
 474 def SDTDoubleToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 475                                          SDTCisInt<0>, SDTCVecEltisVT<1, f64>]>;
 476 def SDTSDoubleToIntRnd: SDTypeProfile<1, 2, [SDTCisInt<0>,SDTCisFP<1>,
 477                                              SDTCVecEltisVT<1, f64>, SDTCisInt<2>]>;
 478 def SDTFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 479                                          SDTCisInt<0>, SDTCVecEltisVT<1, f32>]>;
 480 def SDTSFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisFP<1>,
 481                                             SDTCVecEltisVT<1, f32>, SDTCisInt<2>]>;
 482 def SDTVintToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 483                                            SDTCisFP<0>, SDTCVecEltisVT<1, i32>,
 484                                            SDTCisInt<2>]>;
 485 def SDTVlongToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 486                                            SDTCisFP<0>, SDTCVecEltisVT<1, i64>,
 487                                            SDTCisInt<2>]>;
 488
 489 def SDTVFPToIntRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 490                                            SDTCisFP<1>, SDTCVecEltisVT<0, i32>,
 491                                            SDTCisInt<2>]>;
 492 def SDTVFPToLongRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 493                                            SDTCisFP<1>, SDTCVecEltisVT<0, i64>,
 494                                            SDTCisInt<2>]>;
 495
 496 // Scalar
 497 def X86SintToFpRnd  : SDNode<"X86ISD::SINT_TO_FP_RND",  SDTintToFPRound>;
 498 def X86UintToFpRnd  : SDNode<"X86ISD::UINT_TO_FP_RND",  SDTintToFPRound>;
 499
 500 def X86cvttss2IntRnd      : SDNode<"X86ISD::FP_TO_SINT_RND",  SDTSFloatToIntRnd>;
 501 def X86cvttss2UIntRnd     : SDNode<"X86ISD::FP_TO_UINT_RND",  SDTSFloatToIntRnd>;
 502 def X86cvttsd2IntRnd      : SDNode<"X86ISD::FP_TO_SINT_RND",  SDTSDoubleToIntRnd>;
 503 def X86cvttsd2UIntRnd     : SDNode<"X86ISD::FP_TO_UINT_RND",  SDTSDoubleToIntRnd>;
 504 // Vector with rounding mode
 505
 506 // cvtt fp-to-int staff
 507 def X86VFpToSintRnd   : SDNode<"ISD::FP_TO_SINT",  SDTVFPToIntRound>;
 508 def X86VFpToUintRnd   : SDNode<"ISD::FP_TO_UINT",  SDTVFPToIntRound>;
 509 def X86VFpToSlongRnd  : SDNode<"ISD::FP_TO_SINT",  SDTVFPToLongRound>;
 510 def X86VFpToUlongRnd  : SDNode<"ISD::FP_TO_UINT",  SDTVFPToLongRound>;
 511
 512 def X86VSintToFpRnd   : SDNode<"ISD::SINT_TO_FP",  SDTVintToFPRound>;
 513 def X86VUintToFpRnd   : SDNode<"ISD::UINT_TO_FP",  SDTVintToFPRound>;
 514 def X86VSlongToFpRnd  : SDNode<"ISD::SINT_TO_FP",  SDTVlongToFPRound>;
 515 def X86VUlongToFpRnd  : SDNode<"ISD::UINT_TO_FP",  SDTVlongToFPRound>;
 516
 517 // cvt fp-to-int staff
 518 def X86cvtps2IntRnd      : SDNode<"X86ISD::FP_TO_SINT_RND",  SDTFloatToIntRnd>;
 519 def X86cvtps2UIntRnd     : SDNode<"X86ISD::FP_TO_UINT_RND",  SDTFloatToIntRnd>;
 520 def X86cvtpd2IntRnd      : SDNode<"X86ISD::FP_TO_SINT_RND",  SDTDoubleToIntRnd>;
 521 def X86cvtpd2UIntRnd     : SDNode<"X86ISD::FP_TO_UINT_RND",  SDTDoubleToIntRnd>;
 522
 523 // Vector without rounding mode
 524 def X86cvtps2Int      : SDNode<"X86ISD::FP_TO_SINT_RND",  SDTFloatToInt>;
 525 def X86cvtps2UInt     : SDNode<"X86ISD::FP_TO_UINT_RND",  SDTFloatToInt>;
 526 def X86cvtpd2Int      : SDNode<"X86ISD::FP_TO_SINT_RND",  SDTDoubleToInt>;
 527 def X86cvtpd2UInt     : SDNode<"X86ISD::FP_TO_UINT_RND",  SDTDoubleToInt>;
 528
 529 def X86cvtph2ps     : SDNode<"ISD::FP16_TO_FP",
 530                               SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 531                                                    SDTCVecEltisVT<0, f32>,
 532                                                    SDTCVecEltisVT<1, i16>,
 533                                                    SDTCisFP<0>, SDTCisInt<2>]> >;
 534
 535 def X86cvtps2ph   : SDNode<"ISD::FP_TO_FP16",
 536                         SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>,
 537                                              SDTCVecEltisVT<0, i16>,
 538                                              SDTCVecEltisVT<1, f32>,
 539                                              SDTCisFP<1>, SDTCisInt<2>, SDTCisInt<3>]> >;
 540 def X86vfpextRnd  : SDNode<"X86ISD::VFPEXT",
 541                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 542                                              SDTCisFP<0>, SDTCisFP<1>,
 543                                              SDTCisOpSmallerThanOp<1, 0>,
 544                                              SDTCisInt<2>]>>;
 545 def X86vfproundRnd: SDNode<"X86ISD::VFPROUND",
 546                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 547                                              SDTCisFP<0>, SDTCisFP<1>,
 548                                              SDTCVecEltisVT<0, f32>,
 549                                              SDTCVecEltisVT<1, f64>,
 550                                              SDTCisInt<2>]>>;
 551
 552 //===----------------------------------------------------------------------===//
 553 // SSE Complex Patterns
 554 //===----------------------------------------------------------------------===//
 555
 556 // These are 'extloads' from a scalar to the low element of a vector, zeroing
 557 // the top elements.  These are used for the SSE 'ss' and 'sd' instruction
 558 // forms.
 559 def sse_load_f32 : ComplexPattern<v4f32, 5, "selectScalarSSELoad", [],
 560                                   [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
 561                                    SDNPWantRoot]>;
 562 def sse_load_f64 : ComplexPattern<v2f64, 5, "selectScalarSSELoad", [],
 563                                   [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
 564                                    SDNPWantRoot]>;
 565
 566 def ssmem : Operand<v4f32> {
 567   let PrintMethod = "printf32mem";
 568   let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
 569   let ParserMatchClass = X86Mem32AsmOperand;
 570   let OperandType = "OPERAND_MEMORY";
 571 }
 572 def sdmem : Operand<v2f64> {
 573   let PrintMethod = "printf64mem";
 574   let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
 575   let ParserMatchClass = X86Mem64AsmOperand;
 576   let OperandType = "OPERAND_MEMORY";
 577 }
 578
 579 //===----------------------------------------------------------------------===//
 580 // SSE pattern fragments
 581 //===----------------------------------------------------------------------===//
 582
 583 // 128-bit load pattern fragments
 584 // NOTE: all 128-bit integer vector loads are promoted to v2i64
 585 def loadv4f32    : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
 586 def loadv2f64    : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
 587 def loadv2i64    : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
 588
 589 // 256-bit load pattern fragments
 590 // NOTE: all 256-bit integer vector loads are promoted to v4i64
 591 def loadv8f32    : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
 592 def loadv4f64    : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
 593 def loadv4i64    : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
 594
 595 // 512-bit load pattern fragments
 596 def loadv16f32   : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>;
 597 def loadv8f64    : PatFrag<(ops node:$ptr), (v8f64 (load node:$ptr))>;
 598 def loadv64i8    : PatFrag<(ops node:$ptr), (v64i8 (load node:$ptr))>;
 599 def loadv32i16   : PatFrag<(ops node:$ptr), (v32i16 (load node:$ptr))>;
 600 def loadv16i32   : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>;
 601 def loadv8i64    : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>;
 602
 603 // 128-/256-/512-bit extload pattern fragments
 604 def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>;
 605 def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>;
 606 def extloadv8f32 : PatFrag<(ops node:$ptr), (v8f64 (extloadvf32 node:$ptr))>;
 607
 608 // These are needed to match a scalar load that is used in a vector-only
 609 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
 610 // The memory operand is required to be a 128-bit load, so it must be converted
 611 // from a vector to a scalar.
 612 def loadf32_128 : PatFrag<(ops node:$ptr),
 613   (f32 (vector_extract (loadv4f32 node:$ptr), (iPTR 0)))>;
 614 def loadf64_128 : PatFrag<(ops node:$ptr),
 615   (f64 (vector_extract (loadv2f64 node:$ptr), (iPTR 0)))>;
 616
 617 // Like 'store', but always requires 128-bit vector alignment.
 618 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
 619                            (store node:$val, node:$ptr), [{
 620   return cast<StoreSDNode>(N)->getAlignment() >= 16;
 621 }]>;
 622
 623 // Like 'store', but always requires 256-bit vector alignment.
 624 def alignedstore256 : PatFrag<(ops node:$val, node:$ptr),
 625                               (store node:$val, node:$ptr), [{
 626   return cast<StoreSDNode>(N)->getAlignment() >= 32;
 627 }]>;
 628
 629 // Like 'store', but always requires 512-bit vector alignment.
 630 def alignedstore512 : PatFrag<(ops node:$val, node:$ptr),
 631                               (store node:$val, node:$ptr), [{
 632   return cast<StoreSDNode>(N)->getAlignment() >= 64;
 633 }]>;
 634
 635 // Like 'load', but always requires 128-bit vector alignment.
 636 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 637   return cast<LoadSDNode>(N)->getAlignment() >= 16;
 638 }]>;
 639
 640 // Like 'X86vzload', but always requires 128-bit vector alignment.
 641 def alignedX86vzload : PatFrag<(ops node:$ptr), (X86vzload node:$ptr), [{
 642   return cast<MemSDNode>(N)->getAlignment() >= 16;
 643 }]>;
 644
 645 // Like 'load', but always requires 256-bit vector alignment.
 646 def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 647   return cast<LoadSDNode>(N)->getAlignment() >= 32;
 648 }]>;
 649
 650 // Like 'load', but always requires 512-bit vector alignment.
 651 def alignedload512 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 652   return cast<LoadSDNode>(N)->getAlignment() >= 64;
 653 }]>;
 654
 655 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
 656                                (f32 (alignedload node:$ptr))>;
 657 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
 658                                (f64 (alignedload node:$ptr))>;
 659
 660 // 128-bit aligned load pattern fragments
 661 // NOTE: all 128-bit integer vector loads are promoted to v2i64
 662 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
 663                                (v4f32 (alignedload node:$ptr))>;
 664 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
 665                                (v2f64 (alignedload node:$ptr))>;
 666 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
 667                                (v2i64 (alignedload node:$ptr))>;
 668
 669 // 256-bit aligned load pattern fragments
 670 // NOTE: all 256-bit integer vector loads are promoted to v4i64
 671 def alignedloadv8f32 : PatFrag<(ops node:$ptr),
 672                                (v8f32 (alignedload256 node:$ptr))>;
 673 def alignedloadv4f64 : PatFrag<(ops node:$ptr),
 674                                (v4f64 (alignedload256 node:$ptr))>;
 675 def alignedloadv4i64 : PatFrag<(ops node:$ptr),
 676                                (v4i64 (alignedload256 node:$ptr))>;
 677
 678 // 512-bit aligned load pattern fragments
 679 def alignedloadv16f32 : PatFrag<(ops node:$ptr),
 680                                 (v16f32 (alignedload512 node:$ptr))>;
 681 def alignedloadv16i32 : PatFrag<(ops node:$ptr),
 682                                 (v16i32 (alignedload512 node:$ptr))>;
 683 def alignedloadv8f64  : PatFrag<(ops node:$ptr),
 684                                 (v8f64  (alignedload512 node:$ptr))>;
 685 def alignedloadv8i64  : PatFrag<(ops node:$ptr),
 686                                 (v8i64  (alignedload512 node:$ptr))>;
 687
 688 // Like 'load', but uses special alignment checks suitable for use in
 689 // memory operands in most SSE instructions, which are required to
 690 // be naturally aligned on some targets but not on others.  If the subtarget
 691 // allows unaligned accesses, match any load, though this may require
 692 // setting a feature bit in the processor (on startup, for example).
 693 // Opteron 10h and later implement such a feature.
 694 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 695   return    Subtarget->hasSSEUnalignedMem()
 696          || cast<LoadSDNode>(N)->getAlignment() >= 16;
 697 }]>;
 698
 699 def memopfsf32 : PatFrag<(ops node:$ptr), (f32   (memop node:$ptr))>;
 700 def memopfsf64 : PatFrag<(ops node:$ptr), (f64   (memop node:$ptr))>;
 701
 702 // 128-bit memop pattern fragments
 703 // NOTE: all 128-bit integer vector loads are promoted to v2i64
 704 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
 705 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
 706 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
 707
 708 // These are needed to match a scalar memop that is used in a vector-only
 709 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
 710 // The memory operand is required to be a 128-bit load, so it must be converted
 711 // from a vector to a scalar.
 712 def memopfsf32_128 : PatFrag<(ops node:$ptr),
 713   (f32 (vector_extract (memopv4f32 node:$ptr), (iPTR 0)))>;
 714 def memopfsf64_128 : PatFrag<(ops node:$ptr),
 715   (f64 (vector_extract (memopv2f64 node:$ptr), (iPTR 0)))>;
 716
 717
 718 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
 719 // 16-byte boundary.
 720 // FIXME: 8 byte alignment for mmx reads is not required
 721 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 722   return cast<LoadSDNode>(N)->getAlignment() >= 8;
 723 }]>;
 724
 725 def memopmmx  : PatFrag<(ops node:$ptr), (x86mmx  (memop64 node:$ptr))>;
 726
 727 def mgatherv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 728   (masked_gather node:$src1, node:$src2, node:$src3) , [{
 729   if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
 730     return (Mgt->getIndex().getValueType() == MVT::v4i32 ||
 731             Mgt->getBasePtr().getValueType() == MVT::v4i32);
 732   return false;
 733 }]>;
 734
 735 def mgatherv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 736   (masked_gather node:$src1, node:$src2, node:$src3) , [{
 737   if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
 738     return (Mgt->getIndex().getValueType() == MVT::v8i32 ||
 739             Mgt->getBasePtr().getValueType() == MVT::v8i32);
 740   return false;
 741 }]>;
 742
 743 def mgatherv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 744   (masked_gather node:$src1, node:$src2, node:$src3) , [{
 745   if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
 746     return (Mgt->getIndex().getValueType() == MVT::v2i64 ||
 747             Mgt->getBasePtr().getValueType() == MVT::v2i64);
 748   return false;
 749 }]>;
 750 def mgatherv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 751   (masked_gather node:$src1, node:$src2, node:$src3) , [{
 752   if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
 753     return (Mgt->getIndex().getValueType() == MVT::v4i64 ||
 754             Mgt->getBasePtr().getValueType() == MVT::v4i64);
 755   return false;
 756 }]>;
 757 def mgatherv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 758   (masked_gather node:$src1, node:$src2, node:$src3) , [{
 759   if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
 760     return (Mgt->getIndex().getValueType() == MVT::v8i64 ||
 761             Mgt->getBasePtr().getValueType() == MVT::v8i64);
 762   return false;
 763 }]>;
 764 def mgatherv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 765   (masked_gather node:$src1, node:$src2, node:$src3) , [{
 766   if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
 767     return (Mgt->getIndex().getValueType() == MVT::v16i32 ||
 768             Mgt->getBasePtr().getValueType() == MVT::v16i32);
 769   return false;
 770 }]>;
 771
 772 def mscatterv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 773   (masked_scatter node:$src1, node:$src2, node:$src3) , [{
 774   if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
 775     return (Sc->getIndex().getValueType() == MVT::v2i64 ||
 776             Sc->getBasePtr().getValueType() == MVT::v2i64);
 777   return false;
 778 }]>;
 779
 780 def mscatterv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 781   (masked_scatter node:$src1, node:$src2, node:$src3) , [{
 782   if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
 783     return (Sc->getIndex().getValueType() == MVT::v4i32 ||
 784             Sc->getBasePtr().getValueType() == MVT::v4i32);
 785   return false;
 786 }]>;
 787
 788 def mscatterv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 789   (masked_scatter node:$src1, node:$src2, node:$src3) , [{
 790   if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
 791     return (Sc->getIndex().getValueType() == MVT::v4i64 ||
 792             Sc->getBasePtr().getValueType() == MVT::v4i64);
 793   return false;
 794 }]>;
 795
 796 def mscatterv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 797   (masked_scatter node:$src1, node:$src2, node:$src3) , [{
 798   if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
 799     return (Sc->getIndex().getValueType() == MVT::v8i32 ||
 800             Sc->getBasePtr().getValueType() == MVT::v8i32);
 801   return false;
 802 }]>;
 803
 804 def mscatterv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 805   (masked_scatter node:$src1, node:$src2, node:$src3) , [{
 806   if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
 807     return (Sc->getIndex().getValueType() == MVT::v8i64 ||
 808             Sc->getBasePtr().getValueType() == MVT::v8i64);
 809   return false;
 810 }]>;
 811 def mscatterv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 812   (masked_scatter node:$src1, node:$src2, node:$src3) , [{
 813   if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
 814     return (Sc->getIndex().getValueType() == MVT::v16i32 ||
 815             Sc->getBasePtr().getValueType() == MVT::v16i32);
 816   return false;
 817 }]>;
 818
 819 // 128-bit bitconvert pattern fragments
 820 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
 821 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
 822 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
 823 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
 824 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
 825 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
 826
 827 // 256-bit bitconvert pattern fragments
 828 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
 829 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
 830 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
 831 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
 832 def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>;
 833
 834 // 512-bit bitconvert pattern fragments
 835 def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
 836 def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
 837 def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>;
 838 def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>;
 839
 840 def vzmovl_v2i64 : PatFrag<(ops node:$src),
 841                            (bitconvert (v2i64 (X86vzmovl
 842                              (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
 843 def vzmovl_v4i32 : PatFrag<(ops node:$src),
 844                            (bitconvert (v4i32 (X86vzmovl
 845                              (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
 846
 847 def vzload_v2i64 : PatFrag<(ops node:$src),
 848                            (bitconvert (v2i64 (X86vzload node:$src)))>;
 849
 850
 851 def fp32imm0 : PatLeaf<(f32 fpimm), [{
 852   return N->isExactlyValue(+0.0);
 853 }]>;
 854
 855 def I8Imm : SDNodeXForm<imm, [{
 856   // Transformation function: get the low 8 bits.
 857   return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
 858 }]>;
 859
 860 def FROUND_NO_EXC : ImmLeaf<i32, [{ return Imm == 8; }]>;
 861 def FROUND_CURRENT : ImmLeaf<i32, [{
 862   return Imm == X86::STATIC_ROUNDING::CUR_DIRECTION;
 863 }]>;
 864
 865 // BYTE_imm - Transform bit immediates into byte immediates.
 866 def BYTE_imm  : SDNodeXForm<imm, [{
 867   // Transformation function: imm >> 3
 868   return getI32Imm(N->getZExtValue() >> 3, SDLoc(N));
 869 }]>;
 870
 871 // EXTRACT_get_vextract128_imm xform function: convert extract_subvector index
 872 // to VEXTRACTF128/VEXTRACTI128 imm.
 873 def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{
 874   return getI8Imm(X86::getExtractVEXTRACT128Immediate(N), SDLoc(N));
 875 }]>;
 876
 877 // INSERT_get_vinsert128_imm xform function: convert insert_subvector index to
 878 // VINSERTF128/VINSERTI128 imm.
 879 def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{
 880   return getI8Imm(X86::getInsertVINSERT128Immediate(N), SDLoc(N));
 881 }]>;
 882
 883 // EXTRACT_get_vextract256_imm xform function: convert extract_subvector index
 884 // to VEXTRACTF64x4 imm.
 885 def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{
 886   return getI8Imm(X86::getExtractVEXTRACT256Immediate(N), SDLoc(N));
 887 }]>;
 888
 889 // INSERT_get_vinsert256_imm xform function: convert insert_subvector index to
 890 // VINSERTF64x4 imm.
 891 def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{
 892   return getI8Imm(X86::getInsertVINSERT256Immediate(N), SDLoc(N));
 893 }]>;
 894
 895 def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index),
 896                                    (extract_subvector node:$bigvec,
 897                                                       node:$index), [{
 898   return X86::isVEXTRACT128Index(N);
 899 }], EXTRACT_get_vextract128_imm>;
 900
 901 def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
 902                                       node:$index),
 903                                  (insert_subvector node:$bigvec, node:$smallvec,
 904                                                    node:$index), [{
 905   return X86::isVINSERT128Index(N);
 906 }], INSERT_get_vinsert128_imm>;
 907
 908
 909 def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index),
 910                                    (extract_subvector node:$bigvec,
 911                                                       node:$index), [{
 912   return X86::isVEXTRACT256Index(N);
 913 }], EXTRACT_get_vextract256_imm>;
 914
 915 def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
 916                                       node:$index),
 917                                  (insert_subvector node:$bigvec, node:$smallvec,
 918                                                    node:$index), [{
 919   return X86::isVINSERT256Index(N);
 920 }], INSERT_get_vinsert256_imm>;
 921
 922 def masked_load_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 923                          (masked_load node:$src1, node:$src2, node:$src3), [{
 924   if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
 925     return Load->getAlignment() >= 16;
 926   return false;
 927 }]>;
 928
 929 def masked_load_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 930                          (masked_load node:$src1, node:$src2, node:$src3), [{
 931   if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
 932     return Load->getAlignment() >= 32;
 933   return false;
 934 }]>;
 935
 936 def masked_load_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 937                          (masked_load node:$src1, node:$src2, node:$src3), [{
 938   if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
 939     return Load->getAlignment() >= 64;
 940   return false;
 941 }]>;
 942
 943 def masked_load_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 944                          (masked_load node:$src1, node:$src2, node:$src3), [{
 945   return isa<MaskedLoadSDNode>(N);
 946 }]>;
 947
 948 // masked store fragments.
 949 // X86mstore can't be implemented in core DAG files because some targets
 950 // doesn't support vector type ( llvm-tblgen will fail)
 951 def X86mstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 952                         (masked_store node:$src1, node:$src2, node:$src3), [{
 953   return !cast<MaskedStoreSDNode>(N)->isTruncatingStore();
 954 }]>;
 955
 956 def masked_store_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 957                          (X86mstore node:$src1, node:$src2, node:$src3), [{
 958   if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
 959     return Store->getAlignment() >= 16;
 960   return false;
 961 }]>;
 962
 963 def masked_store_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 964                          (X86mstore node:$src1, node:$src2, node:$src3), [{
 965   if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
 966     return Store->getAlignment() >= 32;
 967   return false;
 968 }]>;
 969
 970 def masked_store_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 971                          (X86mstore node:$src1, node:$src2, node:$src3), [{
 972   if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
 973     return Store->getAlignment() >= 64;
 974   return false;
 975 }]>;
 976
 977 def masked_store_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 978                          (X86mstore node:$src1, node:$src2, node:$src3), [{
 979   return isa<MaskedStoreSDNode>(N);
 980 }]>;
 981
 982 // masked truncstore fragments
 983 // X86mtruncstore can't be implemented in core DAG files because some targets
 984 // doesn't support vector type ( llvm-tblgen will fail)
 985 def X86mtruncstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 986                              (masked_store node:$src1, node:$src2, node:$src3), [{
 987     return cast<MaskedStoreSDNode>(N)->isTruncatingStore();
 988 }]>;
 989 def masked_truncstorevi8 :
 990   PatFrag<(ops node:$src1, node:$src2, node:$src3),
 991           (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
 992   return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
 993 }]>;
 994 def masked_truncstorevi16 :
 995   PatFrag<(ops node:$src1, node:$src2, node:$src3),
 996           (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
 997   return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
 998 }]>;
 999 def masked_truncstorevi32 :
1000   PatFrag<(ops node:$src1, node:$src2, node:$src3),
1001           (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
1002   return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
1003 }]>;