1 //===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides pattern fragments useful for SIMD instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // MMX Pattern Fragments
16 //===----------------------------------------------------------------------===//
18 def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
19 def bc_mmx : PatFrag<(ops node:$in), (x86mmx (bitconvert node:$in))>;
21 //===----------------------------------------------------------------------===//
22 // SSE specific DAG Nodes.
23 //===----------------------------------------------------------------------===//
25 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
26 SDTCisFP<0>, SDTCisInt<2> ]>;
27 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
28 SDTCisFP<1>, SDTCisVT<3, i8>,
31 def X86umin : SDNode<"X86ISD::UMIN", SDTIntBinOp>;
32 def X86umax : SDNode<"X86ISD::UMAX", SDTIntBinOp>;
33 def X86smin : SDNode<"X86ISD::SMIN", SDTIntBinOp>;
34 def X86smax : SDNode<"X86ISD::SMAX", SDTIntBinOp>;
36 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
37 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
39 // Commutative and Associative FMIN and FMAX.
40 def X86fminc : SDNode<"X86ISD::FMINC", SDTFPBinOp,
41 [SDNPCommutative, SDNPAssociative]>;
42 def X86fmaxc : SDNode<"X86ISD::FMAXC", SDTFPBinOp,
43 [SDNPCommutative, SDNPAssociative]>;
45 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
46 [SDNPCommutative, SDNPAssociative]>;
47 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
48 [SDNPCommutative, SDNPAssociative]>;
49 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
50 [SDNPCommutative, SDNPAssociative]>;
51 def X86fandn : SDNode<"X86ISD::FANDN", SDTFPBinOp,
52 [SDNPCommutative, SDNPAssociative]>;
53 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
54 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
55 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
56 def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
57 def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>;
58 def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>;
59 def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>;
60 def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>;
61 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
62 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
63 def X86cmps : SDNode<"X86ISD::FSETCC", SDTX86Cmps>;
64 //def X86cmpsd : SDNode<"X86ISD::FSETCCsd", SDTX86Cmpsd>;
65 def X86pshufb : SDNode<"X86ISD::PSHUFB",
66 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
68 def X86andnp : SDNode<"X86ISD::ANDNP",
69 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
71 def X86psign : SDNode<"X86ISD::PSIGN",
72 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
74 def X86pextrb : SDNode<"X86ISD::PEXTRB",
75 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
76 def X86pextrw : SDNode<"X86ISD::PEXTRW",
77 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
78 def X86pinsrb : SDNode<"X86ISD::PINSRB",
79 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
80 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
81 def X86pinsrw : SDNode<"X86ISD::PINSRW",
82 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
83 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
84 def X86insrtps : SDNode<"X86ISD::INSERTPS",
85 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
86 SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>;
87 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
88 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
90 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
91 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
93 def X86vzext : SDNode<"X86ISD::VZEXT",
94 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
95 SDTCisInt<0>, SDTCisInt<1>,
96 SDTCisOpSmallerThanOp<1, 0>]>>;
98 def X86vsext : SDNode<"X86ISD::VSEXT",
99 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
100 SDTCisInt<0>, SDTCisInt<1>,
101 SDTCisOpSmallerThanOp<1, 0>]>>;
103 def X86vtrunc : SDNode<"X86ISD::VTRUNC",
104 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
105 SDTCisInt<0>, SDTCisInt<1>,
106 SDTCisOpSmallerThanOp<0, 1>]>>;
107 def X86trunc : SDNode<"X86ISD::TRUNC",
108 SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>,
109 SDTCisOpSmallerThanOp<0, 1>]>>;
111 def X86vtruncm : SDNode<"X86ISD::VTRUNCM",
112 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
113 SDTCisInt<0>, SDTCisInt<1>,
114 SDTCisVec<2>, SDTCisInt<2>,
115 SDTCisOpSmallerThanOp<0, 2>]>>;
116 def X86vfpext : SDNode<"X86ISD::VFPEXT",
117 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
118 SDTCisFP<0>, SDTCisFP<1>,
119 SDTCisOpSmallerThanOp<1, 0>]>>;
120 def X86vfpround: SDNode<"X86ISD::VFPROUND",
121 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
122 SDTCisFP<0>, SDTCisFP<1>,
123 SDTCisOpSmallerThanOp<0, 1>]>>;
125 def X86vshldq : SDNode<"X86ISD::VSHLDQ", SDTIntShiftOp>;
126 def X86vshrdq : SDNode<"X86ISD::VSRLDQ", SDTIntShiftOp>;
127 def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP>;
128 def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
129 def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
131 def X86IntCmpMask : SDTypeProfile<1, 2,
132 [SDTCisVec<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>]>;
133 def X86pcmpeqm : SDNode<"X86ISD::PCMPEQM", X86IntCmpMask, [SDNPCommutative]>;
134 def X86pcmpgtm : SDNode<"X86ISD::PCMPGTM", X86IntCmpMask>;
137 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisInt<0>, SDTCisVec<1>,
138 SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
139 def X86CmpMaskCCScalar :
140 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
142 def X86cmpm : SDNode<"X86ISD::CMPM", X86CmpMaskCC>;
143 def X86cmpmu : SDNode<"X86ISD::CMPMU", X86CmpMaskCC>;
144 def X86cmpms : SDNode<"X86ISD::FSETCC", X86CmpMaskCCScalar>;
146 def X86vshl : SDNode<"X86ISD::VSHL",
147 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
149 def X86vsrl : SDNode<"X86ISD::VSRL",
150 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
152 def X86vsra : SDNode<"X86ISD::VSRA",
153 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
156 def X86vshli : SDNode<"X86ISD::VSHLI", SDTIntShiftOp>;
157 def X86vsrli : SDNode<"X86ISD::VSRLI", SDTIntShiftOp>;
158 def X86vsrai : SDNode<"X86ISD::VSRAI", SDTIntShiftOp>;
160 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
162 SDTCisSameAs<2, 1>]>;
163 def X86subus : SDNode<"X86ISD::SUBUS", SDTIntBinOp>;
164 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
165 def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
166 def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>;
167 def X86testm : SDNode<"X86ISD::TESTM", SDTypeProfile<1, 2, [SDTCisVec<0>,
169 SDTCisSameAs<2, 1>]>>;
170 def X86testnm : SDNode<"X86ISD::TESTNM", SDTypeProfile<1, 2, [SDTCisVec<0>,
172 SDTCisSameAs<2, 1>]>>;
173 def X86select : SDNode<"X86ISD::SELECT" , SDTSelect>;
175 def X86pmuludq : SDNode<"X86ISD::PMULUDQ",
176 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
177 SDTCisSameAs<1,2>]>>;
179 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
180 // translated into one of the target nodes below during lowering.
181 // Note: this is a work in progress...
182 def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
183 def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
185 def SDTShuff3Op : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
186 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>;
188 def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
189 SDTCisSameAs<0,1>, SDTCisInt<2>]>;
190 def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
191 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
193 def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
194 def SDTVBroadcastm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>]>;
196 def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
197 SDTCisSameAs<1,2>, SDTCisVT<3, i32>]>;
199 def SDTFma : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
200 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
202 def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>;
204 def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
205 def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
206 def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
208 def X86Shufp : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>;
210 def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
211 def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
212 def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
214 def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>;
215 def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>;
217 def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>;
218 def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>;
219 def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;
221 def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
222 def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
224 def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
225 def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
227 def X86VPermilp : SDNode<"X86ISD::VPERMILP", SDTShuff2OpI>;
228 def X86VPermv : SDNode<"X86ISD::VPERMV", SDTShuff2Op>;
229 def X86VPermi : SDNode<"X86ISD::VPERMI", SDTShuff2OpI>;
230 def X86VPermv3 : SDNode<"X86ISD::VPERMV3", SDTShuff3Op>;
231 def X86VPermiv3 : SDNode<"X86ISD::VPERMIV3", SDTShuff3Op>;
233 def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
235 def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
236 def X86VBroadcastm : SDNode<"X86ISD::VBROADCASTM", SDTVBroadcastm>;
237 def X86Vinsert : SDNode<"X86ISD::VINSERT", SDTypeProfile<1, 3,
238 [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
240 def X86Blendi : SDNode<"X86ISD::BLENDI", SDTBlend>;
241 def X86Fmadd : SDNode<"X86ISD::FMADD", SDTFma>;
242 def X86Fnmadd : SDNode<"X86ISD::FNMADD", SDTFma>;
243 def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFma>;
244 def X86Fnmsub : SDNode<"X86ISD::FNMSUB", SDTFma>;
245 def X86Fmaddsub : SDNode<"X86ISD::FMADDSUB", SDTFma>;
246 def X86Fmsubadd : SDNode<"X86ISD::FMSUBADD", SDTFma>;
248 def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
249 SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>,
251 def SDT_PCMPESTRI : SDTypeProfile<2, 5, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
252 SDTCisVT<2, v16i8>, SDTCisVT<3, i32>,
253 SDTCisVT<4, v16i8>, SDTCisVT<5, i32>,
256 def X86pcmpistri : SDNode<"X86ISD::PCMPISTRI", SDT_PCMPISTRI>;
257 def X86pcmpestri : SDNode<"X86ISD::PCMPESTRI", SDT_PCMPESTRI>;
259 //===----------------------------------------------------------------------===//
260 // SSE Complex Patterns
261 //===----------------------------------------------------------------------===//
263 // These are 'extloads' from a scalar to the low element of a vector, zeroing
264 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
266 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
267 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
269 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
270 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
273 def ssmem : Operand<v4f32> {
274 let PrintMethod = "printf32mem";
275 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
276 let ParserMatchClass = X86Mem32AsmOperand;
277 let OperandType = "OPERAND_MEMORY";
279 def sdmem : Operand<v2f64> {
280 let PrintMethod = "printf64mem";
281 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
282 let ParserMatchClass = X86Mem64AsmOperand;
283 let OperandType = "OPERAND_MEMORY";
286 //===----------------------------------------------------------------------===//
287 // SSE pattern fragments
288 //===----------------------------------------------------------------------===//
290 // 128-bit load pattern fragments
291 // NOTE: all 128-bit integer vector loads are promoted to v2i64
292 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
293 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
294 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
296 // 256-bit load pattern fragments
297 // NOTE: all 256-bit integer vector loads are promoted to v4i64
298 def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
299 def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
300 def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
302 // 512-bit load pattern fragments
303 def loadv16f32 : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>;
304 def loadv8f64 : PatFrag<(ops node:$ptr), (v8f64 (load node:$ptr))>;
305 def loadv16i32 : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>;
306 def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>;
308 // 128-/256-/512-bit extload pattern fragments
309 def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>;
310 def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>;
311 def extloadv8f32 : PatFrag<(ops node:$ptr), (v8f64 (extloadvf32 node:$ptr))>;
313 // Like 'store', but always requires 128-bit vector alignment.
314 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
315 (store node:$val, node:$ptr), [{
316 return cast<StoreSDNode>(N)->getAlignment() >= 16;
319 // Like 'store', but always requires 256-bit vector alignment.
320 def alignedstore256 : PatFrag<(ops node:$val, node:$ptr),
321 (store node:$val, node:$ptr), [{
322 return cast<StoreSDNode>(N)->getAlignment() >= 32;
325 // Like 'store', but always requires 512-bit vector alignment.
326 def alignedstore512 : PatFrag<(ops node:$val, node:$ptr),
327 (store node:$val, node:$ptr), [{
328 return cast<StoreSDNode>(N)->getAlignment() >= 64;
331 // Like 'load', but always requires 128-bit vector alignment.
332 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
333 return cast<LoadSDNode>(N)->getAlignment() >= 16;
336 // Like 'X86vzload', but always requires 128-bit vector alignment.
337 def alignedX86vzload : PatFrag<(ops node:$ptr), (X86vzload node:$ptr), [{
338 return cast<MemSDNode>(N)->getAlignment() >= 16;
341 // Like 'load', but always requires 256-bit vector alignment.
342 def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
343 return cast<LoadSDNode>(N)->getAlignment() >= 32;
346 // Like 'load', but always requires 512-bit vector alignment.
347 def alignedload512 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
348 return cast<LoadSDNode>(N)->getAlignment() >= 64;
351 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
352 (f32 (alignedload node:$ptr))>;
353 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
354 (f64 (alignedload node:$ptr))>;
356 // 128-bit aligned load pattern fragments
357 // NOTE: all 128-bit integer vector loads are promoted to v2i64
358 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
359 (v4f32 (alignedload node:$ptr))>;
360 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
361 (v2f64 (alignedload node:$ptr))>;
362 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
363 (v2i64 (alignedload node:$ptr))>;
365 // 256-bit aligned load pattern fragments
366 // NOTE: all 256-bit integer vector loads are promoted to v4i64
367 def alignedloadv8f32 : PatFrag<(ops node:$ptr),
368 (v8f32 (alignedload256 node:$ptr))>;
369 def alignedloadv4f64 : PatFrag<(ops node:$ptr),
370 (v4f64 (alignedload256 node:$ptr))>;
371 def alignedloadv4i64 : PatFrag<(ops node:$ptr),
372 (v4i64 (alignedload256 node:$ptr))>;
374 // 512-bit aligned load pattern fragments
375 def alignedloadv16f32 : PatFrag<(ops node:$ptr),
376 (v16f32 (alignedload512 node:$ptr))>;
377 def alignedloadv16i32 : PatFrag<(ops node:$ptr),
378 (v16i32 (alignedload512 node:$ptr))>;
379 def alignedloadv8f64 : PatFrag<(ops node:$ptr),
380 (v8f64 (alignedload512 node:$ptr))>;
381 def alignedloadv8i64 : PatFrag<(ops node:$ptr),
382 (v8i64 (alignedload512 node:$ptr))>;
384 // Like 'load', but uses special alignment checks suitable for use in
385 // memory operands in most SSE instructions, which are required to
386 // be naturally aligned on some targets but not on others. If the subtarget
387 // allows unaligned accesses, match any load, though this may require
388 // setting a feature bit in the processor (on startup, for example).
389 // Opteron 10h and later implement such a feature.
390 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
391 return Subtarget->hasVectorUAMem()
392 || cast<LoadSDNode>(N)->getAlignment() >= 16;
395 def memop4 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
396 return Subtarget->hasVectorUAMem()
397 || cast<LoadSDNode>(N)->getAlignment() >= 4;
400 def memop8 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
401 return Subtarget->hasVectorUAMem()
402 || cast<LoadSDNode>(N)->getAlignment() >= 8;
405 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
406 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
408 // 128-bit memop pattern fragments
409 // NOTE: all 128-bit integer vector loads are promoted to v2i64
410 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
411 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
412 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
414 // 256-bit memop pattern fragments
415 // NOTE: all 256-bit integer vector loads are promoted to v4i64
416 def memopv8f32 : PatFrag<(ops node:$ptr), (v8f32 (memop node:$ptr))>;
417 def memopv4f64 : PatFrag<(ops node:$ptr), (v4f64 (memop node:$ptr))>;
418 def memopv4i64 : PatFrag<(ops node:$ptr), (v4i64 (memop node:$ptr))>;
420 // 512-bit memop pattern fragments
421 def memopv16f32 : PatFrag<(ops node:$ptr), (v16f32 (memop4 node:$ptr))>;
422 def memopv8f64 : PatFrag<(ops node:$ptr), (v8f64 (memop8 node:$ptr))>;
423 def memopv16i32 : PatFrag<(ops node:$ptr), (v16i32 (memop4 node:$ptr))>;
424 def memopv8i64 : PatFrag<(ops node:$ptr), (v8i64 (memop8 node:$ptr))>;
426 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
428 // FIXME: 8 byte alignment for mmx reads is not required
429 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
430 return cast<LoadSDNode>(N)->getAlignment() >= 8;
433 def memopmmx : PatFrag<(ops node:$ptr), (x86mmx (memop64 node:$ptr))>;
436 // Like 'store', but requires the non-temporal bit to be set
437 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
438 (st node:$val, node:$ptr), [{
439 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
440 return ST->isNonTemporal();
444 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
445 (st node:$val, node:$ptr), [{
446 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
447 return ST->isNonTemporal() && !ST->isTruncatingStore() &&
448 ST->getAddressingMode() == ISD::UNINDEXED &&
449 ST->getAlignment() >= 16;
453 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
454 (st node:$val, node:$ptr), [{
455 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
456 return ST->isNonTemporal() &&
457 ST->getAlignment() < 16;
461 // 128-bit bitconvert pattern fragments
462 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
463 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
464 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
465 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
466 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
467 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
469 // 256-bit bitconvert pattern fragments
470 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
471 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
472 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
473 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
474 def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>;
476 // 512-bit bitconvert pattern fragments
477 def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
478 def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
479 def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>;
480 def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>;
482 def vzmovl_v2i64 : PatFrag<(ops node:$src),
483 (bitconvert (v2i64 (X86vzmovl
484 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
485 def vzmovl_v4i32 : PatFrag<(ops node:$src),
486 (bitconvert (v4i32 (X86vzmovl
487 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
489 def vzload_v2i64 : PatFrag<(ops node:$src),
490 (bitconvert (v2i64 (X86vzload node:$src)))>;
493 def fp32imm0 : PatLeaf<(f32 fpimm), [{
494 return N->isExactlyValue(+0.0);
497 def I8Imm : SDNodeXForm<imm, [{
498 // Transformation function: get the low 8 bits.
499 return getI8Imm((uint8_t)N->getZExtValue());
502 def FROUND_NO_EXC : ImmLeaf<i32, [{ return Imm == 8; }]>;
503 def FROUND_CURRENT : ImmLeaf<i32, [{ return Imm == 4; }]>;
505 // BYTE_imm - Transform bit immediates into byte immediates.
506 def BYTE_imm : SDNodeXForm<imm, [{
507 // Transformation function: imm >> 3
508 return getI32Imm(N->getZExtValue() >> 3);
511 // EXTRACT_get_vextract128_imm xform function: convert extract_subvector index
512 // to VEXTRACTF128/VEXTRACTI128 imm.
513 def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{
514 return getI8Imm(X86::getExtractVEXTRACT128Immediate(N));
517 // INSERT_get_vinsert128_imm xform function: convert insert_subvector index to
518 // VINSERTF128/VINSERTI128 imm.
519 def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{
520 return getI8Imm(X86::getInsertVINSERT128Immediate(N));
523 // EXTRACT_get_vextract256_imm xform function: convert extract_subvector index
524 // to VEXTRACTF64x4 imm.
525 def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{
526 return getI8Imm(X86::getExtractVEXTRACT256Immediate(N));
529 // INSERT_get_vinsert256_imm xform function: convert insert_subvector index to
531 def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{
532 return getI8Imm(X86::getInsertVINSERT256Immediate(N));
535 def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index),
536 (extract_subvector node:$bigvec,
538 return X86::isVEXTRACT128Index(N);
539 }], EXTRACT_get_vextract128_imm>;
541 def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
543 (insert_subvector node:$bigvec, node:$smallvec,
545 return X86::isVINSERT128Index(N);
546 }], INSERT_get_vinsert128_imm>;
549 def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index),
550 (extract_subvector node:$bigvec,
552 return X86::isVEXTRACT256Index(N);
553 }], EXTRACT_get_vextract256_imm>;
555 def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
557 (insert_subvector node:$bigvec, node:$smallvec,
559 return X86::isVINSERT256Index(N);
560 }], INSERT_get_vinsert256_imm>;