1 //======- X86InstrFragmentsSIMD.td - x86 ISA -------------*- tablegen -*-=====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides pattern fragments useful for SIMD instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // MMX Pattern Fragments
16 //===----------------------------------------------------------------------===//
18 def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
19 def bc_mmx : PatFrag<(ops node:$in), (x86mmx (bitconvert node:$in))>;
21 //===----------------------------------------------------------------------===//
22 // SSE specific DAG Nodes.
23 //===----------------------------------------------------------------------===//
25 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
26 SDTCisFP<0>, SDTCisInt<2> ]>;
27 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
28 SDTCisFP<1>, SDTCisVT<3, i8>]>;
30 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
31 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
32 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
33 [SDNPCommutative, SDNPAssociative]>;
34 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
35 [SDNPCommutative, SDNPAssociative]>;
36 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
37 [SDNPCommutative, SDNPAssociative]>;
38 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
39 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
40 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
41 def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
42 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
43 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
44 def X86cmpss : SDNode<"X86ISD::FSETCCss", SDTX86Cmpss>;
45 def X86cmpsd : SDNode<"X86ISD::FSETCCsd", SDTX86Cmpsd>;
46 def X86pshufb : SDNode<"X86ISD::PSHUFB",
47 SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
49 def X86andnp : SDNode<"X86ISD::ANDNP",
50 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
52 def X86psignb : SDNode<"X86ISD::PSIGNB",
53 SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
55 def X86psignw : SDNode<"X86ISD::PSIGNW",
56 SDTypeProfile<1, 2, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
58 def X86psignd : SDNode<"X86ISD::PSIGND",
59 SDTypeProfile<1, 2, [SDTCisVT<0, v4i32>, SDTCisSameAs<0,1>,
61 def X86pblendv : SDNode<"X86ISD::PBLENDVB",
62 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
63 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>>;
64 def X86pextrb : SDNode<"X86ISD::PEXTRB",
65 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
66 def X86pextrw : SDNode<"X86ISD::PEXTRW",
67 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
68 def X86pinsrb : SDNode<"X86ISD::PINSRB",
69 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
70 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
71 def X86pinsrw : SDNode<"X86ISD::PINSRW",
72 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
73 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
74 def X86insrtps : SDNode<"X86ISD::INSERTPS",
75 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
76 SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>;
77 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
78 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
79 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
80 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
81 def X86vshl : SDNode<"X86ISD::VSHL", SDTIntShiftOp>;
82 def X86vshr : SDNode<"X86ISD::VSRL", SDTIntShiftOp>;
83 def X86cmpps : SDNode<"X86ISD::CMPPS", SDTX86VFCMP>;
84 def X86cmppd : SDNode<"X86ISD::CMPPD", SDTX86VFCMP>;
85 def X86pcmpeqb : SDNode<"X86ISD::PCMPEQB", SDTIntBinOp, [SDNPCommutative]>;
86 def X86pcmpeqw : SDNode<"X86ISD::PCMPEQW", SDTIntBinOp, [SDNPCommutative]>;
87 def X86pcmpeqd : SDNode<"X86ISD::PCMPEQD", SDTIntBinOp, [SDNPCommutative]>;
88 def X86pcmpeqq : SDNode<"X86ISD::PCMPEQQ", SDTIntBinOp, [SDNPCommutative]>;
89 def X86pcmpgtb : SDNode<"X86ISD::PCMPGTB", SDTIntBinOp>;
90 def X86pcmpgtw : SDNode<"X86ISD::PCMPGTW", SDTIntBinOp>;
91 def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>;
92 def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>;
94 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
97 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
98 def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
100 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
101 // translated into one of the target nodes below during lowering.
102 // Note: this is a work in progress...
103 def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
104 def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
107 def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
108 SDTCisSameAs<0,1>, SDTCisInt<2>]>;
109 def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
110 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
112 def X86PAlign : SDNode<"X86ISD::PALIGN", SDTShuff3OpI>;
114 def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
115 def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
116 def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
118 def X86Shufpd : SDNode<"X86ISD::SHUFPD", SDTShuff3OpI>;
119 def X86Shufps : SDNode<"X86ISD::SHUFPS", SDTShuff3OpI>;
121 def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
122 def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
123 def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
125 def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>;
126 def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>;
128 def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>;
129 def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>;
130 def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;
131 def X86Movhlpd : SDNode<"X86ISD::MOVHLPD", SDTShuff2Op>;
133 def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
134 def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
136 def X86Unpcklps : SDNode<"X86ISD::UNPCKLPS", SDTShuff2Op>;
137 def X86Unpcklpd : SDNode<"X86ISD::UNPCKLPD", SDTShuff2Op>;
138 def X86Unpcklpsy : SDNode<"X86ISD::VUNPCKLPSY", SDTShuff2Op>;
139 def X86Unpcklpdy : SDNode<"X86ISD::VUNPCKLPDY", SDTShuff2Op>;
140 def X86Unpckhps : SDNode<"X86ISD::UNPCKHPS", SDTShuff2Op>;
141 def X86Unpckhpd : SDNode<"X86ISD::UNPCKHPD", SDTShuff2Op>;
143 def X86Punpcklbw : SDNode<"X86ISD::PUNPCKLBW", SDTShuff2Op>;
144 def X86Punpcklwd : SDNode<"X86ISD::PUNPCKLWD", SDTShuff2Op>;
145 def X86Punpckldq : SDNode<"X86ISD::PUNPCKLDQ", SDTShuff2Op>;
146 def X86Punpcklqdq : SDNode<"X86ISD::PUNPCKLQDQ", SDTShuff2Op>;
148 def X86Punpckhbw : SDNode<"X86ISD::PUNPCKHBW", SDTShuff2Op>;
149 def X86Punpckhwd : SDNode<"X86ISD::PUNPCKHWD", SDTShuff2Op>;
150 def X86Punpckhdq : SDNode<"X86ISD::PUNPCKHDQ", SDTShuff2Op>;
151 def X86Punpckhqdq : SDNode<"X86ISD::PUNPCKHQDQ", SDTShuff2Op>;
153 def X86VPermil : SDNode<"X86ISD::VPERMIL", SDTShuff2OpI>;
155 //===----------------------------------------------------------------------===//
156 // SSE Complex Patterns
157 //===----------------------------------------------------------------------===//
159 // These are 'extloads' from a scalar to the low element of a vector, zeroing
160 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
162 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
163 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
165 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
166 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
169 def ssmem : Operand<v4f32> {
170 let PrintMethod = "printf32mem";
171 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
172 let ParserMatchClass = X86MemAsmOperand;
173 let OperandType = "OPERAND_MEMORY";
175 def sdmem : Operand<v2f64> {
176 let PrintMethod = "printf64mem";
177 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
178 let ParserMatchClass = X86MemAsmOperand;
179 let OperandType = "OPERAND_MEMORY";
182 //===----------------------------------------------------------------------===//
183 // SSE pattern fragments
184 //===----------------------------------------------------------------------===//
186 // 128-bit load pattern fragments
187 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
188 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
189 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
190 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
192 // 256-bit load pattern fragments
193 def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
194 def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
195 def loadv8i32 : PatFrag<(ops node:$ptr), (v8i32 (load node:$ptr))>;
196 def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
198 // Like 'store', but always requires vector alignment.
199 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
200 (store node:$val, node:$ptr), [{
201 return cast<StoreSDNode>(N)->getAlignment() >= 16;
204 // Like 'load', but always requires vector alignment.
205 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
206 return cast<LoadSDNode>(N)->getAlignment() >= 16;
209 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
210 (f32 (alignedload node:$ptr))>;
211 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
212 (f64 (alignedload node:$ptr))>;
214 // 128-bit aligned load pattern fragments
215 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
216 (v4f32 (alignedload node:$ptr))>;
217 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
218 (v2f64 (alignedload node:$ptr))>;
219 def alignedloadv4i32 : PatFrag<(ops node:$ptr),
220 (v4i32 (alignedload node:$ptr))>;
221 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
222 (v2i64 (alignedload node:$ptr))>;
224 // 256-bit aligned load pattern fragments
225 def alignedloadv8f32 : PatFrag<(ops node:$ptr),
226 (v8f32 (alignedload node:$ptr))>;
227 def alignedloadv4f64 : PatFrag<(ops node:$ptr),
228 (v4f64 (alignedload node:$ptr))>;
229 def alignedloadv8i32 : PatFrag<(ops node:$ptr),
230 (v8i32 (alignedload node:$ptr))>;
231 def alignedloadv4i64 : PatFrag<(ops node:$ptr),
232 (v4i64 (alignedload node:$ptr))>;
234 // Like 'load', but uses special alignment checks suitable for use in
235 // memory operands in most SSE instructions, which are required to
236 // be naturally aligned on some targets but not on others. If the subtarget
237 // allows unaligned accesses, match any load, though this may require
238 // setting a feature bit in the processor (on startup, for example).
239 // Opteron 10h and later implement such a feature.
240 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
241 return Subtarget->hasVectorUAMem()
242 || cast<LoadSDNode>(N)->getAlignment() >= 16;
245 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
246 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
248 // 128-bit memop pattern fragments
249 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
250 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
251 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
252 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
253 def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop node:$ptr))>;
254 def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
256 // 256-bit memop pattern fragments
257 def memopv32i8 : PatFrag<(ops node:$ptr), (v32i8 (memop node:$ptr))>;
258 def memopv8f32 : PatFrag<(ops node:$ptr), (v8f32 (memop node:$ptr))>;
259 def memopv4f64 : PatFrag<(ops node:$ptr), (v4f64 (memop node:$ptr))>;
260 def memopv4i64 : PatFrag<(ops node:$ptr), (v4i64 (memop node:$ptr))>;
261 def memopv8i32 : PatFrag<(ops node:$ptr), (v8i32 (memop node:$ptr))>;
263 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
265 // FIXME: 8 byte alignment for mmx reads is not required
266 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
267 return cast<LoadSDNode>(N)->getAlignment() >= 8;
270 def memopmmx : PatFrag<(ops node:$ptr), (x86mmx (memop64 node:$ptr))>;
273 // Like 'store', but requires the non-temporal bit to be set
274 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
275 (st node:$val, node:$ptr), [{
276 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
277 return ST->isNonTemporal();
281 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
282 (st node:$val, node:$ptr), [{
283 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
284 return ST->isNonTemporal() && !ST->isTruncatingStore() &&
285 ST->getAddressingMode() == ISD::UNINDEXED &&
286 ST->getAlignment() >= 16;
290 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
291 (st node:$val, node:$ptr), [{
292 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
293 return ST->isNonTemporal() &&
294 ST->getAlignment() < 16;
298 // 128-bit bitconvert pattern fragments
299 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
300 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
301 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
302 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
303 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
304 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
306 // 256-bit bitconvert pattern fragments
307 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
308 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
310 def vzmovl_v2i64 : PatFrag<(ops node:$src),
311 (bitconvert (v2i64 (X86vzmovl
312 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
313 def vzmovl_v4i32 : PatFrag<(ops node:$src),
314 (bitconvert (v4i32 (X86vzmovl
315 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
317 def vzload_v2i64 : PatFrag<(ops node:$src),
318 (bitconvert (v2i64 (X86vzload node:$src)))>;
321 def fp32imm0 : PatLeaf<(f32 fpimm), [{
322 return N->isExactlyValue(+0.0);
325 // BYTE_imm - Transform bit immediates into byte immediates.
326 def BYTE_imm : SDNodeXForm<imm, [{
327 // Transformation function: imm >> 3
328 return getI32Imm(N->getZExtValue() >> 3);
331 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
333 def SHUFFLE_get_shuf_imm : SDNodeXForm<vector_shuffle, [{
334 return getI8Imm(X86::getShuffleSHUFImmediate(N));
337 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
339 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<vector_shuffle, [{
340 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
343 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
345 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<vector_shuffle, [{
346 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
349 // SHUFFLE_get_palign_imm xform function: convert vector_shuffle mask to
351 def SHUFFLE_get_palign_imm : SDNodeXForm<vector_shuffle, [{
352 return getI8Imm(X86::getShufflePALIGNRImmediate(N));
355 // EXTRACT_get_vextractf128_imm xform function: convert extract_subvector index
356 // to VEXTRACTF128 imm.
357 def EXTRACT_get_vextractf128_imm : SDNodeXForm<extract_subvector, [{
358 return getI8Imm(X86::getExtractVEXTRACTF128Immediate(N));
361 // INSERT_get_vinsertf128_imm xform function: convert insert_subvector index to
363 def INSERT_get_vinsertf128_imm : SDNodeXForm<insert_subvector, [{
364 return getI8Imm(X86::getInsertVINSERTF128Immediate(N));
367 def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
368 (vector_shuffle node:$lhs, node:$rhs), [{
369 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
370 return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
373 def movddup : PatFrag<(ops node:$lhs, node:$rhs),
374 (vector_shuffle node:$lhs, node:$rhs), [{
375 return X86::isMOVDDUPMask(cast<ShuffleVectorSDNode>(N));
378 def movhlps : PatFrag<(ops node:$lhs, node:$rhs),
379 (vector_shuffle node:$lhs, node:$rhs), [{
380 return X86::isMOVHLPSMask(cast<ShuffleVectorSDNode>(N));
383 def movhlps_undef : PatFrag<(ops node:$lhs, node:$rhs),
384 (vector_shuffle node:$lhs, node:$rhs), [{
385 return X86::isMOVHLPS_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
388 def movlhps : PatFrag<(ops node:$lhs, node:$rhs),
389 (vector_shuffle node:$lhs, node:$rhs), [{
390 return X86::isMOVLHPSMask(cast<ShuffleVectorSDNode>(N));
393 def movlp : PatFrag<(ops node:$lhs, node:$rhs),
394 (vector_shuffle node:$lhs, node:$rhs), [{
395 return X86::isMOVLPMask(cast<ShuffleVectorSDNode>(N));
398 def movl : PatFrag<(ops node:$lhs, node:$rhs),
399 (vector_shuffle node:$lhs, node:$rhs), [{
400 return X86::isMOVLMask(cast<ShuffleVectorSDNode>(N));
403 def unpckl : PatFrag<(ops node:$lhs, node:$rhs),
404 (vector_shuffle node:$lhs, node:$rhs), [{
405 return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N));
408 def unpckh : PatFrag<(ops node:$lhs, node:$rhs),
409 (vector_shuffle node:$lhs, node:$rhs), [{
410 return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N));
413 def unpckl_undef : PatFrag<(ops node:$lhs, node:$rhs),
414 (vector_shuffle node:$lhs, node:$rhs), [{
415 return X86::isUNPCKL_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
418 def unpckh_undef : PatFrag<(ops node:$lhs, node:$rhs),
419 (vector_shuffle node:$lhs, node:$rhs), [{
420 return X86::isUNPCKH_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
423 def pshufd : PatFrag<(ops node:$lhs, node:$rhs),
424 (vector_shuffle node:$lhs, node:$rhs), [{
425 return X86::isPSHUFDMask(cast<ShuffleVectorSDNode>(N));
426 }], SHUFFLE_get_shuf_imm>;
428 def shufp : PatFrag<(ops node:$lhs, node:$rhs),
429 (vector_shuffle node:$lhs, node:$rhs), [{
430 return X86::isSHUFPMask(cast<ShuffleVectorSDNode>(N));
431 }], SHUFFLE_get_shuf_imm>;
433 def pshufhw : PatFrag<(ops node:$lhs, node:$rhs),
434 (vector_shuffle node:$lhs, node:$rhs), [{
435 return X86::isPSHUFHWMask(cast<ShuffleVectorSDNode>(N));
436 }], SHUFFLE_get_pshufhw_imm>;
438 def pshuflw : PatFrag<(ops node:$lhs, node:$rhs),
439 (vector_shuffle node:$lhs, node:$rhs), [{
440 return X86::isPSHUFLWMask(cast<ShuffleVectorSDNode>(N));
441 }], SHUFFLE_get_pshuflw_imm>;
443 def palign : PatFrag<(ops node:$lhs, node:$rhs),
444 (vector_shuffle node:$lhs, node:$rhs), [{
445 return X86::isPALIGNRMask(cast<ShuffleVectorSDNode>(N));
446 }], SHUFFLE_get_palign_imm>;
448 def vextractf128_extract : PatFrag<(ops node:$bigvec, node:$index),
449 (extract_subvector node:$bigvec,
451 return X86::isVEXTRACTF128Index(N);
452 }], EXTRACT_get_vextractf128_imm>;
454 def vinsertf128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
456 (insert_subvector node:$bigvec, node:$smallvec,
458 return X86::isVINSERTF128Index(N);
459 }], INSERT_get_vinsertf128_imm>;