lib/Target/X86/X86InstrFragmentsSIMD.td

   1 //===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file provides pattern fragments useful for SIMD instructions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 // MMX specific DAG Nodes.
  16 //===----------------------------------------------------------------------===//
  17
  18 // Low word of MMX to GPR.
  19 def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1,
  20                             [SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>;
  21 // GPR to low word of MMX.
  22 def MMX_X86movw2d : SDNode<"X86ISD::MMX_MOVW2D", SDTypeProfile<1, 1,
  23                             [SDTCisVT<0, x86mmx>, SDTCisVT<1, i32>]>>;
  24
  25 //===----------------------------------------------------------------------===//
  26 // MMX Pattern Fragments
  27 //===----------------------------------------------------------------------===//
  28
  29 def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
  30 def load_mvmmx : PatFrag<(ops node:$ptr),
  31                          (x86mmx (MMX_X86movw2d (load node:$ptr)))>;
  32 def bc_mmx  : PatFrag<(ops node:$in), (x86mmx  (bitconvert node:$in))>;
  33
  34 //===----------------------------------------------------------------------===//
  35 // SSE specific DAG Nodes.
  36 //===----------------------------------------------------------------------===//
  37
  38 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
  39                                        SDTCisFP<1>, SDTCisVT<3, i8>,
  40                                        SDTCisVec<1>]>;
  41
  42 def X86fmin    : SDNode<"X86ISD::FMIN",      SDTFPBinOp>;
  43 def X86fmax    : SDNode<"X86ISD::FMAX",      SDTFPBinOp>;
  44
  45 // Commutative and Associative FMIN and FMAX.
  46 def X86fminc    : SDNode<"X86ISD::FMINC", SDTFPBinOp,
  47     [SDNPCommutative, SDNPAssociative]>;
  48 def X86fmaxc    : SDNode<"X86ISD::FMAXC", SDTFPBinOp,
  49     [SDNPCommutative, SDNPAssociative]>;
  50
  51 def X86fand    : SDNode<"X86ISD::FAND",      SDTFPBinOp,
  52                         [SDNPCommutative, SDNPAssociative]>;
  53 def X86for     : SDNode<"X86ISD::FOR",       SDTFPBinOp,
  54                         [SDNPCommutative, SDNPAssociative]>;
  55 def X86fxor    : SDNode<"X86ISD::FXOR",      SDTFPBinOp,
  56                         [SDNPCommutative, SDNPAssociative]>;
  57 def X86fandn   : SDNode<"X86ISD::FANDN",     SDTFPBinOp,
  58                         [SDNPCommutative, SDNPAssociative]>;
  59 def X86frsqrt  : SDNode<"X86ISD::FRSQRT",    SDTFPUnaryOp>;
  60 def X86frcp    : SDNode<"X86ISD::FRCP",      SDTFPUnaryOp>;
  61 def X86frsqrt14s: SDNode<"X86ISD::FRSQRT",  SDTFPBinOp>;
  62 def X86frcp14s : SDNode<"X86ISD::FRCP",    SDTFPBinOp>;
  63 def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
  64 def X86fhadd   : SDNode<"X86ISD::FHADD",     SDTFPBinOp>;
  65 def X86fhsub   : SDNode<"X86ISD::FHSUB",     SDTFPBinOp>;
  66 def X86hadd    : SDNode<"X86ISD::HADD",      SDTIntBinOp>;
  67 def X86hsub    : SDNode<"X86ISD::HSUB",      SDTIntBinOp>;
  68 def X86comi    : SDNode<"X86ISD::COMI",      SDTX86CmpTest>;
  69 def X86ucomi   : SDNode<"X86ISD::UCOMI",     SDTX86CmpTest>;
  70 def X86cmps    : SDNode<"X86ISD::FSETCC",     SDTX86Cmps>;
  71 //def X86cmpsd   : SDNode<"X86ISD::FSETCCsd",    SDTX86Cmpsd>;
  72 def X86cvtdq2pd: SDNode<"X86ISD::CVTDQ2PD",
  73                  SDTypeProfile<1, 1, [SDTCisVT<0, v2f64>,
  74                                       SDTCisVT<1, v4i32>]>>;
  75 def X86cvtudq2pd: SDNode<"X86ISD::CVTUDQ2PD",
  76                  SDTypeProfile<1, 1, [SDTCisVT<0, v2f64>,
  77                                       SDTCisVT<1, v4i32>]>>;
  78 def X86pshufb  : SDNode<"X86ISD::PSHUFB",
  79                  SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i8>, SDTCisSameAs<0,1>,
  80                                       SDTCisSameAs<0,2>]>>;
  81 def X86psadbw  : SDNode<"X86ISD::PSADBW",
  82                  SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>,
  83                                       SDTCVecEltisVT<1, i8>,
  84                                       SDTCisSameSizeAs<0,1>,
  85                                       SDTCisSameAs<1,2>]>>;
  86 def X86dbpsadbw : SDNode<"X86ISD::DBPSADBW",
  87                   SDTypeProfile<1, 3, [SDTCVecEltisVT<0, i16>,
  88                                        SDTCVecEltisVT<1, i8>,
  89                                        SDTCisSameSizeAs<0,1>,
  90                                        SDTCisSameAs<1,2>, SDTCisInt<3>]>>;
  91 def X86andnp   : SDNode<"X86ISD::ANDNP",
  92                  SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
  93                                       SDTCisSameAs<0,2>]>>;
  94 def X86psign   : SDNode<"X86ISD::PSIGN",
  95                  SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
  96                                       SDTCisSameAs<0,2>]>>;
  97 def X86pextrb  : SDNode<"X86ISD::PEXTRB",
  98                  SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, v16i8>,
  99                                       SDTCisPtrTy<2>]>>;
 100 def X86pextrw  : SDNode<"X86ISD::PEXTRW",
 101                  SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, v8i16>,
 102                                       SDTCisPtrTy<2>]>>;
 103 def X86pinsrb  : SDNode<"X86ISD::PINSRB",
 104                  SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
 105                                       SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
 106 def X86pinsrw  : SDNode<"X86ISD::PINSRW",
 107                  SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
 108                                       SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
 109 def X86insertps : SDNode<"X86ISD::INSERTPS",
 110                  SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
 111                                       SDTCisVT<2, v4f32>, SDTCisVT<3, i8>]>>;
 112 def X86vzmovl  : SDNode<"X86ISD::VZEXT_MOVL",
 113                  SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
 114
 115 def X86vzload  : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
 116                         [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 117
 118 def X86vzext   : SDNode<"X86ISD::VZEXT",
 119                          SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 120                                               SDTCisInt<0>, SDTCisInt<1>,
 121                                               SDTCisOpSmallerThanOp<1, 0>]>>;
 122
 123 def X86vsext   : SDNode<"X86ISD::VSEXT",
 124                          SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 125                                               SDTCisInt<0>, SDTCisInt<1>,
 126                                               SDTCisOpSmallerThanOp<1, 0>]>>;
 127
 128 def SDTVtrunc    : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 129                                        SDTCisInt<0>, SDTCisInt<1>,
 130                                        SDTCisOpSmallerThanOp<0, 1>]>;
 131
 132 def X86vtrunc    : SDNode<"X86ISD::VTRUNC",   SDTVtrunc>;
 133 def X86vtruncs   : SDNode<"X86ISD::VTRUNCS",  SDTVtrunc>;
 134 def X86vtruncus  : SDNode<"X86ISD::VTRUNCUS", SDTVtrunc>;
 135
 136 def X86trunc    : SDNode<"X86ISD::TRUNC",
 137                          SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>,
 138                                               SDTCisOpSmallerThanOp<0, 1>]>>;
 139 def X86vfpext  : SDNode<"X86ISD::VFPEXT",
 140                         SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 141                                              SDTCisFP<0>, SDTCisFP<1>,
 142                                              SDTCisOpSmallerThanOp<1, 0>]>>;
 143 def X86vfpround: SDNode<"X86ISD::VFPROUND",
 144                         SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 145                                              SDTCisFP<0>, SDTCisFP<1>,
 146                                              SDTCisOpSmallerThanOp<0, 1>]>>;
 147
 148 def X86fround: SDNode<"X86ISD::VFPROUND",
 149                         SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
 150                                              SDTCVecEltisVT<0, f32>,
 151                                              SDTCVecEltisVT<1, f64>,
 152                                              SDTCVecEltisVT<2, f64>,
 153                                              SDTCisOpSmallerThanOp<0, 1>]>>;
 154 def X86froundRnd: SDNode<"X86ISD::VFPROUND",
 155                         SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
 156                                              SDTCVecEltisVT<0, f32>,
 157                                              SDTCVecEltisVT<1, f64>,
 158                                              SDTCVecEltisVT<2, f64>,
 159                                              SDTCisOpSmallerThanOp<0, 1>,
 160                                              SDTCisInt<3>]>>;
 161
 162 def X86fpext  : SDNode<"X86ISD::VFPEXT",
 163                         SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
 164                                              SDTCVecEltisVT<0, f64>,
 165                                              SDTCVecEltisVT<1, f32>,
 166                                              SDTCVecEltisVT<2, f32>,
 167                                              SDTCisOpSmallerThanOp<1, 0>]>>;
 168
 169 def X86fpextRnd  : SDNode<"X86ISD::VFPEXT",
 170                         SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
 171                                              SDTCVecEltisVT<0, f64>,
 172                                              SDTCVecEltisVT<1, f32>,
 173                                              SDTCVecEltisVT<2, f32>,
 174                                              SDTCisOpSmallerThanOp<1, 0>,
 175                                              SDTCisInt<3>]>>;
 176
 177 def X86vshldq  : SDNode<"X86ISD::VSHLDQ",    SDTIntShiftOp>;
 178 def X86vshrdq  : SDNode<"X86ISD::VSRLDQ",    SDTIntShiftOp>;
 179 def X86cmpp    : SDNode<"X86ISD::CMPP",      SDTX86VFCMP>;
 180 def X86pcmpeq  : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
 181 def X86pcmpgt  : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
 182
 183 def X86IntCmpMask : SDTypeProfile<1, 2,
 184     [SDTCisVec<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>]>;
 185 def X86pcmpeqm  : SDNode<"X86ISD::PCMPEQM", X86IntCmpMask, [SDNPCommutative]>;
 186 def X86pcmpgtm  : SDNode<"X86ISD::PCMPGTM", X86IntCmpMask>;
 187
 188 def X86CmpMaskCC :
 189       SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
 190                        SDTCisVec<1>, SDTCisSameAs<2, 1>,
 191                        SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>]>;
 192 def X86CmpMaskCCRound :
 193       SDTypeProfile<1, 4, [SDTCisVec<0>,SDTCVecEltisVT<0, i1>,
 194                        SDTCisVec<1>, SDTCisSameAs<2, 1>,
 195                        SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>,
 196                        SDTCisInt<4>]>;
 197 def X86CmpMaskCCScalar :
 198       SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
 199
 200 def X86CmpMaskCCScalarRound :
 201       SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>,
 202                            SDTCisInt<4>]>;
 203
 204 def X86cmpm     : SDNode<"X86ISD::CMPM",     X86CmpMaskCC>;
 205 def X86cmpmRnd  : SDNode<"X86ISD::CMPM_RND", X86CmpMaskCCRound>;
 206 def X86cmpmu    : SDNode<"X86ISD::CMPMU",    X86CmpMaskCC>;
 207 def X86cmpms    : SDNode<"X86ISD::FSETCC",   X86CmpMaskCCScalar>;
 208 def X86cmpmsRnd : SDNode<"X86ISD::FSETCC",   X86CmpMaskCCScalarRound>;
 209
 210 def X86vshl    : SDNode<"X86ISD::VSHL",
 211                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 212                                       SDTCisVec<2>]>>;
 213 def X86vsrl    : SDNode<"X86ISD::VSRL",
 214                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 215                                       SDTCisVec<2>]>>;
 216 def X86vsra    : SDNode<"X86ISD::VSRA",
 217                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 218                                       SDTCisVec<2>]>>;
 219
 220 def X86vshli   : SDNode<"X86ISD::VSHLI", SDTIntShiftOp>;
 221 def X86vsrli   : SDNode<"X86ISD::VSRLI", SDTIntShiftOp>;
 222 def X86vsrai   : SDNode<"X86ISD::VSRAI", SDTIntShiftOp>;
 223
 224 def X86vprot   : SDNode<"X86ISD::VPROT",
 225                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 226                                              SDTCisSameAs<0,2>]>>;
 227 def X86vproti  : SDNode<"X86ISD::VPROTI",
 228                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 229                                              SDTCisVT<2, i8>]>>;
 230
 231 def X86vpshl   : SDNode<"X86ISD::VPSHL",
 232                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 233                                              SDTCisSameAs<0,2>]>>;
 234 def X86vpsha   : SDNode<"X86ISD::VPSHA",
 235                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 236                                              SDTCisSameAs<0,2>]>>;
 237
 238 def X86vpcom   : SDNode<"X86ISD::VPCOM",
 239                         SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 240                                              SDTCisSameAs<0,2>,
 241                                              SDTCisVT<3, i8>]>>;
 242 def X86vpcomu  : SDNode<"X86ISD::VPCOMU",
 243                         SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 244                                              SDTCisSameAs<0,2>,
 245                                              SDTCisVT<3, i8>]>>;
 246
 247 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
 248                                           SDTCisVec<1>,
 249                                           SDTCisSameAs<2, 1>]>;
 250 def X86addus   : SDNode<"X86ISD::ADDUS", SDTIntBinOp>;
 251 def X86subus   : SDNode<"X86ISD::SUBUS", SDTIntBinOp>;
 252 def X86adds    : SDNode<"X86ISD::ADDS", SDTIntBinOp>;
 253 def X86subs    : SDNode<"X86ISD::SUBS", SDTIntBinOp>;
 254 def X86mulhrs  : SDNode<"X86ISD::MULHRS" , SDTIntBinOp>;
 255 def X86avg     : SDNode<"X86ISD::AVG" , SDTIntBinOp>;
 256 def X86ptest   : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
 257 def X86testp   : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
 258 def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>;
 259 def X86ktest   : SDNode<"X86ISD::KTEST", SDTX86CmpPTest>;
 260 def X86testm   : SDNode<"X86ISD::TESTM", SDTypeProfile<1, 2, [SDTCisVec<0>,
 261                                           SDTCisVec<1>, SDTCisSameAs<2, 1>,
 262                                           SDTCVecEltisVT<0, i1>,
 263                                           SDTCisSameNumEltsAs<0, 1>]>>;
 264 def X86testnm  : SDNode<"X86ISD::TESTNM", SDTypeProfile<1, 2, [SDTCisVec<0>,
 265                                           SDTCisVec<1>, SDTCisSameAs<2, 1>,
 266                                           SDTCVecEltisVT<0, i1>,
 267                                           SDTCisSameNumEltsAs<0, 1>]>>;
 268 def X86select  : SDNode<"X86ISD::SELECT"     , SDTSelect>;
 269
 270 def X86pmuludq : SDNode<"X86ISD::PMULUDQ",
 271                         SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>,
 272                                              SDTCVecEltisVT<1, i32>,
 273                                              SDTCisSameSizeAs<0,1>,
 274                                              SDTCisSameAs<1,2>]>>;
 275 def X86pmuldq  : SDNode<"X86ISD::PMULDQ",
 276                         SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>,
 277                                              SDTCVecEltisVT<1, i32>,
 278                                              SDTCisSameSizeAs<0,1>,
 279                                              SDTCisSameAs<1,2>]>>;
 280
 281 def X86extrqi : SDNode<"X86ISD::EXTRQI",
 282                   SDTypeProfile<1, 3, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
 283                                        SDTCisVT<2, i8>, SDTCisVT<3, i8>]>>;
 284 def X86insertqi : SDNode<"X86ISD::INSERTQI",
 285                     SDTypeProfile<1, 4, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
 286                                          SDTCisSameAs<1,2>, SDTCisVT<3, i8>,
 287                                          SDTCisVT<4, i8>]>>;
 288
 289 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
 290 // translated into one of the target nodes below during lowering.
 291 // Note: this is a work in progress...
 292 def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
 293 def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 294                                 SDTCisSameAs<0,2>]>;
 295 def SDTShuff3Op : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 296                                 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>;
 297
 298 def SDTShuff2OpM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 299                                         SDTCisSameSizeAs<0,2>,
 300                                         SDTCisSameNumEltsAs<0,2>]>;
 301 def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
 302                                  SDTCisSameAs<0,1>, SDTCisVT<2, i8>]>;
 303 def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 304                                  SDTCisSameAs<0,2>, SDTCisVT<3, i8>]>;
 305 def SDTFPBinOpImmRound: SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 306                              SDTCisSameAs<0,2>, SDTCisInt<3>, SDTCisInt<4>]>;
 307 def SDTFPUnaryOpImmRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 308                               SDTCisInt<2>, SDTCisInt<3>]>;
 309
 310 def SDTVBroadcast  : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
 311 def SDTVBroadcastm : SDTypeProfile<1, 1, [SDTCisVec<0>,
 312                                           SDTCisInt<0>, SDTCisInt<1>]>;
 313
 314 def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 315                              SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>;
 316
 317 def SDTTernlog  : SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 318                                 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>,
 319                                 SDTCisVT<4, i8>]>;
 320
 321 def SDTFPBinOpRound : SDTypeProfile<1, 3, [      // fadd_round, fmul_round, etc.
 322   SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>, SDTCisInt<3>]>;
 323
 324 def SDTFPUnaryOpRound : SDTypeProfile<1, 2, [      // fsqrt_round, fgetexp_round, etc.
 325   SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]>;
 326
 327 def SDTFma : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
 328                            SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
 329 def SDTFmaRound : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
 330                            SDTCisSameAs<1,2>, SDTCisSameAs<1,3>, SDTCisInt<4>]>;
 331 def STDFp1SrcRm : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>,
 332                            SDTCisVec<0>, SDTCisVT<2, i32>]>;
 333 def STDFp2SrcRm : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
 334                            SDTCisVec<0>, SDTCisVT<3, i32>]>;
 335 def STDFp3SrcRm : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
 336                            SDTCisVec<0>, SDTCisVT<3, i32>, SDTCisVT<4, i32>]>;
 337
 338 def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>;
 339 def X86VAlign  : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>;
 340
 341 def X86Abs      : SDNode<"X86ISD::ABS", SDTIntUnaryOp>;
 342 def X86Conflict : SDNode<"X86ISD::CONFLICT", SDTIntUnaryOp>;
 343
 344 def X86PShufd  : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
 345 def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
 346 def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
 347
 348 def X86Shufp   : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>;
 349 def X86Shuf128 : SDNode<"X86ISD::SHUF128", SDTShuff3OpI>;
 350
 351 def X86Movddup  : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
 352 def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
 353 def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
 354
 355 def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>;
 356 def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>;
 357
 358 def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>;
 359 def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>;
 360 def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;
 361
 362 def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
 363 def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
 364
 365 def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 366                                    SDTCisSameSizeAs<0,1>,
 367                                    SDTCisSameAs<1,2>]>;
 368 def X86Packss : SDNode<"X86ISD::PACKSS", SDTPack>;
 369 def X86Packus : SDNode<"X86ISD::PACKUS", SDTPack>;
 370
 371 def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
 372 def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
 373
 374 def X86vpmaddubsw  : SDNode<"X86ISD::VPMADDUBSW" , SDTPack>;
 375 def X86vpmaddwd    : SDNode<"X86ISD::VPMADDWD"   , SDTPack>;
 376
 377 def X86VPermilpv  : SDNode<"X86ISD::VPERMILPV", SDTShuff2OpM>;
 378 def X86VPermilpi  : SDNode<"X86ISD::VPERMILPI", SDTShuff2OpI>;
 379 def X86VPermv     : SDNode<"X86ISD::VPERMV",
 380                            SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<1>,
 381                                                 SDTCisSameNumEltsAs<0,1>,
 382                                                 SDTCisSameSizeAs<0,1>,
 383                                                 SDTCisSameAs<0,2>]>>;
 384 def X86VPermi     : SDNode<"X86ISD::VPERMI",    SDTShuff2OpI>;
 385 def X86VPermt2     : SDNode<"X86ISD::VPERMV3",
 386                     SDTypeProfile<1, 3, [SDTCisVec<0>,
 387                                          SDTCisSameAs<0,1>, SDTCisInt<2>,
 388                                          SDTCisVec<2>, SDTCisSameNumEltsAs<0, 2>,
 389                                          SDTCisSameSizeAs<0,2>,
 390                                          SDTCisSameAs<0,3>]>, []>;
 391
 392 def X86VPermi2X   : SDNode<"X86ISD::VPERMIV3", SDTShuff3Op>;
 393 def X86vpternlog  : SDNode<"X86ISD::VPTERNLOG", SDTTernlog>;
 394
 395 def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
 396
 397 def X86VFixupimm   : SDNode<"X86ISD::VFIXUPIMM", SDTFPBinOpImmRound>;
 398 def X86VRange      : SDNode<"X86ISD::VRANGE",    SDTFPBinOpImmRound>;
 399 def X86VReduce     : SDNode<"X86ISD::VREDUCE",   SDTFPUnaryOpImmRound>;
 400 def X86VRndScale   : SDNode<"X86ISD::VRNDSCALE", SDTFPUnaryOpImmRound>;
 401 def X86VGetMant    : SDNode<"X86ISD::VGETMANT",  SDTFPUnaryOpImmRound>;
 402 def X86Vfpclass    : SDNode<"X86ISD::VFPCLASS",
 403                        SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
 404                                             SDTCisVec<1>, SDTCisFP<1>,
 405                                             SDTCisSameNumEltsAs<0,1>,
 406                                             SDTCisVT<2, i32>]>, []>;
 407 def X86Vfpclasss   : SDNode<"X86ISD::VFPCLASSS",
 408                        SDTypeProfile<1, 2, [SDTCisVT<0, i1>,
 409                                             SDTCisFP<1>, SDTCisVT<2, i32>]>,[]>;
 410
 411 def X86SubVBroadcast : SDNode<"X86ISD::SUBV_BROADCAST",
 412                     SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 413                                          SDTCisSubVecOfVec<1, 0>]>, []>;
 414 // SDTCisSubVecOfVec restriction cannot be applied for 128 bit version of VBROADCASTI32x2.
 415 def X86SubV32x2Broadcast : SDNode<"X86ISD::SUBV_BROADCAST",
 416                     SDTypeProfile<1, 1, [SDTCisVec<0>,
 417                                          SDTCisSameAs<0,1>]>, []>;
 418
 419 def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
 420 def X86VBroadcastm : SDNode<"X86ISD::VBROADCASTM", SDTVBroadcastm>;
 421 def X86Vinsert   : SDNode<"X86ISD::VINSERT",  SDTypeProfile<1, 3,
 422                               [SDTCisSameAs<0, 1>, SDTCisEltOfVec<2, 1>,
 423                                SDTCisPtrTy<3>]>, []>;
 424 def X86Vextract   : SDNode<"X86ISD::VEXTRACT",  SDTypeProfile<1, 2,
 425                               [SDTCisEltOfVec<0, 1>, SDTCisVec<1>,
 426                                SDTCisPtrTy<2>]>, []>;
 427
 428 def X86Blendi    : SDNode<"X86ISD::BLENDI",   SDTBlend>;
 429
 430 def X86Addsub    : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>;
 431
 432 def X86faddRnd   : SDNode<"X86ISD::FADD_RND",  SDTFPBinOpRound>;
 433 def X86fsubRnd   : SDNode<"X86ISD::FSUB_RND",  SDTFPBinOpRound>;
 434 def X86fmulRnd   : SDNode<"X86ISD::FMUL_RND",  SDTFPBinOpRound>;
 435 def X86fdivRnd   : SDNode<"X86ISD::FDIV_RND",  SDTFPBinOpRound>;
 436 def X86fmaxRnd   : SDNode<"X86ISD::FMAX_RND",       SDTFPBinOpRound>;
 437 def X86scalef    : SDNode<"X86ISD::SCALEF",         SDTFPBinOpRound>;
 438 def X86fminRnd   : SDNode<"X86ISD::FMIN_RND",       SDTFPBinOpRound>;
 439 def X86fsqrtRnd     : SDNode<"X86ISD::FSQRT_RND",   SDTFPUnaryOpRound>;
 440 def X86fsqrtRnds    : SDNode<"X86ISD::FSQRT_RND",   STDFp2SrcRm>;
 441 def X86fgetexpRnd   : SDNode<"X86ISD::FGETEXP_RND", SDTFPUnaryOpRound>;
 442 def X86fgetexpRnds  : SDNode<"X86ISD::FGETEXP_RND", STDFp2SrcRm>;
 443
 444 def X86Fmadd     : SDNode<"X86ISD::FMADD",     SDTFma>;
 445 def X86Fnmadd    : SDNode<"X86ISD::FNMADD",    SDTFma>;
 446 def X86Fmsub     : SDNode<"X86ISD::FMSUB",     SDTFma>;
 447 def X86Fnmsub    : SDNode<"X86ISD::FNMSUB",    SDTFma>;
 448 def X86Fmaddsub  : SDNode<"X86ISD::FMADDSUB",  SDTFma>;
 449 def X86Fmsubadd  : SDNode<"X86ISD::FMSUBADD",  SDTFma>;
 450
 451 def X86FmaddRnd     : SDNode<"X86ISD::FMADD_RND",     SDTFmaRound>;
 452 def X86FnmaddRnd    : SDNode<"X86ISD::FNMADD_RND",    SDTFmaRound>;
 453 def X86FmsubRnd     : SDNode<"X86ISD::FMSUB_RND",     SDTFmaRound>;
 454 def X86FnmsubRnd    : SDNode<"X86ISD::FNMSUB_RND",    SDTFmaRound>;
 455 def X86FmaddsubRnd  : SDNode<"X86ISD::FMADDSUB_RND",  SDTFmaRound>;
 456 def X86FmsubaddRnd  : SDNode<"X86ISD::FMSUBADD_RND",  SDTFmaRound>;
 457
 458 def X86rsqrt28   : SDNode<"X86ISD::RSQRT28",  STDFp1SrcRm>;
 459 def X86rcp28     : SDNode<"X86ISD::RCP28",    STDFp1SrcRm>;
 460 def X86exp2      : SDNode<"X86ISD::EXP2",     STDFp1SrcRm>;
 461
 462 def X86rsqrt28s  : SDNode<"X86ISD::RSQRT28",   STDFp2SrcRm>;
 463 def X86rcp28s    : SDNode<"X86ISD::RCP28",     STDFp2SrcRm>;
 464 def X86RndScales : SDNode<"X86ISD::VRNDSCALE", STDFp3SrcRm>;
 465 def X86Reduces   : SDNode<"X86ISD::VREDUCE",   STDFp3SrcRm>;
 466 def X86GetMants  : SDNode<"X86ISD::VGETMANT",  STDFp3SrcRm>;
 467
 468 def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
 469                                          SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>,
 470                                          SDTCisVT<4, i8>]>;
 471 def SDT_PCMPESTRI : SDTypeProfile<2, 5, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
 472                                          SDTCisVT<2, v16i8>, SDTCisVT<3, i32>,
 473                                          SDTCisVT<4, v16i8>, SDTCisVT<5, i32>,
 474                                          SDTCisVT<6, i8>]>;
 475
 476 def X86pcmpistri : SDNode<"X86ISD::PCMPISTRI", SDT_PCMPISTRI>;
 477 def X86pcmpestri : SDNode<"X86ISD::PCMPESTRI", SDT_PCMPESTRI>;
 478
 479 def X86compress: SDNode<"X86ISD::COMPRESS", SDTypeProfile<1, 1,
 480                               [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
 481 def X86expand  : SDNode<"X86ISD::EXPAND", SDTypeProfile<1, 1,
 482                               [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
 483
 484 def SDTintToFPRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>,
 485                                           SDTCisSameAs<0,1>, SDTCisInt<2>,
 486                                           SDTCisVT<3, i32>]>;
 487
 488 def SDTDoubleToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 489                                          SDTCisInt<0>, SDTCVecEltisVT<1, f64>]>;
 490 def SDTFloatToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 491                                          SDTCisInt<0>, SDTCVecEltisVT<1, f32>]>;
 492
 493 def SDTDoubleToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 494                                          SDTCisInt<0>, SDTCVecEltisVT<1, f64>]>;
 495 def SDTSDoubleToIntRnd: SDTypeProfile<1, 2, [SDTCisInt<0>,SDTCisFP<1>,
 496                                              SDTCVecEltisVT<1, f64>, SDTCisInt<2>]>;
 497 def SDTFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 498                                          SDTCisInt<0>, SDTCVecEltisVT<1, f32>]>;
 499 def SDTSFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisFP<1>,
 500                                             SDTCVecEltisVT<1, f32>, SDTCisInt<2>]>;
 501 def SDTVintToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 502                                            SDTCisFP<0>, SDTCVecEltisVT<1, i32>,
 503                                            SDTCisInt<2>]>;
 504 def SDTVlongToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 505                                            SDTCisFP<0>, SDTCVecEltisVT<1, i64>,
 506                                            SDTCisInt<2>]>;
 507
 508 def SDTVFPToIntRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 509                                            SDTCisFP<1>, SDTCVecEltisVT<0, i32>,
 510                                            SDTCisInt<2>]>;
 511 def SDTVFPToLongRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 512                                            SDTCisFP<1>, SDTCVecEltisVT<0, i64>,
 513                                            SDTCisInt<2>]>;
 514
 515 // Scalar
 516 def X86SintToFpRnd  : SDNode<"X86ISD::SINT_TO_FP_RND",  SDTintToFPRound>;
 517 def X86UintToFpRnd  : SDNode<"X86ISD::UINT_TO_FP_RND",  SDTintToFPRound>;
 518
 519 def X86cvttss2IntRnd      : SDNode<"X86ISD::FP_TO_SINT_RND",  SDTSFloatToIntRnd>;
 520 def X86cvttss2UIntRnd     : SDNode<"X86ISD::FP_TO_UINT_RND",  SDTSFloatToIntRnd>;
 521 def X86cvttsd2IntRnd      : SDNode<"X86ISD::FP_TO_SINT_RND",  SDTSDoubleToIntRnd>;
 522 def X86cvttsd2UIntRnd     : SDNode<"X86ISD::FP_TO_UINT_RND",  SDTSDoubleToIntRnd>;
 523 // Vector with rounding mode
 524
 525 // cvtt fp-to-int staff
 526 def X86VFpToSintRnd   : SDNode<"ISD::FP_TO_SINT",  SDTVFPToIntRound>;
 527 def X86VFpToUintRnd   : SDNode<"ISD::FP_TO_UINT",  SDTVFPToIntRound>;
 528 def X86VFpToSlongRnd  : SDNode<"ISD::FP_TO_SINT",  SDTVFPToLongRound>;
 529 def X86VFpToUlongRnd  : SDNode<"ISD::FP_TO_UINT",  SDTVFPToLongRound>;
 530
 531 def X86VSintToFpRnd   : SDNode<"ISD::SINT_TO_FP",  SDTVintToFPRound>;
 532 def X86VUintToFpRnd   : SDNode<"ISD::UINT_TO_FP",  SDTVintToFPRound>;
 533 def X86VSlongToFpRnd  : SDNode<"ISD::SINT_TO_FP",  SDTVlongToFPRound>;
 534 def X86VUlongToFpRnd  : SDNode<"ISD::UINT_TO_FP",  SDTVlongToFPRound>;
 535
 536 // cvt fp-to-int staff
 537 def X86cvtps2IntRnd      : SDNode<"X86ISD::FP_TO_SINT_RND",  SDTFloatToIntRnd>;
 538 def X86cvtps2UIntRnd     : SDNode<"X86ISD::FP_TO_UINT_RND",  SDTFloatToIntRnd>;
 539 def X86cvtpd2IntRnd      : SDNode<"X86ISD::FP_TO_SINT_RND",  SDTDoubleToIntRnd>;
 540 def X86cvtpd2UIntRnd     : SDNode<"X86ISD::FP_TO_UINT_RND",  SDTDoubleToIntRnd>;
 541
 542 // Vector without rounding mode
 543 def X86cvtps2Int      : SDNode<"X86ISD::FP_TO_SINT_RND",  SDTFloatToInt>;
 544 def X86cvtps2UInt     : SDNode<"X86ISD::FP_TO_UINT_RND",  SDTFloatToInt>;
 545 def X86cvtpd2Int      : SDNode<"X86ISD::FP_TO_SINT_RND",  SDTDoubleToInt>;
 546 def X86cvtpd2UInt     : SDNode<"X86ISD::FP_TO_UINT_RND",  SDTDoubleToInt>;
 547
 548 def X86cvtph2ps     : SDNode<"ISD::FP16_TO_FP",
 549                               SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 550                                                    SDTCVecEltisVT<0, f32>,
 551                                                    SDTCVecEltisVT<1, i16>,
 552                                                    SDTCisFP<0>,
 553                                                    SDTCisVT<2, i32>]> >;
 554
 555 def X86cvtps2ph   : SDNode<"ISD::FP_TO_FP16",
 556                         SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>,
 557                                              SDTCVecEltisVT<0, i16>,
 558                                              SDTCVecEltisVT<1, f32>,
 559                                              SDTCisFP<1>, SDTCisVT<2, i32>,
 560                                              SDTCisVT<3, i32>]> >;
 561 def X86vfpextRnd  : SDNode<"X86ISD::VFPEXT",
 562                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 563                                              SDTCisFP<0>, SDTCisFP<1>,
 564                                              SDTCVecEltisVT<0, f64>,
 565                                              SDTCVecEltisVT<1, f32>,
 566                                              SDTCisOpSmallerThanOp<1, 0>,
 567                                              SDTCisVT<2, i32>]>>;
 568 def X86vfproundRnd: SDNode<"X86ISD::VFPROUND",
 569                         SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 570                                              SDTCisFP<0>, SDTCisFP<1>,
 571                                              SDTCVecEltisVT<0, f32>,
 572                                              SDTCVecEltisVT<1, f64>,
 573                                              SDTCisOpSmallerThanOp<0, 1>,
 574                                              SDTCisVT<2, i32>]>>;
 575
 576 //===----------------------------------------------------------------------===//
 577 // SSE Complex Patterns
 578 //===----------------------------------------------------------------------===//
 579
 580 // These are 'extloads' from a scalar to the low element of a vector, zeroing
 581 // the top elements.  These are used for the SSE 'ss' and 'sd' instruction
 582 // forms.
 583 def sse_load_f32 : ComplexPattern<v4f32, 5, "selectScalarSSELoad", [],
 584                                   [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
 585                                    SDNPWantRoot]>;
 586 def sse_load_f64 : ComplexPattern<v2f64, 5, "selectScalarSSELoad", [],
 587                                   [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
 588                                    SDNPWantRoot]>;
 589
 590 def ssmem : Operand<v4f32> {
 591   let PrintMethod = "printf32mem";
 592   let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
 593   let ParserMatchClass = X86Mem32AsmOperand;
 594   let OperandType = "OPERAND_MEMORY";
 595 }
 596 def sdmem : Operand<v2f64> {
 597   let PrintMethod = "printf64mem";
 598   let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
 599   let ParserMatchClass = X86Mem64AsmOperand;
 600   let OperandType = "OPERAND_MEMORY";
 601 }
 602
 603 //===----------------------------------------------------------------------===//
 604 // SSE pattern fragments
 605 //===----------------------------------------------------------------------===//
 606
 607 // 128-bit load pattern fragments
 608 // NOTE: all 128-bit integer vector loads are promoted to v2i64
 609 def loadv4f32    : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
 610 def loadv2f64    : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
 611 def loadv2i64    : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
 612
 613 // 256-bit load pattern fragments
 614 // NOTE: all 256-bit integer vector loads are promoted to v4i64
 615 def loadv8f32    : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
 616 def loadv4f64    : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
 617 def loadv4i64    : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
 618
 619 // 512-bit load pattern fragments
 620 def loadv16f32   : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>;
 621 def loadv8f64    : PatFrag<(ops node:$ptr), (v8f64 (load node:$ptr))>;
 622 def loadv64i8    : PatFrag<(ops node:$ptr), (v64i8 (load node:$ptr))>;
 623 def loadv32i16   : PatFrag<(ops node:$ptr), (v32i16 (load node:$ptr))>;
 624 def loadv16i32   : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>;
 625 def loadv8i64    : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>;
 626
 627 // 128-/256-/512-bit extload pattern fragments
 628 def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>;
 629 def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>;
 630 def extloadv8f32 : PatFrag<(ops node:$ptr), (v8f64 (extloadvf32 node:$ptr))>;
 631
 632 // These are needed to match a scalar load that is used in a vector-only
 633 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
 634 // The memory operand is required to be a 128-bit load, so it must be converted
 635 // from a vector to a scalar.
 636 def loadf32_128 : PatFrag<(ops node:$ptr),
 637   (f32 (vector_extract (loadv4f32 node:$ptr), (iPTR 0)))>;
 638 def loadf64_128 : PatFrag<(ops node:$ptr),
 639   (f64 (vector_extract (loadv2f64 node:$ptr), (iPTR 0)))>;
 640
 641 // Like 'store', but always requires 128-bit vector alignment.
 642 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
 643                            (store node:$val, node:$ptr), [{
 644   return cast<StoreSDNode>(N)->getAlignment() >= 16;
 645 }]>;
 646
 647 // Like 'store', but always requires 256-bit vector alignment.
 648 def alignedstore256 : PatFrag<(ops node:$val, node:$ptr),
 649                               (store node:$val, node:$ptr), [{
 650   return cast<StoreSDNode>(N)->getAlignment() >= 32;
 651 }]>;
 652
 653 // Like 'store', but always requires 512-bit vector alignment.
 654 def alignedstore512 : PatFrag<(ops node:$val, node:$ptr),
 655                               (store node:$val, node:$ptr), [{
 656   return cast<StoreSDNode>(N)->getAlignment() >= 64;
 657 }]>;
 658
 659 // Like 'load', but always requires 128-bit vector alignment.
 660 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 661   return cast<LoadSDNode>(N)->getAlignment() >= 16;
 662 }]>;
 663
 664 // Like 'X86vzload', but always requires 128-bit vector alignment.
 665 def alignedX86vzload : PatFrag<(ops node:$ptr), (X86vzload node:$ptr), [{
 666   return cast<MemSDNode>(N)->getAlignment() >= 16;
 667 }]>;
 668
 669 // Like 'load', but always requires 256-bit vector alignment.
 670 def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 671   return cast<LoadSDNode>(N)->getAlignment() >= 32;
 672 }]>;
 673
 674 // Like 'load', but always requires 512-bit vector alignment.
 675 def alignedload512 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 676   return cast<LoadSDNode>(N)->getAlignment() >= 64;
 677 }]>;
 678
 679 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
 680                                (f32 (alignedload node:$ptr))>;
 681 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
 682                                (f64 (alignedload node:$ptr))>;
 683
 684 // 128-bit aligned load pattern fragments
 685 // NOTE: all 128-bit integer vector loads are promoted to v2i64
 686 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
 687                                (v4f32 (alignedload node:$ptr))>;
 688 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
 689                                (v2f64 (alignedload node:$ptr))>;
 690 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
 691                                (v2i64 (alignedload node:$ptr))>;
 692
 693 // 256-bit aligned load pattern fragments
 694 // NOTE: all 256-bit integer vector loads are promoted to v4i64
 695 def alignedloadv8f32 : PatFrag<(ops node:$ptr),
 696                                (v8f32 (alignedload256 node:$ptr))>;
 697 def alignedloadv4f64 : PatFrag<(ops node:$ptr),
 698                                (v4f64 (alignedload256 node:$ptr))>;
 699 def alignedloadv4i64 : PatFrag<(ops node:$ptr),
 700                                (v4i64 (alignedload256 node:$ptr))>;
 701
 702 // 512-bit aligned load pattern fragments
 703 def alignedloadv16f32 : PatFrag<(ops node:$ptr),
 704                                 (v16f32 (alignedload512 node:$ptr))>;
 705 def alignedloadv16i32 : PatFrag<(ops node:$ptr),
 706                                 (v16i32 (alignedload512 node:$ptr))>;
 707 def alignedloadv8f64  : PatFrag<(ops node:$ptr),
 708                                 (v8f64  (alignedload512 node:$ptr))>;
 709 def alignedloadv8i64  : PatFrag<(ops node:$ptr),
 710                                 (v8i64  (alignedload512 node:$ptr))>;
 711
 712 // Like 'load', but uses special alignment checks suitable for use in
 713 // memory operands in most SSE instructions, which are required to
 714 // be naturally aligned on some targets but not on others.  If the subtarget
 715 // allows unaligned accesses, match any load, though this may require
 716 // setting a feature bit in the processor (on startup, for example).
 717 // Opteron 10h and later implement such a feature.
 718 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 719   return    Subtarget->hasSSEUnalignedMem()
 720          || cast<LoadSDNode>(N)->getAlignment() >= 16;
 721 }]>;
 722
 723 def memopfsf32 : PatFrag<(ops node:$ptr), (f32   (memop node:$ptr))>;
 724 def memopfsf64 : PatFrag<(ops node:$ptr), (f64   (memop node:$ptr))>;
 725
 726 // 128-bit memop pattern fragments
 727 // NOTE: all 128-bit integer vector loads are promoted to v2i64
 728 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
 729 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
 730 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
 731
 732 // These are needed to match a scalar memop that is used in a vector-only
 733 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
 734 // The memory operand is required to be a 128-bit load, so it must be converted
 735 // from a vector to a scalar.
 736 def memopfsf32_128 : PatFrag<(ops node:$ptr),
 737   (f32 (vector_extract (memopv4f32 node:$ptr), (iPTR 0)))>;
 738 def memopfsf64_128 : PatFrag<(ops node:$ptr),
 739   (f64 (vector_extract (memopv2f64 node:$ptr), (iPTR 0)))>;
 740
 741
 742 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
 743 // 16-byte boundary.
 744 // FIXME: 8 byte alignment for mmx reads is not required
 745 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 746   return cast<LoadSDNode>(N)->getAlignment() >= 8;
 747 }]>;
 748
 749 def memopmmx  : PatFrag<(ops node:$ptr), (x86mmx  (memop64 node:$ptr))>;
 750
 751 def mgatherv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 752   (masked_gather node:$src1, node:$src2, node:$src3) , [{
 753   if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
 754     return (Mgt->getIndex().getValueType() == MVT::v4i32 ||
 755             Mgt->getBasePtr().getValueType() == MVT::v4i32);
 756   return false;
 757 }]>;
 758
 759 def mgatherv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 760   (masked_gather node:$src1, node:$src2, node:$src3) , [{
 761   if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
 762     return (Mgt->getIndex().getValueType() == MVT::v8i32 ||
 763             Mgt->getBasePtr().getValueType() == MVT::v8i32);
 764   return false;
 765 }]>;
 766
 767 def mgatherv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 768   (masked_gather node:$src1, node:$src2, node:$src3) , [{
 769   if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
 770     return (Mgt->getIndex().getValueType() == MVT::v2i64 ||
 771             Mgt->getBasePtr().getValueType() == MVT::v2i64);
 772   return false;
 773 }]>;
 774 def mgatherv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 775   (masked_gather node:$src1, node:$src2, node:$src3) , [{
 776   if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
 777     return (Mgt->getIndex().getValueType() == MVT::v4i64 ||
 778             Mgt->getBasePtr().getValueType() == MVT::v4i64);
 779   return false;
 780 }]>;
 781 def mgatherv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 782   (masked_gather node:$src1, node:$src2, node:$src3) , [{
 783   if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
 784     return (Mgt->getIndex().getValueType() == MVT::v8i64 ||
 785             Mgt->getBasePtr().getValueType() == MVT::v8i64);
 786   return false;
 787 }]>;
 788 def mgatherv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 789   (masked_gather node:$src1, node:$src2, node:$src3) , [{
 790   if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
 791     return (Mgt->getIndex().getValueType() == MVT::v16i32 ||
 792             Mgt->getBasePtr().getValueType() == MVT::v16i32);
 793   return false;
 794 }]>;
 795
 796 def mscatterv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 797   (masked_scatter node:$src1, node:$src2, node:$src3) , [{
 798   if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
 799     return (Sc->getIndex().getValueType() == MVT::v2i64 ||
 800             Sc->getBasePtr().getValueType() == MVT::v2i64);
 801   return false;
 802 }]>;
 803
 804 def mscatterv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 805   (masked_scatter node:$src1, node:$src2, node:$src3) , [{
 806   if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
 807     return (Sc->getIndex().getValueType() == MVT::v4i32 ||
 808             Sc->getBasePtr().getValueType() == MVT::v4i32);
 809   return false;
 810 }]>;
 811
 812 def mscatterv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 813   (masked_scatter node:$src1, node:$src2, node:$src3) , [{
 814   if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
 815     return (Sc->getIndex().getValueType() == MVT::v4i64 ||
 816             Sc->getBasePtr().getValueType() == MVT::v4i64);
 817   return false;
 818 }]>;
 819
 820 def mscatterv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 821   (masked_scatter node:$src1, node:$src2, node:$src3) , [{
 822   if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
 823     return (Sc->getIndex().getValueType() == MVT::v8i32 ||
 824             Sc->getBasePtr().getValueType() == MVT::v8i32);
 825   return false;
 826 }]>;
 827
 828 def mscatterv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 829   (masked_scatter node:$src1, node:$src2, node:$src3) , [{
 830   if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
 831     return (Sc->getIndex().getValueType() == MVT::v8i64 ||
 832             Sc->getBasePtr().getValueType() == MVT::v8i64);
 833   return false;
 834 }]>;
 835 def mscatterv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 836   (masked_scatter node:$src1, node:$src2, node:$src3) , [{
 837   if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
 838     return (Sc->getIndex().getValueType() == MVT::v16i32 ||
 839             Sc->getBasePtr().getValueType() == MVT::v16i32);
 840   return false;
 841 }]>;
 842
 843 // 128-bit bitconvert pattern fragments
 844 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
 845 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
 846 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
 847 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
 848 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
 849 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
 850
 851 // 256-bit bitconvert pattern fragments
 852 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
 853 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
 854 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
 855 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
 856 def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>;
 857
 858 // 512-bit bitconvert pattern fragments
 859 def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
 860 def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
 861 def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>;
 862 def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>;
 863
 864 def vzmovl_v2i64 : PatFrag<(ops node:$src),
 865                            (bitconvert (v2i64 (X86vzmovl
 866                              (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
 867 def vzmovl_v4i32 : PatFrag<(ops node:$src),
 868                            (bitconvert (v4i32 (X86vzmovl
 869                              (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
 870
 871 def vzload_v2i64 : PatFrag<(ops node:$src),
 872                            (bitconvert (v2i64 (X86vzload node:$src)))>;
 873
 874
 875 def fp32imm0 : PatLeaf<(f32 fpimm), [{
 876   return N->isExactlyValue(+0.0);
 877 }]>;
 878
 879 def I8Imm : SDNodeXForm<imm, [{
 880   // Transformation function: get the low 8 bits.
 881   return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
 882 }]>;
 883
 884 def FROUND_NO_EXC : ImmLeaf<i32, [{ return Imm == 8; }]>;
 885 def FROUND_CURRENT : ImmLeaf<i32, [{
 886   return Imm == X86::STATIC_ROUNDING::CUR_DIRECTION;
 887 }]>;
 888
 889 // BYTE_imm - Transform bit immediates into byte immediates.
 890 def BYTE_imm  : SDNodeXForm<imm, [{
 891   // Transformation function: imm >> 3
 892   return getI32Imm(N->getZExtValue() >> 3, SDLoc(N));
 893 }]>;
 894
 895 // EXTRACT_get_vextract128_imm xform function: convert extract_subvector index
 896 // to VEXTRACTF128/VEXTRACTI128 imm.
 897 def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{
 898   return getI8Imm(X86::getExtractVEXTRACT128Immediate(N), SDLoc(N));
 899 }]>;
 900
 901 // INSERT_get_vinsert128_imm xform function: convert insert_subvector index to
 902 // VINSERTF128/VINSERTI128 imm.
 903 def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{
 904   return getI8Imm(X86::getInsertVINSERT128Immediate(N), SDLoc(N));
 905 }]>;
 906
 907 // EXTRACT_get_vextract256_imm xform function: convert extract_subvector index
 908 // to VEXTRACTF64x4 imm.
 909 def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{
 910   return getI8Imm(X86::getExtractVEXTRACT256Immediate(N), SDLoc(N));
 911 }]>;
 912
 913 // INSERT_get_vinsert256_imm xform function: convert insert_subvector index to
 914 // VINSERTF64x4 imm.
 915 def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{
 916   return getI8Imm(X86::getInsertVINSERT256Immediate(N), SDLoc(N));
 917 }]>;
 918
 919 def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index),
 920                                    (extract_subvector node:$bigvec,
 921                                                       node:$index), [{
 922   return X86::isVEXTRACT128Index(N);
 923 }], EXTRACT_get_vextract128_imm>;
 924
 925 def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
 926                                       node:$index),
 927                                  (insert_subvector node:$bigvec, node:$smallvec,
 928                                                    node:$index), [{
 929   return X86::isVINSERT128Index(N);
 930 }], INSERT_get_vinsert128_imm>;
 931
 932
 933 def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index),
 934                                    (extract_subvector node:$bigvec,
 935                                                       node:$index), [{
 936   return X86::isVEXTRACT256Index(N);
 937 }], EXTRACT_get_vextract256_imm>;
 938
 939 def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
 940                                       node:$index),
 941                                  (insert_subvector node:$bigvec, node:$smallvec,
 942                                                    node:$index), [{
 943   return X86::isVINSERT256Index(N);
 944 }], INSERT_get_vinsert256_imm>;
 945
 946 def masked_load_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 947                          (masked_load node:$src1, node:$src2, node:$src3), [{
 948   if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
 949     return Load->getAlignment() >= 16;
 950   return false;
 951 }]>;
 952
 953 def masked_load_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 954                          (masked_load node:$src1, node:$src2, node:$src3), [{
 955   if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
 956     return Load->getAlignment() >= 32;
 957   return false;
 958 }]>;
 959
 960 def masked_load_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 961                          (masked_load node:$src1, node:$src2, node:$src3), [{
 962   if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
 963     return Load->getAlignment() >= 64;
 964   return false;
 965 }]>;
 966
 967 def masked_load_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 968                          (masked_load node:$src1, node:$src2, node:$src3), [{
 969   return isa<MaskedLoadSDNode>(N);
 970 }]>;
 971
 972 // masked store fragments.
 973 // X86mstore can't be implemented in core DAG files because some targets
 974 // doesn't support vector type ( llvm-tblgen will fail)
 975 def X86mstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 976                         (masked_store node:$src1, node:$src2, node:$src3), [{
 977   return !cast<MaskedStoreSDNode>(N)->isTruncatingStore();
 978 }]>;
 979
 980 def masked_store_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 981                          (X86mstore node:$src1, node:$src2, node:$src3), [{
 982   if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
 983     return Store->getAlignment() >= 16;
 984   return false;
 985 }]>;
 986
 987 def masked_store_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 988                          (X86mstore node:$src1, node:$src2, node:$src3), [{
 989   if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
 990     return Store->getAlignment() >= 32;
 991   return false;
 992 }]>;
 993
 994 def masked_store_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 995                          (X86mstore node:$src1, node:$src2, node:$src3), [{
 996   if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
 997     return Store->getAlignment() >= 64;
 998   return false;
 999 }]>;
1000
1001 def masked_store_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1002                          (X86mstore node:$src1, node:$src2, node:$src3), [{
1003   return isa<MaskedStoreSDNode>(N);
1004 }]>;
1005
1006 // masked truncstore fragments
1007 // X86mtruncstore can't be implemented in core DAG files because some targets
1008 // doesn't support vector type ( llvm-tblgen will fail)
1009 def X86mtruncstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1010                              (masked_store node:$src1, node:$src2, node:$src3), [{
1011     return cast<MaskedStoreSDNode>(N)->isTruncatingStore();
1012 }]>;
1013 def masked_truncstorevi8 :
1014   PatFrag<(ops node:$src1, node:$src2, node:$src3),
1015           (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
1016   return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
1017 }]>;
1018 def masked_truncstorevi16 :
1019   PatFrag<(ops node:$src1, node:$src2, node:$src3),
1020           (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
1021   return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
1022 }]>;
1023 def masked_truncstorevi32 :
1024   PatFrag<(ops node:$src1, node:$src2, node:$src3),
1025           (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
1026   return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
1027 }]>;