1 //===-- X86InstrFormats.td - X86 Instruction Formats -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // X86 Instruction Format Definitions.
14 // Format specifies the encoding used by the instruction. This is part of the
15 // ad-hoc solution used to emit machine instruction encodings by our machine
17 class Format<bits<6> val> {
21 def Pseudo : Format<0>; def RawFrm : Format<1>;
22 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
23 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
24 def MRMSrcMem : Format<6>; def RawFrmMemOffs : Format<7>;
25 def RawFrmSrc : Format<8>; def RawFrmDst : Format<9>;
26 def RawFrmDstSrc: Format<10>;
27 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
28 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
29 def MRM6r : Format<22>; def MRM7r : Format<23>;
30 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
31 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
32 def MRM6m : Format<30>; def MRM7m : Format<31>;
33 def MRM_C1 : Format<33>;
34 def MRM_C2 : Format<34>;
35 def MRM_C3 : Format<35>;
36 def MRM_C4 : Format<36>;
37 def MRM_C8 : Format<37>;
38 def MRM_C9 : Format<38>;
39 def MRM_CA : Format<39>;
40 def MRM_CB : Format<40>;
41 def MRM_E8 : Format<41>;
42 def MRM_F0 : Format<42>;
43 def RawFrmImm8 : Format<43>;
44 def RawFrmImm16 : Format<44>;
45 def MRM_F8 : Format<45>;
46 def MRM_F9 : Format<46>;
47 def MRM_D0 : Format<47>;
48 def MRM_D1 : Format<48>;
49 def MRM_D4 : Format<49>;
50 def MRM_D5 : Format<50>;
51 def MRM_D6 : Format<51>;
52 def MRM_D8 : Format<52>;
53 def MRM_D9 : Format<53>;
54 def MRM_DA : Format<54>;
55 def MRM_DB : Format<55>;
56 def MRM_DC : Format<56>;
57 def MRM_DD : Format<57>;
58 def MRM_DE : Format<58>;
59 def MRM_DF : Format<59>;
61 // ImmType - This specifies the immediate type used by an instruction. This is
62 // part of the ad-hoc solution used to emit machine instruction encodings by our
63 // machine code emitter.
64 class ImmType<bits<4> val> {
67 def NoImm : ImmType<0>;
68 def Imm8 : ImmType<1>;
69 def Imm8PCRel : ImmType<2>;
70 def Imm16 : ImmType<3>;
71 def Imm16PCRel : ImmType<4>;
72 def Imm32 : ImmType<5>;
73 def Imm32PCRel : ImmType<6>;
74 def Imm32S : ImmType<7>;
75 def Imm64 : ImmType<8>;
77 // FPFormat - This specifies what form this FP instruction has. This is used by
78 // the Floating-Point stackifier pass.
79 class FPFormat<bits<3> val> {
82 def NotFP : FPFormat<0>;
83 def ZeroArgFP : FPFormat<1>;
84 def OneArgFP : FPFormat<2>;
85 def OneArgFPRW : FPFormat<3>;
86 def TwoArgFP : FPFormat<4>;
87 def CompareFP : FPFormat<5>;
88 def CondMovFP : FPFormat<6>;
89 def SpecialFP : FPFormat<7>;
91 // Class specifying the SSE execution domain, used by the SSEDomainFix pass.
92 // Keep in sync with tables in X86InstrInfo.cpp.
93 class Domain<bits<2> val> {
96 def GenericDomain : Domain<0>;
97 def SSEPackedSingle : Domain<1>;
98 def SSEPackedDouble : Domain<2>;
99 def SSEPackedInt : Domain<3>;
101 // Class specifying the vector form of the decompressed
102 // displacement of 8-bit.
103 class CD8VForm<bits<3> val> {
106 def CD8VF : CD8VForm<0>; // v := VL
107 def CD8VH : CD8VForm<1>; // v := VL/2
108 def CD8VQ : CD8VForm<2>; // v := VL/4
109 def CD8VO : CD8VForm<3>; // v := VL/8
110 def CD8VT1 : CD8VForm<4>; // v := 1
111 def CD8VT2 : CD8VForm<5>; // v := 2
112 def CD8VT4 : CD8VForm<6>; // v := 4
113 def CD8VT8 : CD8VForm<7>; // v := 8
115 // Prefix byte classes which are used to indicate to the ad-hoc machine code
116 // emitter that various prefix bytes are required.
117 class OpSize { bit hasOpSizePrefix = 1; }
118 class OpSize16 { bit hasOpSize16Prefix = 1; }
119 class AdSize { bit hasAdSizePrefix = 1; }
120 class REX_W { bit hasREX_WPrefix = 1; }
121 class LOCK { bit hasLockPrefix = 1; }
122 class TB { bits<5> Prefix = 1; }
123 class REP { bits<5> Prefix = 2; }
124 class D8 { bits<5> Prefix = 3; }
125 class D9 { bits<5> Prefix = 4; }
126 class DA { bits<5> Prefix = 5; }
127 class DB { bits<5> Prefix = 6; }
128 class DC { bits<5> Prefix = 7; }
129 class DD { bits<5> Prefix = 8; }
130 class DE { bits<5> Prefix = 9; }
131 class DF { bits<5> Prefix = 10; }
132 class XD { bits<5> Prefix = 11; }
133 class XS { bits<5> Prefix = 12; }
134 class T8 { bits<5> Prefix = 13; }
135 class TA { bits<5> Prefix = 14; }
136 class A6 { bits<5> Prefix = 15; }
137 class A7 { bits<5> Prefix = 16; }
138 class T8XD { bits<5> Prefix = 17; }
139 class T8XS { bits<5> Prefix = 18; }
140 class TAXD { bits<5> Prefix = 19; }
141 class XOP8 { bits<5> Prefix = 20; }
142 class XOP9 { bits<5> Prefix = 21; }
143 class XOPA { bits<5> Prefix = 22; }
144 class PD { bits<5> Prefix = 23; }
145 class T8PD { bits<5> Prefix = 24; }
146 class TAPD { bits<5> Prefix = 25; }
147 class VEX { bit hasVEXPrefix = 1; }
148 class VEX_W { bit hasVEX_WPrefix = 1; }
149 class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; }
150 class VEX_4VOp3 : VEX { bit hasVEX_4VOp3Prefix = 1; }
151 class VEX_I8IMM { bit hasVEX_i8ImmReg = 1; }
152 class VEX_L { bit hasVEX_L = 1; }
153 class VEX_LIG { bit ignoresVEX_L = 1; }
154 class EVEX : VEX { bit hasEVEXPrefix = 1; }
155 class EVEX_4V : VEX_4V { bit hasEVEXPrefix = 1; }
156 class EVEX_K { bit hasEVEX_K = 1; }
157 class EVEX_KZ : EVEX_K { bit hasEVEX_Z = 1; }
158 class EVEX_B { bit hasEVEX_B = 1; }
159 class EVEX_RC { bit hasEVEX_RC = 1; }
160 class EVEX_V512 { bit hasEVEX_L2 = 1; bit hasVEX_L = 0; }
161 class EVEX_CD8<int esize, CD8VForm form> {
162 bits<2> EVEX_CD8E = !if(!eq(esize, 8), 0b00,
163 !if(!eq(esize, 16), 0b01,
164 !if(!eq(esize, 32), 0b10,
165 !if(!eq(esize, 64), 0b11, ?))));
166 bits<3> EVEX_CD8V = form.Value;
168 class Has3DNow0F0FOpcode { bit has3DNow0F0FOpcode = 1; }
169 class MemOp4 { bit hasMemOp4Prefix = 1; }
170 class XOP { bit hasXOP_Prefix = 1; }
171 class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
174 Domain d = GenericDomain>
176 let Namespace = "X86";
178 bits<8> Opcode = opcod;
180 bits<6> FormBits = Form.Value;
183 dag OutOperandList = outs;
184 dag InOperandList = ins;
185 string AsmString = AsmStr;
187 // If this is a pseudo instruction, mark it isCodeGenOnly.
188 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
190 let Itinerary = itin;
193 // Attributes specific to X86 instructions...
195 bit ForceDisassemble = 0; // Force instruction to disassemble even though it's
196 // isCodeGenonly. Needed to hide an ambiguous
197 // AsmString from the parser, but still disassemble.
199 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
200 bit hasOpSize16Prefix = 0;// Does this inst have a 0x66 prefix in 16-bit mode?
201 bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix?
203 bits<5> Prefix = 0; // Which prefix byte does this inst have?
204 bit hasREX_WPrefix = 0; // Does this inst require the REX.W prefix?
205 FPFormat FPForm = NotFP; // What flavor of FP instruction is this?
206 bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix?
207 Domain ExeDomain = d;
208 bit hasVEXPrefix = 0; // Does this inst require a VEX prefix?
209 bit hasVEX_WPrefix = 0; // Does this inst set the VEX_W field?
210 bit hasVEX_4VPrefix = 0; // Does this inst require the VEX.VVVV field?
211 bit hasVEX_4VOp3Prefix = 0; // Does this inst require the VEX.VVVV field to
212 // encode the third operand?
213 bit hasVEX_i8ImmReg = 0; // Does this inst require the last source register
214 // to be encoded in a immediate field?
215 bit hasVEX_L = 0; // Does this inst use large (256-bit) registers?
216 bit ignoresVEX_L = 0; // Does this instruction ignore the L-bit
217 bit hasEVEXPrefix = 0; // Does this inst require EVEX form?
218 bit hasEVEX_K = 0; // Does this inst require masking?
219 bit hasEVEX_Z = 0; // Does this inst set the EVEX_Z field?
220 bit hasEVEX_L2 = 0; // Does this inst set the EVEX_L2 field?
221 bit hasEVEX_B = 0; // Does this inst set the EVEX_B field?
222 bits<2> EVEX_CD8E = 0; // Compressed disp8 form - element-size.
223 bits<3> EVEX_CD8V = 0; // Compressed disp8 form - vector-width.
224 bit has3DNow0F0FOpcode =0;// Wacky 3dNow! encoding?
225 bit hasMemOp4Prefix = 0; // Same bit as VEX_W, but used for swapping operands
226 bit hasXOP_Prefix = 0; // Does this inst require an XOP prefix?
227 bit hasEVEX_RC = 0; // Explicitly specified rounding control in FP instruction.
229 // TSFlags layout should be kept in sync with X86InstrInfo.h.
230 let TSFlags{5-0} = FormBits;
231 let TSFlags{6} = hasOpSizePrefix;
232 let TSFlags{7} = hasOpSize16Prefix;
233 let TSFlags{8} = hasAdSizePrefix;
234 let TSFlags{13-9} = Prefix;
235 let TSFlags{14} = hasREX_WPrefix;
236 let TSFlags{18-15} = ImmT.Value;
237 let TSFlags{21-19} = FPForm.Value;
238 let TSFlags{22} = hasLockPrefix;
239 let TSFlags{24-23} = ExeDomain.Value;
240 let TSFlags{32-25} = Opcode;
241 let TSFlags{33} = hasVEXPrefix;
242 let TSFlags{34} = hasVEX_WPrefix;
243 let TSFlags{35} = hasVEX_4VPrefix;
244 let TSFlags{36} = hasVEX_4VOp3Prefix;
245 let TSFlags{37} = hasVEX_i8ImmReg;
246 let TSFlags{38} = hasVEX_L;
247 let TSFlags{39} = ignoresVEX_L;
248 let TSFlags{40} = hasEVEXPrefix;
249 let TSFlags{41} = hasEVEX_K;
250 let TSFlags{42} = hasEVEX_Z;
251 let TSFlags{43} = hasEVEX_L2;
252 let TSFlags{44} = hasEVEX_B;
253 let TSFlags{46-45} = EVEX_CD8E;
254 let TSFlags{49-47} = EVEX_CD8V;
255 let TSFlags{50} = has3DNow0F0FOpcode;
256 let TSFlags{51} = hasMemOp4Prefix;
257 let TSFlags{52} = hasXOP_Prefix;
258 let TSFlags{53} = hasEVEX_RC;
261 class PseudoI<dag oops, dag iops, list<dag> pattern>
262 : X86Inst<0, Pseudo, NoImm, oops, iops, "", NoItinerary> {
263 let Pattern = pattern;
266 class I<bits<8> o, Format f, dag outs, dag ins, string asm,
267 list<dag> pattern, InstrItinClass itin = NoItinerary,
268 Domain d = GenericDomain>
269 : X86Inst<o, f, NoImm, outs, ins, asm, itin, d> {
270 let Pattern = pattern;
273 class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm,
274 list<dag> pattern, InstrItinClass itin = NoItinerary,
275 Domain d = GenericDomain>
276 : X86Inst<o, f, Imm8, outs, ins, asm, itin, d> {
277 let Pattern = pattern;
280 class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
281 list<dag> pattern, InstrItinClass itin = NoItinerary>
282 : X86Inst<o, f, Imm8PCRel, outs, ins, asm, itin> {
283 let Pattern = pattern;
286 class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm,
287 list<dag> pattern, InstrItinClass itin = NoItinerary>
288 : X86Inst<o, f, Imm16, outs, ins, asm, itin> {
289 let Pattern = pattern;
292 class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm,
293 list<dag> pattern, InstrItinClass itin = NoItinerary>
294 : X86Inst<o, f, Imm32, outs, ins, asm, itin> {
295 let Pattern = pattern;
298 class Ii32S<bits<8> o, Format f, dag outs, dag ins, string asm,
299 list<dag> pattern, InstrItinClass itin = NoItinerary>
300 : X86Inst<o, f, Imm32S, outs, ins, asm, itin> {
301 let Pattern = pattern;
305 class Ii16PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
306 list<dag> pattern, InstrItinClass itin = NoItinerary>
307 : X86Inst<o, f, Imm16PCRel, outs, ins, asm, itin> {
308 let Pattern = pattern;
312 class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
313 list<dag> pattern, InstrItinClass itin = NoItinerary>
314 : X86Inst<o, f, Imm32PCRel, outs, ins, asm, itin> {
315 let Pattern = pattern;
319 // FPStack Instruction Templates:
320 // FPI - Floating Point Instruction template.
321 class FPI<bits<8> o, Format F, dag outs, dag ins, string asm,
322 InstrItinClass itin = NoItinerary>
323 : I<o, F, outs, ins, asm, [], itin> {}
325 // FpI_ - Floating Point Pseudo Instruction template. Not Predicated.
326 class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern,
327 InstrItinClass itin = NoItinerary>
328 : X86Inst<0, Pseudo, NoImm, outs, ins, "", itin> {
330 let Pattern = pattern;
333 // Templates for instructions that use a 16- or 32-bit segmented address as
334 // their only operand: lcall (FAR CALL) and ljmp (FAR JMP)
336 // Iseg16 - 16-bit segment selector, 16-bit offset
337 // Iseg32 - 16-bit segment selector, 32-bit offset
339 class Iseg16 <bits<8> o, Format f, dag outs, dag ins, string asm,
340 list<dag> pattern, InstrItinClass itin = NoItinerary>
341 : X86Inst<o, f, Imm16, outs, ins, asm, itin> {
342 let Pattern = pattern;
346 class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm,
347 list<dag> pattern, InstrItinClass itin = NoItinerary>
348 : X86Inst<o, f, Imm32, outs, ins, asm, itin> {
349 let Pattern = pattern;
357 // SI - SSE 1 & 2 scalar instructions
358 class SI<bits<8> o, Format F, dag outs, dag ins, string asm,
359 list<dag> pattern, InstrItinClass itin = NoItinerary>
360 : I<o, F, outs, ins, asm, pattern, itin> {
361 let Predicates = !if(hasEVEXPrefix /* EVEX */, [HasAVX512],
362 !if(hasVEXPrefix /* VEX */, [UseAVX],
363 !if(!eq(Prefix, __xs.Prefix), [UseSSE1],
364 !if(!eq(Prefix, __xd.Prefix), [UseSSE2],
365 !if(!eq(Prefix, __pd.Prefix), [UseSSE2], [UseSSE1])))));
367 // AVX instructions have a 'v' prefix in the mnemonic
368 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
371 // SIi8 - SSE 1 & 2 scalar instructions
372 class SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
373 list<dag> pattern, InstrItinClass itin = NoItinerary>
374 : Ii8<o, F, outs, ins, asm, pattern, itin> {
375 let Predicates = !if(hasEVEXPrefix /* EVEX */, [HasAVX512],
376 !if(hasVEXPrefix /* VEX */, [UseAVX],
377 !if(!eq(Prefix, __xs.Prefix), [UseSSE1], [UseSSE2])));
379 // AVX instructions have a 'v' prefix in the mnemonic
380 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
383 // PI - SSE 1 & 2 packed instructions
384 class PI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
385 InstrItinClass itin, Domain d>
386 : I<o, F, outs, ins, asm, pattern, itin, d> {
387 let Predicates = !if(hasEVEXPrefix /* EVEX */, [HasAVX512],
388 !if(hasVEXPrefix /* VEX */, [HasAVX],
389 !if(!eq(Prefix, __pd.Prefix), [UseSSE2], [UseSSE1])));
391 // AVX instructions have a 'v' prefix in the mnemonic
392 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
395 // MMXPI - SSE 1 & 2 packed instructions with MMX operands
396 class MMXPI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
397 InstrItinClass itin, Domain d>
398 : I<o, F, outs, ins, asm, pattern, itin, d> {
399 let Predicates = !if(!eq(Prefix, __pd.Prefix), [HasSSE2], [HasSSE1]);
402 // PIi8 - SSE 1 & 2 packed instructions with immediate
403 class PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
404 list<dag> pattern, InstrItinClass itin, Domain d>
405 : Ii8<o, F, outs, ins, asm, pattern, itin, d> {
406 let Predicates = !if(hasEVEXPrefix /* EVEX */, [HasAVX512],
407 !if(hasVEXPrefix /* VEX */, [HasAVX],
408 !if(!eq(Prefix, __pd.Prefix), [UseSSE2], [UseSSE1])));
410 // AVX instructions have a 'v' prefix in the mnemonic
411 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
414 // SSE1 Instruction Templates:
416 // SSI - SSE1 instructions with XS prefix.
417 // PSI - SSE1 instructions with TB prefix.
418 // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
419 // VSSI - SSE1 instructions with XS prefix in AVX form.
420 // VPSI - SSE1 instructions with TB prefix in AVX form, packed single.
422 class SSI<bits<8> o, Format F, dag outs, dag ins, string asm,
423 list<dag> pattern, InstrItinClass itin = NoItinerary>
424 : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE1]>;
425 class SSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
426 list<dag> pattern, InstrItinClass itin = NoItinerary>
427 : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE1]>;
428 class PSI<bits<8> o, Format F, dag outs, dag ins, string asm,
429 list<dag> pattern, InstrItinClass itin = NoItinerary>
430 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, TB,
432 class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
433 list<dag> pattern, InstrItinClass itin = NoItinerary>
434 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, TB,
436 class VSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
437 list<dag> pattern, InstrItinClass itin = NoItinerary>
438 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS,
440 class VPSI<bits<8> o, Format F, dag outs, dag ins, string asm,
441 list<dag> pattern, InstrItinClass itin = NoItinerary>
442 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedSingle>, TB,
445 // SSE2 Instruction Templates:
447 // SDI - SSE2 instructions with XD prefix.
448 // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
449 // S2SI - SSE2 instructions with XS prefix.
450 // SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
451 // PDI - SSE2 instructions with PD prefix, packed double domain.
452 // PDIi8 - SSE2 instructions with ImmT == Imm8 and PD prefix.
453 // VSDI - SSE2 scalar instructions with XD prefix in AVX form.
454 // VPDI - SSE2 vector instructions with PD prefix in AVX form,
455 // packed double domain.
456 // VS2I - SSE2 scalar instructions with PD prefix in AVX form.
457 // S2I - SSE2 scalar instructions with PD prefix.
458 // MMXSDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix as well as
460 // MMXSSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix as well as
463 class SDI<bits<8> o, Format F, dag outs, dag ins, string asm,
464 list<dag> pattern, InstrItinClass itin = NoItinerary>
465 : I<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[UseSSE2]>;
466 class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
467 list<dag> pattern, InstrItinClass itin = NoItinerary>
468 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[UseSSE2]>;
469 class S2SI<bits<8> o, Format F, dag outs, dag ins, string asm,
470 list<dag> pattern, InstrItinClass itin = NoItinerary>
471 : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE2]>;
472 class S2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
473 list<dag> pattern, InstrItinClass itin = NoItinerary>
474 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[UseSSE2]>;
475 class PDI<bits<8> o, Format F, dag outs, dag ins, string asm,
476 list<dag> pattern, InstrItinClass itin = NoItinerary>
477 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD,
479 class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
480 list<dag> pattern, InstrItinClass itin = NoItinerary>
481 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD,
483 class VSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
484 list<dag> pattern, InstrItinClass itin = NoItinerary>
485 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XD,
487 class VS2SI<bits<8> o, Format F, dag outs, dag ins, string asm,
488 list<dag> pattern, InstrItinClass itin = NoItinerary>
489 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS,
491 class VPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
492 list<dag> pattern, InstrItinClass itin = NoItinerary>
493 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedDouble>,
494 PD, Requires<[HasAVX]>;
495 class VS2I<bits<8> o, Format F, dag outs, dag ins, string asm,
496 list<dag> pattern, InstrItinClass itin = NoItinerary>
497 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, PD,
499 class S2I<bits<8> o, Format F, dag outs, dag ins, string asm,
500 list<dag> pattern, InstrItinClass itin = NoItinerary>
501 : I<o, F, outs, ins, asm, pattern, itin>, PD, Requires<[UseSSE2]>;
502 class MMXSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
503 list<dag> pattern, InstrItinClass itin = NoItinerary>
504 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasSSE2]>;
505 class MMXS2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
506 list<dag> pattern, InstrItinClass itin = NoItinerary>
507 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>;
509 // SSE3 Instruction Templates:
511 // S3I - SSE3 instructions with PD prefixes.
512 // S3SI - SSE3 instructions with XS prefix.
513 // S3DI - SSE3 instructions with XD prefix.
515 class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm,
516 list<dag> pattern, InstrItinClass itin = NoItinerary>
517 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, XS,
519 class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm,
520 list<dag> pattern, InstrItinClass itin = NoItinerary>
521 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, XD,
523 class S3I<bits<8> o, Format F, dag outs, dag ins, string asm,
524 list<dag> pattern, InstrItinClass itin = NoItinerary>
525 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD,
529 // SSSE3 Instruction Templates:
531 // SS38I - SSSE3 instructions with T8 prefix.
532 // SS3AI - SSSE3 instructions with TA prefix.
533 // MMXSS38I - SSSE3 instructions with T8 prefix and MMX operands.
534 // MMXSS3AI - SSSE3 instructions with TA prefix and MMX operands.
536 // Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version
537 // uses the MMX registers. The 64-bit versions are grouped with the MMX
538 // classes. They need to be enabled even if AVX is enabled.
540 class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
541 list<dag> pattern, InstrItinClass itin = NoItinerary>
542 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
543 Requires<[UseSSSE3]>;
544 class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
545 list<dag> pattern, InstrItinClass itin = NoItinerary>
546 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
547 Requires<[UseSSSE3]>;
548 class MMXSS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
549 list<dag> pattern, InstrItinClass itin = NoItinerary>
550 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
551 Requires<[HasSSSE3]>;
552 class MMXSS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
553 list<dag> pattern, InstrItinClass itin = NoItinerary>
554 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
555 Requires<[HasSSSE3]>;
557 // SSE4.1 Instruction Templates:
559 // SS48I - SSE 4.1 instructions with T8 prefix.
560 // SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8.
562 class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm,
563 list<dag> pattern, InstrItinClass itin = NoItinerary>
564 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
565 Requires<[UseSSE41]>;
566 class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
567 list<dag> pattern, InstrItinClass itin = NoItinerary>
568 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
569 Requires<[UseSSE41]>;
571 // SSE4.2 Instruction Templates:
573 // SS428I - SSE 4.2 instructions with T8 prefix.
574 class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm,
575 list<dag> pattern, InstrItinClass itin = NoItinerary>
576 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
577 Requires<[UseSSE42]>;
579 // SS42FI - SSE 4.2 instructions with T8XD prefix.
580 // NOTE: 'HasSSE42' is used as SS42FI is only used for CRC32 insns.
581 class SS42FI<bits<8> o, Format F, dag outs, dag ins, string asm,
582 list<dag> pattern, InstrItinClass itin = NoItinerary>
583 : I<o, F, outs, ins, asm, pattern, itin>, T8XD, Requires<[HasSSE42]>;
585 // SS42AI = SSE 4.2 instructions with TA prefix
586 class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm,
587 list<dag> pattern, InstrItinClass itin = NoItinerary>
588 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
589 Requires<[UseSSE42]>;
591 // AVX Instruction Templates:
592 // Instructions introduced in AVX (no SSE equivalent forms)
594 // AVX8I - AVX instructions with T8PD prefix.
595 // AVXAIi8 - AVX instructions with TAPD prefix and ImmT = Imm8.
596 class AVX8I<bits<8> o, Format F, dag outs, dag ins, string asm,
597 list<dag> pattern, InstrItinClass itin = NoItinerary>
598 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
600 class AVXAIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
601 list<dag> pattern, InstrItinClass itin = NoItinerary>
602 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
605 // AVX2 Instruction Templates:
606 // Instructions introduced in AVX2 (no SSE equivalent forms)
608 // AVX28I - AVX2 instructions with T8PD prefix.
609 // AVX2AIi8 - AVX2 instructions with TAPD prefix and ImmT = Imm8.
610 class AVX28I<bits<8> o, Format F, dag outs, dag ins, string asm,
611 list<dag> pattern, InstrItinClass itin = NoItinerary>
612 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
614 class AVX2AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
615 list<dag> pattern, InstrItinClass itin = NoItinerary>
616 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
620 // AVX-512 Instruction Templates:
621 // Instructions introduced in AVX-512 (no SSE equivalent forms)
623 // AVX5128I - AVX-512 instructions with T8PD prefix.
624 // AVX512AIi8 - AVX-512 instructions with TAPD prefix and ImmT = Imm8.
625 // AVX512PDI - AVX-512 instructions with PD, double packed.
626 // AVX512PSI - AVX-512 instructions with TB, single packed.
627 // AVX512XS8I - AVX-512 instructions with T8 and XS prefixes.
628 // AVX512XSI - AVX-512 instructions with XS prefix, generic domain.
629 // AVX512BI - AVX-512 instructions with PD, int packed domain.
630 // AVX512SI - AVX-512 scalar instructions with PD prefix.
632 class AVX5128I<bits<8> o, Format F, dag outs, dag ins, string asm,
633 list<dag> pattern, InstrItinClass itin = NoItinerary>
634 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
635 Requires<[HasAVX512]>;
636 class AVX512XS8I<bits<8> o, Format F, dag outs, dag ins, string asm,
637 list<dag> pattern, InstrItinClass itin = NoItinerary>
638 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8XS,
639 Requires<[HasAVX512]>;
640 class AVX512XSI<bits<8> o, Format F, dag outs, dag ins, string asm,
641 list<dag> pattern, InstrItinClass itin = NoItinerary>
642 : I<o, F, outs, ins, asm, pattern, itin>, XS,
643 Requires<[HasAVX512]>;
644 class AVX512XDI<bits<8> o, Format F, dag outs, dag ins, string asm,
645 list<dag> pattern, InstrItinClass itin = NoItinerary>
646 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, XD,
647 Requires<[HasAVX512]>;
648 class AVX512BI<bits<8> o, Format F, dag outs, dag ins, string asm,
649 list<dag> pattern, InstrItinClass itin = NoItinerary>
650 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, PD,
651 Requires<[HasAVX512]>;
652 class AVX512BIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
653 list<dag> pattern, InstrItinClass itin = NoItinerary>
654 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, PD,
655 Requires<[HasAVX512]>;
656 class AVX512AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
657 list<dag> pattern, InstrItinClass itin = NoItinerary>
658 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
659 Requires<[HasAVX512]>;
660 class AVX512Ii8<bits<8> o, Format F, dag outs, dag ins, string asm,
661 list<dag> pattern, InstrItinClass itin = NoItinerary>
662 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TB,
663 Requires<[HasAVX512]>;
664 class AVX512PDI<bits<8> o, Format F, dag outs, dag ins, string asm,
665 list<dag> pattern, InstrItinClass itin = NoItinerary>
666 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD,
667 Requires<[HasAVX512]>;
668 class AVX512PSI<bits<8> o, Format F, dag outs, dag ins, string asm,
669 list<dag> pattern, InstrItinClass itin = NoItinerary>
670 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, TB,
671 Requires<[HasAVX512]>;
672 class AVX512PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
673 list<dag> pattern, Domain d, InstrItinClass itin = NoItinerary>
674 : Ii8<o, F, outs, ins, asm, pattern, itin, d>, TB, Requires<[HasAVX512]>;
675 class AVX512PI<bits<8> o, Format F, dag outs, dag ins, string asm,
676 list<dag> pattern, Domain d, InstrItinClass itin = NoItinerary>
677 : I<o, F, outs, ins, asm, pattern, itin, d>, TB, Requires<[HasAVX512]>;
678 class AVX512FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
679 list<dag>pattern, InstrItinClass itin = NoItinerary>
680 : I<o, F, outs, ins, asm, pattern, itin>, T8PD,
681 EVEX_4V, Requires<[HasAVX512]>;
683 // AES Instruction Templates:
686 // These use the same encoding as the SSE4.2 T8 and TA encodings.
687 class AES8I<bits<8> o, Format F, dag outs, dag ins, string asm,
688 list<dag>pattern, InstrItinClass itin = IIC_AES>
689 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
692 class AESAI<bits<8> o, Format F, dag outs, dag ins, string asm,
693 list<dag> pattern, InstrItinClass itin = NoItinerary>
694 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
697 // PCLMUL Instruction Templates
698 class PCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
699 list<dag>pattern, InstrItinClass itin = NoItinerary>
700 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
701 Requires<[HasPCLMUL]>;
703 class AVXPCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
704 list<dag>pattern, InstrItinClass itin = NoItinerary>
705 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
706 VEX_4V, Requires<[HasAVX, HasPCLMUL]>;
708 // FMA3 Instruction Templates
709 class FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
710 list<dag>pattern, InstrItinClass itin = NoItinerary>
711 : I<o, F, outs, ins, asm, pattern, itin>, T8PD,
712 VEX_4V, FMASC, Requires<[HasFMA]>;
714 // FMA4 Instruction Templates
715 class FMA4<bits<8> o, Format F, dag outs, dag ins, string asm,
716 list<dag>pattern, InstrItinClass itin = NoItinerary>
717 : Ii8<o, F, outs, ins, asm, pattern, itin>, TAPD,
718 VEX_4V, VEX_I8IMM, FMASC, Requires<[HasFMA4]>;
720 // XOP 2, 3 and 4 Operand Instruction Template
721 class IXOP<bits<8> o, Format F, dag outs, dag ins, string asm,
722 list<dag> pattern, InstrItinClass itin = NoItinerary>
723 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>,
724 XOP, XOP9, Requires<[HasXOP]>;
726 // XOP 2, 3 and 4 Operand Instruction Templates with imm byte
727 class IXOPi8<bits<8> o, Format F, dag outs, dag ins, string asm,
728 list<dag> pattern, InstrItinClass itin = NoItinerary>
729 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>,
730 XOP, XOP8, Requires<[HasXOP]>;
732 // XOP 5 operand instruction (VEX encoding!)
733 class IXOP5<bits<8> o, Format F, dag outs, dag ins, string asm,
734 list<dag>pattern, InstrItinClass itin = NoItinerary>
735 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
736 VEX_4V, VEX_I8IMM, Requires<[HasXOP]>;
738 // X86-64 Instruction templates...
741 class RI<bits<8> o, Format F, dag outs, dag ins, string asm,
742 list<dag> pattern, InstrItinClass itin = NoItinerary>
743 : I<o, F, outs, ins, asm, pattern, itin>, REX_W;
744 class RIi8 <bits<8> o, Format F, dag outs, dag ins, string asm,
745 list<dag> pattern, InstrItinClass itin = NoItinerary>
746 : Ii8<o, F, outs, ins, asm, pattern, itin>, REX_W;
747 class RIi16 <bits<8> o, Format F, dag outs, dag ins, string asm,
748 list<dag> pattern, InstrItinClass itin = NoItinerary>
749 : Ii16<o, F, outs, ins, asm, pattern, itin>, REX_W;
750 class RIi32 <bits<8> o, Format F, dag outs, dag ins, string asm,
751 list<dag> pattern, InstrItinClass itin = NoItinerary>
752 : Ii32<o, F, outs, ins, asm, pattern, itin>, REX_W;
753 class RIi32S <bits<8> o, Format F, dag outs, dag ins, string asm,
754 list<dag> pattern, InstrItinClass itin = NoItinerary>
755 : Ii32S<o, F, outs, ins, asm, pattern, itin>, REX_W;
757 class RIi64<bits<8> o, Format f, dag outs, dag ins, string asm,
758 list<dag> pattern, InstrItinClass itin = NoItinerary>
759 : X86Inst<o, f, Imm64, outs, ins, asm, itin>, REX_W {
760 let Pattern = pattern;
764 class RIi64_NOREX<bits<8> o, Format f, dag outs, dag ins, string asm,
765 list<dag> pattern, InstrItinClass itin = NoItinerary>
766 : X86Inst<o, f, Imm64, outs, ins, asm, itin> {
767 let Pattern = pattern;
771 class RSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
772 list<dag> pattern, InstrItinClass itin = NoItinerary>
773 : SSI<o, F, outs, ins, asm, pattern, itin>, REX_W;
774 class RSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
775 list<dag> pattern, InstrItinClass itin = NoItinerary>
776 : SDI<o, F, outs, ins, asm, pattern, itin>, REX_W;
777 class RPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
778 list<dag> pattern, InstrItinClass itin = NoItinerary>
779 : PDI<o, F, outs, ins, asm, pattern, itin>, REX_W;
780 class VRPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
781 list<dag> pattern, InstrItinClass itin = NoItinerary>
782 : VPDI<o, F, outs, ins, asm, pattern, itin>, VEX_W;
783 class RS2I<bits<8> o, Format F, dag outs, dag ins, string asm,
784 list<dag> pattern, InstrItinClass itin = NoItinerary>
785 : S2I<o, F, outs, ins, asm, pattern, itin>, REX_W;
786 class VRS2I<bits<8> o, Format F, dag outs, dag ins, string asm,
787 list<dag> pattern, InstrItinClass itin = NoItinerary>
788 : VS2I<o, F, outs, ins, asm, pattern, itin>, VEX_W;
790 // MMX Instruction templates
793 // MMXI - MMX instructions with TB prefix.
794 // MMXI32 - MMX instructions with TB prefix valid only in 32 bit mode.
795 // MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode.
796 // MMX2I - MMX / SSE2 instructions with PD prefix.
797 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
798 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
799 // MMXID - MMX instructions with XD prefix.
800 // MMXIS - MMX instructions with XS prefix.
801 class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm,
802 list<dag> pattern, InstrItinClass itin = NoItinerary>
803 : I<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX]>;
804 class MMXI32<bits<8> o, Format F, dag outs, dag ins, string asm,
805 list<dag> pattern, InstrItinClass itin = NoItinerary>
806 : I<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX,Not64BitMode]>;
807 class MMXI64<bits<8> o, Format F, dag outs, dag ins, string asm,
808 list<dag> pattern, InstrItinClass itin = NoItinerary>
809 : I<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX,In64BitMode]>;
810 class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm,
811 list<dag> pattern, InstrItinClass itin = NoItinerary>
812 : I<o, F, outs, ins, asm, pattern, itin>, TB, REX_W, Requires<[HasMMX]>;
813 class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm,
814 list<dag> pattern, InstrItinClass itin = NoItinerary>
815 : I<o, F, outs, ins, asm, pattern, itin>, PD, Requires<[HasMMX]>;
816 class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
817 list<dag> pattern, InstrItinClass itin = NoItinerary>
818 : Ii8<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX]>;
819 class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm,
820 list<dag> pattern, InstrItinClass itin = NoItinerary>
821 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasMMX]>;
822 class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm,
823 list<dag> pattern, InstrItinClass itin = NoItinerary>
824 : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[HasMMX]>;