1 //==- X86InstrFPStack.td - Describe the X86 Instruction Set --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 x87 FPU instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // FPStack specific DAG Nodes.
18 //===----------------------------------------------------------------------===//
20 def SDTX86FpGet : SDTypeProfile<1, 0, [SDTCisFP<0>]>;
21 def SDTX86FpGet2 : SDTypeProfile<2, 0, [SDTCisVT<0, f80>,
23 def SDTX86FpSet : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
24 def SDTX86Fld : SDTypeProfile<1, 2, [SDTCisFP<0>,
26 SDTCisVT<2, OtherVT>]>;
27 def SDTX86Fst : SDTypeProfile<0, 3, [SDTCisFP<0>,
29 SDTCisVT<2, OtherVT>]>;
30 def SDTX86Fild : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisPtrTy<1>,
31 SDTCisVT<2, OtherVT>]>;
32 def SDTX86FpToIMem : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>;
34 def SDTX86CwdStore : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
36 def X86fpget_st0 : SDNode<"X86ISD::FP_GET_ST0", SDTX86FpGet,
37 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
38 def X86fpset : SDNode<"X86ISD::FP_SET_RESULT", SDTX86FpSet,
39 [SDNPHasChain, SDNPOutFlag]>;
40 def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld,
41 [SDNPHasChain, SDNPMayLoad]>;
42 def X86fst : SDNode<"X86ISD::FST", SDTX86Fst,
43 [SDNPHasChain, SDNPInFlag, SDNPMayStore]>;
44 def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild,
45 [SDNPHasChain, SDNPMayLoad]>;
46 def X86fildflag : SDNode<"X86ISD::FILD_FLAG", SDTX86Fild,
47 [SDNPHasChain, SDNPOutFlag, SDNPMayLoad]>;
48 def X86fp_to_i16mem : SDNode<"X86ISD::FP_TO_INT16_IN_MEM", SDTX86FpToIMem,
49 [SDNPHasChain, SDNPMayStore]>;
50 def X86fp_to_i32mem : SDNode<"X86ISD::FP_TO_INT32_IN_MEM", SDTX86FpToIMem,
51 [SDNPHasChain, SDNPMayStore]>;
52 def X86fp_to_i64mem : SDNode<"X86ISD::FP_TO_INT64_IN_MEM", SDTX86FpToIMem,
53 [SDNPHasChain, SDNPMayStore]>;
54 def X86fp_cwd_get16 : SDNode<"X86ISD::FNSTCW16m", SDTX86CwdStore,
55 [SDNPHasChain, SDNPMayStore, SDNPSideEffect]>;
57 //===----------------------------------------------------------------------===//
58 // FPStack pattern fragments
59 //===----------------------------------------------------------------------===//
61 def fpimm0 : PatLeaf<(fpimm), [{
62 return N->isExactlyValue(+0.0);
65 def fpimmneg0 : PatLeaf<(fpimm), [{
66 return N->isExactlyValue(-0.0);
69 def fpimm1 : PatLeaf<(fpimm), [{
70 return N->isExactlyValue(+1.0);
73 def fpimmneg1 : PatLeaf<(fpimm), [{
74 return N->isExactlyValue(-1.0);
77 // Some 'special' instructions
78 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
79 def FP32_TO_INT16_IN_MEM : I<0, Pseudo,
80 (outs), (ins i16mem:$dst, RFP32:$src),
81 "#FP32_TO_INT16_IN_MEM PSEUDO!",
82 [(X86fp_to_i16mem RFP32:$src, addr:$dst)]>;
83 def FP32_TO_INT32_IN_MEM : I<0, Pseudo,
84 (outs), (ins i32mem:$dst, RFP32:$src),
85 "#FP32_TO_INT32_IN_MEM PSEUDO!",
86 [(X86fp_to_i32mem RFP32:$src, addr:$dst)]>;
87 def FP32_TO_INT64_IN_MEM : I<0, Pseudo,
88 (outs), (ins i64mem:$dst, RFP32:$src),
89 "#FP32_TO_INT64_IN_MEM PSEUDO!",
90 [(X86fp_to_i64mem RFP32:$src, addr:$dst)]>;
91 def FP64_TO_INT16_IN_MEM : I<0, Pseudo,
92 (outs), (ins i16mem:$dst, RFP64:$src),
93 "#FP64_TO_INT16_IN_MEM PSEUDO!",
94 [(X86fp_to_i16mem RFP64:$src, addr:$dst)]>;
95 def FP64_TO_INT32_IN_MEM : I<0, Pseudo,
96 (outs), (ins i32mem:$dst, RFP64:$src),
97 "#FP64_TO_INT32_IN_MEM PSEUDO!",
98 [(X86fp_to_i32mem RFP64:$src, addr:$dst)]>;
99 def FP64_TO_INT64_IN_MEM : I<0, Pseudo,
100 (outs), (ins i64mem:$dst, RFP64:$src),
101 "#FP64_TO_INT64_IN_MEM PSEUDO!",
102 [(X86fp_to_i64mem RFP64:$src, addr:$dst)]>;
103 def FP80_TO_INT16_IN_MEM : I<0, Pseudo,
104 (outs), (ins i16mem:$dst, RFP80:$src),
105 "#FP80_TO_INT16_IN_MEM PSEUDO!",
106 [(X86fp_to_i16mem RFP80:$src, addr:$dst)]>;
107 def FP80_TO_INT32_IN_MEM : I<0, Pseudo,
108 (outs), (ins i32mem:$dst, RFP80:$src),
109 "#FP80_TO_INT32_IN_MEM PSEUDO!",
110 [(X86fp_to_i32mem RFP80:$src, addr:$dst)]>;
111 def FP80_TO_INT64_IN_MEM : I<0, Pseudo,
112 (outs), (ins i64mem:$dst, RFP80:$src),
113 "#FP80_TO_INT64_IN_MEM PSEUDO!",
114 [(X86fp_to_i64mem RFP80:$src, addr:$dst)]>;
117 let isTerminator = 1 in
118 let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
119 def FP_REG_KILL : I<0, Pseudo, (outs), (ins), "#FP_REG_KILL", []>;
121 // All FP Stack operations are represented with four instructions here. The
122 // first three instructions, generated by the instruction selector, use "RFP32"
123 // "RFP64" or "RFP80" registers: traditional register files to reference 32-bit,
124 // 64-bit or 80-bit floating point values. These sizes apply to the values,
125 // not the registers, which are always 80 bits; RFP32, RFP64 and RFP80 can be
126 // copied to each other without losing information. These instructions are all
127 // pseudo instructions and use the "_Fp" suffix.
128 // In some cases there are additional variants with a mixture of different
130 // The second instruction is defined with FPI, which is the actual instruction
131 // emitted by the assembler. These use "RST" registers, although frequently
132 // the actual register(s) used are implicit. These are always 80 bits.
133 // The FP stackifier pass converts one to the other after register allocation
136 // Note that the FpI instruction should have instruction selection info (e.g.
137 // a pattern) and the FPI instruction should have emission info (e.g. opcode
138 // encoding and asm printing info).
140 // Pseudo Instructions for FP stack return values.
141 def FpGET_ST0_32 : FpI_<(outs RFP32:$dst), (ins), SpecialFP,
142 [(set RFP32:$dst, X86fpget_st0)]>; // FPR = ST(0)
143 def FpGET_ST0_64 : FpI_<(outs RFP64:$dst), (ins), SpecialFP,
144 [(set RFP64:$dst, X86fpget_st0)]>; // FPR = ST(0)
145 def FpGET_ST0_80 : FpI_<(outs RFP80:$dst), (ins), SpecialFP,
146 [(set RFP80:$dst, X86fpget_st0)]>; // FPR = ST(0)
148 def FpGET_ST0_ST1 : FpI_<(outs RFP80:$dst1, RFP80:$dst2), (ins), SpecialFP,
149 []>; // FPR = ST(0), FPR = ST(1)
152 let Defs = [ST0] in {
153 def FpSETRESULT32 : FpI_<(outs), (ins RFP32:$src), SpecialFP,
154 [(X86fpset RFP32:$src)]>;// ST(0) = FPR
156 def FpSETRESULT64 : FpI_<(outs), (ins RFP64:$src), SpecialFP,
157 [(X86fpset RFP64:$src)]>;// ST(0) = FPR
159 def FpSETRESULT80 : FpI_<(outs), (ins RFP80:$src), SpecialFP,
160 [(X86fpset RFP80:$src)]>;// ST(0) = FPR
163 // FpIf32, FpIf64 - Floating Point Psuedo Instruction template.
164 // f32 instructions can use SSE1 and are predicated on FPStackf32 == !SSE1.
165 // f64 instructions can use SSE2 and are predicated on FPStackf64 == !SSE2.
166 // f80 instructions cannot use SSE and use neither of these.
167 class FpIf32<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
168 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32]>;
169 class FpIf64<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
170 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64]>;
172 // Register copies. Just copies, the shortening ones do not truncate.
173 let neverHasSideEffects = 1 in {
174 def MOV_Fp3232 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), SpecialFP, []>;
175 def MOV_Fp3264 : FpIf32<(outs RFP64:$dst), (ins RFP32:$src), SpecialFP, []>;
176 def MOV_Fp6432 : FpIf32<(outs RFP32:$dst), (ins RFP64:$src), SpecialFP, []>;
177 def MOV_Fp6464 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), SpecialFP, []>;
178 def MOV_Fp8032 : FpIf32<(outs RFP32:$dst), (ins RFP80:$src), SpecialFP, []>;
179 def MOV_Fp3280 : FpIf32<(outs RFP80:$dst), (ins RFP32:$src), SpecialFP, []>;
180 def MOV_Fp8064 : FpIf64<(outs RFP64:$dst), (ins RFP80:$src), SpecialFP, []>;
181 def MOV_Fp6480 : FpIf64<(outs RFP80:$dst), (ins RFP64:$src), SpecialFP, []>;
182 def MOV_Fp8080 : FpI_ <(outs RFP80:$dst), (ins RFP80:$src), SpecialFP, []>;
185 // Factoring for arithmetic.
186 multiclass FPBinary_rr<SDNode OpNode> {
187 // Register op register -> register
188 // These are separated out because they have no reversed form.
189 def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), TwoArgFP,
190 [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>;
191 def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), TwoArgFP,
192 [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>;
193 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), TwoArgFP,
194 [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>;
196 // The FopST0 series are not included here because of the irregularities
197 // in where the 'r' goes in assembly output.
198 // These instructions cannot address 80-bit memory.
199 multiclass FPBinary<SDNode OpNode, Format fp, string asmstring> {
200 // ST(0) = ST(0) + [mem]
201 def _Fp32m : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, f32mem:$src2), OneArgFPRW,
203 (OpNode RFP32:$src1, (loadf32 addr:$src2)))]>;
204 def _Fp64m : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, f64mem:$src2), OneArgFPRW,
206 (OpNode RFP64:$src1, (loadf64 addr:$src2)))]>;
207 def _Fp64m32: FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, f32mem:$src2), OneArgFPRW,
209 (OpNode RFP64:$src1, (f64 (extloadf32 addr:$src2))))]>;
210 def _Fp80m32: FpI_<(outs RFP80:$dst), (ins RFP80:$src1, f32mem:$src2), OneArgFPRW,
212 (OpNode RFP80:$src1, (f80 (extloadf32 addr:$src2))))]>;
213 def _Fp80m64: FpI_<(outs RFP80:$dst), (ins RFP80:$src1, f64mem:$src2), OneArgFPRW,
215 (OpNode RFP80:$src1, (f80 (extloadf64 addr:$src2))))]>;
216 def _F32m : FPI<0xD8, fp, (outs), (ins f32mem:$src),
217 !strconcat("f", !strconcat(asmstring, "{s}\t$src"))> { let mayLoad = 1; }
218 def _F64m : FPI<0xDC, fp, (outs), (ins f64mem:$src),
219 !strconcat("f", !strconcat(asmstring, "{l}\t$src"))> { let mayLoad = 1; }
220 // ST(0) = ST(0) + [memint]
221 def _FpI16m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i16mem:$src2), OneArgFPRW,
222 [(set RFP32:$dst, (OpNode RFP32:$src1,
223 (X86fild addr:$src2, i16)))]>;
224 def _FpI32m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i32mem:$src2), OneArgFPRW,
225 [(set RFP32:$dst, (OpNode RFP32:$src1,
226 (X86fild addr:$src2, i32)))]>;
227 def _FpI16m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i16mem:$src2), OneArgFPRW,
228 [(set RFP64:$dst, (OpNode RFP64:$src1,
229 (X86fild addr:$src2, i16)))]>;
230 def _FpI32m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i32mem:$src2), OneArgFPRW,
231 [(set RFP64:$dst, (OpNode RFP64:$src1,
232 (X86fild addr:$src2, i32)))]>;
233 def _FpI16m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i16mem:$src2), OneArgFPRW,
234 [(set RFP80:$dst, (OpNode RFP80:$src1,
235 (X86fild addr:$src2, i16)))]>;
236 def _FpI32m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i32mem:$src2), OneArgFPRW,
237 [(set RFP80:$dst, (OpNode RFP80:$src1,
238 (X86fild addr:$src2, i32)))]>;
239 def _FI16m : FPI<0xDE, fp, (outs), (ins i16mem:$src),
240 !strconcat("fi", !strconcat(asmstring, "{s}\t$src"))> { let mayLoad = 1; }
241 def _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src),
242 !strconcat("fi", !strconcat(asmstring, "{l}\t$src"))> { let mayLoad = 1; }
245 defm ADD : FPBinary_rr<fadd>;
246 defm SUB : FPBinary_rr<fsub>;
247 defm MUL : FPBinary_rr<fmul>;
248 defm DIV : FPBinary_rr<fdiv>;
249 defm ADD : FPBinary<fadd, MRM0m, "add">;
250 defm SUB : FPBinary<fsub, MRM4m, "sub">;
251 defm SUBR: FPBinary<fsub ,MRM5m, "subr">;
252 defm MUL : FPBinary<fmul, MRM1m, "mul">;
253 defm DIV : FPBinary<fdiv, MRM6m, "div">;
254 defm DIVR: FPBinary<fdiv, MRM7m, "divr">;
256 class FPST0rInst<bits<8> o, string asm>
257 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, D8;
258 class FPrST0Inst<bits<8> o, string asm>
259 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, DC;
260 class FPrST0PInst<bits<8> o, string asm>
261 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, DE;
263 // NOTE: GAS and apparently all other AT&T style assemblers have a broken notion
264 // of some of the 'reverse' forms of the fsub and fdiv instructions. As such,
265 // we have to put some 'r's in and take them out of weird places.
266 def ADD_FST0r : FPST0rInst <0xC0, "fadd\t$op">;
267 def ADD_FrST0 : FPrST0Inst <0xC0, "fadd\t{%st(0), $op|$op, %ST(0)}">;
268 def ADD_FPrST0 : FPrST0PInst<0xC0, "faddp\t$op">;
269 def SUBR_FST0r : FPST0rInst <0xE8, "fsubr\t$op">;
270 def SUB_FrST0 : FPrST0Inst <0xE8, "fsub{r}\t{%st(0), $op|$op, %ST(0)}">;
271 def SUB_FPrST0 : FPrST0PInst<0xE8, "fsub{r}p\t$op">;
272 def SUB_FST0r : FPST0rInst <0xE0, "fsub\t$op">;
273 def SUBR_FrST0 : FPrST0Inst <0xE0, "fsub{|r}\t{%st(0), $op|$op, %ST(0)}">;
274 def SUBR_FPrST0 : FPrST0PInst<0xE0, "fsub{|r}p\t$op">;
275 def MUL_FST0r : FPST0rInst <0xC8, "fmul\t$op">;
276 def MUL_FrST0 : FPrST0Inst <0xC8, "fmul\t{%st(0), $op|$op, %ST(0)}">;
277 def MUL_FPrST0 : FPrST0PInst<0xC8, "fmulp\t$op">;
278 def DIVR_FST0r : FPST0rInst <0xF8, "fdivr\t$op">;
279 def DIV_FrST0 : FPrST0Inst <0xF8, "fdiv{r}\t{%st(0), $op|$op, %ST(0)}">;
280 def DIV_FPrST0 : FPrST0PInst<0xF8, "fdiv{r}p\t$op">;
281 def DIV_FST0r : FPST0rInst <0xF0, "fdiv\t$op">;
282 def DIVR_FrST0 : FPrST0Inst <0xF0, "fdiv{|r}\t{%st(0), $op|$op, %ST(0)}">;
283 def DIVR_FPrST0 : FPrST0PInst<0xF0, "fdiv{|r}p\t$op">;
286 multiclass FPUnary<SDNode OpNode, bits<8> opcode, string asmstring> {
287 def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), OneArgFPRW,
288 [(set RFP32:$dst, (OpNode RFP32:$src))]>;
289 def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), OneArgFPRW,
290 [(set RFP64:$dst, (OpNode RFP64:$src))]>;
291 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), OneArgFPRW,
292 [(set RFP80:$dst, (OpNode RFP80:$src))]>;
293 def _F : FPI<opcode, RawFrm, (outs), (ins), asmstring>, D9;
296 defm CHS : FPUnary<fneg, 0xE0, "fchs">;
297 defm ABS : FPUnary<fabs, 0xE1, "fabs">;
298 defm SQRT: FPUnary<fsqrt,0xFA, "fsqrt">;
299 defm SIN : FPUnary<fsin, 0xFE, "fsin">;
300 defm COS : FPUnary<fcos, 0xFF, "fcos">;
302 let neverHasSideEffects = 1 in {
303 def TST_Fp32 : FpIf32<(outs), (ins RFP32:$src), OneArgFP, []>;
304 def TST_Fp64 : FpIf64<(outs), (ins RFP64:$src), OneArgFP, []>;
305 def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>;
307 def TST_F : FPI<0xE4, RawFrm, (outs), (ins), "ftst">, D9;
309 // Floating point cmovs.
310 multiclass FPCMov<PatLeaf cc> {
311 def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2),
313 [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2,
315 def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2),
317 [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2,
319 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2),
321 [(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2,
324 let Uses = [EFLAGS], isTwoAddress = 1 in {
325 defm CMOVB : FPCMov<X86_COND_B>;
326 defm CMOVBE : FPCMov<X86_COND_BE>;
327 defm CMOVE : FPCMov<X86_COND_E>;
328 defm CMOVP : FPCMov<X86_COND_P>;
329 defm CMOVNB : FPCMov<X86_COND_AE>;
330 defm CMOVNBE: FPCMov<X86_COND_A>;
331 defm CMOVNE : FPCMov<X86_COND_NE>;
332 defm CMOVNP : FPCMov<X86_COND_NP>;
335 // These are not factored because there's no clean way to pass DA/DB.
336 def CMOVB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
337 "fcmovb\t{$op, %st(0)|%ST(0), $op}">, DA;
338 def CMOVBE_F : FPI<0xD0, AddRegFrm, (outs RST:$op), (ins),
339 "fcmovbe\t{$op, %st(0)|%ST(0), $op}">, DA;
340 def CMOVE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins),
341 "fcmove\t{$op, %st(0)|%ST(0), $op}">, DA;
342 def CMOVP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
343 "fcmovu\t {$op, %st(0)|%ST(0), $op}">, DA;
344 def CMOVNB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
345 "fcmovnb\t{$op, %st(0)|%ST(0), $op}">, DB;
346 def CMOVNBE_F: FPI<0xD0, AddRegFrm, (outs RST:$op), (ins),
347 "fcmovnbe\t{$op, %st(0)|%ST(0), $op}">, DB;
348 def CMOVNE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins),
349 "fcmovne\t{$op, %st(0)|%ST(0), $op}">, DB;
350 def CMOVNP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
351 "fcmovnu\t{$op, %st(0)|%ST(0), $op}">, DB;
353 // Floating point loads & stores.
354 let isSimpleLoad = 1 in {
355 def LD_Fp32m : FpIf32<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP,
356 [(set RFP32:$dst, (loadf32 addr:$src))]>;
357 let isReMaterializable = 1, mayHaveSideEffects = 1 in
358 def LD_Fp64m : FpIf64<(outs RFP64:$dst), (ins f64mem:$src), ZeroArgFP,
359 [(set RFP64:$dst, (loadf64 addr:$src))]>;
360 def LD_Fp80m : FpI_<(outs RFP80:$dst), (ins f80mem:$src), ZeroArgFP,
361 [(set RFP80:$dst, (loadf80 addr:$src))]>;
363 def LD_Fp32m64 : FpIf64<(outs RFP64:$dst), (ins f32mem:$src), ZeroArgFP,
364 [(set RFP64:$dst, (f64 (extloadf32 addr:$src)))]>;
365 def LD_Fp64m80 : FpI_<(outs RFP80:$dst), (ins f64mem:$src), ZeroArgFP,
366 [(set RFP80:$dst, (f80 (extloadf64 addr:$src)))]>;
367 def LD_Fp32m80 : FpI_<(outs RFP80:$dst), (ins f32mem:$src), ZeroArgFP,
368 [(set RFP80:$dst, (f80 (extloadf32 addr:$src)))]>;
369 def ILD_Fp16m32: FpIf32<(outs RFP32:$dst), (ins i16mem:$src), ZeroArgFP,
370 [(set RFP32:$dst, (X86fild addr:$src, i16))]>;
371 def ILD_Fp32m32: FpIf32<(outs RFP32:$dst), (ins i32mem:$src), ZeroArgFP,
372 [(set RFP32:$dst, (X86fild addr:$src, i32))]>;
373 def ILD_Fp64m32: FpIf32<(outs RFP32:$dst), (ins i64mem:$src), ZeroArgFP,
374 [(set RFP32:$dst, (X86fild addr:$src, i64))]>;
375 def ILD_Fp16m64: FpIf64<(outs RFP64:$dst), (ins i16mem:$src), ZeroArgFP,
376 [(set RFP64:$dst, (X86fild addr:$src, i16))]>;
377 def ILD_Fp32m64: FpIf64<(outs RFP64:$dst), (ins i32mem:$src), ZeroArgFP,
378 [(set RFP64:$dst, (X86fild addr:$src, i32))]>;
379 def ILD_Fp64m64: FpIf64<(outs RFP64:$dst), (ins i64mem:$src), ZeroArgFP,
380 [(set RFP64:$dst, (X86fild addr:$src, i64))]>;
381 def ILD_Fp16m80: FpI_<(outs RFP80:$dst), (ins i16mem:$src), ZeroArgFP,
382 [(set RFP80:$dst, (X86fild addr:$src, i16))]>;
383 def ILD_Fp32m80: FpI_<(outs RFP80:$dst), (ins i32mem:$src), ZeroArgFP,
384 [(set RFP80:$dst, (X86fild addr:$src, i32))]>;
385 def ILD_Fp64m80: FpI_<(outs RFP80:$dst), (ins i64mem:$src), ZeroArgFP,
386 [(set RFP80:$dst, (X86fild addr:$src, i64))]>;
388 def ST_Fp32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP,
389 [(store RFP32:$src, addr:$op)]>;
390 def ST_Fp64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP,
391 [(truncstoref32 RFP64:$src, addr:$op)]>;
392 def ST_Fp64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP,
393 [(store RFP64:$src, addr:$op)]>;
394 def ST_Fp80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP,
395 [(truncstoref32 RFP80:$src, addr:$op)]>;
396 def ST_Fp80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP,
397 [(truncstoref64 RFP80:$src, addr:$op)]>;
398 // FST does not support 80-bit memory target; FSTP must be used.
400 let mayStore = 1, neverHasSideEffects = 1 in {
401 def ST_FpP32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, []>;
402 def ST_FpP64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, []>;
403 def ST_FpP64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, []>;
404 def ST_FpP80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, []>;
405 def ST_FpP80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, []>;
407 def ST_FpP80m : FpI_<(outs), (ins f80mem:$op, RFP80:$src), OneArgFP,
408 [(store RFP80:$src, addr:$op)]>;
409 let mayStore = 1, neverHasSideEffects = 1 in {
410 def IST_Fp16m32 : FpIf32<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, []>;
411 def IST_Fp32m32 : FpIf32<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, []>;
412 def IST_Fp64m32 : FpIf32<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, []>;
413 def IST_Fp16m64 : FpIf64<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, []>;
414 def IST_Fp32m64 : FpIf64<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, []>;
415 def IST_Fp64m64 : FpIf64<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, []>;
416 def IST_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, []>;
417 def IST_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, []>;
418 def IST_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, []>;
422 def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src">;
423 def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src">;
424 def LD_F80m : FPI<0xDB, MRM5m, (outs), (ins f80mem:$src), "fld{t}\t$src">;
425 def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src">;
426 def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src">;
427 def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src">;
429 let mayStore = 1 in {
430 def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst">;
431 def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst">;
432 def ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s}\t$dst">;
433 def ST_FP64m : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l}\t$dst">;
434 def ST_FP80m : FPI<0xDB, MRM7m, (outs), (ins f80mem:$dst), "fstp{t}\t$dst">;
435 def IST_F16m : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s}\t$dst">;
436 def IST_F32m : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l}\t$dst">;
437 def IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s}\t$dst">;
438 def IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l}\t$dst">;
439 def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst">;
442 // FISTTP requires SSE3 even though it's a FPStack op.
443 def ISTT_Fp16m32 : FpI_<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP,
444 [(X86fp_to_i16mem RFP32:$src, addr:$op)]>,
446 def ISTT_Fp32m32 : FpI_<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP,
447 [(X86fp_to_i32mem RFP32:$src, addr:$op)]>,
449 def ISTT_Fp64m32 : FpI_<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP,
450 [(X86fp_to_i64mem RFP32:$src, addr:$op)]>,
452 def ISTT_Fp16m64 : FpI_<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP,
453 [(X86fp_to_i16mem RFP64:$src, addr:$op)]>,
455 def ISTT_Fp32m64 : FpI_<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP,
456 [(X86fp_to_i32mem RFP64:$src, addr:$op)]>,
458 def ISTT_Fp64m64 : FpI_<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP,
459 [(X86fp_to_i64mem RFP64:$src, addr:$op)]>,
461 def ISTT_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP,
462 [(X86fp_to_i16mem RFP80:$src, addr:$op)]>,
464 def ISTT_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP,
465 [(X86fp_to_i32mem RFP80:$src, addr:$op)]>,
467 def ISTT_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP,
468 [(X86fp_to_i64mem RFP80:$src, addr:$op)]>,
471 let mayStore = 1 in {
472 def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst">;
473 def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst">;
474 def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), "fisttp{ll}\t$dst">;
477 // FP Stack manipulation instructions.
478 def LD_Frr : FPI<0xC0, AddRegFrm, (outs), (ins RST:$op), "fld\t$op">, D9;
479 def ST_Frr : FPI<0xD0, AddRegFrm, (outs), (ins RST:$op), "fst\t$op">, DD;
480 def ST_FPrr : FPI<0xD8, AddRegFrm, (outs), (ins RST:$op), "fstp\t$op">, DD;
481 def XCH_F : FPI<0xC8, AddRegFrm, (outs), (ins RST:$op), "fxch\t$op">, D9;
483 // Floating point constant loads.
484 let isReMaterializable = 1 in {
485 def LD_Fp032 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP,
486 [(set RFP32:$dst, fpimm0)]>;
487 def LD_Fp132 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP,
488 [(set RFP32:$dst, fpimm1)]>;
489 def LD_Fp064 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP,
490 [(set RFP64:$dst, fpimm0)]>;
491 def LD_Fp164 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP,
492 [(set RFP64:$dst, fpimm1)]>;
493 def LD_Fp080 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP,
494 [(set RFP80:$dst, fpimm0)]>;
495 def LD_Fp180 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP,
496 [(set RFP80:$dst, fpimm1)]>;
499 def LD_F0 : FPI<0xEE, RawFrm, (outs), (ins), "fldz">, D9;
500 def LD_F1 : FPI<0xE8, RawFrm, (outs), (ins), "fld1">, D9;
503 // Floating point compares.
504 let Defs = [EFLAGS] in {
505 def UCOM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
506 []>; // FPSW = cmp ST(0) with ST(i)
507 def UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
508 []>; // FPSW = cmp ST(0) with ST(i)
509 def UCOM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
510 []>; // FPSW = cmp ST(0) with ST(i)
512 def UCOM_FpIr32: FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
513 [(X86cmp RFP32:$lhs, RFP32:$rhs),
514 (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
515 def UCOM_FpIr64: FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
516 [(X86cmp RFP64:$lhs, RFP64:$rhs),
517 (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
518 def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
519 [(X86cmp RFP80:$lhs, RFP80:$rhs),
520 (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
523 let Defs = [EFLAGS], Uses = [ST0] in {
524 def UCOM_Fr : FPI<0xE0, AddRegFrm, // FPSW = cmp ST(0) with ST(i)
525 (outs), (ins RST:$reg),
527 def UCOM_FPr : FPI<0xE8, AddRegFrm, // FPSW = cmp ST(0) with ST(i), pop
528 (outs), (ins RST:$reg),
530 def UCOM_FPPr : FPI<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop
534 def UCOM_FIr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i)
535 (outs), (ins RST:$reg),
536 "fucomi\t{$reg, %st(0)|%ST(0), $reg}">, DB;
537 def UCOM_FIPr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop
538 (outs), (ins RST:$reg),
539 "fucomip\t{$reg, %st(0)|%ST(0), $reg}">, DF;
542 // Floating point flag ops.
544 def FNSTSW8r : I<0xE0, RawFrm, // AX = fp flags
545 (outs), (ins), "fnstsw", []>, DF;
547 def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world
548 (outs), (ins i16mem:$dst), "fnstcw\t$dst",
549 [(X86fp_cwd_get16 addr:$dst)]>;
552 def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
553 (outs), (ins i16mem:$dst), "fldcw\t$dst", []>;
555 //===----------------------------------------------------------------------===//
556 // Non-Instruction Patterns
557 //===----------------------------------------------------------------------===//
559 // Required for RET of f32 / f64 / f80 values.
560 def : Pat<(X86fld addr:$src, f32), (LD_Fp32m addr:$src)>;
561 def : Pat<(X86fld addr:$src, f64), (LD_Fp64m addr:$src)>;
562 def : Pat<(X86fld addr:$src, f80), (LD_Fp80m addr:$src)>;
564 // Required for CALL which return f32 / f64 / f80 values.
565 def : Pat<(X86fst RFP32:$src, addr:$op, f32), (ST_Fp32m addr:$op, RFP32:$src)>;
566 def : Pat<(X86fst RFP64:$src, addr:$op, f32), (ST_Fp64m32 addr:$op, RFP64:$src)>;
567 def : Pat<(X86fst RFP64:$src, addr:$op, f64), (ST_Fp64m addr:$op, RFP64:$src)>;
568 def : Pat<(X86fst RFP80:$src, addr:$op, f32), (ST_Fp80m32 addr:$op, RFP80:$src)>;
569 def : Pat<(X86fst RFP80:$src, addr:$op, f64), (ST_Fp80m64 addr:$op, RFP80:$src)>;
570 def : Pat<(X86fst RFP80:$src, addr:$op, f80), (ST_FpP80m addr:$op, RFP80:$src)>;
572 // Floating point constant -0.0 and -1.0
573 def : Pat<(f32 fpimmneg0), (CHS_Fp32 (LD_Fp032))>, Requires<[FPStackf32]>;
574 def : Pat<(f32 fpimmneg1), (CHS_Fp32 (LD_Fp132))>, Requires<[FPStackf32]>;
575 def : Pat<(f64 fpimmneg0), (CHS_Fp64 (LD_Fp064))>, Requires<[FPStackf64]>;
576 def : Pat<(f64 fpimmneg1), (CHS_Fp64 (LD_Fp164))>, Requires<[FPStackf64]>;
577 def : Pat<(f80 fpimmneg0), (CHS_Fp80 (LD_Fp080))>;
578 def : Pat<(f80 fpimmneg1), (CHS_Fp80 (LD_Fp180))>;
580 // Used to conv. i64 to f64 since there isn't a SSE version.
581 def : Pat<(X86fildflag addr:$src, i64), (ILD_Fp64m64 addr:$src)>;
583 // FP extensions map onto simple pseudo-value conversions if they are to/from
585 def : Pat<(f64 (fextend RFP32:$src)), (MOV_Fp3264 RFP32:$src)>,
586 Requires<[FPStackf32]>;
587 def : Pat<(f80 (fextend RFP32:$src)), (MOV_Fp3280 RFP32:$src)>,
588 Requires<[FPStackf32]>;
589 def : Pat<(f80 (fextend RFP64:$src)), (MOV_Fp6480 RFP64:$src)>,
590 Requires<[FPStackf64]>;
592 // FP truncations map onto simple pseudo-value conversions if they are to/from
593 // the FP stack. We have validated that only value-preserving truncations make
595 def : Pat<(f32 (fround RFP64:$src)), (MOV_Fp6432 RFP64:$src)>,
596 Requires<[FPStackf32]>;
597 def : Pat<(f32 (fround RFP80:$src)), (MOV_Fp8032 RFP80:$src)>,
598 Requires<[FPStackf32]>;
599 def : Pat<(f64 (fround RFP80:$src)), (MOV_Fp8064 RFP80:$src)>,
600 Requires<[FPStackf64]>;