1 //====- X86InstrFMA.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes FMA (Fused Multiply-Add) instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // FMA3 - Intel 3 operand Fused Multiply-Add instructions
16 //===----------------------------------------------------------------------===//
18 multiclass fma3p_rm<bits<8> opc, string OpcodeStr> {
19 def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
20 (ins VR128:$src1, VR128:$src2),
21 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
23 def m : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
24 (ins VR128:$src1, f128mem:$src2),
25 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
27 def rY : FMA3<opc, MRMSrcReg, (outs VR256:$dst),
28 (ins VR256:$src1, VR256:$src2),
29 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
31 def mY : FMA3<opc, MRMSrcMem, (outs VR256:$dst),
32 (ins VR256:$src1, f256mem:$src2),
33 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
37 multiclass fma3p_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
38 string OpcodeStr, string PackTy> {
39 defm r132 : fma3p_rm<opc132, !strconcat(OpcodeStr, !strconcat("132", PackTy))>;
40 defm r213 : fma3p_rm<opc213, !strconcat(OpcodeStr, !strconcat("213", PackTy))>;
41 defm r231 : fma3p_rm<opc231, !strconcat(OpcodeStr, !strconcat("231", PackTy))>;
45 let ExeDomain = SSEPackedSingle in {
46 defm VFMADDPS : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "ps">;
47 defm VFMSUBPS : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "ps">;
48 defm VFMADDSUBPS : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "ps">;
49 defm VFMSUBADDPS : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "ps">;
52 let ExeDomain = SSEPackedDouble in {
53 defm VFMADDPD : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "pd">, VEX_W;
54 defm VFMSUBPD : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "pd">, VEX_W;
55 defm VFMADDSUBPD : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "pd">, VEX_W;
56 defm VFMSUBADDPD : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "pd">, VEX_W;
59 // Fused Negative Multiply-Add
60 let ExeDomain = SSEPackedSingle in {
61 defm VFNMADDPS : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "ps">;
62 defm VFNMSUBPS : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "ps">;
64 let ExeDomain = SSEPackedDouble in {
65 defm VFNMADDPD : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "pd">, VEX_W;
66 defm VFNMSUBPD : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "pd">, VEX_W;
69 multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand x86memop> {
70 def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
71 (ins VR128:$src1, VR128:$src2),
72 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
74 def m : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
75 (ins VR128:$src1, x86memop:$src2),
76 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
80 multiclass fma3s_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
82 defm SSr132 : fma3s_rm<opc132, !strconcat(OpcodeStr, "132ss"), f32mem>;
83 defm SSr213 : fma3s_rm<opc213, !strconcat(OpcodeStr, "213ss"), f32mem>;
84 defm SSr231 : fma3s_rm<opc231, !strconcat(OpcodeStr, "231ss"), f32mem>;
85 defm SDr132 : fma3s_rm<opc132, !strconcat(OpcodeStr, "132sd"), f64mem>, VEX_W;
86 defm SDr213 : fma3s_rm<opc213, !strconcat(OpcodeStr, "213sd"), f64mem>, VEX_W;
87 defm SDr231 : fma3s_rm<opc231, !strconcat(OpcodeStr, "231sd"), f64mem>, VEX_W;
90 defm VFMADD : fma3s_forms<0x99, 0xA9, 0xB9, "vfmadd">;
91 defm VFMSUB : fma3s_forms<0x9B, 0xAB, 0xBB, "vfmsub">;
93 defm VFNMADD : fma3s_forms<0x9D, 0xAD, 0xBD, "vfnmadd">;
94 defm VFNMSUB : fma3s_forms<0x9F, 0xAF, 0xBF, "vfnmsub">;
96 //===----------------------------------------------------------------------===//
97 // FMA4 - AMD 4 operand Fused Multiply-Add instructions
98 //===----------------------------------------------------------------------===//
101 multiclass fma4s<bits<8> opc, string OpcodeStr, Operand memop> {
102 def rr : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
103 (ins VR128:$src1, VR128:$src2, VR128:$src3),
104 !strconcat(OpcodeStr,
105 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
107 def rm : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
108 (ins VR128:$src1, VR128:$src2, memop:$src3),
109 !strconcat(OpcodeStr,
110 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
112 def mr : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
113 (ins VR128:$src1, memop:$src2, VR128:$src3),
114 !strconcat(OpcodeStr,
115 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
119 multiclass fma4p<bits<8> opc, string OpcodeStr,
120 Intrinsic Int128, Intrinsic Int256,
121 PatFrag ld_frag128, PatFrag ld_frag256> {
122 def rr : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
123 (ins VR128:$src1, VR128:$src2, VR128:$src3),
124 !strconcat(OpcodeStr,
125 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
127 (Int128 VR128:$src1, VR128:$src2, VR128:$src3))]>, XOP_W;
128 def rm : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
129 (ins VR128:$src1, VR128:$src2, f128mem:$src3),
130 !strconcat(OpcodeStr,
131 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
132 [(set VR128:$dst, (Int128 VR128:$src1, VR128:$src2,
133 (ld_frag128 addr:$src3)))]>, XOP_W;
134 def mr : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
135 (ins VR128:$src1, f128mem:$src2, VR128:$src3),
136 !strconcat(OpcodeStr,
137 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
139 (Int128 VR128:$src1, (ld_frag128 addr:$src2), VR128:$src3))]>;
140 def rrY : FMA4<opc, MRMSrcReg, (outs VR256:$dst),
141 (ins VR256:$src1, VR256:$src2, VR256:$src3),
142 !strconcat(OpcodeStr,
143 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
145 (Int256 VR256:$src1, VR256:$src2, VR256:$src3))]>, XOP_W;
146 def rmY : FMA4<opc, MRMSrcMem, (outs VR256:$dst),
147 (ins VR256:$src1, VR256:$src2, f256mem:$src3),
148 !strconcat(OpcodeStr,
149 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
150 [(set VR256:$dst, (Int256 VR256:$src1, VR256:$src2,
151 (ld_frag256 addr:$src3)))]>, XOP_W;
152 def mrY : FMA4<opc, MRMSrcMem, (outs VR256:$dst),
153 (ins VR256:$src1, f256mem:$src2, VR256:$src3),
154 !strconcat(OpcodeStr,
155 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
157 (Int256 VR256:$src1, (ld_frag256 addr:$src2), VR256:$src3))]>;
160 let isAsmParserOnly = 1 in {
161 defm VFMADDSS4 : fma4s<0x6A, "vfmaddss", ssmem>;
162 defm VFMADDSD4 : fma4s<0x6B, "vfmaddsd", sdmem>;
163 defm VFMADDPS4 : fma4p<0x68, "vfmaddps", int_x86_fma4_vfmadd_ps,
164 int_x86_fma4_vfmadd_ps_256, memopv4f32, memopv8f32>;
165 defm VFMADDPD4 : fma4p<0x69, "vfmaddpd", int_x86_fma4_vfmadd_pd,
166 int_x86_fma4_vfmadd_pd_256, memopv2f64, memopv4f64>;
167 defm VFMSUBSS4 : fma4s<0x6E, "vfmsubss", ssmem>;
168 defm VFMSUBSD4 : fma4s<0x6F, "vfmsubsd", sdmem>;
169 defm VFMSUBPS4 : fma4p<0x6C, "vfmsubps", int_x86_fma4_vfmsub_ps,
170 int_x86_fma4_vfmsub_ps_256, memopv4f32, memopv8f32>;
171 defm VFMSUBPD4 : fma4p<0x6D, "vfmsubpd", int_x86_fma4_vfmsub_pd,
172 int_x86_fma4_vfmsub_pd_256, memopv2f64, memopv4f64>;
173 defm VFNMADDSS4 : fma4s<0x7A, "vfnmaddss", ssmem>;
174 defm VFNMADDSD4 : fma4s<0x7B, "vfnmaddsd", sdmem>;
175 defm VFNMADDPS4 : fma4p<0x78, "vfnmaddps", int_x86_fma4_vfnmadd_ps,
176 int_x86_fma4_vfnmadd_ps_256, memopv4f32, memopv8f32>;
177 defm VFNMADDPD4 : fma4p<0x79, "vfnmaddpd", int_x86_fma4_vfnmadd_pd,
178 int_x86_fma4_vfnmadd_pd_256, memopv2f64, memopv4f64>;
179 defm VFNMSUBSS4 : fma4s<0x7E, "vfnmsubss", ssmem>;
180 defm VFNMSUBSD4 : fma4s<0x7F, "vfnmsubsd", sdmem>;
181 defm VFNMSUBPS4 : fma4p<0x7C, "vfnmsubps", int_x86_fma4_vfnmsub_ps,
182 int_x86_fma4_vfnmsub_ps_256, memopv4f32, memopv8f32>;
183 defm VFNMSUBPD4 : fma4p<0x7D, "vfnmsubpd", int_x86_fma4_vfnmsub_pd,
184 int_x86_fma4_vfnmsub_pd_256, memopv2f64, memopv4f64>;
185 defm VFMADDSUBPS4 : fma4p<0x5C, "vfmaddsubps", int_x86_fma4_vfmaddsub_ps,
186 int_x86_fma4_vfmaddsub_ps_256, memopv4f32, memopv8f32>;
187 defm VFMADDSUBPD4 : fma4p<0x5D, "vfmaddsubpd", int_x86_fma4_vfmaddsub_pd,
188 int_x86_fma4_vfmaddsub_pd_256, memopv2f64, memopv4f64>;
189 defm VFMSUBADDPS4 : fma4p<0x5E, "vfmsubaddps", int_x86_fma4_vfmsubadd_ps,
190 int_x86_fma4_vfmsubadd_ps_256, memopv4f32, memopv8f32>;
191 defm VFMSUBADDPD4 : fma4p<0x5F, "vfmsubaddpd", int_x86_fma4_vfmsubadd_pd,
192 int_x86_fma4_vfmsubadd_pd_256, memopv2f64, memopv4f64>;
195 // FMA4 Intrinsics patterns
197 let Predicates = [HasFMA4] in {
200 def : Pat<(int_x86_fma4_vfmadd_ss VR128:$src1, VR128:$src2, VR128:$src3),
201 (VFMADDSS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
202 def : Pat<(int_x86_fma4_vfmadd_ss VR128:$src1, VR128:$src2, sse_load_f32:$src3),
203 (VFMADDSS4rm VR128:$src1, VR128:$src2, sse_load_f32:$src3)>;
204 def : Pat<(int_x86_fma4_vfmadd_ss VR128:$src1, sse_load_f32:$src2, VR128:$src3),
205 (VFMADDSS4mr VR128:$src1, sse_load_f32:$src2, VR128:$src3)>;
207 def : Pat<(int_x86_fma4_vfmadd_sd VR128:$src1, VR128:$src2, VR128:$src3),
208 (VFMADDSD4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
209 def : Pat<(int_x86_fma4_vfmadd_sd VR128:$src1, VR128:$src2, sse_load_f64:$src3),
210 (VFMADDSD4rm VR128:$src1, VR128:$src2, sse_load_f64:$src3)>;
211 def : Pat<(int_x86_fma4_vfmadd_sd VR128:$src1, sse_load_f64:$src2, VR128:$src3),
212 (VFMADDSD4mr VR128:$src1, sse_load_f64:$src2, VR128:$src3)>;
215 def : Pat<(int_x86_fma4_vfmsub_ss VR128:$src1, VR128:$src2, VR128:$src3),
216 (VFMSUBSS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
217 def : Pat<(int_x86_fma4_vfmsub_ss VR128:$src1, VR128:$src2, sse_load_f32:$src3),
218 (VFMSUBSS4rm VR128:$src1, VR128:$src2, sse_load_f32:$src3)>;
219 def : Pat<(int_x86_fma4_vfmsub_ss VR128:$src1, sse_load_f32:$src2, VR128:$src3),
220 (VFMSUBSS4mr VR128:$src1, sse_load_f32:$src2, VR128:$src3)>;
222 def : Pat<(int_x86_fma4_vfmsub_sd VR128:$src1, VR128:$src2, VR128:$src3),
223 (VFMSUBSD4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
224 def : Pat<(int_x86_fma4_vfmsub_sd VR128:$src1, VR128:$src2, sse_load_f64:$src3),
225 (VFMSUBSD4rm VR128:$src1, VR128:$src2, sse_load_f64:$src3)>;
226 def : Pat<(int_x86_fma4_vfmsub_sd VR128:$src1, sse_load_f64:$src2, VR128:$src3),
227 (VFMSUBSD4mr VR128:$src1, sse_load_f64:$src2, VR128:$src3)>;
230 def : Pat<(int_x86_fma4_vfnmadd_ss VR128:$src1, VR128:$src2, VR128:$src3),
231 (VFNMADDSS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
232 def : Pat<(int_x86_fma4_vfnmadd_ss VR128:$src1, VR128:$src2, sse_load_f32:$src3),
233 (VFNMADDSS4rm VR128:$src1, VR128:$src2, sse_load_f32:$src3)>;
234 def : Pat<(int_x86_fma4_vfnmadd_ss VR128:$src1, sse_load_f32:$src2, VR128:$src3),
235 (VFNMADDSS4mr VR128:$src1, sse_load_f32:$src2, VR128:$src3)>;
237 def : Pat<(int_x86_fma4_vfnmadd_sd VR128:$src1, VR128:$src2, VR128:$src3),
238 (VFNMADDSD4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
239 def : Pat<(int_x86_fma4_vfnmadd_sd VR128:$src1, VR128:$src2, sse_load_f64:$src3),
240 (VFNMADDSD4rm VR128:$src1, VR128:$src2, sse_load_f64:$src3)>;
241 def : Pat<(int_x86_fma4_vfnmadd_sd VR128:$src1, sse_load_f64:$src2, VR128:$src3),
242 (VFNMADDSD4mr VR128:$src1, sse_load_f64:$src2, VR128:$src3)>;
245 def : Pat<(int_x86_fma4_vfnmsub_ss VR128:$src1, VR128:$src2, VR128:$src3),
246 (VFNMSUBSS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
247 def : Pat<(int_x86_fma4_vfnmsub_ss VR128:$src1, VR128:$src2, sse_load_f32:$src3),
248 (VFNMSUBSS4rm VR128:$src1, VR128:$src2, sse_load_f32:$src3)>;
249 def : Pat<(int_x86_fma4_vfnmsub_ss VR128:$src1, sse_load_f32:$src2, VR128:$src3),
250 (VFNMSUBSS4mr VR128:$src1, sse_load_f32:$src2, VR128:$src3)>;
252 def : Pat<(int_x86_fma4_vfnmsub_sd VR128:$src1, VR128:$src2, VR128:$src3),
253 (VFNMSUBSD4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
254 def : Pat<(int_x86_fma4_vfnmsub_sd VR128:$src1, VR128:$src2, sse_load_f64:$src3),
255 (VFNMSUBSD4rm VR128:$src1, VR128:$src2, sse_load_f64:$src3)>;
256 def : Pat<(int_x86_fma4_vfnmsub_sd VR128:$src1, sse_load_f64:$src2, VR128:$src3),
257 (VFNMSUBSD4mr VR128:$src1, sse_load_f64:$src2, VR128:$src3)>;
260 def : Pat<(int_x86_fma4_vfmaddsub_ps VR128:$src1, (memopv4f32 addr:$src2),
262 (VFMADDSUBPS4mr VR128:$src1, addr:$src2, VR128:$src3)>;
264 def : Pat<(int_x86_fma4_vfmaddsub_pd VR128:$src1, (memopv2f64 addr:$src2),
266 (VFMADDSUBPD4mr VR128:$src1, addr:$src2, VR128:$src3)>;
270 def : Pat<(int_x86_fma4_vfmsubadd_ps VR128:$src1, (memopv4f32 addr:$src2),
272 (VFMSUBADDPS4mr VR128:$src1, addr:$src2, VR128:$src3)>;
274 def : Pat<(int_x86_fma4_vfmsubadd_pd VR128:$src1, (memopv2f64 addr:$src2),
276 (VFMSUBADDPD4mr VR128:$src1, addr:$src2, VR128:$src3)>;
278 } // Predicates = [HasFMA4]