1 //===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the various pseudo instructions used by the compiler,
11 // as well as Pat patterns used during instruction selection.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Pattern Matching Support
18 def GetLo32XForm : SDNodeXForm<imm, [{
19 // Transformation function: get the low 32 bits.
20 return getI32Imm((unsigned)N->getZExtValue());
23 def GetLo8XForm : SDNodeXForm<imm, [{
24 // Transformation function: get the low 8 bits.
25 return getI8Imm((uint8_t)N->getZExtValue());
29 //===----------------------------------------------------------------------===//
30 // Random Pseudo Instructions.
32 // PIC base construction. This expands to code that looks like this:
35 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
36 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
40 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
41 // a stack adjustment and the codegen must know that they may modify the stack
42 // pointer before prolog-epilog rewriting occurs.
43 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
44 // sub / add which can clobber EFLAGS.
45 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
46 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
48 [(X86callseq_start timm:$amt)]>,
49 Requires<[In32BitMode]>;
50 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
52 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
53 Requires<[In32BitMode]>;
56 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
57 // a stack adjustment and the codegen must know that they may modify the stack
58 // pointer before prolog-epilog rewriting occurs.
59 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
60 // sub / add which can clobber EFLAGS.
61 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
62 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
64 [(X86callseq_start timm:$amt)]>,
65 Requires<[In64BitMode]>;
66 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
68 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
69 Requires<[In64BitMode]>;
74 // x86-64 va_start lowering magic.
75 let usesCustomInserter = 1 in {
76 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
79 i64imm:$regsavefi, i64imm:$offset,
81 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
82 [(X86vastart_save_xmm_regs GR8:$al,
86 // The VAARG_64 pseudo-instruction takes the address of the va_list,
87 // and places the address of the next argument into a register.
88 let Defs = [EFLAGS] in
89 def VAARG_64 : I<0, Pseudo,
91 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align),
92 "#VAARG_64 $dst, $ap, $size, $mode, $align",
94 (X86vaarg64 addr:$ap, imm:$size, imm:$mode, imm:$align)),
97 // Dynamic stack allocation yields a _chkstk or _alloca call for all Windows
98 // targets. These calls are needed to probe the stack when allocating more than
99 // 4k bytes in one go. Touching the stack at 4K increments is necessary to
100 // ensure that the guard pages used by the OS virtual memory manager are
101 // allocated in correct sequence.
102 // The main point of having separate instruction are extra unmodelled effects
103 // (compared to ordinary calls) like stack pointer change.
105 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
106 def WIN_ALLOCA : I<0, Pseudo, (outs), (ins),
107 "# dynamic stack allocation",
113 //===----------------------------------------------------------------------===//
114 // EH Pseudo Instructions
116 let isTerminator = 1, isReturn = 1, isBarrier = 1,
117 hasCtrlDep = 1, isCodeGenOnly = 1 in {
118 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
119 "ret\t#eh_return, addr: $addr",
120 [(X86ehret GR32:$addr)]>;
124 let isTerminator = 1, isReturn = 1, isBarrier = 1,
125 hasCtrlDep = 1, isCodeGenOnly = 1 in {
126 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
127 "ret\t#eh_return, addr: $addr",
128 [(X86ehret GR64:$addr)]>;
132 //===----------------------------------------------------------------------===//
133 // Alias Instructions
134 //===----------------------------------------------------------------------===//
136 // Alias instructions that map movr0 to xor.
137 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
138 // FIXME: Set encoding to pseudo.
139 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
140 isCodeGenOnly = 1 in {
141 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "",
142 [(set GR8:$dst, 0)]>;
144 // We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller
145 // encoding and avoids a partial-register update sometimes, but doing so
146 // at isel time interferes with rematerialization in the current register
147 // allocator. For now, this is rewritten when the instruction is lowered
149 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
151 [(set GR16:$dst, 0)]>, OpSize;
153 // FIXME: Set encoding to pseudo.
154 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "",
155 [(set GR32:$dst, 0)]>;
158 // We want to rewrite MOV64r0 in terms of MOV32r0, because it's sometimes a
159 // smaller encoding, but doing so at isel time interferes with rematerialization
160 // in the current register allocator. For now, this is rewritten when the
161 // instruction is lowered to an MCInst.
162 // FIXME: AddedComplexity gives this a higher priority than MOV64ri32. Remove
163 // when we have a better way to specify isel priority.
164 let Defs = [EFLAGS], isCodeGenOnly=1,
165 AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
166 def MOV64r0 : I<0x31, MRMInitReg, (outs GR64:$dst), (ins), "",
167 [(set GR64:$dst, 0)]>;
169 // Materialize i64 constant where top 32-bits are zero. This could theoretically
170 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
171 // that would make it more difficult to rematerialize.
172 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1,
174 def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
175 "", [(set GR64:$dst, i64immZExt32:$src)]>;
177 // Use sbb to materialize carry bit.
178 let Uses = [EFLAGS], Defs = [EFLAGS], isCodeGenOnly = 1 in {
179 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
180 // However, Pat<> can't replicate the destination reg into the inputs of the
182 // FIXME: Change these to have encoding Pseudo when X86MCCodeEmitter replaces
184 def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins), "",
185 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
186 def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins), "",
187 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>,
189 def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins), "",
190 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
191 def SETB_C64r : RI<0x19, MRMInitReg, (outs GR64:$dst), (ins), "",
192 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
196 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
198 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
200 def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
203 def : Pat<(i16 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
205 def : Pat<(i32 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
207 def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
210 // We canonicalize 'setb' to "(and (sbb reg,reg), 1)" on the hope that the and
211 // will be eliminated and that the sbb can be extended up to a wider type. When
212 // this happens, it is great. However, if we are left with an 8-bit sbb and an
213 // and, we might as well just match it as a setb.
214 def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1),
217 // (add OP, SETB) -> (adc OP, 0)
218 def : Pat<(add (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR8:$op),
219 (ADC8ri GR8:$op, 0)>;
220 def : Pat<(add (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR32:$op),
221 (ADC32ri8 GR32:$op, 0)>;
222 def : Pat<(add (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR64:$op),
223 (ADC64ri8 GR64:$op, 0)>;
225 // (sub OP, SETB) -> (sbb OP, 0)
226 def : Pat<(sub GR8:$op, (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
227 (SBB8ri GR8:$op, 0)>;
228 def : Pat<(sub GR32:$op, (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
229 (SBB32ri8 GR32:$op, 0)>;
230 def : Pat<(sub GR64:$op, (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
231 (SBB64ri8 GR64:$op, 0)>;
233 // (sub OP, SETCC_CARRY) -> (adc OP, 0)
234 def : Pat<(sub GR8:$op, (i8 (X86setcc_c X86_COND_B, EFLAGS))),
235 (ADC8ri GR8:$op, 0)>;
236 def : Pat<(sub GR32:$op, (i32 (X86setcc_c X86_COND_B, EFLAGS))),
237 (ADC32ri8 GR32:$op, 0)>;
238 def : Pat<(sub GR64:$op, (i64 (X86setcc_c X86_COND_B, EFLAGS))),
239 (ADC64ri8 GR64:$op, 0)>;
241 //===----------------------------------------------------------------------===//
242 // String Pseudo Instructions
244 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
245 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
246 [(X86rep_movs i8)]>, REP;
247 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
248 [(X86rep_movs i16)]>, REP, OpSize;
249 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
250 [(X86rep_movs i32)]>, REP;
253 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in
254 def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
255 [(X86rep_movs i64)]>, REP;
258 // FIXME: Should use "(X86rep_stos AL)" as the pattern.
259 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI], isCodeGenOnly = 1 in
260 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
261 [(X86rep_stos i8)]>, REP;
262 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI], isCodeGenOnly = 1 in
263 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
264 [(X86rep_stos i16)]>, REP, OpSize;
265 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI], isCodeGenOnly = 1 in
266 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
267 [(X86rep_stos i32)]>, REP;
269 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI], isCodeGenOnly = 1 in
270 def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
271 [(X86rep_stos i64)]>, REP;
274 //===----------------------------------------------------------------------===//
275 // Thread Local Storage Instructions
279 // All calls clobber the non-callee saved registers. ESP is marked as
280 // a use to prevent stack-pointer assignments that appear immediately
281 // before calls from potentially appearing dead.
282 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
283 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
284 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
285 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
287 def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
289 [(X86tlsaddr tls32addr:$sym)]>,
290 Requires<[In32BitMode]>;
292 // All calls clobber the non-callee saved registers. RSP is marked as
293 // a use to prevent stack-pointer assignments that appear immediately
294 // before calls from potentially appearing dead.
295 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
296 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
297 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
298 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
299 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
301 def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
303 [(X86tlsaddr tls64addr:$sym)]>,
304 Requires<[In64BitMode]>;
306 // Darwin TLS Support
307 // For i386, the address of the thunk is passed on the stack, on return the
308 // address of the variable is in %eax. %ecx is trashed during the function
309 // call. All other registers are preserved.
310 let Defs = [EAX, ECX, EFLAGS],
312 usesCustomInserter = 1 in
313 def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
315 [(X86TLSCall addr:$sym)]>,
316 Requires<[In32BitMode]>;
318 // For x86_64, the address of the thunk is passed in %rdi, on return
319 // the address of the variable is in %rax. All other registers are preserved.
320 let Defs = [RAX, EFLAGS],
322 usesCustomInserter = 1 in
323 def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
325 [(X86TLSCall addr:$sym)]>,
326 Requires<[In64BitMode]>;
329 //===----------------------------------------------------------------------===//
330 // Conditional Move Pseudo Instructions
332 let Constraints = "$src1 = $dst" in {
335 let Uses = [EFLAGS] in {
337 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
338 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
339 // however that requires promoting the operands, and can induce additional
340 // i8 register pressure. Note that CMOV_GR8 is conservatively considered to
341 // clobber EFLAGS, because if one of the operands is zero, the expansion
342 // could involve an xor.
343 let usesCustomInserter = 1, Constraints = "", Defs = [EFLAGS] in {
344 def CMOV_GR8 : I<0, Pseudo,
345 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
347 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
348 imm:$cond, EFLAGS))]>;
350 let Predicates = [NoCMov] in {
351 def CMOV_GR32 : I<0, Pseudo,
352 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cond),
353 "#CMOV_GR32* PSEUDO!",
355 (X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>;
356 def CMOV_GR16 : I<0, Pseudo,
357 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cond),
358 "#CMOV_GR16* PSEUDO!",
360 (X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>;
361 def CMOV_RFP32 : I<0, Pseudo,
363 (ins RFP32:$src1, RFP32:$src2, i8imm:$cond),
364 "#CMOV_RFP32 PSEUDO!",
366 (X86cmov RFP32:$src1, RFP32:$src2, imm:$cond,
368 def CMOV_RFP64 : I<0, Pseudo,
370 (ins RFP64:$src1, RFP64:$src2, i8imm:$cond),
371 "#CMOV_RFP64 PSEUDO!",
373 (X86cmov RFP64:$src1, RFP64:$src2, imm:$cond,
375 def CMOV_RFP80 : I<0, Pseudo,
377 (ins RFP80:$src1, RFP80:$src2, i8imm:$cond),
378 "#CMOV_RFP80 PSEUDO!",
380 (X86cmov RFP80:$src1, RFP80:$src2, imm:$cond,
382 } // Predicates = [NoCMov]
383 } // UsesCustomInserter = 1, Constraints = "", Defs = [EFLAGS]
386 } // Constraints = "$src1 = $dst" in
389 //===----------------------------------------------------------------------===//
390 // Atomic Instruction Pseudo Instructions
391 //===----------------------------------------------------------------------===//
393 // Atomic exchange, and, or, xor
394 let Constraints = "$val = $dst", Defs = [EFLAGS],
395 usesCustomInserter = 1 in {
397 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
399 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
400 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
402 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
403 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
405 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
406 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
407 "#ATOMNAND8 PSEUDO!",
408 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
410 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
411 "#ATOMAND16 PSEUDO!",
412 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
413 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
415 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
416 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
417 "#ATOMXOR16 PSEUDO!",
418 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
419 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
420 "#ATOMNAND16 PSEUDO!",
421 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
422 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
423 "#ATOMMIN16 PSEUDO!",
424 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
425 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
426 "#ATOMMAX16 PSEUDO!",
427 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
428 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
429 "#ATOMUMIN16 PSEUDO!",
430 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
431 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
432 "#ATOMUMAX16 PSEUDO!",
433 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
436 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
437 "#ATOMAND32 PSEUDO!",
438 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
439 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
441 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
442 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
443 "#ATOMXOR32 PSEUDO!",
444 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
445 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
446 "#ATOMNAND32 PSEUDO!",
447 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
448 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
449 "#ATOMMIN32 PSEUDO!",
450 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
451 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
452 "#ATOMMAX32 PSEUDO!",
453 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
454 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
455 "#ATOMUMIN32 PSEUDO!",
456 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
457 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
458 "#ATOMUMAX32 PSEUDO!",
459 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
463 def ATOMAND64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
464 "#ATOMAND64 PSEUDO!",
465 [(set GR64:$dst, (atomic_load_and_64 addr:$ptr, GR64:$val))]>;
466 def ATOMOR64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
468 [(set GR64:$dst, (atomic_load_or_64 addr:$ptr, GR64:$val))]>;
469 def ATOMXOR64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
470 "#ATOMXOR64 PSEUDO!",
471 [(set GR64:$dst, (atomic_load_xor_64 addr:$ptr, GR64:$val))]>;
472 def ATOMNAND64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
473 "#ATOMNAND64 PSEUDO!",
474 [(set GR64:$dst, (atomic_load_nand_64 addr:$ptr, GR64:$val))]>;
475 def ATOMMIN64: I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val),
476 "#ATOMMIN64 PSEUDO!",
477 [(set GR64:$dst, (atomic_load_min_64 addr:$ptr, GR64:$val))]>;
478 def ATOMMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
479 "#ATOMMAX64 PSEUDO!",
480 [(set GR64:$dst, (atomic_load_max_64 addr:$ptr, GR64:$val))]>;
481 def ATOMUMIN64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
482 "#ATOMUMIN64 PSEUDO!",
483 [(set GR64:$dst, (atomic_load_umin_64 addr:$ptr, GR64:$val))]>;
484 def ATOMUMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
485 "#ATOMUMAX64 PSEUDO!",
486 [(set GR64:$dst, (atomic_load_umax_64 addr:$ptr, GR64:$val))]>;
489 let Constraints = "$val1 = $dst1, $val2 = $dst2",
490 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
491 Uses = [EAX, EBX, ECX, EDX],
492 mayLoad = 1, mayStore = 1,
493 usesCustomInserter = 1 in {
494 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
495 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
496 "#ATOMAND6432 PSEUDO!", []>;
497 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
498 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
499 "#ATOMOR6432 PSEUDO!", []>;
500 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
501 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
502 "#ATOMXOR6432 PSEUDO!", []>;
503 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
504 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
505 "#ATOMNAND6432 PSEUDO!", []>;
506 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
507 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
508 "#ATOMADD6432 PSEUDO!", []>;
509 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
510 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
511 "#ATOMSUB6432 PSEUDO!", []>;
512 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
513 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
514 "#ATOMSWAP6432 PSEUDO!", []>;
517 //===----------------------------------------------------------------------===//
518 // Normal-Instructions-With-Lock-Prefix Pseudo Instructions
519 //===----------------------------------------------------------------------===//
521 // FIXME: Use normal instructions and add lock prefix dynamically.
525 // TODO: Get this to fold the constant into the instruction.
526 let isCodeGenOnly = 1 in
527 def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero),
529 "or{l}\t{$zero, $dst|$dst, $zero}",
530 []>, Requires<[In32BitMode]>, LOCK;
532 let hasSideEffects = 1 in
533 def Int_MemBarrier : I<0, Pseudo, (outs), (ins),
537 // TODO: Get this to fold the constant into the instruction.
538 let hasSideEffects = 1, Defs = [ESP], isCodeGenOnly = 1 in
539 def Int_MemBarrierNoSSE64 : RI<0x09, MRM1r, (outs), (ins GR64:$zero),
541 "or{q}\t{$zero, (%rsp)|(%rsp), $zero}",
542 [(X86MemBarrierNoSSE GR64:$zero)]>,
543 Requires<[In64BitMode]>, LOCK;
546 // RegOpc corresponds to the mr version of the instruction
547 // ImmOpc corresponds to the mi version of the instruction
548 // ImmOpc8 corresponds to the mi8 version of the instruction
549 // ImmMod corresponds to the instruction format of the mi and mi8 versions
550 multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8,
551 Format ImmMod, string mnemonic> {
552 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1 in {
554 def #NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
555 RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 },
556 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
557 !strconcat("lock\n\t", mnemonic, "{b}\t",
558 "{$src2, $dst|$dst, $src2}"),
560 def #NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
561 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
562 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
563 !strconcat("lock\n\t", mnemonic, "{w}\t",
564 "{$src2, $dst|$dst, $src2}"),
566 def #NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
567 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
568 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
569 !strconcat("lock\n\t", mnemonic, "{l}\t",
570 "{$src2, $dst|$dst, $src2}"),
572 def #NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
573 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
574 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
575 !strconcat("lock\n\t", mnemonic, "{q}\t",
576 "{$src2, $dst|$dst, $src2}"),
579 def #NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
580 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 },
581 ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2),
582 !strconcat("lock\n\t", mnemonic, "{b}\t",
583 "{$src2, $dst|$dst, $src2}"),
586 def #NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
587 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
588 ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2),
589 !strconcat("lock\n\t", mnemonic, "{w}\t",
590 "{$src2, $dst|$dst, $src2}"),
593 def #NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
594 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
595 ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2),
596 !strconcat("lock\n\t", mnemonic, "{l}\t",
597 "{$src2, $dst|$dst, $src2}"),
600 def #NAME#64mi32 : RIi32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
601 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
602 ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2),
603 !strconcat("lock\n\t", mnemonic, "{q}\t",
604 "{$src2, $dst|$dst, $src2}"),
607 def #NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
608 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
609 ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2),
610 !strconcat("lock\n\t", mnemonic, "{w}\t",
611 "{$src2, $dst|$dst, $src2}"),
613 def #NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
614 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
615 ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2),
616 !strconcat("lock\n\t", mnemonic, "{l}\t",
617 "{$src2, $dst|$dst, $src2}"),
619 def #NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
620 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
621 ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2),
622 !strconcat("lock\n\t", mnemonic, "{q}\t",
623 "{$src2, $dst|$dst, $src2}"),
630 defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, "add">;
631 defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, "sub">;
632 defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, "or">;
633 defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, "and">;
634 defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, "xor">;
636 // Optimized codegen when the non-memory output is not used.
637 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1 in {
639 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
641 "inc{b}\t$dst", []>, LOCK;
642 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
644 "inc{w}\t$dst", []>, OpSize, LOCK;
645 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
647 "inc{l}\t$dst", []>, LOCK;
648 def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst),
650 "inc{q}\t$dst", []>, LOCK;
652 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
654 "dec{b}\t$dst", []>, LOCK;
655 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
657 "dec{w}\t$dst", []>, OpSize, LOCK;
658 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
660 "dec{l}\t$dst", []>, LOCK;
661 def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst),
663 "dec{q}\t$dst", []>, LOCK;
666 // Atomic compare and swap.
667 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX],
668 isCodeGenOnly = 1 in {
669 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr),
672 [(X86cas8 addr:$ptr)]>, TB, LOCK;
674 let Defs = [AL, EFLAGS], Uses = [AL], isCodeGenOnly = 1 in {
675 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
677 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
678 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
681 let Defs = [AX, EFLAGS], Uses = [AX], isCodeGenOnly = 1 in {
682 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
684 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
685 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
688 let Defs = [EAX, EFLAGS], Uses = [EAX], isCodeGenOnly = 1 in {
689 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
691 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
692 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
695 let Defs = [RAX, EFLAGS], Uses = [RAX], isCodeGenOnly = 1 in {
696 def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap),
698 "cmpxchgq\t$swap,$ptr",
699 [(X86cas addr:$ptr, GR64:$swap, 8)]>, TB, LOCK;
702 // Atomic exchange and add
703 let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1 in {
704 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
706 "xadd{b}\t{$val, $ptr|$ptr, $val}",
707 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
709 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins GR16:$val, i16mem:$ptr),
711 "xadd{w}\t{$val, $ptr|$ptr, $val}",
712 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
714 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins GR32:$val, i32mem:$ptr),
716 "xadd{l}\t{$val, $ptr|$ptr, $val}",
717 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
719 def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins GR64:$val,i64mem:$ptr),
722 [(set GR64:$dst, (atomic_load_add_64 addr:$ptr, GR64:$val))]>,
726 //===----------------------------------------------------------------------===//
727 // Conditional Move Pseudo Instructions.
728 //===----------------------------------------------------------------------===//
731 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after
732 // instruction selection into a branch sequence.
733 let Uses = [EFLAGS], usesCustomInserter = 1 in {
734 def CMOV_FR32 : I<0, Pseudo,
735 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
736 "#CMOV_FR32 PSEUDO!",
737 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
739 def CMOV_FR64 : I<0, Pseudo,
740 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
741 "#CMOV_FR64 PSEUDO!",
742 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
744 def CMOV_V4F32 : I<0, Pseudo,
745 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
746 "#CMOV_V4F32 PSEUDO!",
748 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
750 def CMOV_V2F64 : I<0, Pseudo,
751 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
752 "#CMOV_V2F64 PSEUDO!",
754 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
756 def CMOV_V2I64 : I<0, Pseudo,
757 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
758 "#CMOV_V2I64 PSEUDO!",
760 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
762 def CMOV_V8F32 : I<0, Pseudo,
763 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
764 "#CMOV_V8F32 PSEUDO!",
766 (v8f32 (X86cmov VR256:$t, VR256:$f, imm:$cond,
768 def CMOV_V4F64 : I<0, Pseudo,
769 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
770 "#CMOV_V4F64 PSEUDO!",
772 (v4f64 (X86cmov VR256:$t, VR256:$f, imm:$cond,
774 def CMOV_V4I64 : I<0, Pseudo,
775 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
776 "#CMOV_V4I64 PSEUDO!",
778 (v4i64 (X86cmov VR256:$t, VR256:$f, imm:$cond,
783 //===----------------------------------------------------------------------===//
784 // DAG Pattern Matching Rules
785 //===----------------------------------------------------------------------===//
787 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
788 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
789 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
790 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
791 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
792 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
793 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
795 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
796 (ADD32ri GR32:$src1, tconstpool:$src2)>;
797 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
798 (ADD32ri GR32:$src1, tjumptable:$src2)>;
799 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
800 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
801 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
802 (ADD32ri GR32:$src1, texternalsym:$src2)>;
803 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
804 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
806 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
807 (MOV32mi addr:$dst, tglobaladdr:$src)>;
808 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
809 (MOV32mi addr:$dst, texternalsym:$src)>;
810 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
811 (MOV32mi addr:$dst, tblockaddress:$src)>;
815 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
816 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
817 // 'movabs' predicate should handle this sort of thing.
818 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
819 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
820 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
821 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
822 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
823 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
824 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
825 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
826 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
827 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>;
829 // In static codegen with small code model, we can get the address of a label
830 // into a register with 'movl'. FIXME: This is a hack, the 'imm' predicate of
831 // the MOV64ri64i32 should accept these.
832 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
833 (MOV64ri64i32 tconstpool :$dst)>, Requires<[SmallCode]>;
834 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
835 (MOV64ri64i32 tjumptable :$dst)>, Requires<[SmallCode]>;
836 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
837 (MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>;
838 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
839 (MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>;
840 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
841 (MOV64ri64i32 tblockaddress:$dst)>, Requires<[SmallCode]>;
843 // In kernel code model, we can get the address of a label
844 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
845 // the MOV64ri32 should accept these.
846 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
847 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
848 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
849 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
850 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
851 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
852 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
853 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
854 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
855 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>;
857 // If we have small model and -static mode, it is safe to store global addresses
858 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
859 // for MOV64mi32 should handle this sort of thing.
860 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
861 (MOV64mi32 addr:$dst, tconstpool:$src)>,
862 Requires<[NearData, IsStatic]>;
863 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
864 (MOV64mi32 addr:$dst, tjumptable:$src)>,
865 Requires<[NearData, IsStatic]>;
866 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
867 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
868 Requires<[NearData, IsStatic]>;
869 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
870 (MOV64mi32 addr:$dst, texternalsym:$src)>,
871 Requires<[NearData, IsStatic]>;
872 def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst),
873 (MOV64mi32 addr:$dst, tblockaddress:$src)>,
874 Requires<[NearData, IsStatic]>;
880 // tls has some funny stuff here...
881 // This corresponds to movabs $foo@tpoff, %rax
882 def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)),
883 (MOV64ri tglobaltlsaddr :$dst)>;
884 // This corresponds to add $foo@tpoff, %rax
885 def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)),
886 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>;
887 // This corresponds to mov foo@tpoff(%rbx), %eax
888 def : Pat<(load (i64 (X86Wrapper tglobaltlsaddr :$dst))),
889 (MOV64rm tglobaltlsaddr :$dst)>;
892 // Direct PC relative function call for small code model. 32-bit displacement
893 // sign extended to 64-bit.
894 def : Pat<(X86call (i64 tglobaladdr:$dst)),
895 (CALL64pcrel32 tglobaladdr:$dst)>, Requires<[NotWin64]>;
896 def : Pat<(X86call (i64 texternalsym:$dst)),
897 (CALL64pcrel32 texternalsym:$dst)>, Requires<[NotWin64]>;
899 def : Pat<(X86call (i64 tglobaladdr:$dst)),
900 (WINCALL64pcrel32 tglobaladdr:$dst)>, Requires<[IsWin64]>;
901 def : Pat<(X86call (i64 texternalsym:$dst)),
902 (WINCALL64pcrel32 texternalsym:$dst)>, Requires<[IsWin64]>;
905 def : Pat<(X86tcret GR32_TC:$dst, imm:$off),
906 (TCRETURNri GR32_TC:$dst, imm:$off)>,
907 Requires<[In32BitMode]>;
909 // FIXME: This is disabled for 32-bit PIC mode because the global base
910 // register which is part of the address mode may be assigned a
911 // callee-saved register.
912 def : Pat<(X86tcret (load addr:$dst), imm:$off),
913 (TCRETURNmi addr:$dst, imm:$off)>,
914 Requires<[In32BitMode, IsNotPIC]>;
916 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
917 (TCRETURNdi texternalsym:$dst, imm:$off)>,
918 Requires<[In32BitMode]>;
920 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
921 (TCRETURNdi texternalsym:$dst, imm:$off)>,
922 Requires<[In32BitMode]>;
924 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
925 (TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>,
926 Requires<[In64BitMode]>;
928 def : Pat<(X86tcret (load addr:$dst), imm:$off),
929 (TCRETURNmi64 addr:$dst, imm:$off)>,
930 Requires<[In64BitMode]>;
932 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
933 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>,
934 Requires<[In64BitMode]>;
936 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
937 (TCRETURNdi64 texternalsym:$dst, imm:$off)>,
938 Requires<[In64BitMode]>;
940 // Normal calls, with various flavors of addresses.
941 def : Pat<(X86call (i32 tglobaladdr:$dst)),
942 (CALLpcrel32 tglobaladdr:$dst)>;
943 def : Pat<(X86call (i32 texternalsym:$dst)),
944 (CALLpcrel32 texternalsym:$dst)>;
945 def : Pat<(X86call (i32 imm:$dst)),
946 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
950 // TEST R,R is smaller than CMP R,0
951 def : Pat<(X86cmp GR8:$src1, 0),
952 (TEST8rr GR8:$src1, GR8:$src1)>;
953 def : Pat<(X86cmp GR16:$src1, 0),
954 (TEST16rr GR16:$src1, GR16:$src1)>;
955 def : Pat<(X86cmp GR32:$src1, 0),
956 (TEST32rr GR32:$src1, GR32:$src1)>;
957 def : Pat<(X86cmp GR64:$src1, 0),
958 (TEST64rr GR64:$src1, GR64:$src1)>;
960 // Conditional moves with folded loads with operands swapped and conditions
962 multiclass CMOVmr<PatLeaf InvertedCond, Instruction Inst16, Instruction Inst32,
963 Instruction Inst64> {
964 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS),
965 (Inst16 GR16:$src2, addr:$src1)>;
966 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS),
967 (Inst32 GR32:$src2, addr:$src1)>;
968 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS),
969 (Inst64 GR64:$src2, addr:$src1)>;
972 defm : CMOVmr<X86_COND_B , CMOVAE16rm, CMOVAE32rm, CMOVAE64rm>;
973 defm : CMOVmr<X86_COND_AE, CMOVB16rm , CMOVB32rm , CMOVB64rm>;
974 defm : CMOVmr<X86_COND_E , CMOVNE16rm, CMOVNE32rm, CMOVNE64rm>;
975 defm : CMOVmr<X86_COND_NE, CMOVE16rm , CMOVE32rm , CMOVE64rm>;
976 defm : CMOVmr<X86_COND_BE, CMOVA16rm , CMOVA32rm , CMOVA64rm>;
977 defm : CMOVmr<X86_COND_A , CMOVBE16rm, CMOVBE32rm, CMOVBE64rm>;
978 defm : CMOVmr<X86_COND_L , CMOVGE16rm, CMOVGE32rm, CMOVGE64rm>;
979 defm : CMOVmr<X86_COND_GE, CMOVL16rm , CMOVL32rm , CMOVL64rm>;
980 defm : CMOVmr<X86_COND_LE, CMOVG16rm , CMOVG32rm , CMOVG64rm>;
981 defm : CMOVmr<X86_COND_G , CMOVLE16rm, CMOVLE32rm, CMOVLE64rm>;
982 defm : CMOVmr<X86_COND_P , CMOVNP16rm, CMOVNP32rm, CMOVNP64rm>;
983 defm : CMOVmr<X86_COND_NP, CMOVP16rm , CMOVP32rm , CMOVP64rm>;
984 defm : CMOVmr<X86_COND_S , CMOVNS16rm, CMOVNS32rm, CMOVNS64rm>;
985 defm : CMOVmr<X86_COND_NS, CMOVS16rm , CMOVS32rm , CMOVS64rm>;
986 defm : CMOVmr<X86_COND_O , CMOVNO16rm, CMOVNO32rm, CMOVNO64rm>;
987 defm : CMOVmr<X86_COND_NO, CMOVO16rm , CMOVO32rm , CMOVO64rm>;
989 // zextload bool -> zextload byte
990 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
991 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
992 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
993 def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
995 // extload bool -> extload byte
996 // When extloading from 16-bit and smaller memory locations into 64-bit
997 // registers, use zero-extending loads so that the entire 64-bit register is
998 // defined, avoiding partial-register updates.
1000 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
1001 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
1002 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
1003 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
1004 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
1005 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
1007 def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1008 def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>;
1009 def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
1010 // For other extloads, use subregs, since the high contents of the register are
1011 // defined after an extload.
1012 def : Pat<(extloadi64i32 addr:$src),
1013 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src),
1016 // anyext. Define these to do an explicit zero-extend to
1017 // avoid partial-register updates.
1018 def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG
1019 (MOVZX32rr8 GR8 :$src), sub_16bit)>;
1020 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
1022 // Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
1023 def : Pat<(i32 (anyext GR16:$src)),
1024 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>;
1026 def : Pat<(i64 (anyext GR8 :$src)), (MOVZX64rr8 GR8 :$src)>;
1027 def : Pat<(i64 (anyext GR16:$src)), (MOVZX64rr16 GR16 :$src)>;
1028 def : Pat<(i64 (anyext GR32:$src)),
1029 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1032 // Any instruction that defines a 32-bit result leaves the high half of the
1033 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
1034 // be copying from a truncate. And x86's cmov doesn't do anything if the
1035 // condition is false. But any other 32-bit operation will zero-extend
1037 def def32 : PatLeaf<(i32 GR32:$src), [{
1038 return N->getOpcode() != ISD::TRUNCATE &&
1039 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
1040 N->getOpcode() != ISD::CopyFromReg &&
1041 N->getOpcode() != X86ISD::CMOV;
1044 // In the case of a 32-bit def that is known to implicitly zero-extend,
1045 // we can use a SUBREG_TO_REG.
1046 def : Pat<(i64 (zext def32:$src)),
1047 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1049 //===----------------------------------------------------------------------===//
1050 // Pattern match OR as ADD
1051 //===----------------------------------------------------------------------===//
1053 // If safe, we prefer to pattern match OR as ADD at isel time. ADD can be
1054 // 3-addressified into an LEA instruction to avoid copies. However, we also
1055 // want to finally emit these instructions as an or at the end of the code
1056 // generator to make the generated code easier to read. To do this, we select
1057 // into "disjoint bits" pseudo ops.
1059 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
1060 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
1061 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1062 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
1064 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
1065 APInt Mask = APInt::getAllOnesValue(BitWidth);
1066 APInt KnownZero0, KnownOne0;
1067 CurDAG->ComputeMaskedBits(N->getOperand(0), Mask, KnownZero0, KnownOne0, 0);
1068 APInt KnownZero1, KnownOne1;
1069 CurDAG->ComputeMaskedBits(N->getOperand(1), Mask, KnownZero1, KnownOne1, 0);
1070 return (~KnownZero0 & ~KnownZero1) == 0;
1074 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
1075 let AddedComplexity = 5 in { // Try this before the selecting to OR
1077 let isConvertibleToThreeAddress = 1,
1078 Constraints = "$src1 = $dst", Defs = [EFLAGS] in {
1079 let isCommutable = 1 in {
1080 def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1081 "", // orw/addw REG, REG
1082 [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>;
1083 def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1084 "", // orl/addl REG, REG
1085 [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>;
1086 def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1087 "", // orq/addq REG, REG
1088 [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>;
1091 // NOTE: These are order specific, we want the ri8 forms to be listed
1092 // first so that they are slightly preferred to the ri forms.
1094 def ADD16ri8_DB : I<0, Pseudo,
1095 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1096 "", // orw/addw REG, imm8
1097 [(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>;
1098 def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1099 "", // orw/addw REG, imm
1100 [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>;
1102 def ADD32ri8_DB : I<0, Pseudo,
1103 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1104 "", // orl/addl REG, imm8
1105 [(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>;
1106 def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1107 "", // orl/addl REG, imm
1108 [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>;
1111 def ADD64ri8_DB : I<0, Pseudo,
1112 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
1113 "", // orq/addq REG, imm8
1114 [(set GR64:$dst, (or_is_add GR64:$src1,
1115 i64immSExt8:$src2))]>;
1116 def ADD64ri32_DB : I<0, Pseudo,
1117 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1118 "", // orq/addq REG, imm
1119 [(set GR64:$dst, (or_is_add GR64:$src1,
1120 i64immSExt32:$src2))]>;
1122 } // AddedComplexity
1125 //===----------------------------------------------------------------------===//
1127 //===----------------------------------------------------------------------===//
1129 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1130 // +128 doesn't, so in this special case use a sub instead of an add.
1131 def : Pat<(add GR16:$src1, 128),
1132 (SUB16ri8 GR16:$src1, -128)>;
1133 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
1134 (SUB16mi8 addr:$dst, -128)>;
1136 def : Pat<(add GR32:$src1, 128),
1137 (SUB32ri8 GR32:$src1, -128)>;
1138 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
1139 (SUB32mi8 addr:$dst, -128)>;
1141 def : Pat<(add GR64:$src1, 128),
1142 (SUB64ri8 GR64:$src1, -128)>;
1143 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1144 (SUB64mi8 addr:$dst, -128)>;
1146 // The same trick applies for 32-bit immediate fields in 64-bit
1148 def : Pat<(add GR64:$src1, 0x0000000080000000),
1149 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1150 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1151 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1153 // To avoid needing to materialize an immediate in a register, use a 32-bit and
1154 // with implicit zero-extension instead of a 64-bit and if the immediate has at
1155 // least 32 bits of leading zeros. If in addition the last 32 bits can be
1156 // represented with a sign extension of a 8 bit constant, use that.
1158 def : Pat<(and GR64:$src, i64immZExt32SExt8:$imm),
1162 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1163 (i32 (GetLo8XForm imm:$imm))),
1166 def : Pat<(and GR64:$src, i64immZExt32:$imm),
1170 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1171 (i32 (GetLo32XForm imm:$imm))),
1175 // r & (2^16-1) ==> movz
1176 def : Pat<(and GR32:$src1, 0xffff),
1177 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
1178 // r & (2^8-1) ==> movz
1179 def : Pat<(and GR32:$src1, 0xff),
1180 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
1183 Requires<[In32BitMode]>;
1184 // r & (2^8-1) ==> movz
1185 def : Pat<(and GR16:$src1, 0xff),
1186 (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG
1187 (i16 (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD)), sub_8bit)),
1189 Requires<[In32BitMode]>;
1191 // r & (2^32-1) ==> movz
1192 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1193 (MOVZX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
1194 // r & (2^16-1) ==> movz
1195 def : Pat<(and GR64:$src, 0xffff),
1196 (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit)))>;
1197 // r & (2^8-1) ==> movz
1198 def : Pat<(and GR64:$src, 0xff),
1199 (MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit)))>;
1200 // r & (2^8-1) ==> movz
1201 def : Pat<(and GR32:$src1, 0xff),
1202 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>,
1203 Requires<[In64BitMode]>;
1204 // r & (2^8-1) ==> movz
1205 def : Pat<(and GR16:$src1, 0xff),
1206 (EXTRACT_SUBREG (MOVZX32rr8 (i8
1207 (EXTRACT_SUBREG GR16:$src1, sub_8bit))), sub_16bit)>,
1208 Requires<[In64BitMode]>;
1211 // sext_inreg patterns
1212 def : Pat<(sext_inreg GR32:$src, i16),
1213 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>;
1214 def : Pat<(sext_inreg GR32:$src, i8),
1215 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1218 Requires<[In32BitMode]>;
1220 def : Pat<(sext_inreg GR16:$src, i8),
1221 (EXTRACT_SUBREG (i32 (MOVSX32rr8 (EXTRACT_SUBREG
1222 (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), sub_8bit))),
1224 Requires<[In32BitMode]>;
1226 def : Pat<(sext_inreg GR64:$src, i32),
1227 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
1228 def : Pat<(sext_inreg GR64:$src, i16),
1229 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>;
1230 def : Pat<(sext_inreg GR64:$src, i8),
1231 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>;
1232 def : Pat<(sext_inreg GR32:$src, i8),
1233 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>,
1234 Requires<[In64BitMode]>;
1235 def : Pat<(sext_inreg GR16:$src, i8),
1236 (EXTRACT_SUBREG (MOVSX32rr8
1237 (EXTRACT_SUBREG GR16:$src, sub_8bit)), sub_16bit)>,
1238 Requires<[In64BitMode]>;
1240 // sext, sext_load, zext, zext_load
1241 def: Pat<(i16 (sext GR8:$src)),
1242 (EXTRACT_SUBREG (MOVSX32rr8 GR8:$src), sub_16bit)>;
1243 def: Pat<(sextloadi16i8 addr:$src),
1244 (EXTRACT_SUBREG (MOVSX32rm8 addr:$src), sub_16bit)>;
1245 def: Pat<(i16 (zext GR8:$src)),
1246 (EXTRACT_SUBREG (MOVZX32rr8 GR8:$src), sub_16bit)>;
1247 def: Pat<(zextloadi16i8 addr:$src),
1248 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>;
1251 def : Pat<(i16 (trunc GR32:$src)),
1252 (EXTRACT_SUBREG GR32:$src, sub_16bit)>;
1253 def : Pat<(i8 (trunc GR32:$src)),
1254 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1256 Requires<[In32BitMode]>;
1257 def : Pat<(i8 (trunc GR16:$src)),
1258 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1260 Requires<[In32BitMode]>;
1261 def : Pat<(i32 (trunc GR64:$src)),
1262 (EXTRACT_SUBREG GR64:$src, sub_32bit)>;
1263 def : Pat<(i16 (trunc GR64:$src)),
1264 (EXTRACT_SUBREG GR64:$src, sub_16bit)>;
1265 def : Pat<(i8 (trunc GR64:$src)),
1266 (EXTRACT_SUBREG GR64:$src, sub_8bit)>;
1267 def : Pat<(i8 (trunc GR32:$src)),
1268 (EXTRACT_SUBREG GR32:$src, sub_8bit)>,
1269 Requires<[In64BitMode]>;
1270 def : Pat<(i8 (trunc GR16:$src)),
1271 (EXTRACT_SUBREG GR16:$src, sub_8bit)>,
1272 Requires<[In64BitMode]>;
1274 // h-register tricks
1275 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
1276 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1278 Requires<[In32BitMode]>;
1279 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
1280 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1282 Requires<[In32BitMode]>;
1283 def : Pat<(srl GR16:$src, (i8 8)),
1286 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1289 Requires<[In32BitMode]>;
1290 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1291 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1294 Requires<[In32BitMode]>;
1295 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1296 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1299 Requires<[In32BitMode]>;
1300 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1301 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1304 Requires<[In32BitMode]>;
1305 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1306 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1309 Requires<[In32BitMode]>;
1311 // h-register tricks.
1312 // For now, be conservative on x86-64 and use an h-register extract only if the
1313 // value is immediately zero-extended or stored, which are somewhat common
1314 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
1315 // from being allocated in the same instruction as the h register, as there's
1316 // currently no way to describe this requirement to the register allocator.
1318 // h-register extract and zero-extend.
1319 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
1323 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1326 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1328 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1330 Requires<[In64BitMode]>;
1331 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1332 (MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1335 Requires<[In64BitMode]>;
1336 def : Pat<(srl GR16:$src, (i8 8)),
1339 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1342 Requires<[In64BitMode]>;
1343 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1345 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1347 Requires<[In64BitMode]>;
1348 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1350 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1352 Requires<[In64BitMode]>;
1353 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
1357 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1360 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
1364 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1368 // h-register extract and store.
1369 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
1372 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1374 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
1377 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1379 Requires<[In64BitMode]>;
1380 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
1383 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1385 Requires<[In64BitMode]>;
1388 // (shl x, 1) ==> (add x, x)
1389 // Note that if x is undef (immediate or otherwise), we could theoretically
1390 // end up with the two uses of x getting different values, producing a result
1391 // where the least significant bit is not 0. However, the probability of this
1392 // happening is considered low enough that this is officially not a
1394 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
1395 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
1396 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
1397 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1399 // (shl x (and y, 31)) ==> (shl x, y)
1400 def : Pat<(shl GR8:$src1, (and CL, 31)),
1401 (SHL8rCL GR8:$src1)>;
1402 def : Pat<(shl GR16:$src1, (and CL, 31)),
1403 (SHL16rCL GR16:$src1)>;
1404 def : Pat<(shl GR32:$src1, (and CL, 31)),
1405 (SHL32rCL GR32:$src1)>;
1406 def : Pat<(store (shl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
1407 (SHL8mCL addr:$dst)>;
1408 def : Pat<(store (shl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
1409 (SHL16mCL addr:$dst)>;
1410 def : Pat<(store (shl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
1411 (SHL32mCL addr:$dst)>;
1413 def : Pat<(srl GR8:$src1, (and CL, 31)),
1414 (SHR8rCL GR8:$src1)>;
1415 def : Pat<(srl GR16:$src1, (and CL, 31)),
1416 (SHR16rCL GR16:$src1)>;
1417 def : Pat<(srl GR32:$src1, (and CL, 31)),
1418 (SHR32rCL GR32:$src1)>;
1419 def : Pat<(store (srl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
1420 (SHR8mCL addr:$dst)>;
1421 def : Pat<(store (srl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
1422 (SHR16mCL addr:$dst)>;
1423 def : Pat<(store (srl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
1424 (SHR32mCL addr:$dst)>;
1426 def : Pat<(sra GR8:$src1, (and CL, 31)),
1427 (SAR8rCL GR8:$src1)>;
1428 def : Pat<(sra GR16:$src1, (and CL, 31)),
1429 (SAR16rCL GR16:$src1)>;
1430 def : Pat<(sra GR32:$src1, (and CL, 31)),
1431 (SAR32rCL GR32:$src1)>;
1432 def : Pat<(store (sra (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
1433 (SAR8mCL addr:$dst)>;
1434 def : Pat<(store (sra (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
1435 (SAR16mCL addr:$dst)>;
1436 def : Pat<(store (sra (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
1437 (SAR32mCL addr:$dst)>;
1439 // (shl x (and y, 63)) ==> (shl x, y)
1440 def : Pat<(shl GR64:$src1, (and CL, 63)),
1441 (SHL64rCL GR64:$src1)>;
1442 def : Pat<(store (shl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1443 (SHL64mCL addr:$dst)>;
1445 def : Pat<(srl GR64:$src1, (and CL, 63)),
1446 (SHR64rCL GR64:$src1)>;
1447 def : Pat<(store (srl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1448 (SHR64mCL addr:$dst)>;
1450 def : Pat<(sra GR64:$src1, (and CL, 63)),
1451 (SAR64rCL GR64:$src1)>;
1452 def : Pat<(store (sra (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1453 (SAR64mCL addr:$dst)>;
1456 // (anyext (setcc_carry)) -> (setcc_carry)
1457 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1459 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1461 def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))),
1467 //===----------------------------------------------------------------------===//
1468 // EFLAGS-defining Patterns
1469 //===----------------------------------------------------------------------===//
1472 def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>;
1473 def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
1474 def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
1477 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
1478 (ADD8rm GR8:$src1, addr:$src2)>;
1479 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
1480 (ADD16rm GR16:$src1, addr:$src2)>;
1481 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
1482 (ADD32rm GR32:$src1, addr:$src2)>;
1485 def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>;
1486 def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
1487 def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
1488 def : Pat<(add GR16:$src1, i16immSExt8:$src2),
1489 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
1490 def : Pat<(add GR32:$src1, i32immSExt8:$src2),
1491 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
1494 def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>;
1495 def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
1496 def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
1499 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
1500 (SUB8rm GR8:$src1, addr:$src2)>;
1501 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
1502 (SUB16rm GR16:$src1, addr:$src2)>;
1503 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
1504 (SUB32rm GR32:$src1, addr:$src2)>;
1507 def : Pat<(sub GR8:$src1, imm:$src2),
1508 (SUB8ri GR8:$src1, imm:$src2)>;
1509 def : Pat<(sub GR16:$src1, imm:$src2),
1510 (SUB16ri GR16:$src1, imm:$src2)>;
1511 def : Pat<(sub GR32:$src1, imm:$src2),
1512 (SUB32ri GR32:$src1, imm:$src2)>;
1513 def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
1514 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
1515 def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
1516 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
1519 def : Pat<(mul GR16:$src1, GR16:$src2),
1520 (IMUL16rr GR16:$src1, GR16:$src2)>;
1521 def : Pat<(mul GR32:$src1, GR32:$src2),
1522 (IMUL32rr GR32:$src1, GR32:$src2)>;
1525 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
1526 (IMUL16rm GR16:$src1, addr:$src2)>;
1527 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
1528 (IMUL32rm GR32:$src1, addr:$src2)>;
1531 def : Pat<(mul GR16:$src1, imm:$src2),
1532 (IMUL16rri GR16:$src1, imm:$src2)>;
1533 def : Pat<(mul GR32:$src1, imm:$src2),
1534 (IMUL32rri GR32:$src1, imm:$src2)>;
1535 def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
1536 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
1537 def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
1538 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
1540 // reg = mul mem, imm
1541 def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
1542 (IMUL16rmi addr:$src1, imm:$src2)>;
1543 def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
1544 (IMUL32rmi addr:$src1, imm:$src2)>;
1545 def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
1546 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
1547 def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
1548 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
1550 // Patterns for nodes that do not produce flags, for instructions that do.
1553 def : Pat<(add GR64:$src1, GR64:$src2),
1554 (ADD64rr GR64:$src1, GR64:$src2)>;
1555 def : Pat<(add GR64:$src1, i64immSExt8:$src2),
1556 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1557 def : Pat<(add GR64:$src1, i64immSExt32:$src2),
1558 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1559 def : Pat<(add GR64:$src1, (loadi64 addr:$src2)),
1560 (ADD64rm GR64:$src1, addr:$src2)>;
1563 def : Pat<(sub GR64:$src1, GR64:$src2),
1564 (SUB64rr GR64:$src1, GR64:$src2)>;
1565 def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)),
1566 (SUB64rm GR64:$src1, addr:$src2)>;
1567 def : Pat<(sub GR64:$src1, i64immSExt8:$src2),
1568 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1569 def : Pat<(sub GR64:$src1, i64immSExt32:$src2),
1570 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1573 def : Pat<(mul GR64:$src1, GR64:$src2),
1574 (IMUL64rr GR64:$src1, GR64:$src2)>;
1575 def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)),
1576 (IMUL64rm GR64:$src1, addr:$src2)>;
1577 def : Pat<(mul GR64:$src1, i64immSExt8:$src2),
1578 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
1579 def : Pat<(mul GR64:$src1, i64immSExt32:$src2),
1580 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
1581 def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2),
1582 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
1583 def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2),
1584 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
1587 def : Pat<(add GR8 :$src, 1), (INC8r GR8 :$src)>;
1588 def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>, Requires<[In32BitMode]>;
1589 def : Pat<(add GR16:$src, 1), (INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1590 def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>, Requires<[In32BitMode]>;
1591 def : Pat<(add GR32:$src, 1), (INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1592 def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>;
1595 def : Pat<(add GR8 :$src, -1), (DEC8r GR8 :$src)>;
1596 def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
1597 def : Pat<(add GR16:$src, -1), (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1598 def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
1599 def : Pat<(add GR32:$src, -1), (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1600 def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>;
1603 def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
1604 def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
1605 def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
1606 def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>;
1609 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
1610 (OR8rm GR8:$src1, addr:$src2)>;
1611 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
1612 (OR16rm GR16:$src1, addr:$src2)>;
1613 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
1614 (OR32rm GR32:$src1, addr:$src2)>;
1615 def : Pat<(or GR64:$src1, (loadi64 addr:$src2)),
1616 (OR64rm GR64:$src1, addr:$src2)>;
1619 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
1620 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
1621 def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
1622 def : Pat<(or GR16:$src1, i16immSExt8:$src2),
1623 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1624 def : Pat<(or GR32:$src1, i32immSExt8:$src2),
1625 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1626 def : Pat<(or GR64:$src1, i64immSExt8:$src2),
1627 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1628 def : Pat<(or GR64:$src1, i64immSExt32:$src2),
1629 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1632 def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>;
1633 def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
1634 def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
1635 def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>;
1638 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
1639 (XOR8rm GR8:$src1, addr:$src2)>;
1640 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
1641 (XOR16rm GR16:$src1, addr:$src2)>;
1642 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
1643 (XOR32rm GR32:$src1, addr:$src2)>;
1644 def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)),
1645 (XOR64rm GR64:$src1, addr:$src2)>;
1648 def : Pat<(xor GR8:$src1, imm:$src2),
1649 (XOR8ri GR8:$src1, imm:$src2)>;
1650 def : Pat<(xor GR16:$src1, imm:$src2),
1651 (XOR16ri GR16:$src1, imm:$src2)>;
1652 def : Pat<(xor GR32:$src1, imm:$src2),
1653 (XOR32ri GR32:$src1, imm:$src2)>;
1654 def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
1655 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1656 def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
1657 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1658 def : Pat<(xor GR64:$src1, i64immSExt8:$src2),
1659 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1660 def : Pat<(xor GR64:$src1, i64immSExt32:$src2),
1661 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1664 def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>;
1665 def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
1666 def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
1667 def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>;
1670 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
1671 (AND8rm GR8:$src1, addr:$src2)>;
1672 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
1673 (AND16rm GR16:$src1, addr:$src2)>;
1674 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
1675 (AND32rm GR32:$src1, addr:$src2)>;
1676 def : Pat<(and GR64:$src1, (loadi64 addr:$src2)),
1677 (AND64rm GR64:$src1, addr:$src2)>;
1680 def : Pat<(and GR8:$src1, imm:$src2),
1681 (AND8ri GR8:$src1, imm:$src2)>;
1682 def : Pat<(and GR16:$src1, imm:$src2),
1683 (AND16ri GR16:$src1, imm:$src2)>;
1684 def : Pat<(and GR32:$src1, imm:$src2),
1685 (AND32ri GR32:$src1, imm:$src2)>;
1686 def : Pat<(and GR16:$src1, i16immSExt8:$src2),
1687 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
1688 def : Pat<(and GR32:$src1, i32immSExt8:$src2),
1689 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
1690 def : Pat<(and GR64:$src1, i64immSExt8:$src2),
1691 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
1692 def : Pat<(and GR64:$src1, i64immSExt32:$src2),
1693 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>;