1 //===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the various pseudo instructions used by the compiler,
11 // as well as Pat patterns used during instruction selection.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Pattern Matching Support
18 def GetLo32XForm : SDNodeXForm<imm, [{
19 // Transformation function: get the low 32 bits.
20 return getI32Imm((unsigned)N->getZExtValue());
23 def GetLo8XForm : SDNodeXForm<imm, [{
24 // Transformation function: get the low 8 bits.
25 return getI8Imm((uint8_t)N->getZExtValue());
29 //===----------------------------------------------------------------------===//
30 // Random Pseudo Instructions.
32 // PIC base construction. This expands to code that looks like this:
35 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
36 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
40 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
41 // a stack adjustment and the codegen must know that they may modify the stack
42 // pointer before prolog-epilog rewriting occurs.
43 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
44 // sub / add which can clobber EFLAGS.
45 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
46 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
48 [(X86callseq_start timm:$amt)]>,
49 Requires<[In32BitMode]>;
50 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
52 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
53 Requires<[In32BitMode]>;
56 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
57 // a stack adjustment and the codegen must know that they may modify the stack
58 // pointer before prolog-epilog rewriting occurs.
59 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
60 // sub / add which can clobber EFLAGS.
61 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
62 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
64 [(X86callseq_start timm:$amt)]>,
65 Requires<[In64BitMode]>;
66 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
68 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
69 Requires<[In64BitMode]>;
74 // x86-64 va_start lowering magic.
75 let usesCustomInserter = 1 in {
76 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
79 i64imm:$regsavefi, i64imm:$offset,
81 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
82 [(X86vastart_save_xmm_regs GR8:$al,
86 // The VAARG_64 pseudo-instruction takes the address of the va_list,
87 // and places the address of the next argument into a register.
88 let Defs = [EFLAGS] in
89 def VAARG_64 : I<0, Pseudo,
91 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align),
92 "#VAARG_64 $dst, $ap, $size, $mode, $align",
94 (X86vaarg64 addr:$ap, imm:$size, imm:$mode, imm:$align)),
97 // Dynamic stack allocation yields a _chkstk or _alloca call for all Windows
98 // targets. These calls are needed to probe the stack when allocating more than
99 // 4k bytes in one go. Touching the stack at 4K increments is necessary to
100 // ensure that the guard pages used by the OS virtual memory manager are
101 // allocated in correct sequence.
102 // The main point of having separate instruction are extra unmodelled effects
103 // (compared to ordinary calls) like stack pointer change.
105 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
106 def WIN_ALLOCA : I<0, Pseudo, (outs), (ins),
107 "# dynamic stack allocation",
110 // When using segmented stacks these are lowered into instructions which first
111 // check if the current stacklet has enough free memory. If it does, memory is
112 // allocated by bumping the stack pointer. Otherwise memory is allocated from
115 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP, EAX] in
116 def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size),
117 "# variable sized alloca for segmented stacks",
119 (X86SegAlloca GR32:$size))]>,
120 Requires<[In32BitMode]>;
122 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP, RAX] in
123 def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size),
124 "# variable sized alloca for segmented stacks",
126 (X86SegAlloca GR64:$size))]>,
127 Requires<[In64BitMode]>;
133 //===----------------------------------------------------------------------===//
134 // EH Pseudo Instructions
136 let isTerminator = 1, isReturn = 1, isBarrier = 1,
137 hasCtrlDep = 1, isCodeGenOnly = 1 in {
138 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
139 "ret\t#eh_return, addr: $addr",
140 [(X86ehret GR32:$addr)]>;
144 let isTerminator = 1, isReturn = 1, isBarrier = 1,
145 hasCtrlDep = 1, isCodeGenOnly = 1 in {
146 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
147 "ret\t#eh_return, addr: $addr",
148 [(X86ehret GR64:$addr)]>;
152 //===----------------------------------------------------------------------===//
153 // Alias Instructions
154 //===----------------------------------------------------------------------===//
156 // Alias instructions that map movr0 to xor.
157 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
158 // FIXME: Set encoding to pseudo.
159 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
160 isCodeGenOnly = 1 in {
161 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "",
162 [(set GR8:$dst, 0)]>;
164 // We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller
165 // encoding and avoids a partial-register update sometimes, but doing so
166 // at isel time interferes with rematerialization in the current register
167 // allocator. For now, this is rewritten when the instruction is lowered
169 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
171 [(set GR16:$dst, 0)]>, OpSize;
173 // FIXME: Set encoding to pseudo.
174 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "",
175 [(set GR32:$dst, 0)]>;
178 // We want to rewrite MOV64r0 in terms of MOV32r0, because it's sometimes a
179 // smaller encoding, but doing so at isel time interferes with rematerialization
180 // in the current register allocator. For now, this is rewritten when the
181 // instruction is lowered to an MCInst.
182 // FIXME: AddedComplexity gives this a higher priority than MOV64ri32. Remove
183 // when we have a better way to specify isel priority.
184 let Defs = [EFLAGS], isCodeGenOnly=1,
185 AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
186 def MOV64r0 : I<0x31, MRMInitReg, (outs GR64:$dst), (ins), "",
187 [(set GR64:$dst, 0)]>;
189 // Materialize i64 constant where top 32-bits are zero. This could theoretically
190 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
191 // that would make it more difficult to rematerialize.
192 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1,
194 def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
195 "", [(set GR64:$dst, i64immZExt32:$src)]>;
197 // Use sbb to materialize carry bit.
198 let Uses = [EFLAGS], Defs = [EFLAGS], isCodeGenOnly = 1 in {
199 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
200 // However, Pat<> can't replicate the destination reg into the inputs of the
202 // FIXME: Change these to have encoding Pseudo when X86MCCodeEmitter replaces
204 def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins), "",
205 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
206 def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins), "",
207 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>,
209 def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins), "",
210 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
211 def SETB_C64r : RI<0x19, MRMInitReg, (outs GR64:$dst), (ins), "",
212 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
216 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
218 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
220 def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
223 def : Pat<(i16 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
225 def : Pat<(i32 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
227 def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
230 // We canonicalize 'setb' to "(and (sbb reg,reg), 1)" on the hope that the and
231 // will be eliminated and that the sbb can be extended up to a wider type. When
232 // this happens, it is great. However, if we are left with an 8-bit sbb and an
233 // and, we might as well just match it as a setb.
234 def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1),
237 // (add OP, SETB) -> (adc OP, 0)
238 def : Pat<(add (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR8:$op),
239 (ADC8ri GR8:$op, 0)>;
240 def : Pat<(add (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR32:$op),
241 (ADC32ri8 GR32:$op, 0)>;
242 def : Pat<(add (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR64:$op),
243 (ADC64ri8 GR64:$op, 0)>;
245 // (sub OP, SETB) -> (sbb OP, 0)
246 def : Pat<(sub GR8:$op, (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
247 (SBB8ri GR8:$op, 0)>;
248 def : Pat<(sub GR32:$op, (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
249 (SBB32ri8 GR32:$op, 0)>;
250 def : Pat<(sub GR64:$op, (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
251 (SBB64ri8 GR64:$op, 0)>;
253 // (sub OP, SETCC_CARRY) -> (adc OP, 0)
254 def : Pat<(sub GR8:$op, (i8 (X86setcc_c X86_COND_B, EFLAGS))),
255 (ADC8ri GR8:$op, 0)>;
256 def : Pat<(sub GR32:$op, (i32 (X86setcc_c X86_COND_B, EFLAGS))),
257 (ADC32ri8 GR32:$op, 0)>;
258 def : Pat<(sub GR64:$op, (i64 (X86setcc_c X86_COND_B, EFLAGS))),
259 (ADC64ri8 GR64:$op, 0)>;
261 //===----------------------------------------------------------------------===//
262 // String Pseudo Instructions
264 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
265 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
266 [(X86rep_movs i8)]>, REP;
267 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
268 [(X86rep_movs i16)]>, REP, OpSize;
269 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
270 [(X86rep_movs i32)]>, REP;
273 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in
274 def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
275 [(X86rep_movs i64)]>, REP;
278 // FIXME: Should use "(X86rep_stos AL)" as the pattern.
279 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI], isCodeGenOnly = 1 in
280 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
281 [(X86rep_stos i8)]>, REP;
282 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI], isCodeGenOnly = 1 in
283 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
284 [(X86rep_stos i16)]>, REP, OpSize;
285 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI], isCodeGenOnly = 1 in
286 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
287 [(X86rep_stos i32)]>, REP;
289 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI], isCodeGenOnly = 1 in
290 def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
291 [(X86rep_stos i64)]>, REP;
294 //===----------------------------------------------------------------------===//
295 // Thread Local Storage Instructions
299 // All calls clobber the non-callee saved registers. ESP is marked as
300 // a use to prevent stack-pointer assignments that appear immediately
301 // before calls from potentially appearing dead.
302 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
303 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
304 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
305 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
307 def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
309 [(X86tlsaddr tls32addr:$sym)]>,
310 Requires<[In32BitMode]>;
312 // All calls clobber the non-callee saved registers. RSP is marked as
313 // a use to prevent stack-pointer assignments that appear immediately
314 // before calls from potentially appearing dead.
315 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
316 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
317 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
318 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
319 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
321 def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
323 [(X86tlsaddr tls64addr:$sym)]>,
324 Requires<[In64BitMode]>;
326 // Darwin TLS Support
327 // For i386, the address of the thunk is passed on the stack, on return the
328 // address of the variable is in %eax. %ecx is trashed during the function
329 // call. All other registers are preserved.
330 let Defs = [EAX, ECX, EFLAGS],
332 usesCustomInserter = 1 in
333 def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
335 [(X86TLSCall addr:$sym)]>,
336 Requires<[In32BitMode]>;
338 // For x86_64, the address of the thunk is passed in %rdi, on return
339 // the address of the variable is in %rax. All other registers are preserved.
340 let Defs = [RAX, EFLAGS],
342 usesCustomInserter = 1 in
343 def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
345 [(X86TLSCall addr:$sym)]>,
346 Requires<[In64BitMode]>;
349 //===----------------------------------------------------------------------===//
350 // Conditional Move Pseudo Instructions
352 let Constraints = "$src1 = $dst" in {
355 let Uses = [EFLAGS] in {
357 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
358 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
359 // however that requires promoting the operands, and can induce additional
360 // i8 register pressure. Note that CMOV_GR8 is conservatively considered to
361 // clobber EFLAGS, because if one of the operands is zero, the expansion
362 // could involve an xor.
363 let usesCustomInserter = 1, Constraints = "", Defs = [EFLAGS] in {
364 def CMOV_GR8 : I<0, Pseudo,
365 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
367 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
368 imm:$cond, EFLAGS))]>;
370 let Predicates = [NoCMov] in {
371 def CMOV_GR32 : I<0, Pseudo,
372 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cond),
373 "#CMOV_GR32* PSEUDO!",
375 (X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>;
376 def CMOV_GR16 : I<0, Pseudo,
377 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cond),
378 "#CMOV_GR16* PSEUDO!",
380 (X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>;
381 def CMOV_RFP32 : I<0, Pseudo,
383 (ins RFP32:$src1, RFP32:$src2, i8imm:$cond),
384 "#CMOV_RFP32 PSEUDO!",
386 (X86cmov RFP32:$src1, RFP32:$src2, imm:$cond,
388 def CMOV_RFP64 : I<0, Pseudo,
390 (ins RFP64:$src1, RFP64:$src2, i8imm:$cond),
391 "#CMOV_RFP64 PSEUDO!",
393 (X86cmov RFP64:$src1, RFP64:$src2, imm:$cond,
395 def CMOV_RFP80 : I<0, Pseudo,
397 (ins RFP80:$src1, RFP80:$src2, i8imm:$cond),
398 "#CMOV_RFP80 PSEUDO!",
400 (X86cmov RFP80:$src1, RFP80:$src2, imm:$cond,
402 } // Predicates = [NoCMov]
403 } // UsesCustomInserter = 1, Constraints = "", Defs = [EFLAGS]
406 } // Constraints = "$src1 = $dst" in
409 //===----------------------------------------------------------------------===//
410 // Atomic Instruction Pseudo Instructions
411 //===----------------------------------------------------------------------===//
413 // Atomic exchange, and, or, xor
414 let Constraints = "$val = $dst", Defs = [EFLAGS],
415 usesCustomInserter = 1 in {
417 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
419 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
420 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
422 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
423 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
425 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
426 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
427 "#ATOMNAND8 PSEUDO!",
428 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
430 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
431 "#ATOMAND16 PSEUDO!",
432 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
433 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
435 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
436 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
437 "#ATOMXOR16 PSEUDO!",
438 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
439 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
440 "#ATOMNAND16 PSEUDO!",
441 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
442 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
443 "#ATOMMIN16 PSEUDO!",
444 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
445 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
446 "#ATOMMAX16 PSEUDO!",
447 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
448 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
449 "#ATOMUMIN16 PSEUDO!",
450 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
451 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
452 "#ATOMUMAX16 PSEUDO!",
453 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
456 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
457 "#ATOMAND32 PSEUDO!",
458 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
459 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
461 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
462 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
463 "#ATOMXOR32 PSEUDO!",
464 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
465 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
466 "#ATOMNAND32 PSEUDO!",
467 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
468 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
469 "#ATOMMIN32 PSEUDO!",
470 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
471 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
472 "#ATOMMAX32 PSEUDO!",
473 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
474 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
475 "#ATOMUMIN32 PSEUDO!",
476 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
477 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
478 "#ATOMUMAX32 PSEUDO!",
479 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
483 def ATOMAND64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
484 "#ATOMAND64 PSEUDO!",
485 [(set GR64:$dst, (atomic_load_and_64 addr:$ptr, GR64:$val))]>;
486 def ATOMOR64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
488 [(set GR64:$dst, (atomic_load_or_64 addr:$ptr, GR64:$val))]>;
489 def ATOMXOR64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
490 "#ATOMXOR64 PSEUDO!",
491 [(set GR64:$dst, (atomic_load_xor_64 addr:$ptr, GR64:$val))]>;
492 def ATOMNAND64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
493 "#ATOMNAND64 PSEUDO!",
494 [(set GR64:$dst, (atomic_load_nand_64 addr:$ptr, GR64:$val))]>;
495 def ATOMMIN64: I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val),
496 "#ATOMMIN64 PSEUDO!",
497 [(set GR64:$dst, (atomic_load_min_64 addr:$ptr, GR64:$val))]>;
498 def ATOMMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
499 "#ATOMMAX64 PSEUDO!",
500 [(set GR64:$dst, (atomic_load_max_64 addr:$ptr, GR64:$val))]>;
501 def ATOMUMIN64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
502 "#ATOMUMIN64 PSEUDO!",
503 [(set GR64:$dst, (atomic_load_umin_64 addr:$ptr, GR64:$val))]>;
504 def ATOMUMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
505 "#ATOMUMAX64 PSEUDO!",
506 [(set GR64:$dst, (atomic_load_umax_64 addr:$ptr, GR64:$val))]>;
509 let Constraints = "$val1 = $dst1, $val2 = $dst2",
510 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
511 Uses = [EAX, EBX, ECX, EDX],
512 mayLoad = 1, mayStore = 1,
513 usesCustomInserter = 1 in {
514 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
515 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
516 "#ATOMAND6432 PSEUDO!", []>;
517 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
518 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
519 "#ATOMOR6432 PSEUDO!", []>;
520 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
521 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
522 "#ATOMXOR6432 PSEUDO!", []>;
523 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
524 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
525 "#ATOMNAND6432 PSEUDO!", []>;
526 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
527 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
528 "#ATOMADD6432 PSEUDO!", []>;
529 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
530 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
531 "#ATOMSUB6432 PSEUDO!", []>;
532 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
533 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
534 "#ATOMSWAP6432 PSEUDO!", []>;
537 //===----------------------------------------------------------------------===//
538 // Normal-Instructions-With-Lock-Prefix Pseudo Instructions
539 //===----------------------------------------------------------------------===//
541 // FIXME: Use normal instructions and add lock prefix dynamically.
545 // TODO: Get this to fold the constant into the instruction.
546 let isCodeGenOnly = 1 in
547 def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero),
549 "or{l}\t{$zero, $dst|$dst, $zero}",
550 []>, Requires<[In32BitMode]>, LOCK;
552 let hasSideEffects = 1 in
553 def Int_MemBarrier : I<0, Pseudo, (outs), (ins),
557 // TODO: Get this to fold the constant into the instruction.
558 let hasSideEffects = 1, Defs = [ESP], isCodeGenOnly = 1 in
559 def Int_MemBarrierNoSSE64 : RI<0x09, MRM1r, (outs), (ins GR64:$zero),
561 "or{q}\t{$zero, (%rsp)|(%rsp), $zero}",
562 [(X86MemBarrierNoSSE GR64:$zero)]>,
563 Requires<[In64BitMode]>, LOCK;
566 // RegOpc corresponds to the mr version of the instruction
567 // ImmOpc corresponds to the mi version of the instruction
568 // ImmOpc8 corresponds to the mi8 version of the instruction
569 // ImmMod corresponds to the instruction format of the mi and mi8 versions
570 multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8,
571 Format ImmMod, string mnemonic> {
572 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1 in {
574 def #NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
575 RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 },
576 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
577 !strconcat("lock\n\t", mnemonic, "{b}\t",
578 "{$src2, $dst|$dst, $src2}"),
580 def #NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
581 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
582 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
583 !strconcat("lock\n\t", mnemonic, "{w}\t",
584 "{$src2, $dst|$dst, $src2}"),
586 def #NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
587 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
588 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
589 !strconcat("lock\n\t", mnemonic, "{l}\t",
590 "{$src2, $dst|$dst, $src2}"),
592 def #NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
593 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
594 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
595 !strconcat("lock\n\t", mnemonic, "{q}\t",
596 "{$src2, $dst|$dst, $src2}"),
599 def #NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
600 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 },
601 ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2),
602 !strconcat("lock\n\t", mnemonic, "{b}\t",
603 "{$src2, $dst|$dst, $src2}"),
606 def #NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
607 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
608 ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2),
609 !strconcat("lock\n\t", mnemonic, "{w}\t",
610 "{$src2, $dst|$dst, $src2}"),
613 def #NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
614 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
615 ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2),
616 !strconcat("lock\n\t", mnemonic, "{l}\t",
617 "{$src2, $dst|$dst, $src2}"),
620 def #NAME#64mi32 : RIi32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
621 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
622 ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2),
623 !strconcat("lock\n\t", mnemonic, "{q}\t",
624 "{$src2, $dst|$dst, $src2}"),
627 def #NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
628 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
629 ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2),
630 !strconcat("lock\n\t", mnemonic, "{w}\t",
631 "{$src2, $dst|$dst, $src2}"),
633 def #NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
634 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
635 ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2),
636 !strconcat("lock\n\t", mnemonic, "{l}\t",
637 "{$src2, $dst|$dst, $src2}"),
639 def #NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
640 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
641 ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2),
642 !strconcat("lock\n\t", mnemonic, "{q}\t",
643 "{$src2, $dst|$dst, $src2}"),
650 defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, "add">;
651 defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, "sub">;
652 defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, "or">;
653 defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, "and">;
654 defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, "xor">;
656 // Optimized codegen when the non-memory output is not used.
657 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1 in {
659 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
661 "inc{b}\t$dst", []>, LOCK;
662 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
664 "inc{w}\t$dst", []>, OpSize, LOCK;
665 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
667 "inc{l}\t$dst", []>, LOCK;
668 def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst),
670 "inc{q}\t$dst", []>, LOCK;
672 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
674 "dec{b}\t$dst", []>, LOCK;
675 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
677 "dec{w}\t$dst", []>, OpSize, LOCK;
678 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
680 "dec{l}\t$dst", []>, LOCK;
681 def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst),
683 "dec{q}\t$dst", []>, LOCK;
686 // Atomic compare and swap.
687 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX],
689 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr),
692 [(X86cas8 addr:$ptr)]>, TB, LOCK;
694 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX],
696 def LCMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$ptr),
699 [(X86cas16 addr:$ptr)]>, TB, LOCK,
700 Requires<[HasCmpxchg16b]>;
702 let Defs = [AL, EFLAGS], Uses = [AL], isCodeGenOnly = 1 in {
703 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
705 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
706 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
709 let Defs = [AX, EFLAGS], Uses = [AX], isCodeGenOnly = 1 in {
710 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
712 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
713 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
716 let Defs = [EAX, EFLAGS], Uses = [EAX], isCodeGenOnly = 1 in {
717 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
719 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
720 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
723 let Defs = [RAX, EFLAGS], Uses = [RAX], isCodeGenOnly = 1 in {
724 def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap),
726 "cmpxchgq\t$swap,$ptr",
727 [(X86cas addr:$ptr, GR64:$swap, 8)]>, TB, LOCK;
730 // Atomic exchange and add
731 let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1 in {
732 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
734 "xadd{b}\t{$val, $ptr|$ptr, $val}",
735 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
737 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins GR16:$val, i16mem:$ptr),
739 "xadd{w}\t{$val, $ptr|$ptr, $val}",
740 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
742 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins GR32:$val, i32mem:$ptr),
744 "xadd{l}\t{$val, $ptr|$ptr, $val}",
745 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
747 def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins GR64:$val,i64mem:$ptr),
750 [(set GR64:$dst, (atomic_load_add_64 addr:$ptr, GR64:$val))]>,
754 //===----------------------------------------------------------------------===//
755 // Conditional Move Pseudo Instructions.
756 //===----------------------------------------------------------------------===//
759 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after
760 // instruction selection into a branch sequence.
761 let Uses = [EFLAGS], usesCustomInserter = 1 in {
762 def CMOV_FR32 : I<0, Pseudo,
763 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
764 "#CMOV_FR32 PSEUDO!",
765 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
767 def CMOV_FR64 : I<0, Pseudo,
768 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
769 "#CMOV_FR64 PSEUDO!",
770 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
772 def CMOV_V4F32 : I<0, Pseudo,
773 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
774 "#CMOV_V4F32 PSEUDO!",
776 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
778 def CMOV_V2F64 : I<0, Pseudo,
779 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
780 "#CMOV_V2F64 PSEUDO!",
782 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
784 def CMOV_V2I64 : I<0, Pseudo,
785 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
786 "#CMOV_V2I64 PSEUDO!",
788 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
790 def CMOV_V8F32 : I<0, Pseudo,
791 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
792 "#CMOV_V8F32 PSEUDO!",
794 (v8f32 (X86cmov VR256:$t, VR256:$f, imm:$cond,
796 def CMOV_V4F64 : I<0, Pseudo,
797 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
798 "#CMOV_V4F64 PSEUDO!",
800 (v4f64 (X86cmov VR256:$t, VR256:$f, imm:$cond,
802 def CMOV_V4I64 : I<0, Pseudo,
803 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
804 "#CMOV_V4I64 PSEUDO!",
806 (v4i64 (X86cmov VR256:$t, VR256:$f, imm:$cond,
811 //===----------------------------------------------------------------------===//
812 // DAG Pattern Matching Rules
813 //===----------------------------------------------------------------------===//
815 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
816 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
817 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
818 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
819 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
820 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
821 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
823 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
824 (ADD32ri GR32:$src1, tconstpool:$src2)>;
825 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
826 (ADD32ri GR32:$src1, tjumptable:$src2)>;
827 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
828 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
829 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
830 (ADD32ri GR32:$src1, texternalsym:$src2)>;
831 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
832 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
834 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
835 (MOV32mi addr:$dst, tglobaladdr:$src)>;
836 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
837 (MOV32mi addr:$dst, texternalsym:$src)>;
838 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
839 (MOV32mi addr:$dst, tblockaddress:$src)>;
843 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
844 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
845 // 'movabs' predicate should handle this sort of thing.
846 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
847 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
848 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
849 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
850 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
851 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
852 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
853 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
854 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
855 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>;
857 // In static codegen with small code model, we can get the address of a label
858 // into a register with 'movl'. FIXME: This is a hack, the 'imm' predicate of
859 // the MOV64ri64i32 should accept these.
860 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
861 (MOV64ri64i32 tconstpool :$dst)>, Requires<[SmallCode]>;
862 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
863 (MOV64ri64i32 tjumptable :$dst)>, Requires<[SmallCode]>;
864 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
865 (MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>;
866 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
867 (MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>;
868 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
869 (MOV64ri64i32 tblockaddress:$dst)>, Requires<[SmallCode]>;
871 // In kernel code model, we can get the address of a label
872 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
873 // the MOV64ri32 should accept these.
874 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
875 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
876 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
877 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
878 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
879 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
880 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
881 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
882 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
883 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>;
885 // If we have small model and -static mode, it is safe to store global addresses
886 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
887 // for MOV64mi32 should handle this sort of thing.
888 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
889 (MOV64mi32 addr:$dst, tconstpool:$src)>,
890 Requires<[NearData, IsStatic]>;
891 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
892 (MOV64mi32 addr:$dst, tjumptable:$src)>,
893 Requires<[NearData, IsStatic]>;
894 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
895 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
896 Requires<[NearData, IsStatic]>;
897 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
898 (MOV64mi32 addr:$dst, texternalsym:$src)>,
899 Requires<[NearData, IsStatic]>;
900 def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst),
901 (MOV64mi32 addr:$dst, tblockaddress:$src)>,
902 Requires<[NearData, IsStatic]>;
908 // tls has some funny stuff here...
909 // This corresponds to movabs $foo@tpoff, %rax
910 def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)),
911 (MOV64ri tglobaltlsaddr :$dst)>;
912 // This corresponds to add $foo@tpoff, %rax
913 def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)),
914 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>;
915 // This corresponds to mov foo@tpoff(%rbx), %eax
916 def : Pat<(load (i64 (X86Wrapper tglobaltlsaddr :$dst))),
917 (MOV64rm tglobaltlsaddr :$dst)>;
920 // Direct PC relative function call for small code model. 32-bit displacement
921 // sign extended to 64-bit.
922 def : Pat<(X86call (i64 tglobaladdr:$dst)),
923 (CALL64pcrel32 tglobaladdr:$dst)>, Requires<[NotWin64]>;
924 def : Pat<(X86call (i64 texternalsym:$dst)),
925 (CALL64pcrel32 texternalsym:$dst)>, Requires<[NotWin64]>;
927 def : Pat<(X86call (i64 tglobaladdr:$dst)),
928 (WINCALL64pcrel32 tglobaladdr:$dst)>, Requires<[IsWin64]>;
929 def : Pat<(X86call (i64 texternalsym:$dst)),
930 (WINCALL64pcrel32 texternalsym:$dst)>, Requires<[IsWin64]>;
933 def : Pat<(X86tcret GR32_TC:$dst, imm:$off),
934 (TCRETURNri GR32_TC:$dst, imm:$off)>,
935 Requires<[In32BitMode]>;
937 // FIXME: This is disabled for 32-bit PIC mode because the global base
938 // register which is part of the address mode may be assigned a
939 // callee-saved register.
940 def : Pat<(X86tcret (load addr:$dst), imm:$off),
941 (TCRETURNmi addr:$dst, imm:$off)>,
942 Requires<[In32BitMode, IsNotPIC]>;
944 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
945 (TCRETURNdi texternalsym:$dst, imm:$off)>,
946 Requires<[In32BitMode]>;
948 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
949 (TCRETURNdi texternalsym:$dst, imm:$off)>,
950 Requires<[In32BitMode]>;
952 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
953 (TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>,
954 Requires<[In64BitMode]>;
956 def : Pat<(X86tcret (load addr:$dst), imm:$off),
957 (TCRETURNmi64 addr:$dst, imm:$off)>,
958 Requires<[In64BitMode]>;
960 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
961 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>,
962 Requires<[In64BitMode]>;
964 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
965 (TCRETURNdi64 texternalsym:$dst, imm:$off)>,
966 Requires<[In64BitMode]>;
968 // Normal calls, with various flavors of addresses.
969 def : Pat<(X86call (i32 tglobaladdr:$dst)),
970 (CALLpcrel32 tglobaladdr:$dst)>;
971 def : Pat<(X86call (i32 texternalsym:$dst)),
972 (CALLpcrel32 texternalsym:$dst)>;
973 def : Pat<(X86call (i32 imm:$dst)),
974 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
978 // TEST R,R is smaller than CMP R,0
979 def : Pat<(X86cmp GR8:$src1, 0),
980 (TEST8rr GR8:$src1, GR8:$src1)>;
981 def : Pat<(X86cmp GR16:$src1, 0),
982 (TEST16rr GR16:$src1, GR16:$src1)>;
983 def : Pat<(X86cmp GR32:$src1, 0),
984 (TEST32rr GR32:$src1, GR32:$src1)>;
985 def : Pat<(X86cmp GR64:$src1, 0),
986 (TEST64rr GR64:$src1, GR64:$src1)>;
988 // Conditional moves with folded loads with operands swapped and conditions
990 multiclass CMOVmr<PatLeaf InvertedCond, Instruction Inst16, Instruction Inst32,
991 Instruction Inst64> {
992 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS),
993 (Inst16 GR16:$src2, addr:$src1)>;
994 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS),
995 (Inst32 GR32:$src2, addr:$src1)>;
996 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS),
997 (Inst64 GR64:$src2, addr:$src1)>;
1000 defm : CMOVmr<X86_COND_B , CMOVAE16rm, CMOVAE32rm, CMOVAE64rm>;
1001 defm : CMOVmr<X86_COND_AE, CMOVB16rm , CMOVB32rm , CMOVB64rm>;
1002 defm : CMOVmr<X86_COND_E , CMOVNE16rm, CMOVNE32rm, CMOVNE64rm>;
1003 defm : CMOVmr<X86_COND_NE, CMOVE16rm , CMOVE32rm , CMOVE64rm>;
1004 defm : CMOVmr<X86_COND_BE, CMOVA16rm , CMOVA32rm , CMOVA64rm>;
1005 defm : CMOVmr<X86_COND_A , CMOVBE16rm, CMOVBE32rm, CMOVBE64rm>;
1006 defm : CMOVmr<X86_COND_L , CMOVGE16rm, CMOVGE32rm, CMOVGE64rm>;
1007 defm : CMOVmr<X86_COND_GE, CMOVL16rm , CMOVL32rm , CMOVL64rm>;
1008 defm : CMOVmr<X86_COND_LE, CMOVG16rm , CMOVG32rm , CMOVG64rm>;
1009 defm : CMOVmr<X86_COND_G , CMOVLE16rm, CMOVLE32rm, CMOVLE64rm>;
1010 defm : CMOVmr<X86_COND_P , CMOVNP16rm, CMOVNP32rm, CMOVNP64rm>;
1011 defm : CMOVmr<X86_COND_NP, CMOVP16rm , CMOVP32rm , CMOVP64rm>;
1012 defm : CMOVmr<X86_COND_S , CMOVNS16rm, CMOVNS32rm, CMOVNS64rm>;
1013 defm : CMOVmr<X86_COND_NS, CMOVS16rm , CMOVS32rm , CMOVS64rm>;
1014 defm : CMOVmr<X86_COND_O , CMOVNO16rm, CMOVNO32rm, CMOVNO64rm>;
1015 defm : CMOVmr<X86_COND_NO, CMOVO16rm , CMOVO32rm , CMOVO64rm>;
1017 // zextload bool -> zextload byte
1018 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
1019 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
1020 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
1021 def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1023 // extload bool -> extload byte
1024 // When extloading from 16-bit and smaller memory locations into 64-bit
1025 // registers, use zero-extending loads so that the entire 64-bit register is
1026 // defined, avoiding partial-register updates.
1028 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
1029 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
1030 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
1031 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
1032 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
1033 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
1035 def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1036 def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>;
1037 def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
1038 // For other extloads, use subregs, since the high contents of the register are
1039 // defined after an extload.
1040 def : Pat<(extloadi64i32 addr:$src),
1041 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src),
1044 // anyext. Define these to do an explicit zero-extend to
1045 // avoid partial-register updates.
1046 def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG
1047 (MOVZX32rr8 GR8 :$src), sub_16bit)>;
1048 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
1050 // Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
1051 def : Pat<(i32 (anyext GR16:$src)),
1052 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>;
1054 def : Pat<(i64 (anyext GR8 :$src)), (MOVZX64rr8 GR8 :$src)>;
1055 def : Pat<(i64 (anyext GR16:$src)), (MOVZX64rr16 GR16 :$src)>;
1056 def : Pat<(i64 (anyext GR32:$src)),
1057 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1060 // Any instruction that defines a 32-bit result leaves the high half of the
1061 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
1062 // be copying from a truncate. And x86's cmov doesn't do anything if the
1063 // condition is false. But any other 32-bit operation will zero-extend
1065 def def32 : PatLeaf<(i32 GR32:$src), [{
1066 return N->getOpcode() != ISD::TRUNCATE &&
1067 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
1068 N->getOpcode() != ISD::CopyFromReg &&
1069 N->getOpcode() != X86ISD::CMOV;
1072 // In the case of a 32-bit def that is known to implicitly zero-extend,
1073 // we can use a SUBREG_TO_REG.
1074 def : Pat<(i64 (zext def32:$src)),
1075 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1077 //===----------------------------------------------------------------------===//
1078 // Pattern match OR as ADD
1079 //===----------------------------------------------------------------------===//
1081 // If safe, we prefer to pattern match OR as ADD at isel time. ADD can be
1082 // 3-addressified into an LEA instruction to avoid copies. However, we also
1083 // want to finally emit these instructions as an or at the end of the code
1084 // generator to make the generated code easier to read. To do this, we select
1085 // into "disjoint bits" pseudo ops.
1087 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
1088 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
1089 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1090 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
1092 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
1093 APInt Mask = APInt::getAllOnesValue(BitWidth);
1094 APInt KnownZero0, KnownOne0;
1095 CurDAG->ComputeMaskedBits(N->getOperand(0), Mask, KnownZero0, KnownOne0, 0);
1096 APInt KnownZero1, KnownOne1;
1097 CurDAG->ComputeMaskedBits(N->getOperand(1), Mask, KnownZero1, KnownOne1, 0);
1098 return (~KnownZero0 & ~KnownZero1) == 0;
1102 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
1103 let AddedComplexity = 5 in { // Try this before the selecting to OR
1105 let isConvertibleToThreeAddress = 1,
1106 Constraints = "$src1 = $dst", Defs = [EFLAGS] in {
1107 let isCommutable = 1 in {
1108 def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1109 "", // orw/addw REG, REG
1110 [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>;
1111 def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1112 "", // orl/addl REG, REG
1113 [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>;
1114 def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1115 "", // orq/addq REG, REG
1116 [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>;
1119 // NOTE: These are order specific, we want the ri8 forms to be listed
1120 // first so that they are slightly preferred to the ri forms.
1122 def ADD16ri8_DB : I<0, Pseudo,
1123 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1124 "", // orw/addw REG, imm8
1125 [(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>;
1126 def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1127 "", // orw/addw REG, imm
1128 [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>;
1130 def ADD32ri8_DB : I<0, Pseudo,
1131 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1132 "", // orl/addl REG, imm8
1133 [(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>;
1134 def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1135 "", // orl/addl REG, imm
1136 [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>;
1139 def ADD64ri8_DB : I<0, Pseudo,
1140 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
1141 "", // orq/addq REG, imm8
1142 [(set GR64:$dst, (or_is_add GR64:$src1,
1143 i64immSExt8:$src2))]>;
1144 def ADD64ri32_DB : I<0, Pseudo,
1145 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1146 "", // orq/addq REG, imm
1147 [(set GR64:$dst, (or_is_add GR64:$src1,
1148 i64immSExt32:$src2))]>;
1150 } // AddedComplexity
1153 //===----------------------------------------------------------------------===//
1155 //===----------------------------------------------------------------------===//
1157 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1158 // +128 doesn't, so in this special case use a sub instead of an add.
1159 def : Pat<(add GR16:$src1, 128),
1160 (SUB16ri8 GR16:$src1, -128)>;
1161 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
1162 (SUB16mi8 addr:$dst, -128)>;
1164 def : Pat<(add GR32:$src1, 128),
1165 (SUB32ri8 GR32:$src1, -128)>;
1166 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
1167 (SUB32mi8 addr:$dst, -128)>;
1169 def : Pat<(add GR64:$src1, 128),
1170 (SUB64ri8 GR64:$src1, -128)>;
1171 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1172 (SUB64mi8 addr:$dst, -128)>;
1174 // The same trick applies for 32-bit immediate fields in 64-bit
1176 def : Pat<(add GR64:$src1, 0x0000000080000000),
1177 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1178 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1179 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1181 // To avoid needing to materialize an immediate in a register, use a 32-bit and
1182 // with implicit zero-extension instead of a 64-bit and if the immediate has at
1183 // least 32 bits of leading zeros. If in addition the last 32 bits can be
1184 // represented with a sign extension of a 8 bit constant, use that.
1186 def : Pat<(and GR64:$src, i64immZExt32SExt8:$imm),
1190 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1191 (i32 (GetLo8XForm imm:$imm))),
1194 def : Pat<(and GR64:$src, i64immZExt32:$imm),
1198 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1199 (i32 (GetLo32XForm imm:$imm))),
1203 // r & (2^16-1) ==> movz
1204 def : Pat<(and GR32:$src1, 0xffff),
1205 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
1206 // r & (2^8-1) ==> movz
1207 def : Pat<(and GR32:$src1, 0xff),
1208 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
1211 Requires<[In32BitMode]>;
1212 // r & (2^8-1) ==> movz
1213 def : Pat<(and GR16:$src1, 0xff),
1214 (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG
1215 (i16 (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD)), sub_8bit)),
1217 Requires<[In32BitMode]>;
1219 // r & (2^32-1) ==> movz
1220 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1221 (MOVZX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
1222 // r & (2^16-1) ==> movz
1223 def : Pat<(and GR64:$src, 0xffff),
1224 (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit)))>;
1225 // r & (2^8-1) ==> movz
1226 def : Pat<(and GR64:$src, 0xff),
1227 (MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit)))>;
1228 // r & (2^8-1) ==> movz
1229 def : Pat<(and GR32:$src1, 0xff),
1230 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>,
1231 Requires<[In64BitMode]>;
1232 // r & (2^8-1) ==> movz
1233 def : Pat<(and GR16:$src1, 0xff),
1234 (EXTRACT_SUBREG (MOVZX32rr8 (i8
1235 (EXTRACT_SUBREG GR16:$src1, sub_8bit))), sub_16bit)>,
1236 Requires<[In64BitMode]>;
1239 // sext_inreg patterns
1240 def : Pat<(sext_inreg GR32:$src, i16),
1241 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>;
1242 def : Pat<(sext_inreg GR32:$src, i8),
1243 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1246 Requires<[In32BitMode]>;
1248 def : Pat<(sext_inreg GR16:$src, i8),
1249 (EXTRACT_SUBREG (i32 (MOVSX32rr8 (EXTRACT_SUBREG
1250 (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), sub_8bit))),
1252 Requires<[In32BitMode]>;
1254 def : Pat<(sext_inreg GR64:$src, i32),
1255 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
1256 def : Pat<(sext_inreg GR64:$src, i16),
1257 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>;
1258 def : Pat<(sext_inreg GR64:$src, i8),
1259 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>;
1260 def : Pat<(sext_inreg GR32:$src, i8),
1261 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>,
1262 Requires<[In64BitMode]>;
1263 def : Pat<(sext_inreg GR16:$src, i8),
1264 (EXTRACT_SUBREG (MOVSX32rr8
1265 (EXTRACT_SUBREG GR16:$src, sub_8bit)), sub_16bit)>,
1266 Requires<[In64BitMode]>;
1268 // sext, sext_load, zext, zext_load
1269 def: Pat<(i16 (sext GR8:$src)),
1270 (EXTRACT_SUBREG (MOVSX32rr8 GR8:$src), sub_16bit)>;
1271 def: Pat<(sextloadi16i8 addr:$src),
1272 (EXTRACT_SUBREG (MOVSX32rm8 addr:$src), sub_16bit)>;
1273 def: Pat<(i16 (zext GR8:$src)),
1274 (EXTRACT_SUBREG (MOVZX32rr8 GR8:$src), sub_16bit)>;
1275 def: Pat<(zextloadi16i8 addr:$src),
1276 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>;
1279 def : Pat<(i16 (trunc GR32:$src)),
1280 (EXTRACT_SUBREG GR32:$src, sub_16bit)>;
1281 def : Pat<(i8 (trunc GR32:$src)),
1282 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1284 Requires<[In32BitMode]>;
1285 def : Pat<(i8 (trunc GR16:$src)),
1286 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1288 Requires<[In32BitMode]>;
1289 def : Pat<(i32 (trunc GR64:$src)),
1290 (EXTRACT_SUBREG GR64:$src, sub_32bit)>;
1291 def : Pat<(i16 (trunc GR64:$src)),
1292 (EXTRACT_SUBREG GR64:$src, sub_16bit)>;
1293 def : Pat<(i8 (trunc GR64:$src)),
1294 (EXTRACT_SUBREG GR64:$src, sub_8bit)>;
1295 def : Pat<(i8 (trunc GR32:$src)),
1296 (EXTRACT_SUBREG GR32:$src, sub_8bit)>,
1297 Requires<[In64BitMode]>;
1298 def : Pat<(i8 (trunc GR16:$src)),
1299 (EXTRACT_SUBREG GR16:$src, sub_8bit)>,
1300 Requires<[In64BitMode]>;
1302 // h-register tricks
1303 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
1304 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1306 Requires<[In32BitMode]>;
1307 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
1308 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1310 Requires<[In32BitMode]>;
1311 def : Pat<(srl GR16:$src, (i8 8)),
1314 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1317 Requires<[In32BitMode]>;
1318 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1319 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1322 Requires<[In32BitMode]>;
1323 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1324 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1327 Requires<[In32BitMode]>;
1328 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1329 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1332 Requires<[In32BitMode]>;
1333 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1334 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1337 Requires<[In32BitMode]>;
1339 // h-register tricks.
1340 // For now, be conservative on x86-64 and use an h-register extract only if the
1341 // value is immediately zero-extended or stored, which are somewhat common
1342 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
1343 // from being allocated in the same instruction as the h register, as there's
1344 // currently no way to describe this requirement to the register allocator.
1346 // h-register extract and zero-extend.
1347 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
1351 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1354 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1356 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1358 Requires<[In64BitMode]>;
1359 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1360 (MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1363 Requires<[In64BitMode]>;
1364 def : Pat<(srl GR16:$src, (i8 8)),
1367 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1370 Requires<[In64BitMode]>;
1371 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1373 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1375 Requires<[In64BitMode]>;
1376 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1378 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1380 Requires<[In64BitMode]>;
1381 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
1385 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1388 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
1392 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1396 // h-register extract and store.
1397 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
1400 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1402 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
1405 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1407 Requires<[In64BitMode]>;
1408 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
1411 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1413 Requires<[In64BitMode]>;
1416 // (shl x, 1) ==> (add x, x)
1417 // Note that if x is undef (immediate or otherwise), we could theoretically
1418 // end up with the two uses of x getting different values, producing a result
1419 // where the least significant bit is not 0. However, the probability of this
1420 // happening is considered low enough that this is officially not a
1422 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
1423 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
1424 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
1425 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1427 // (shl x (and y, 31)) ==> (shl x, y)
1428 def : Pat<(shl GR8:$src1, (and CL, 31)),
1429 (SHL8rCL GR8:$src1)>;
1430 def : Pat<(shl GR16:$src1, (and CL, 31)),
1431 (SHL16rCL GR16:$src1)>;
1432 def : Pat<(shl GR32:$src1, (and CL, 31)),
1433 (SHL32rCL GR32:$src1)>;
1434 def : Pat<(store (shl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
1435 (SHL8mCL addr:$dst)>;
1436 def : Pat<(store (shl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
1437 (SHL16mCL addr:$dst)>;
1438 def : Pat<(store (shl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
1439 (SHL32mCL addr:$dst)>;
1441 def : Pat<(srl GR8:$src1, (and CL, 31)),
1442 (SHR8rCL GR8:$src1)>;
1443 def : Pat<(srl GR16:$src1, (and CL, 31)),
1444 (SHR16rCL GR16:$src1)>;
1445 def : Pat<(srl GR32:$src1, (and CL, 31)),
1446 (SHR32rCL GR32:$src1)>;
1447 def : Pat<(store (srl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
1448 (SHR8mCL addr:$dst)>;
1449 def : Pat<(store (srl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
1450 (SHR16mCL addr:$dst)>;
1451 def : Pat<(store (srl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
1452 (SHR32mCL addr:$dst)>;
1454 def : Pat<(sra GR8:$src1, (and CL, 31)),
1455 (SAR8rCL GR8:$src1)>;
1456 def : Pat<(sra GR16:$src1, (and CL, 31)),
1457 (SAR16rCL GR16:$src1)>;
1458 def : Pat<(sra GR32:$src1, (and CL, 31)),
1459 (SAR32rCL GR32:$src1)>;
1460 def : Pat<(store (sra (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
1461 (SAR8mCL addr:$dst)>;
1462 def : Pat<(store (sra (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
1463 (SAR16mCL addr:$dst)>;
1464 def : Pat<(store (sra (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
1465 (SAR32mCL addr:$dst)>;
1467 // (shl x (and y, 63)) ==> (shl x, y)
1468 def : Pat<(shl GR64:$src1, (and CL, 63)),
1469 (SHL64rCL GR64:$src1)>;
1470 def : Pat<(store (shl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1471 (SHL64mCL addr:$dst)>;
1473 def : Pat<(srl GR64:$src1, (and CL, 63)),
1474 (SHR64rCL GR64:$src1)>;
1475 def : Pat<(store (srl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1476 (SHR64mCL addr:$dst)>;
1478 def : Pat<(sra GR64:$src1, (and CL, 63)),
1479 (SAR64rCL GR64:$src1)>;
1480 def : Pat<(store (sra (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1481 (SAR64mCL addr:$dst)>;
1484 // (anyext (setcc_carry)) -> (setcc_carry)
1485 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1487 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1489 def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))),
1495 //===----------------------------------------------------------------------===//
1496 // EFLAGS-defining Patterns
1497 //===----------------------------------------------------------------------===//
1500 def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>;
1501 def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
1502 def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
1505 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
1506 (ADD8rm GR8:$src1, addr:$src2)>;
1507 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
1508 (ADD16rm GR16:$src1, addr:$src2)>;
1509 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
1510 (ADD32rm GR32:$src1, addr:$src2)>;
1513 def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>;
1514 def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
1515 def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
1516 def : Pat<(add GR16:$src1, i16immSExt8:$src2),
1517 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
1518 def : Pat<(add GR32:$src1, i32immSExt8:$src2),
1519 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
1522 def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>;
1523 def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
1524 def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
1527 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
1528 (SUB8rm GR8:$src1, addr:$src2)>;
1529 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
1530 (SUB16rm GR16:$src1, addr:$src2)>;
1531 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
1532 (SUB32rm GR32:$src1, addr:$src2)>;
1535 def : Pat<(sub GR8:$src1, imm:$src2),
1536 (SUB8ri GR8:$src1, imm:$src2)>;
1537 def : Pat<(sub GR16:$src1, imm:$src2),
1538 (SUB16ri GR16:$src1, imm:$src2)>;
1539 def : Pat<(sub GR32:$src1, imm:$src2),
1540 (SUB32ri GR32:$src1, imm:$src2)>;
1541 def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
1542 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
1543 def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
1544 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
1547 def : Pat<(mul GR16:$src1, GR16:$src2),
1548 (IMUL16rr GR16:$src1, GR16:$src2)>;
1549 def : Pat<(mul GR32:$src1, GR32:$src2),
1550 (IMUL32rr GR32:$src1, GR32:$src2)>;
1553 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
1554 (IMUL16rm GR16:$src1, addr:$src2)>;
1555 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
1556 (IMUL32rm GR32:$src1, addr:$src2)>;
1559 def : Pat<(mul GR16:$src1, imm:$src2),
1560 (IMUL16rri GR16:$src1, imm:$src2)>;
1561 def : Pat<(mul GR32:$src1, imm:$src2),
1562 (IMUL32rri GR32:$src1, imm:$src2)>;
1563 def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
1564 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
1565 def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
1566 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
1568 // reg = mul mem, imm
1569 def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
1570 (IMUL16rmi addr:$src1, imm:$src2)>;
1571 def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
1572 (IMUL32rmi addr:$src1, imm:$src2)>;
1573 def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
1574 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
1575 def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
1576 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
1578 // Patterns for nodes that do not produce flags, for instructions that do.
1581 def : Pat<(add GR64:$src1, GR64:$src2),
1582 (ADD64rr GR64:$src1, GR64:$src2)>;
1583 def : Pat<(add GR64:$src1, i64immSExt8:$src2),
1584 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1585 def : Pat<(add GR64:$src1, i64immSExt32:$src2),
1586 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1587 def : Pat<(add GR64:$src1, (loadi64 addr:$src2)),
1588 (ADD64rm GR64:$src1, addr:$src2)>;
1591 def : Pat<(sub GR64:$src1, GR64:$src2),
1592 (SUB64rr GR64:$src1, GR64:$src2)>;
1593 def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)),
1594 (SUB64rm GR64:$src1, addr:$src2)>;
1595 def : Pat<(sub GR64:$src1, i64immSExt8:$src2),
1596 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1597 def : Pat<(sub GR64:$src1, i64immSExt32:$src2),
1598 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1601 def : Pat<(mul GR64:$src1, GR64:$src2),
1602 (IMUL64rr GR64:$src1, GR64:$src2)>;
1603 def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)),
1604 (IMUL64rm GR64:$src1, addr:$src2)>;
1605 def : Pat<(mul GR64:$src1, i64immSExt8:$src2),
1606 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
1607 def : Pat<(mul GR64:$src1, i64immSExt32:$src2),
1608 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
1609 def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2),
1610 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
1611 def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2),
1612 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
1615 def : Pat<(add GR8 :$src, 1), (INC8r GR8 :$src)>;
1616 def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>, Requires<[In32BitMode]>;
1617 def : Pat<(add GR16:$src, 1), (INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1618 def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>, Requires<[In32BitMode]>;
1619 def : Pat<(add GR32:$src, 1), (INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1620 def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>;
1623 def : Pat<(add GR8 :$src, -1), (DEC8r GR8 :$src)>;
1624 def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
1625 def : Pat<(add GR16:$src, -1), (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1626 def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
1627 def : Pat<(add GR32:$src, -1), (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1628 def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>;
1631 def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
1632 def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
1633 def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
1634 def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>;
1637 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
1638 (OR8rm GR8:$src1, addr:$src2)>;
1639 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
1640 (OR16rm GR16:$src1, addr:$src2)>;
1641 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
1642 (OR32rm GR32:$src1, addr:$src2)>;
1643 def : Pat<(or GR64:$src1, (loadi64 addr:$src2)),
1644 (OR64rm GR64:$src1, addr:$src2)>;
1647 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
1648 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
1649 def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
1650 def : Pat<(or GR16:$src1, i16immSExt8:$src2),
1651 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1652 def : Pat<(or GR32:$src1, i32immSExt8:$src2),
1653 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1654 def : Pat<(or GR64:$src1, i64immSExt8:$src2),
1655 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1656 def : Pat<(or GR64:$src1, i64immSExt32:$src2),
1657 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1660 def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>;
1661 def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
1662 def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
1663 def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>;
1666 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
1667 (XOR8rm GR8:$src1, addr:$src2)>;
1668 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
1669 (XOR16rm GR16:$src1, addr:$src2)>;
1670 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
1671 (XOR32rm GR32:$src1, addr:$src2)>;
1672 def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)),
1673 (XOR64rm GR64:$src1, addr:$src2)>;
1676 def : Pat<(xor GR8:$src1, imm:$src2),
1677 (XOR8ri GR8:$src1, imm:$src2)>;
1678 def : Pat<(xor GR16:$src1, imm:$src2),
1679 (XOR16ri GR16:$src1, imm:$src2)>;
1680 def : Pat<(xor GR32:$src1, imm:$src2),
1681 (XOR32ri GR32:$src1, imm:$src2)>;
1682 def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
1683 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1684 def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
1685 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1686 def : Pat<(xor GR64:$src1, i64immSExt8:$src2),
1687 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1688 def : Pat<(xor GR64:$src1, i64immSExt32:$src2),
1689 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1692 def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>;
1693 def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
1694 def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
1695 def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>;
1698 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
1699 (AND8rm GR8:$src1, addr:$src2)>;
1700 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
1701 (AND16rm GR16:$src1, addr:$src2)>;
1702 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
1703 (AND32rm GR32:$src1, addr:$src2)>;
1704 def : Pat<(and GR64:$src1, (loadi64 addr:$src2)),
1705 (AND64rm GR64:$src1, addr:$src2)>;
1708 def : Pat<(and GR8:$src1, imm:$src2),
1709 (AND8ri GR8:$src1, imm:$src2)>;
1710 def : Pat<(and GR16:$src1, imm:$src2),
1711 (AND16ri GR16:$src1, imm:$src2)>;
1712 def : Pat<(and GR32:$src1, imm:$src2),
1713 (AND32ri GR32:$src1, imm:$src2)>;
1714 def : Pat<(and GR16:$src1, i16immSExt8:$src2),
1715 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
1716 def : Pat<(and GR32:$src1, i32immSExt8:$src2),
1717 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
1718 def : Pat<(and GR64:$src1, i64immSExt8:$src2),
1719 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
1720 def : Pat<(and GR64:$src1, i64immSExt32:$src2),
1721 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>;
1723 def : Pat<(atomic_load_8 addr:$src), (MOV8rm addr:$src)>;
1724 def : Pat<(atomic_load_16 addr:$src), (MOV16rm addr:$src)>;
1725 def : Pat<(atomic_load_32 addr:$src), (MOV32rm addr:$src)>;
1726 def : Pat<(atomic_load_64 addr:$src), (MOV64rm addr:$src)>;
1728 def : Pat<(atomic_store_8 addr:$ptr, GR8:$val),
1729 (MOV8mr addr:$ptr, GR8:$val)>;
1730 def : Pat<(atomic_store_16 addr:$ptr, GR16:$val),
1731 (MOV16mr addr:$ptr, GR16:$val)>;
1732 def : Pat<(atomic_store_32 addr:$ptr, GR32:$val),
1733 (MOV32mr addr:$ptr, GR32:$val)>;
1734 def : Pat<(atomic_store_64 addr:$ptr, GR64:$val),
1735 (MOV64mr addr:$ptr, GR64:$val)>;