1 //===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the various pseudo instructions used by the compiler,
11 // as well as Pat patterns used during instruction selection.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Pattern Matching Support
18 def GetLo32XForm : SDNodeXForm<imm, [{
19 // Transformation function: get the low 32 bits.
20 return getI32Imm((unsigned)N->getZExtValue());
23 def GetLo8XForm : SDNodeXForm<imm, [{
24 // Transformation function: get the low 8 bits.
25 return getI8Imm((uint8_t)N->getZExtValue());
29 //===----------------------------------------------------------------------===//
30 // Random Pseudo Instructions.
32 // PIC base construction. This expands to code that looks like this:
35 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
36 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
40 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
41 // a stack adjustment and the codegen must know that they may modify the stack
42 // pointer before prolog-epilog rewriting occurs.
43 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
44 // sub / add which can clobber EFLAGS.
45 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
46 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
48 [(X86callseq_start timm:$amt)]>,
49 Requires<[In32BitMode]>;
50 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
52 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
53 Requires<[In32BitMode]>;
56 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
57 // a stack adjustment and the codegen must know that they may modify the stack
58 // pointer before prolog-epilog rewriting occurs.
59 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
60 // sub / add which can clobber EFLAGS.
61 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
62 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
64 [(X86callseq_start timm:$amt)]>,
65 Requires<[In64BitMode]>;
66 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
68 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
69 Requires<[In64BitMode]>;
74 // x86-64 va_start lowering magic.
75 let usesCustomInserter = 1 in {
76 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
79 i64imm:$regsavefi, i64imm:$offset,
81 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
82 [(X86vastart_save_xmm_regs GR8:$al,
86 // The VAARG_64 pseudo-instruction takes the address of the va_list,
87 // and places the address of the next argument into a register.
88 let Defs = [EFLAGS] in
89 def VAARG_64 : I<0, Pseudo,
91 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align),
92 "#VAARG_64 $dst, $ap, $size, $mode, $align",
94 (X86vaarg64 addr:$ap, imm:$size, imm:$mode, imm:$align)),
97 // Dynamic stack allocation yields a _chkstk or _alloca call for all Windows
98 // targets. These calls are needed to probe the stack when allocating more than
99 // 4k bytes in one go. Touching the stack at 4K increments is necessary to
100 // ensure that the guard pages used by the OS virtual memory manager are
101 // allocated in correct sequence.
102 // The main point of having separate instruction are extra unmodelled effects
103 // (compared to ordinary calls) like stack pointer change.
105 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
106 def WIN_ALLOCA : I<0, Pseudo, (outs), (ins),
107 "# dynamic stack allocation",
110 // When using segmented stacks these are lowered into instructions which first
111 // check if the current stacklet has enough free memory. If it does, memory is
112 // allocated by bumping the stack pointer. Otherwise memory is allocated from
115 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP, EAX] in
116 def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size),
117 "# variable sized alloca for segmented stacks",
119 (X86SegAlloca GR32:$size))]>,
120 Requires<[In32BitMode]>;
122 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP, RAX] in
123 def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size),
124 "# variable sized alloca for segmented stacks",
126 (X86SegAlloca GR64:$size))]>,
127 Requires<[In64BitMode]>;
133 //===----------------------------------------------------------------------===//
134 // EH Pseudo Instructions
136 let isTerminator = 1, isReturn = 1, isBarrier = 1,
137 hasCtrlDep = 1, isCodeGenOnly = 1 in {
138 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
139 "ret\t#eh_return, addr: $addr",
140 [(X86ehret GR32:$addr)]>;
144 let isTerminator = 1, isReturn = 1, isBarrier = 1,
145 hasCtrlDep = 1, isCodeGenOnly = 1 in {
146 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
147 "ret\t#eh_return, addr: $addr",
148 [(X86ehret GR64:$addr)]>;
152 //===----------------------------------------------------------------------===//
153 // Alias Instructions
154 //===----------------------------------------------------------------------===//
156 // Alias instructions that map movr0 to xor.
157 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
158 // FIXME: Set encoding to pseudo.
159 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
160 isCodeGenOnly = 1 in {
161 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "",
162 [(set GR8:$dst, 0)]>;
164 // We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller
165 // encoding and avoids a partial-register update sometimes, but doing so
166 // at isel time interferes with rematerialization in the current register
167 // allocator. For now, this is rewritten when the instruction is lowered
169 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
171 [(set GR16:$dst, 0)]>, OpSize;
173 // FIXME: Set encoding to pseudo.
174 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "",
175 [(set GR32:$dst, 0)]>;
178 // We want to rewrite MOV64r0 in terms of MOV32r0, because it's sometimes a
179 // smaller encoding, but doing so at isel time interferes with rematerialization
180 // in the current register allocator. For now, this is rewritten when the
181 // instruction is lowered to an MCInst.
182 // FIXME: AddedComplexity gives this a higher priority than MOV64ri32. Remove
183 // when we have a better way to specify isel priority.
184 let Defs = [EFLAGS], isCodeGenOnly=1,
185 AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
186 def MOV64r0 : I<0x31, MRMInitReg, (outs GR64:$dst), (ins), "",
187 [(set GR64:$dst, 0)]>;
189 // Materialize i64 constant where top 32-bits are zero. This could theoretically
190 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
191 // that would make it more difficult to rematerialize.
192 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1,
194 def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
195 "", [(set GR64:$dst, i64immZExt32:$src)]>;
197 // Use sbb to materialize carry bit.
198 let Uses = [EFLAGS], Defs = [EFLAGS], isCodeGenOnly = 1 in {
199 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
200 // However, Pat<> can't replicate the destination reg into the inputs of the
202 // FIXME: Change these to have encoding Pseudo when X86MCCodeEmitter replaces
204 def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins), "",
205 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
206 def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins), "",
207 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>,
209 def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins), "",
210 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
211 def SETB_C64r : RI<0x19, MRMInitReg, (outs GR64:$dst), (ins), "",
212 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
216 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
218 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
220 def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
223 def : Pat<(i16 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
225 def : Pat<(i32 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
227 def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
230 // We canonicalize 'setb' to "(and (sbb reg,reg), 1)" on the hope that the and
231 // will be eliminated and that the sbb can be extended up to a wider type. When
232 // this happens, it is great. However, if we are left with an 8-bit sbb and an
233 // and, we might as well just match it as a setb.
234 def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1),
237 // (add OP, SETB) -> (adc OP, 0)
238 def : Pat<(add (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR8:$op),
239 (ADC8ri GR8:$op, 0)>;
240 def : Pat<(add (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR32:$op),
241 (ADC32ri8 GR32:$op, 0)>;
242 def : Pat<(add (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR64:$op),
243 (ADC64ri8 GR64:$op, 0)>;
245 // (sub OP, SETB) -> (sbb OP, 0)
246 def : Pat<(sub GR8:$op, (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
247 (SBB8ri GR8:$op, 0)>;
248 def : Pat<(sub GR32:$op, (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
249 (SBB32ri8 GR32:$op, 0)>;
250 def : Pat<(sub GR64:$op, (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
251 (SBB64ri8 GR64:$op, 0)>;
253 // (sub OP, SETCC_CARRY) -> (adc OP, 0)
254 def : Pat<(sub GR8:$op, (i8 (X86setcc_c X86_COND_B, EFLAGS))),
255 (ADC8ri GR8:$op, 0)>;
256 def : Pat<(sub GR32:$op, (i32 (X86setcc_c X86_COND_B, EFLAGS))),
257 (ADC32ri8 GR32:$op, 0)>;
258 def : Pat<(sub GR64:$op, (i64 (X86setcc_c X86_COND_B, EFLAGS))),
259 (ADC64ri8 GR64:$op, 0)>;
261 //===----------------------------------------------------------------------===//
262 // String Pseudo Instructions
264 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
265 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
266 [(X86rep_movs i8)]>, REP;
267 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
268 [(X86rep_movs i16)]>, REP, OpSize;
269 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
270 [(X86rep_movs i32)]>, REP;
273 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in
274 def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
275 [(X86rep_movs i64)]>, REP;
278 // FIXME: Should use "(X86rep_stos AL)" as the pattern.
279 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI], isCodeGenOnly = 1 in
280 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
281 [(X86rep_stos i8)]>, REP;
282 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI], isCodeGenOnly = 1 in
283 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
284 [(X86rep_stos i16)]>, REP, OpSize;
285 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI], isCodeGenOnly = 1 in
286 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
287 [(X86rep_stos i32)]>, REP;
289 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI], isCodeGenOnly = 1 in
290 def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
291 [(X86rep_stos i64)]>, REP;
294 //===----------------------------------------------------------------------===//
295 // Thread Local Storage Instructions
299 // All calls clobber the non-callee saved registers. ESP is marked as
300 // a use to prevent stack-pointer assignments that appear immediately
301 // before calls from potentially appearing dead.
302 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
303 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
304 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
305 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
307 def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
309 [(X86tlsaddr tls32addr:$sym)]>,
310 Requires<[In32BitMode]>;
312 // All calls clobber the non-callee saved registers. RSP is marked as
313 // a use to prevent stack-pointer assignments that appear immediately
314 // before calls from potentially appearing dead.
315 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
316 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
317 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
318 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
319 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
321 def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
323 [(X86tlsaddr tls64addr:$sym)]>,
324 Requires<[In64BitMode]>;
326 // Darwin TLS Support
327 // For i386, the address of the thunk is passed on the stack, on return the
328 // address of the variable is in %eax. %ecx is trashed during the function
329 // call. All other registers are preserved.
330 let Defs = [EAX, ECX, EFLAGS],
332 usesCustomInserter = 1 in
333 def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
335 [(X86TLSCall addr:$sym)]>,
336 Requires<[In32BitMode]>;
338 // For x86_64, the address of the thunk is passed in %rdi, on return
339 // the address of the variable is in %rax. All other registers are preserved.
340 let Defs = [RAX, EFLAGS],
342 usesCustomInserter = 1 in
343 def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
345 [(X86TLSCall addr:$sym)]>,
346 Requires<[In64BitMode]>;
349 //===----------------------------------------------------------------------===//
350 // Conditional Move Pseudo Instructions
352 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
353 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
354 // however that requires promoting the operands, and can induce additional
355 // i8 register pressure.
356 let usesCustomInserter = 1, Uses = [EFLAGS] in {
357 def CMOV_GR8 : I<0, Pseudo,
358 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
360 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
361 imm:$cond, EFLAGS))]>;
363 let Predicates = [NoCMov] in {
364 def CMOV_GR32 : I<0, Pseudo,
365 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cond),
366 "#CMOV_GR32* PSEUDO!",
368 (X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>;
369 def CMOV_GR16 : I<0, Pseudo,
370 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cond),
371 "#CMOV_GR16* PSEUDO!",
373 (X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>;
374 def CMOV_RFP32 : I<0, Pseudo,
376 (ins RFP32:$src1, RFP32:$src2, i8imm:$cond),
377 "#CMOV_RFP32 PSEUDO!",
379 (X86cmov RFP32:$src1, RFP32:$src2, imm:$cond,
381 def CMOV_RFP64 : I<0, Pseudo,
383 (ins RFP64:$src1, RFP64:$src2, i8imm:$cond),
384 "#CMOV_RFP64 PSEUDO!",
386 (X86cmov RFP64:$src1, RFP64:$src2, imm:$cond,
388 def CMOV_RFP80 : I<0, Pseudo,
390 (ins RFP80:$src1, RFP80:$src2, i8imm:$cond),
391 "#CMOV_RFP80 PSEUDO!",
393 (X86cmov RFP80:$src1, RFP80:$src2, imm:$cond,
395 } // Predicates = [NoCMov]
396 } // UsesCustomInserter = 1, Uses = [EFLAGS]
399 //===----------------------------------------------------------------------===//
400 // Atomic Instruction Pseudo Instructions
401 //===----------------------------------------------------------------------===//
403 // Atomic exchange, and, or, xor
404 let Constraints = "$val = $dst", Defs = [EFLAGS],
405 usesCustomInserter = 1 in {
407 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
409 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
410 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
412 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
413 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
415 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
416 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
417 "#ATOMNAND8 PSEUDO!",
418 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
420 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
421 "#ATOMAND16 PSEUDO!",
422 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
423 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
425 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
426 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
427 "#ATOMXOR16 PSEUDO!",
428 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
429 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
430 "#ATOMNAND16 PSEUDO!",
431 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
432 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
433 "#ATOMMIN16 PSEUDO!",
434 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
435 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
436 "#ATOMMAX16 PSEUDO!",
437 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
438 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
439 "#ATOMUMIN16 PSEUDO!",
440 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
441 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
442 "#ATOMUMAX16 PSEUDO!",
443 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
446 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
447 "#ATOMAND32 PSEUDO!",
448 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
449 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
451 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
452 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
453 "#ATOMXOR32 PSEUDO!",
454 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
455 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
456 "#ATOMNAND32 PSEUDO!",
457 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
458 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
459 "#ATOMMIN32 PSEUDO!",
460 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
461 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
462 "#ATOMMAX32 PSEUDO!",
463 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
464 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
465 "#ATOMUMIN32 PSEUDO!",
466 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
467 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
468 "#ATOMUMAX32 PSEUDO!",
469 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
473 def ATOMAND64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
474 "#ATOMAND64 PSEUDO!",
475 [(set GR64:$dst, (atomic_load_and_64 addr:$ptr, GR64:$val))]>;
476 def ATOMOR64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
478 [(set GR64:$dst, (atomic_load_or_64 addr:$ptr, GR64:$val))]>;
479 def ATOMXOR64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
480 "#ATOMXOR64 PSEUDO!",
481 [(set GR64:$dst, (atomic_load_xor_64 addr:$ptr, GR64:$val))]>;
482 def ATOMNAND64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
483 "#ATOMNAND64 PSEUDO!",
484 [(set GR64:$dst, (atomic_load_nand_64 addr:$ptr, GR64:$val))]>;
485 def ATOMMIN64: I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val),
486 "#ATOMMIN64 PSEUDO!",
487 [(set GR64:$dst, (atomic_load_min_64 addr:$ptr, GR64:$val))]>;
488 def ATOMMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
489 "#ATOMMAX64 PSEUDO!",
490 [(set GR64:$dst, (atomic_load_max_64 addr:$ptr, GR64:$val))]>;
491 def ATOMUMIN64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
492 "#ATOMUMIN64 PSEUDO!",
493 [(set GR64:$dst, (atomic_load_umin_64 addr:$ptr, GR64:$val))]>;
494 def ATOMUMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
495 "#ATOMUMAX64 PSEUDO!",
496 [(set GR64:$dst, (atomic_load_umax_64 addr:$ptr, GR64:$val))]>;
499 let Constraints = "$val1 = $dst1, $val2 = $dst2",
500 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
501 Uses = [EAX, EBX, ECX, EDX],
502 mayLoad = 1, mayStore = 1,
503 usesCustomInserter = 1 in {
504 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
505 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
506 "#ATOMAND6432 PSEUDO!", []>;
507 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
508 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
509 "#ATOMOR6432 PSEUDO!", []>;
510 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
511 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
512 "#ATOMXOR6432 PSEUDO!", []>;
513 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
514 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
515 "#ATOMNAND6432 PSEUDO!", []>;
516 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
517 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
518 "#ATOMADD6432 PSEUDO!", []>;
519 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
520 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
521 "#ATOMSUB6432 PSEUDO!", []>;
522 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
523 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
524 "#ATOMSWAP6432 PSEUDO!", []>;
527 //===----------------------------------------------------------------------===//
528 // Normal-Instructions-With-Lock-Prefix Pseudo Instructions
529 //===----------------------------------------------------------------------===//
531 // FIXME: Use normal instructions and add lock prefix dynamically.
535 // TODO: Get this to fold the constant into the instruction.
536 let isCodeGenOnly = 1 in
537 def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero),
539 "or{l}\t{$zero, $dst|$dst, $zero}",
540 []>, Requires<[In32BitMode]>, LOCK;
542 let hasSideEffects = 1 in
543 def Int_MemBarrier : I<0, Pseudo, (outs), (ins),
547 // TODO: Get this to fold the constant into the instruction.
548 let hasSideEffects = 1, Defs = [ESP], isCodeGenOnly = 1 in
549 def Int_MemBarrierNoSSE64 : RI<0x09, MRM1r, (outs), (ins GR64:$zero),
551 "or{q}\t{$zero, (%rsp)|(%rsp), $zero}",
552 [(X86MemBarrierNoSSE GR64:$zero)]>,
553 Requires<[In64BitMode]>, LOCK;
556 // RegOpc corresponds to the mr version of the instruction
557 // ImmOpc corresponds to the mi version of the instruction
558 // ImmOpc8 corresponds to the mi8 version of the instruction
559 // ImmMod corresponds to the instruction format of the mi and mi8 versions
560 multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8,
561 Format ImmMod, string mnemonic> {
562 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1 in {
564 def #NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
565 RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 },
566 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
567 !strconcat("lock\n\t", mnemonic, "{b}\t",
568 "{$src2, $dst|$dst, $src2}"),
570 def #NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
571 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
572 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
573 !strconcat("lock\n\t", mnemonic, "{w}\t",
574 "{$src2, $dst|$dst, $src2}"),
576 def #NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
577 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
578 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
579 !strconcat("lock\n\t", mnemonic, "{l}\t",
580 "{$src2, $dst|$dst, $src2}"),
582 def #NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
583 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
584 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
585 !strconcat("lock\n\t", mnemonic, "{q}\t",
586 "{$src2, $dst|$dst, $src2}"),
589 def #NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
590 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 },
591 ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2),
592 !strconcat("lock\n\t", mnemonic, "{b}\t",
593 "{$src2, $dst|$dst, $src2}"),
596 def #NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
597 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
598 ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2),
599 !strconcat("lock\n\t", mnemonic, "{w}\t",
600 "{$src2, $dst|$dst, $src2}"),
603 def #NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
604 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
605 ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2),
606 !strconcat("lock\n\t", mnemonic, "{l}\t",
607 "{$src2, $dst|$dst, $src2}"),
610 def #NAME#64mi32 : RIi32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
611 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
612 ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2),
613 !strconcat("lock\n\t", mnemonic, "{q}\t",
614 "{$src2, $dst|$dst, $src2}"),
617 def #NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
618 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
619 ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2),
620 !strconcat("lock\n\t", mnemonic, "{w}\t",
621 "{$src2, $dst|$dst, $src2}"),
623 def #NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
624 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
625 ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2),
626 !strconcat("lock\n\t", mnemonic, "{l}\t",
627 "{$src2, $dst|$dst, $src2}"),
629 def #NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
630 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
631 ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2),
632 !strconcat("lock\n\t", mnemonic, "{q}\t",
633 "{$src2, $dst|$dst, $src2}"),
640 defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, "add">;
641 defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, "sub">;
642 defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, "or">;
643 defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, "and">;
644 defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, "xor">;
646 // Optimized codegen when the non-memory output is not used.
647 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1 in {
649 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
651 "inc{b}\t$dst", []>, LOCK;
652 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
654 "inc{w}\t$dst", []>, OpSize, LOCK;
655 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
657 "inc{l}\t$dst", []>, LOCK;
658 def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst),
660 "inc{q}\t$dst", []>, LOCK;
662 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
664 "dec{b}\t$dst", []>, LOCK;
665 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
667 "dec{w}\t$dst", []>, OpSize, LOCK;
668 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
670 "dec{l}\t$dst", []>, LOCK;
671 def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst),
673 "dec{q}\t$dst", []>, LOCK;
676 // Atomic compare and swap.
677 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX],
679 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr),
682 [(X86cas8 addr:$ptr)]>, TB, LOCK;
684 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX],
686 def LCMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$ptr),
689 [(X86cas16 addr:$ptr)]>, TB, LOCK,
690 Requires<[HasCmpxchg16b]>;
692 let Defs = [AL, EFLAGS], Uses = [AL], isCodeGenOnly = 1 in {
693 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
695 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
696 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
699 let Defs = [AX, EFLAGS], Uses = [AX], isCodeGenOnly = 1 in {
700 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
702 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
703 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
706 let Defs = [EAX, EFLAGS], Uses = [EAX], isCodeGenOnly = 1 in {
707 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
709 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
710 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
713 let Defs = [RAX, EFLAGS], Uses = [RAX], isCodeGenOnly = 1 in {
714 def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap),
716 "cmpxchgq\t$swap,$ptr",
717 [(X86cas addr:$ptr, GR64:$swap, 8)]>, TB, LOCK;
720 // Atomic exchange and add
721 let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1 in {
722 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
724 "xadd{b}\t{$val, $ptr|$ptr, $val}",
725 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
727 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins GR16:$val, i16mem:$ptr),
729 "xadd{w}\t{$val, $ptr|$ptr, $val}",
730 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
732 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins GR32:$val, i32mem:$ptr),
734 "xadd{l}\t{$val, $ptr|$ptr, $val}",
735 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
737 def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins GR64:$val,i64mem:$ptr),
740 [(set GR64:$dst, (atomic_load_add_64 addr:$ptr, GR64:$val))]>,
744 //===----------------------------------------------------------------------===//
745 // Conditional Move Pseudo Instructions.
746 //===----------------------------------------------------------------------===//
749 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after
750 // instruction selection into a branch sequence.
751 let Uses = [EFLAGS], usesCustomInserter = 1 in {
752 def CMOV_FR32 : I<0, Pseudo,
753 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
754 "#CMOV_FR32 PSEUDO!",
755 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
757 def CMOV_FR64 : I<0, Pseudo,
758 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
759 "#CMOV_FR64 PSEUDO!",
760 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
762 def CMOV_V4F32 : I<0, Pseudo,
763 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
764 "#CMOV_V4F32 PSEUDO!",
766 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
768 def CMOV_V2F64 : I<0, Pseudo,
769 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
770 "#CMOV_V2F64 PSEUDO!",
772 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
774 def CMOV_V2I64 : I<0, Pseudo,
775 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
776 "#CMOV_V2I64 PSEUDO!",
778 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
780 def CMOV_V8F32 : I<0, Pseudo,
781 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
782 "#CMOV_V8F32 PSEUDO!",
784 (v8f32 (X86cmov VR256:$t, VR256:$f, imm:$cond,
786 def CMOV_V4F64 : I<0, Pseudo,
787 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
788 "#CMOV_V4F64 PSEUDO!",
790 (v4f64 (X86cmov VR256:$t, VR256:$f, imm:$cond,
792 def CMOV_V4I64 : I<0, Pseudo,
793 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
794 "#CMOV_V4I64 PSEUDO!",
796 (v4i64 (X86cmov VR256:$t, VR256:$f, imm:$cond,
801 //===----------------------------------------------------------------------===//
802 // DAG Pattern Matching Rules
803 //===----------------------------------------------------------------------===//
805 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
806 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
807 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
808 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
809 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
810 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
811 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
813 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
814 (ADD32ri GR32:$src1, tconstpool:$src2)>;
815 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
816 (ADD32ri GR32:$src1, tjumptable:$src2)>;
817 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
818 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
819 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
820 (ADD32ri GR32:$src1, texternalsym:$src2)>;
821 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
822 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
824 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
825 (MOV32mi addr:$dst, tglobaladdr:$src)>;
826 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
827 (MOV32mi addr:$dst, texternalsym:$src)>;
828 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
829 (MOV32mi addr:$dst, tblockaddress:$src)>;
833 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
834 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
835 // 'movabs' predicate should handle this sort of thing.
836 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
837 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
838 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
839 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
840 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
841 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
842 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
843 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
844 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
845 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>;
847 // In static codegen with small code model, we can get the address of a label
848 // into a register with 'movl'. FIXME: This is a hack, the 'imm' predicate of
849 // the MOV64ri64i32 should accept these.
850 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
851 (MOV64ri64i32 tconstpool :$dst)>, Requires<[SmallCode]>;
852 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
853 (MOV64ri64i32 tjumptable :$dst)>, Requires<[SmallCode]>;
854 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
855 (MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>;
856 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
857 (MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>;
858 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
859 (MOV64ri64i32 tblockaddress:$dst)>, Requires<[SmallCode]>;
861 // In kernel code model, we can get the address of a label
862 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
863 // the MOV64ri32 should accept these.
864 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
865 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
866 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
867 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
868 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
869 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
870 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
871 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
872 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
873 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>;
875 // If we have small model and -static mode, it is safe to store global addresses
876 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
877 // for MOV64mi32 should handle this sort of thing.
878 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
879 (MOV64mi32 addr:$dst, tconstpool:$src)>,
880 Requires<[NearData, IsStatic]>;
881 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
882 (MOV64mi32 addr:$dst, tjumptable:$src)>,
883 Requires<[NearData, IsStatic]>;
884 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
885 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
886 Requires<[NearData, IsStatic]>;
887 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
888 (MOV64mi32 addr:$dst, texternalsym:$src)>,
889 Requires<[NearData, IsStatic]>;
890 def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst),
891 (MOV64mi32 addr:$dst, tblockaddress:$src)>,
892 Requires<[NearData, IsStatic]>;
898 // tls has some funny stuff here...
899 // This corresponds to movabs $foo@tpoff, %rax
900 def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)),
901 (MOV64ri tglobaltlsaddr :$dst)>;
902 // This corresponds to add $foo@tpoff, %rax
903 def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)),
904 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>;
905 // This corresponds to mov foo@tpoff(%rbx), %eax
906 def : Pat<(load (i64 (X86Wrapper tglobaltlsaddr :$dst))),
907 (MOV64rm tglobaltlsaddr :$dst)>;
910 // Direct PC relative function call for small code model. 32-bit displacement
911 // sign extended to 64-bit.
912 def : Pat<(X86call (i64 tglobaladdr:$dst)),
913 (CALL64pcrel32 tglobaladdr:$dst)>, Requires<[NotWin64]>;
914 def : Pat<(X86call (i64 texternalsym:$dst)),
915 (CALL64pcrel32 texternalsym:$dst)>, Requires<[NotWin64]>;
917 def : Pat<(X86call (i64 tglobaladdr:$dst)),
918 (WINCALL64pcrel32 tglobaladdr:$dst)>, Requires<[IsWin64]>;
919 def : Pat<(X86call (i64 texternalsym:$dst)),
920 (WINCALL64pcrel32 texternalsym:$dst)>, Requires<[IsWin64]>;
923 def : Pat<(X86tcret GR32_TC:$dst, imm:$off),
924 (TCRETURNri GR32_TC:$dst, imm:$off)>,
925 Requires<[In32BitMode]>;
927 // FIXME: This is disabled for 32-bit PIC mode because the global base
928 // register which is part of the address mode may be assigned a
929 // callee-saved register.
930 def : Pat<(X86tcret (load addr:$dst), imm:$off),
931 (TCRETURNmi addr:$dst, imm:$off)>,
932 Requires<[In32BitMode, IsNotPIC]>;
934 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
935 (TCRETURNdi texternalsym:$dst, imm:$off)>,
936 Requires<[In32BitMode]>;
938 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
939 (TCRETURNdi texternalsym:$dst, imm:$off)>,
940 Requires<[In32BitMode]>;
942 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
943 (TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>,
944 Requires<[In64BitMode]>;
946 def : Pat<(X86tcret (load addr:$dst), imm:$off),
947 (TCRETURNmi64 addr:$dst, imm:$off)>,
948 Requires<[In64BitMode]>;
950 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
951 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>,
952 Requires<[In64BitMode]>;
954 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
955 (TCRETURNdi64 texternalsym:$dst, imm:$off)>,
956 Requires<[In64BitMode]>;
958 // Normal calls, with various flavors of addresses.
959 def : Pat<(X86call (i32 tglobaladdr:$dst)),
960 (CALLpcrel32 tglobaladdr:$dst)>;
961 def : Pat<(X86call (i32 texternalsym:$dst)),
962 (CALLpcrel32 texternalsym:$dst)>;
963 def : Pat<(X86call (i32 imm:$dst)),
964 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
968 // TEST R,R is smaller than CMP R,0
969 def : Pat<(X86cmp GR8:$src1, 0),
970 (TEST8rr GR8:$src1, GR8:$src1)>;
971 def : Pat<(X86cmp GR16:$src1, 0),
972 (TEST16rr GR16:$src1, GR16:$src1)>;
973 def : Pat<(X86cmp GR32:$src1, 0),
974 (TEST32rr GR32:$src1, GR32:$src1)>;
975 def : Pat<(X86cmp GR64:$src1, 0),
976 (TEST64rr GR64:$src1, GR64:$src1)>;
978 // Conditional moves with folded loads with operands swapped and conditions
980 multiclass CMOVmr<PatLeaf InvertedCond, Instruction Inst16, Instruction Inst32,
981 Instruction Inst64> {
982 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS),
983 (Inst16 GR16:$src2, addr:$src1)>;
984 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS),
985 (Inst32 GR32:$src2, addr:$src1)>;
986 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS),
987 (Inst64 GR64:$src2, addr:$src1)>;
990 defm : CMOVmr<X86_COND_B , CMOVAE16rm, CMOVAE32rm, CMOVAE64rm>;
991 defm : CMOVmr<X86_COND_AE, CMOVB16rm , CMOVB32rm , CMOVB64rm>;
992 defm : CMOVmr<X86_COND_E , CMOVNE16rm, CMOVNE32rm, CMOVNE64rm>;
993 defm : CMOVmr<X86_COND_NE, CMOVE16rm , CMOVE32rm , CMOVE64rm>;
994 defm : CMOVmr<X86_COND_BE, CMOVA16rm , CMOVA32rm , CMOVA64rm>;
995 defm : CMOVmr<X86_COND_A , CMOVBE16rm, CMOVBE32rm, CMOVBE64rm>;
996 defm : CMOVmr<X86_COND_L , CMOVGE16rm, CMOVGE32rm, CMOVGE64rm>;
997 defm : CMOVmr<X86_COND_GE, CMOVL16rm , CMOVL32rm , CMOVL64rm>;
998 defm : CMOVmr<X86_COND_LE, CMOVG16rm , CMOVG32rm , CMOVG64rm>;
999 defm : CMOVmr<X86_COND_G , CMOVLE16rm, CMOVLE32rm, CMOVLE64rm>;
1000 defm : CMOVmr<X86_COND_P , CMOVNP16rm, CMOVNP32rm, CMOVNP64rm>;
1001 defm : CMOVmr<X86_COND_NP, CMOVP16rm , CMOVP32rm , CMOVP64rm>;
1002 defm : CMOVmr<X86_COND_S , CMOVNS16rm, CMOVNS32rm, CMOVNS64rm>;
1003 defm : CMOVmr<X86_COND_NS, CMOVS16rm , CMOVS32rm , CMOVS64rm>;
1004 defm : CMOVmr<X86_COND_O , CMOVNO16rm, CMOVNO32rm, CMOVNO64rm>;
1005 defm : CMOVmr<X86_COND_NO, CMOVO16rm , CMOVO32rm , CMOVO64rm>;
1007 // zextload bool -> zextload byte
1008 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
1009 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
1010 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
1011 def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1013 // extload bool -> extload byte
1014 // When extloading from 16-bit and smaller memory locations into 64-bit
1015 // registers, use zero-extending loads so that the entire 64-bit register is
1016 // defined, avoiding partial-register updates.
1018 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
1019 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
1020 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
1021 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
1022 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
1023 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
1025 def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1026 def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>;
1027 def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
1028 // For other extloads, use subregs, since the high contents of the register are
1029 // defined after an extload.
1030 def : Pat<(extloadi64i32 addr:$src),
1031 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src),
1034 // anyext. Define these to do an explicit zero-extend to
1035 // avoid partial-register updates.
1036 def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG
1037 (MOVZX32rr8 GR8 :$src), sub_16bit)>;
1038 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
1040 // Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
1041 def : Pat<(i32 (anyext GR16:$src)),
1042 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>;
1044 def : Pat<(i64 (anyext GR8 :$src)), (MOVZX64rr8 GR8 :$src)>;
1045 def : Pat<(i64 (anyext GR16:$src)), (MOVZX64rr16 GR16 :$src)>;
1046 def : Pat<(i64 (anyext GR32:$src)),
1047 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1050 // Any instruction that defines a 32-bit result leaves the high half of the
1051 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
1052 // be copying from a truncate. And x86's cmov doesn't do anything if the
1053 // condition is false. But any other 32-bit operation will zero-extend
1055 def def32 : PatLeaf<(i32 GR32:$src), [{
1056 return N->getOpcode() != ISD::TRUNCATE &&
1057 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
1058 N->getOpcode() != ISD::CopyFromReg &&
1059 N->getOpcode() != X86ISD::CMOV;
1062 // In the case of a 32-bit def that is known to implicitly zero-extend,
1063 // we can use a SUBREG_TO_REG.
1064 def : Pat<(i64 (zext def32:$src)),
1065 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1067 //===----------------------------------------------------------------------===//
1068 // Pattern match OR as ADD
1069 //===----------------------------------------------------------------------===//
1071 // If safe, we prefer to pattern match OR as ADD at isel time. ADD can be
1072 // 3-addressified into an LEA instruction to avoid copies. However, we also
1073 // want to finally emit these instructions as an or at the end of the code
1074 // generator to make the generated code easier to read. To do this, we select
1075 // into "disjoint bits" pseudo ops.
1077 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
1078 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
1079 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1080 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
1082 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
1083 APInt Mask = APInt::getAllOnesValue(BitWidth);
1084 APInt KnownZero0, KnownOne0;
1085 CurDAG->ComputeMaskedBits(N->getOperand(0), Mask, KnownZero0, KnownOne0, 0);
1086 APInt KnownZero1, KnownOne1;
1087 CurDAG->ComputeMaskedBits(N->getOperand(1), Mask, KnownZero1, KnownOne1, 0);
1088 return (~KnownZero0 & ~KnownZero1) == 0;
1092 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
1093 let AddedComplexity = 5 in { // Try this before the selecting to OR
1095 let isConvertibleToThreeAddress = 1,
1096 Constraints = "$src1 = $dst", Defs = [EFLAGS] in {
1097 let isCommutable = 1 in {
1098 def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1099 "", // orw/addw REG, REG
1100 [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>;
1101 def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1102 "", // orl/addl REG, REG
1103 [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>;
1104 def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1105 "", // orq/addq REG, REG
1106 [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>;
1109 // NOTE: These are order specific, we want the ri8 forms to be listed
1110 // first so that they are slightly preferred to the ri forms.
1112 def ADD16ri8_DB : I<0, Pseudo,
1113 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1114 "", // orw/addw REG, imm8
1115 [(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>;
1116 def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1117 "", // orw/addw REG, imm
1118 [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>;
1120 def ADD32ri8_DB : I<0, Pseudo,
1121 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1122 "", // orl/addl REG, imm8
1123 [(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>;
1124 def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1125 "", // orl/addl REG, imm
1126 [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>;
1129 def ADD64ri8_DB : I<0, Pseudo,
1130 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
1131 "", // orq/addq REG, imm8
1132 [(set GR64:$dst, (or_is_add GR64:$src1,
1133 i64immSExt8:$src2))]>;
1134 def ADD64ri32_DB : I<0, Pseudo,
1135 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1136 "", // orq/addq REG, imm
1137 [(set GR64:$dst, (or_is_add GR64:$src1,
1138 i64immSExt32:$src2))]>;
1140 } // AddedComplexity
1143 //===----------------------------------------------------------------------===//
1145 //===----------------------------------------------------------------------===//
1147 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1148 // +128 doesn't, so in this special case use a sub instead of an add.
1149 def : Pat<(add GR16:$src1, 128),
1150 (SUB16ri8 GR16:$src1, -128)>;
1151 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
1152 (SUB16mi8 addr:$dst, -128)>;
1154 def : Pat<(add GR32:$src1, 128),
1155 (SUB32ri8 GR32:$src1, -128)>;
1156 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
1157 (SUB32mi8 addr:$dst, -128)>;
1159 def : Pat<(add GR64:$src1, 128),
1160 (SUB64ri8 GR64:$src1, -128)>;
1161 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1162 (SUB64mi8 addr:$dst, -128)>;
1164 // The same trick applies for 32-bit immediate fields in 64-bit
1166 def : Pat<(add GR64:$src1, 0x0000000080000000),
1167 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1168 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1169 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1171 // To avoid needing to materialize an immediate in a register, use a 32-bit and
1172 // with implicit zero-extension instead of a 64-bit and if the immediate has at
1173 // least 32 bits of leading zeros. If in addition the last 32 bits can be
1174 // represented with a sign extension of a 8 bit constant, use that.
1176 def : Pat<(and GR64:$src, i64immZExt32SExt8:$imm),
1180 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1181 (i32 (GetLo8XForm imm:$imm))),
1184 def : Pat<(and GR64:$src, i64immZExt32:$imm),
1188 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1189 (i32 (GetLo32XForm imm:$imm))),
1193 // r & (2^16-1) ==> movz
1194 def : Pat<(and GR32:$src1, 0xffff),
1195 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
1196 // r & (2^8-1) ==> movz
1197 def : Pat<(and GR32:$src1, 0xff),
1198 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
1201 Requires<[In32BitMode]>;
1202 // r & (2^8-1) ==> movz
1203 def : Pat<(and GR16:$src1, 0xff),
1204 (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG
1205 (i16 (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD)), sub_8bit)),
1207 Requires<[In32BitMode]>;
1209 // r & (2^32-1) ==> movz
1210 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1211 (MOVZX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
1212 // r & (2^16-1) ==> movz
1213 def : Pat<(and GR64:$src, 0xffff),
1214 (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit)))>;
1215 // r & (2^8-1) ==> movz
1216 def : Pat<(and GR64:$src, 0xff),
1217 (MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit)))>;
1218 // r & (2^8-1) ==> movz
1219 def : Pat<(and GR32:$src1, 0xff),
1220 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>,
1221 Requires<[In64BitMode]>;
1222 // r & (2^8-1) ==> movz
1223 def : Pat<(and GR16:$src1, 0xff),
1224 (EXTRACT_SUBREG (MOVZX32rr8 (i8
1225 (EXTRACT_SUBREG GR16:$src1, sub_8bit))), sub_16bit)>,
1226 Requires<[In64BitMode]>;
1229 // sext_inreg patterns
1230 def : Pat<(sext_inreg GR32:$src, i16),
1231 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>;
1232 def : Pat<(sext_inreg GR32:$src, i8),
1233 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1236 Requires<[In32BitMode]>;
1238 def : Pat<(sext_inreg GR16:$src, i8),
1239 (EXTRACT_SUBREG (i32 (MOVSX32rr8 (EXTRACT_SUBREG
1240 (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), sub_8bit))),
1242 Requires<[In32BitMode]>;
1244 def : Pat<(sext_inreg GR64:$src, i32),
1245 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
1246 def : Pat<(sext_inreg GR64:$src, i16),
1247 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>;
1248 def : Pat<(sext_inreg GR64:$src, i8),
1249 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>;
1250 def : Pat<(sext_inreg GR32:$src, i8),
1251 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>,
1252 Requires<[In64BitMode]>;
1253 def : Pat<(sext_inreg GR16:$src, i8),
1254 (EXTRACT_SUBREG (MOVSX32rr8
1255 (EXTRACT_SUBREG GR16:$src, sub_8bit)), sub_16bit)>,
1256 Requires<[In64BitMode]>;
1258 // sext, sext_load, zext, zext_load
1259 def: Pat<(i16 (sext GR8:$src)),
1260 (EXTRACT_SUBREG (MOVSX32rr8 GR8:$src), sub_16bit)>;
1261 def: Pat<(sextloadi16i8 addr:$src),
1262 (EXTRACT_SUBREG (MOVSX32rm8 addr:$src), sub_16bit)>;
1263 def: Pat<(i16 (zext GR8:$src)),
1264 (EXTRACT_SUBREG (MOVZX32rr8 GR8:$src), sub_16bit)>;
1265 def: Pat<(zextloadi16i8 addr:$src),
1266 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>;
1269 def : Pat<(i16 (trunc GR32:$src)),
1270 (EXTRACT_SUBREG GR32:$src, sub_16bit)>;
1271 def : Pat<(i8 (trunc GR32:$src)),
1272 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1274 Requires<[In32BitMode]>;
1275 def : Pat<(i8 (trunc GR16:$src)),
1276 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1278 Requires<[In32BitMode]>;
1279 def : Pat<(i32 (trunc GR64:$src)),
1280 (EXTRACT_SUBREG GR64:$src, sub_32bit)>;
1281 def : Pat<(i16 (trunc GR64:$src)),
1282 (EXTRACT_SUBREG GR64:$src, sub_16bit)>;
1283 def : Pat<(i8 (trunc GR64:$src)),
1284 (EXTRACT_SUBREG GR64:$src, sub_8bit)>;
1285 def : Pat<(i8 (trunc GR32:$src)),
1286 (EXTRACT_SUBREG GR32:$src, sub_8bit)>,
1287 Requires<[In64BitMode]>;
1288 def : Pat<(i8 (trunc GR16:$src)),
1289 (EXTRACT_SUBREG GR16:$src, sub_8bit)>,
1290 Requires<[In64BitMode]>;
1292 // h-register tricks
1293 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
1294 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1296 Requires<[In32BitMode]>;
1297 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
1298 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1300 Requires<[In32BitMode]>;
1301 def : Pat<(srl GR16:$src, (i8 8)),
1304 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1307 Requires<[In32BitMode]>;
1308 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1309 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1312 Requires<[In32BitMode]>;
1313 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1314 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1317 Requires<[In32BitMode]>;
1318 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1319 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1322 Requires<[In32BitMode]>;
1323 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1324 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1327 Requires<[In32BitMode]>;
1329 // h-register tricks.
1330 // For now, be conservative on x86-64 and use an h-register extract only if the
1331 // value is immediately zero-extended or stored, which are somewhat common
1332 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
1333 // from being allocated in the same instruction as the h register, as there's
1334 // currently no way to describe this requirement to the register allocator.
1336 // h-register extract and zero-extend.
1337 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
1341 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1344 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1346 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1348 Requires<[In64BitMode]>;
1349 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1350 (MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1353 Requires<[In64BitMode]>;
1354 def : Pat<(srl GR16:$src, (i8 8)),
1357 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1360 Requires<[In64BitMode]>;
1361 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1363 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1365 Requires<[In64BitMode]>;
1366 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1368 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1370 Requires<[In64BitMode]>;
1371 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
1375 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1378 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
1382 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1386 // h-register extract and store.
1387 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
1390 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1392 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
1395 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1397 Requires<[In64BitMode]>;
1398 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
1401 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1403 Requires<[In64BitMode]>;
1406 // (shl x, 1) ==> (add x, x)
1407 // Note that if x is undef (immediate or otherwise), we could theoretically
1408 // end up with the two uses of x getting different values, producing a result
1409 // where the least significant bit is not 0. However, the probability of this
1410 // happening is considered low enough that this is officially not a
1412 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
1413 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
1414 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
1415 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1417 // (shl x (and y, 31)) ==> (shl x, y)
1418 def : Pat<(shl GR8:$src1, (and CL, 31)),
1419 (SHL8rCL GR8:$src1)>;
1420 def : Pat<(shl GR16:$src1, (and CL, 31)),
1421 (SHL16rCL GR16:$src1)>;
1422 def : Pat<(shl GR32:$src1, (and CL, 31)),
1423 (SHL32rCL GR32:$src1)>;
1424 def : Pat<(store (shl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
1425 (SHL8mCL addr:$dst)>;
1426 def : Pat<(store (shl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
1427 (SHL16mCL addr:$dst)>;
1428 def : Pat<(store (shl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
1429 (SHL32mCL addr:$dst)>;
1431 def : Pat<(srl GR8:$src1, (and CL, 31)),
1432 (SHR8rCL GR8:$src1)>;
1433 def : Pat<(srl GR16:$src1, (and CL, 31)),
1434 (SHR16rCL GR16:$src1)>;
1435 def : Pat<(srl GR32:$src1, (and CL, 31)),
1436 (SHR32rCL GR32:$src1)>;
1437 def : Pat<(store (srl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
1438 (SHR8mCL addr:$dst)>;
1439 def : Pat<(store (srl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
1440 (SHR16mCL addr:$dst)>;
1441 def : Pat<(store (srl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
1442 (SHR32mCL addr:$dst)>;
1444 def : Pat<(sra GR8:$src1, (and CL, 31)),
1445 (SAR8rCL GR8:$src1)>;
1446 def : Pat<(sra GR16:$src1, (and CL, 31)),
1447 (SAR16rCL GR16:$src1)>;
1448 def : Pat<(sra GR32:$src1, (and CL, 31)),
1449 (SAR32rCL GR32:$src1)>;
1450 def : Pat<(store (sra (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
1451 (SAR8mCL addr:$dst)>;
1452 def : Pat<(store (sra (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
1453 (SAR16mCL addr:$dst)>;
1454 def : Pat<(store (sra (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
1455 (SAR32mCL addr:$dst)>;
1457 // (shl x (and y, 63)) ==> (shl x, y)
1458 def : Pat<(shl GR64:$src1, (and CL, 63)),
1459 (SHL64rCL GR64:$src1)>;
1460 def : Pat<(store (shl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1461 (SHL64mCL addr:$dst)>;
1463 def : Pat<(srl GR64:$src1, (and CL, 63)),
1464 (SHR64rCL GR64:$src1)>;
1465 def : Pat<(store (srl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1466 (SHR64mCL addr:$dst)>;
1468 def : Pat<(sra GR64:$src1, (and CL, 63)),
1469 (SAR64rCL GR64:$src1)>;
1470 def : Pat<(store (sra (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1471 (SAR64mCL addr:$dst)>;
1474 // (anyext (setcc_carry)) -> (setcc_carry)
1475 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1477 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1479 def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))),
1485 //===----------------------------------------------------------------------===//
1486 // EFLAGS-defining Patterns
1487 //===----------------------------------------------------------------------===//
1490 def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>;
1491 def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
1492 def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
1495 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
1496 (ADD8rm GR8:$src1, addr:$src2)>;
1497 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
1498 (ADD16rm GR16:$src1, addr:$src2)>;
1499 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
1500 (ADD32rm GR32:$src1, addr:$src2)>;
1503 def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>;
1504 def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
1505 def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
1506 def : Pat<(add GR16:$src1, i16immSExt8:$src2),
1507 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
1508 def : Pat<(add GR32:$src1, i32immSExt8:$src2),
1509 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
1512 def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>;
1513 def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
1514 def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
1517 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
1518 (SUB8rm GR8:$src1, addr:$src2)>;
1519 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
1520 (SUB16rm GR16:$src1, addr:$src2)>;
1521 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
1522 (SUB32rm GR32:$src1, addr:$src2)>;
1525 def : Pat<(sub GR8:$src1, imm:$src2),
1526 (SUB8ri GR8:$src1, imm:$src2)>;
1527 def : Pat<(sub GR16:$src1, imm:$src2),
1528 (SUB16ri GR16:$src1, imm:$src2)>;
1529 def : Pat<(sub GR32:$src1, imm:$src2),
1530 (SUB32ri GR32:$src1, imm:$src2)>;
1531 def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
1532 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
1533 def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
1534 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
1537 def : Pat<(mul GR16:$src1, GR16:$src2),
1538 (IMUL16rr GR16:$src1, GR16:$src2)>;
1539 def : Pat<(mul GR32:$src1, GR32:$src2),
1540 (IMUL32rr GR32:$src1, GR32:$src2)>;
1543 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
1544 (IMUL16rm GR16:$src1, addr:$src2)>;
1545 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
1546 (IMUL32rm GR32:$src1, addr:$src2)>;
1549 def : Pat<(mul GR16:$src1, imm:$src2),
1550 (IMUL16rri GR16:$src1, imm:$src2)>;
1551 def : Pat<(mul GR32:$src1, imm:$src2),
1552 (IMUL32rri GR32:$src1, imm:$src2)>;
1553 def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
1554 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
1555 def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
1556 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
1558 // reg = mul mem, imm
1559 def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
1560 (IMUL16rmi addr:$src1, imm:$src2)>;
1561 def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
1562 (IMUL32rmi addr:$src1, imm:$src2)>;
1563 def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
1564 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
1565 def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
1566 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
1568 // Patterns for nodes that do not produce flags, for instructions that do.
1571 def : Pat<(add GR64:$src1, GR64:$src2),
1572 (ADD64rr GR64:$src1, GR64:$src2)>;
1573 def : Pat<(add GR64:$src1, i64immSExt8:$src2),
1574 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1575 def : Pat<(add GR64:$src1, i64immSExt32:$src2),
1576 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1577 def : Pat<(add GR64:$src1, (loadi64 addr:$src2)),
1578 (ADD64rm GR64:$src1, addr:$src2)>;
1581 def : Pat<(sub GR64:$src1, GR64:$src2),
1582 (SUB64rr GR64:$src1, GR64:$src2)>;
1583 def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)),
1584 (SUB64rm GR64:$src1, addr:$src2)>;
1585 def : Pat<(sub GR64:$src1, i64immSExt8:$src2),
1586 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1587 def : Pat<(sub GR64:$src1, i64immSExt32:$src2),
1588 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1591 def : Pat<(mul GR64:$src1, GR64:$src2),
1592 (IMUL64rr GR64:$src1, GR64:$src2)>;
1593 def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)),
1594 (IMUL64rm GR64:$src1, addr:$src2)>;
1595 def : Pat<(mul GR64:$src1, i64immSExt8:$src2),
1596 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
1597 def : Pat<(mul GR64:$src1, i64immSExt32:$src2),
1598 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
1599 def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2),
1600 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
1601 def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2),
1602 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
1605 def : Pat<(add GR8 :$src, 1), (INC8r GR8 :$src)>;
1606 def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>, Requires<[In32BitMode]>;
1607 def : Pat<(add GR16:$src, 1), (INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1608 def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>, Requires<[In32BitMode]>;
1609 def : Pat<(add GR32:$src, 1), (INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1610 def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>;
1613 def : Pat<(add GR8 :$src, -1), (DEC8r GR8 :$src)>;
1614 def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
1615 def : Pat<(add GR16:$src, -1), (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1616 def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
1617 def : Pat<(add GR32:$src, -1), (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1618 def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>;
1621 def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
1622 def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
1623 def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
1624 def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>;
1627 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
1628 (OR8rm GR8:$src1, addr:$src2)>;
1629 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
1630 (OR16rm GR16:$src1, addr:$src2)>;
1631 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
1632 (OR32rm GR32:$src1, addr:$src2)>;
1633 def : Pat<(or GR64:$src1, (loadi64 addr:$src2)),
1634 (OR64rm GR64:$src1, addr:$src2)>;
1637 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
1638 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
1639 def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
1640 def : Pat<(or GR16:$src1, i16immSExt8:$src2),
1641 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1642 def : Pat<(or GR32:$src1, i32immSExt8:$src2),
1643 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1644 def : Pat<(or GR64:$src1, i64immSExt8:$src2),
1645 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1646 def : Pat<(or GR64:$src1, i64immSExt32:$src2),
1647 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1650 def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>;
1651 def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
1652 def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
1653 def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>;
1656 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
1657 (XOR8rm GR8:$src1, addr:$src2)>;
1658 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
1659 (XOR16rm GR16:$src1, addr:$src2)>;
1660 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
1661 (XOR32rm GR32:$src1, addr:$src2)>;
1662 def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)),
1663 (XOR64rm GR64:$src1, addr:$src2)>;
1666 def : Pat<(xor GR8:$src1, imm:$src2),
1667 (XOR8ri GR8:$src1, imm:$src2)>;
1668 def : Pat<(xor GR16:$src1, imm:$src2),
1669 (XOR16ri GR16:$src1, imm:$src2)>;
1670 def : Pat<(xor GR32:$src1, imm:$src2),
1671 (XOR32ri GR32:$src1, imm:$src2)>;
1672 def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
1673 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1674 def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
1675 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1676 def : Pat<(xor GR64:$src1, i64immSExt8:$src2),
1677 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1678 def : Pat<(xor GR64:$src1, i64immSExt32:$src2),
1679 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1682 def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>;
1683 def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
1684 def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
1685 def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>;
1688 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
1689 (AND8rm GR8:$src1, addr:$src2)>;
1690 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
1691 (AND16rm GR16:$src1, addr:$src2)>;
1692 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
1693 (AND32rm GR32:$src1, addr:$src2)>;
1694 def : Pat<(and GR64:$src1, (loadi64 addr:$src2)),
1695 (AND64rm GR64:$src1, addr:$src2)>;
1698 def : Pat<(and GR8:$src1, imm:$src2),
1699 (AND8ri GR8:$src1, imm:$src2)>;
1700 def : Pat<(and GR16:$src1, imm:$src2),
1701 (AND16ri GR16:$src1, imm:$src2)>;
1702 def : Pat<(and GR32:$src1, imm:$src2),
1703 (AND32ri GR32:$src1, imm:$src2)>;
1704 def : Pat<(and GR16:$src1, i16immSExt8:$src2),
1705 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
1706 def : Pat<(and GR32:$src1, i32immSExt8:$src2),
1707 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
1708 def : Pat<(and GR64:$src1, i64immSExt8:$src2),
1709 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
1710 def : Pat<(and GR64:$src1, i64immSExt32:$src2),
1711 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>;
1713 def : Pat<(atomic_load_8 addr:$src), (MOV8rm addr:$src)>;
1714 def : Pat<(atomic_load_16 addr:$src), (MOV16rm addr:$src)>;
1715 def : Pat<(atomic_load_32 addr:$src), (MOV32rm addr:$src)>;
1716 def : Pat<(atomic_load_64 addr:$src), (MOV64rm addr:$src)>;
1718 def : Pat<(atomic_store_8 addr:$ptr, GR8:$val),
1719 (MOV8mr addr:$ptr, GR8:$val)>;
1720 def : Pat<(atomic_store_16 addr:$ptr, GR16:$val),
1721 (MOV16mr addr:$ptr, GR16:$val)>;
1722 def : Pat<(atomic_store_32 addr:$ptr, GR32:$val),
1723 (MOV32mr addr:$ptr, GR32:$val)>;
1724 def : Pat<(atomic_store_64 addr:$ptr, GR64:$val),
1725 (MOV64mr addr:$ptr, GR64:$val)>;