1 //===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the various pseudo instructions used by the compiler,
11 // as well as Pat patterns used during instruction selection.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Pattern Matching Support
18 def GetLo32XForm : SDNodeXForm<imm, [{
19 // Transformation function: get the low 32 bits.
20 return getI32Imm((unsigned)N->getZExtValue());
23 def GetLo8XForm : SDNodeXForm<imm, [{
24 // Transformation function: get the low 8 bits.
25 return getI8Imm((uint8_t)N->getZExtValue());
29 //===----------------------------------------------------------------------===//
30 // Random Pseudo Instructions.
32 // PIC base construction. This expands to code that looks like this:
35 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
36 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
40 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
41 // a stack adjustment and the codegen must know that they may modify the stack
42 // pointer before prolog-epilog rewriting occurs.
43 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
44 // sub / add which can clobber EFLAGS.
45 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
46 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
48 [(X86callseq_start timm:$amt)]>,
49 Requires<[In32BitMode]>;
50 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
52 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
53 Requires<[In32BitMode]>;
56 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
57 // a stack adjustment and the codegen must know that they may modify the stack
58 // pointer before prolog-epilog rewriting occurs.
59 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
60 // sub / add which can clobber EFLAGS.
61 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
62 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
64 [(X86callseq_start timm:$amt)]>,
65 Requires<[In64BitMode]>;
66 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
68 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
69 Requires<[In64BitMode]>;
74 // x86-64 va_start lowering magic.
75 let usesCustomInserter = 1 in {
76 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
79 i64imm:$regsavefi, i64imm:$offset,
81 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
82 [(X86vastart_save_xmm_regs GR8:$al,
86 // The VAARG_64 pseudo-instruction takes the address of the va_list,
87 // and places the address of the next argument into a register.
88 let Defs = [EFLAGS] in
89 def VAARG_64 : I<0, Pseudo,
91 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align),
92 "#VAARG_64 $dst, $ap, $size, $mode, $align",
94 (X86vaarg64 addr:$ap, imm:$size, imm:$mode, imm:$align)),
97 // Dynamic stack allocation yields a _chkstk or _alloca call for all Windows
98 // targets. These calls are needed to probe the stack when allocating more than
99 // 4k bytes in one go. Touching the stack at 4K increments is necessary to
100 // ensure that the guard pages used by the OS virtual memory manager are
101 // allocated in correct sequence.
102 // The main point of having separate instruction are extra unmodelled effects
103 // (compared to ordinary calls) like stack pointer change.
105 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
106 def WIN_ALLOCA : I<0, Pseudo, (outs), (ins),
107 "# dynamic stack allocation",
110 // When using segmented stacks these are lowered into instructions which first
111 // check if the current stacklet has enough free memory. If it does, memory is
112 // allocated by bumping the stack pointer. Otherwise memory is allocated from
115 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
116 def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size),
117 "# variable sized alloca for segmented stacks",
119 (X86SegAlloca GR32:$size))]>,
120 Requires<[In32BitMode]>;
122 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
123 def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size),
124 "# variable sized alloca for segmented stacks",
126 (X86SegAlloca GR64:$size))]>,
127 Requires<[In64BitMode]>;
130 // The MSVC runtime contains an _ftol2 routine for converting floating-point
131 // to integer values. It has a strange calling convention: the input is
132 // popped from the x87 stack, and the return value is given in EDX:EAX. No
133 // other registers (aside from flags) are touched.
134 // Microsoft toolchains do not support 80-bit precision, so a WIN_FTOL_80
135 // variant is unnecessary.
137 let Defs = [EAX, EDX, EFLAGS], FPForm = SpecialFP in {
138 def WIN_FTOL_32 : I<0, Pseudo, (outs), (ins RFP32:$src),
140 [(X86WinFTOL RFP32:$src)]>,
141 Requires<[In32BitMode]>;
143 def WIN_FTOL_64 : I<0, Pseudo, (outs), (ins RFP64:$src),
145 [(X86WinFTOL RFP64:$src)]>,
146 Requires<[In32BitMode]>;
149 //===----------------------------------------------------------------------===//
150 // EH Pseudo Instructions
152 let isTerminator = 1, isReturn = 1, isBarrier = 1,
153 hasCtrlDep = 1, isCodeGenOnly = 1 in {
154 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
155 "ret\t#eh_return, addr: $addr",
156 [(X86ehret GR32:$addr)], IIC_RET>;
160 let isTerminator = 1, isReturn = 1, isBarrier = 1,
161 hasCtrlDep = 1, isCodeGenOnly = 1 in {
162 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
163 "ret\t#eh_return, addr: $addr",
164 [(X86ehret GR64:$addr)], IIC_RET>;
168 //===----------------------------------------------------------------------===//
169 // Pseudo instructions used by segmented stacks.
172 // This is lowered into a RET instruction by MCInstLower. We need
173 // this so that we don't have to have a MachineBasicBlock which ends
174 // with a RET and also has successors.
175 let isPseudo = 1 in {
176 def MORESTACK_RET: I<0, Pseudo, (outs), (ins),
179 // This instruction is lowered to a RET followed by a MOV. The two
180 // instructions are not generated on a higher level since then the
181 // verifier sees a MachineBasicBlock ending with a non-terminator.
182 def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins),
186 //===----------------------------------------------------------------------===//
187 // Alias Instructions
188 //===----------------------------------------------------------------------===//
190 // Alias instructions that map movr0 to xor.
191 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
192 // FIXME: Set encoding to pseudo.
193 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
194 isCodeGenOnly = 1 in {
195 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "",
196 [(set GR8:$dst, 0)], IIC_ALU_NONMEM>;
198 // We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller
199 // encoding and avoids a partial-register update sometimes, but doing so
200 // at isel time interferes with rematerialization in the current register
201 // allocator. For now, this is rewritten when the instruction is lowered
203 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
205 [(set GR16:$dst, 0)], IIC_ALU_NONMEM>, OpSize;
207 // FIXME: Set encoding to pseudo.
208 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "",
209 [(set GR32:$dst, 0)], IIC_ALU_NONMEM>;
212 // We want to rewrite MOV64r0 in terms of MOV32r0, because it's sometimes a
213 // smaller encoding, but doing so at isel time interferes with rematerialization
214 // in the current register allocator. For now, this is rewritten when the
215 // instruction is lowered to an MCInst.
216 // FIXME: AddedComplexity gives this a higher priority than MOV64ri32. Remove
217 // when we have a better way to specify isel priority.
218 let Defs = [EFLAGS], isCodeGenOnly=1,
219 AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
220 def MOV64r0 : I<0x31, MRMInitReg, (outs GR64:$dst), (ins), "",
221 [(set GR64:$dst, 0)], IIC_ALU_NONMEM>;
223 // Materialize i64 constant where top 32-bits are zero. This could theoretically
224 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
225 // that would make it more difficult to rematerialize.
226 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1,
228 def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
229 "", [(set GR64:$dst, i64immZExt32:$src)],
232 // Use sbb to materialize carry bit.
233 let Uses = [EFLAGS], Defs = [EFLAGS], isCodeGenOnly = 1 in {
234 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
235 // However, Pat<> can't replicate the destination reg into the inputs of the
237 // FIXME: Change these to have encoding Pseudo when X86MCCodeEmitter replaces
239 def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins), "",
240 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))],
242 def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins), "",
243 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))],
246 def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins), "",
247 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))],
249 def SETB_C64r : RI<0x19, MRMInitReg, (outs GR64:$dst), (ins), "",
250 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))],
255 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
257 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
259 def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
262 def : Pat<(i16 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
264 def : Pat<(i32 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
266 def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
269 // We canonicalize 'setb' to "(and (sbb reg,reg), 1)" on the hope that the and
270 // will be eliminated and that the sbb can be extended up to a wider type. When
271 // this happens, it is great. However, if we are left with an 8-bit sbb and an
272 // and, we might as well just match it as a setb.
273 def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1),
276 // (add OP, SETB) -> (adc OP, 0)
277 def : Pat<(add (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR8:$op),
278 (ADC8ri GR8:$op, 0)>;
279 def : Pat<(add (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR32:$op),
280 (ADC32ri8 GR32:$op, 0)>;
281 def : Pat<(add (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR64:$op),
282 (ADC64ri8 GR64:$op, 0)>;
284 // (sub OP, SETB) -> (sbb OP, 0)
285 def : Pat<(sub GR8:$op, (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
286 (SBB8ri GR8:$op, 0)>;
287 def : Pat<(sub GR32:$op, (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
288 (SBB32ri8 GR32:$op, 0)>;
289 def : Pat<(sub GR64:$op, (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
290 (SBB64ri8 GR64:$op, 0)>;
292 // (sub OP, SETCC_CARRY) -> (adc OP, 0)
293 def : Pat<(sub GR8:$op, (i8 (X86setcc_c X86_COND_B, EFLAGS))),
294 (ADC8ri GR8:$op, 0)>;
295 def : Pat<(sub GR32:$op, (i32 (X86setcc_c X86_COND_B, EFLAGS))),
296 (ADC32ri8 GR32:$op, 0)>;
297 def : Pat<(sub GR64:$op, (i64 (X86setcc_c X86_COND_B, EFLAGS))),
298 (ADC64ri8 GR64:$op, 0)>;
300 //===----------------------------------------------------------------------===//
301 // String Pseudo Instructions
303 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
304 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
305 [(X86rep_movs i8)], IIC_REP_MOVS>, REP;
306 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
307 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize;
308 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
309 [(X86rep_movs i32)], IIC_REP_MOVS>, REP;
312 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in
313 def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
314 [(X86rep_movs i64)], IIC_REP_MOVS>, REP;
317 // FIXME: Should use "(X86rep_stos AL)" as the pattern.
318 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI], isCodeGenOnly = 1 in
319 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
320 [(X86rep_stos i8)], IIC_REP_STOS>, REP;
321 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI], isCodeGenOnly = 1 in
322 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
323 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize;
324 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI], isCodeGenOnly = 1 in
325 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
326 [(X86rep_stos i32)], IIC_REP_STOS>, REP;
328 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI], isCodeGenOnly = 1 in
329 def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
330 [(X86rep_stos i64)], IIC_REP_STOS>, REP;
333 //===----------------------------------------------------------------------===//
334 // Thread Local Storage Instructions
338 // All calls clobber the non-callee saved registers. ESP is marked as
339 // a use to prevent stack-pointer assignments that appear immediately
340 // before calls from potentially appearing dead.
341 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
342 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
343 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
344 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
346 def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
348 [(X86tlsaddr tls32addr:$sym)]>,
349 Requires<[In32BitMode]>;
351 // All calls clobber the non-callee saved registers. RSP is marked as
352 // a use to prevent stack-pointer assignments that appear immediately
353 // before calls from potentially appearing dead.
354 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
355 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
356 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
357 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
358 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
360 def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
362 [(X86tlsaddr tls64addr:$sym)]>,
363 Requires<[In64BitMode]>;
365 // Darwin TLS Support
366 // For i386, the address of the thunk is passed on the stack, on return the
367 // address of the variable is in %eax. %ecx is trashed during the function
368 // call. All other registers are preserved.
369 let Defs = [EAX, ECX, EFLAGS],
371 usesCustomInserter = 1 in
372 def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
374 [(X86TLSCall addr:$sym)]>,
375 Requires<[In32BitMode]>;
377 // For x86_64, the address of the thunk is passed in %rdi, on return
378 // the address of the variable is in %rax. All other registers are preserved.
379 let Defs = [RAX, EFLAGS],
381 usesCustomInserter = 1 in
382 def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
384 [(X86TLSCall addr:$sym)]>,
385 Requires<[In64BitMode]>;
388 //===----------------------------------------------------------------------===//
389 // Conditional Move Pseudo Instructions
391 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
392 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
393 // however that requires promoting the operands, and can induce additional
394 // i8 register pressure.
395 let usesCustomInserter = 1, Uses = [EFLAGS] in {
396 def CMOV_GR8 : I<0, Pseudo,
397 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
399 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
400 imm:$cond, EFLAGS))]>;
402 let Predicates = [NoCMov] in {
403 def CMOV_GR32 : I<0, Pseudo,
404 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cond),
405 "#CMOV_GR32* PSEUDO!",
407 (X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>;
408 def CMOV_GR16 : I<0, Pseudo,
409 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cond),
410 "#CMOV_GR16* PSEUDO!",
412 (X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>;
413 def CMOV_RFP32 : I<0, Pseudo,
415 (ins RFP32:$src1, RFP32:$src2, i8imm:$cond),
416 "#CMOV_RFP32 PSEUDO!",
418 (X86cmov RFP32:$src1, RFP32:$src2, imm:$cond,
420 def CMOV_RFP64 : I<0, Pseudo,
422 (ins RFP64:$src1, RFP64:$src2, i8imm:$cond),
423 "#CMOV_RFP64 PSEUDO!",
425 (X86cmov RFP64:$src1, RFP64:$src2, imm:$cond,
427 def CMOV_RFP80 : I<0, Pseudo,
429 (ins RFP80:$src1, RFP80:$src2, i8imm:$cond),
430 "#CMOV_RFP80 PSEUDO!",
432 (X86cmov RFP80:$src1, RFP80:$src2, imm:$cond,
434 } // Predicates = [NoCMov]
435 } // UsesCustomInserter = 1, Uses = [EFLAGS]
438 //===----------------------------------------------------------------------===//
439 // Atomic Instruction Pseudo Instructions
440 //===----------------------------------------------------------------------===//
442 // Atomic exchange, and, or, xor
443 let Constraints = "$val = $dst", Defs = [EFLAGS],
444 usesCustomInserter = 1 in {
446 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
448 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
449 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
451 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
452 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
454 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
455 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
456 "#ATOMNAND8 PSEUDO!",
457 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
459 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
460 "#ATOMAND16 PSEUDO!",
461 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
462 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
464 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
465 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
466 "#ATOMXOR16 PSEUDO!",
467 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
468 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
469 "#ATOMNAND16 PSEUDO!",
470 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
471 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
472 "#ATOMMIN16 PSEUDO!",
473 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
474 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
475 "#ATOMMAX16 PSEUDO!",
476 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
477 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
478 "#ATOMUMIN16 PSEUDO!",
479 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
480 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
481 "#ATOMUMAX16 PSEUDO!",
482 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
485 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
486 "#ATOMAND32 PSEUDO!",
487 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
488 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
490 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
491 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
492 "#ATOMXOR32 PSEUDO!",
493 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
494 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
495 "#ATOMNAND32 PSEUDO!",
496 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
497 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
498 "#ATOMMIN32 PSEUDO!",
499 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
500 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
501 "#ATOMMAX32 PSEUDO!",
502 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
503 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
504 "#ATOMUMIN32 PSEUDO!",
505 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
506 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
507 "#ATOMUMAX32 PSEUDO!",
508 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
512 def ATOMAND64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
513 "#ATOMAND64 PSEUDO!",
514 [(set GR64:$dst, (atomic_load_and_64 addr:$ptr, GR64:$val))]>;
515 def ATOMOR64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
517 [(set GR64:$dst, (atomic_load_or_64 addr:$ptr, GR64:$val))]>;
518 def ATOMXOR64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
519 "#ATOMXOR64 PSEUDO!",
520 [(set GR64:$dst, (atomic_load_xor_64 addr:$ptr, GR64:$val))]>;
521 def ATOMNAND64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
522 "#ATOMNAND64 PSEUDO!",
523 [(set GR64:$dst, (atomic_load_nand_64 addr:$ptr, GR64:$val))]>;
524 def ATOMMIN64: I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val),
525 "#ATOMMIN64 PSEUDO!",
526 [(set GR64:$dst, (atomic_load_min_64 addr:$ptr, GR64:$val))]>;
527 def ATOMMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
528 "#ATOMMAX64 PSEUDO!",
529 [(set GR64:$dst, (atomic_load_max_64 addr:$ptr, GR64:$val))]>;
530 def ATOMUMIN64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
531 "#ATOMUMIN64 PSEUDO!",
532 [(set GR64:$dst, (atomic_load_umin_64 addr:$ptr, GR64:$val))]>;
533 def ATOMUMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
534 "#ATOMUMAX64 PSEUDO!",
535 [(set GR64:$dst, (atomic_load_umax_64 addr:$ptr, GR64:$val))]>;
538 let Constraints = "$val1 = $dst1, $val2 = $dst2",
539 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
540 Uses = [EAX, EBX, ECX, EDX],
541 mayLoad = 1, mayStore = 1,
542 usesCustomInserter = 1 in {
543 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
544 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
545 "#ATOMAND6432 PSEUDO!", []>;
546 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
547 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
548 "#ATOMOR6432 PSEUDO!", []>;
549 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
550 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
551 "#ATOMXOR6432 PSEUDO!", []>;
552 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
553 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
554 "#ATOMNAND6432 PSEUDO!", []>;
555 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
556 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
557 "#ATOMADD6432 PSEUDO!", []>;
558 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
559 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
560 "#ATOMSUB6432 PSEUDO!", []>;
561 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
562 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
563 "#ATOMSWAP6432 PSEUDO!", []>;
566 //===----------------------------------------------------------------------===//
567 // Normal-Instructions-With-Lock-Prefix Pseudo Instructions
568 //===----------------------------------------------------------------------===//
570 // FIXME: Use normal instructions and add lock prefix dynamically.
574 // TODO: Get this to fold the constant into the instruction.
575 let isCodeGenOnly = 1, Defs = [EFLAGS] in
576 def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero),
578 "or{l}\t{$zero, $dst|$dst, $zero}",
579 [], IIC_ALU_MEM>, Requires<[In32BitMode]>, LOCK;
581 let hasSideEffects = 1 in
582 def Int_MemBarrier : I<0, Pseudo, (outs), (ins),
586 // RegOpc corresponds to the mr version of the instruction
587 // ImmOpc corresponds to the mi version of the instruction
588 // ImmOpc8 corresponds to the mi8 version of the instruction
589 // ImmMod corresponds to the instruction format of the mi and mi8 versions
590 multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8,
591 Format ImmMod, string mnemonic> {
592 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1 in {
594 def #NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
595 RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 },
596 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
597 !strconcat("lock\n\t", mnemonic, "{b}\t",
598 "{$src2, $dst|$dst, $src2}"),
599 [], IIC_ALU_NONMEM>, LOCK;
600 def #NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
601 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
602 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
603 !strconcat("lock\n\t", mnemonic, "{w}\t",
604 "{$src2, $dst|$dst, $src2}"),
605 [], IIC_ALU_NONMEM>, OpSize, LOCK;
606 def #NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
607 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
608 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
609 !strconcat("lock\n\t", mnemonic, "{l}\t",
610 "{$src2, $dst|$dst, $src2}"),
611 [], IIC_ALU_NONMEM>, LOCK;
612 def #NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
613 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
614 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
615 !strconcat("lock\n\t", mnemonic, "{q}\t",
616 "{$src2, $dst|$dst, $src2}"),
617 [], IIC_ALU_NONMEM>, LOCK;
619 def #NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
620 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 },
621 ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2),
622 !strconcat("lock\n\t", mnemonic, "{b}\t",
623 "{$src2, $dst|$dst, $src2}"),
624 [], IIC_ALU_MEM>, LOCK;
626 def #NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
627 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
628 ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2),
629 !strconcat("lock\n\t", mnemonic, "{w}\t",
630 "{$src2, $dst|$dst, $src2}"),
631 [], IIC_ALU_MEM>, LOCK;
633 def #NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
634 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
635 ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2),
636 !strconcat("lock\n\t", mnemonic, "{l}\t",
637 "{$src2, $dst|$dst, $src2}"),
638 [], IIC_ALU_MEM>, LOCK;
640 def #NAME#64mi32 : RIi32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
641 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
642 ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2),
643 !strconcat("lock\n\t", mnemonic, "{q}\t",
644 "{$src2, $dst|$dst, $src2}"),
645 [], IIC_ALU_MEM>, LOCK;
647 def #NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
648 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
649 ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2),
650 !strconcat("lock\n\t", mnemonic, "{w}\t",
651 "{$src2, $dst|$dst, $src2}"),
652 [], IIC_ALU_MEM>, LOCK;
653 def #NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
654 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
655 ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2),
656 !strconcat("lock\n\t", mnemonic, "{l}\t",
657 "{$src2, $dst|$dst, $src2}"),
658 [], IIC_ALU_MEM>, LOCK;
659 def #NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
660 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
661 ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2),
662 !strconcat("lock\n\t", mnemonic, "{q}\t",
663 "{$src2, $dst|$dst, $src2}"),
664 [], IIC_ALU_MEM>, LOCK;
670 defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, "add">;
671 defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, "sub">;
672 defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, "or">;
673 defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, "and">;
674 defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, "xor">;
676 // Optimized codegen when the non-memory output is not used.
677 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1 in {
679 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
681 "inc{b}\t$dst", [], IIC_UNARY_MEM>, LOCK;
682 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
684 "inc{w}\t$dst", [], IIC_UNARY_MEM>, OpSize, LOCK;
685 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
687 "inc{l}\t$dst", [], IIC_UNARY_MEM>, LOCK;
688 def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst),
690 "inc{q}\t$dst", [], IIC_UNARY_MEM>, LOCK;
692 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
694 "dec{b}\t$dst", [], IIC_UNARY_MEM>, LOCK;
695 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
697 "dec{w}\t$dst", [], IIC_UNARY_MEM>, OpSize, LOCK;
698 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
700 "dec{l}\t$dst", [], IIC_UNARY_MEM>, LOCK;
701 def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst),
703 "dec{q}\t$dst", [], IIC_UNARY_MEM>, LOCK;
706 // Atomic compare and swap.
707 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX],
709 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr),
712 [(X86cas8 addr:$ptr)], IIC_CMPX_LOCK_8B>, TB, LOCK;
714 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX],
716 def LCMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$ptr),
719 [(X86cas16 addr:$ptr)], IIC_CMPX_LOCK_16B>, TB, LOCK,
720 Requires<[HasCmpxchg16b]>;
722 let Defs = [AL, EFLAGS], Uses = [AL], isCodeGenOnly = 1 in {
723 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
725 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
726 [(X86cas addr:$ptr, GR8:$swap, 1)], IIC_CMPX_LOCK_8>, TB, LOCK;
729 let Defs = [AX, EFLAGS], Uses = [AX], isCodeGenOnly = 1 in {
730 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
732 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
733 [(X86cas addr:$ptr, GR16:$swap, 2)], IIC_CMPX_LOCK>, TB, OpSize, LOCK;
736 let Defs = [EAX, EFLAGS], Uses = [EAX], isCodeGenOnly = 1 in {
737 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
739 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
740 [(X86cas addr:$ptr, GR32:$swap, 4)], IIC_CMPX_LOCK>, TB, LOCK;
743 let Defs = [RAX, EFLAGS], Uses = [RAX], isCodeGenOnly = 1 in {
744 def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap),
746 "cmpxchg{q}\t{$swap, $ptr|$ptr, $swap}",
747 [(X86cas addr:$ptr, GR64:$swap, 8)], IIC_CMPX_LOCK>, TB, LOCK;
750 // Atomic exchange and add
751 let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1 in {
752 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
754 "xadd{b}\t{$val, $ptr|$ptr, $val}",
755 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))],
758 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins GR16:$val, i16mem:$ptr),
760 "xadd{w}\t{$val, $ptr|$ptr, $val}",
761 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))],
764 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins GR32:$val, i32mem:$ptr),
766 "xadd{l}\t{$val, $ptr|$ptr, $val}",
767 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))],
770 def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins GR64:$val,i64mem:$ptr),
772 "xadd{q}\t{$val, $ptr|$ptr, $val}",
773 [(set GR64:$dst, (atomic_load_add_64 addr:$ptr, GR64:$val))],
778 def ACQUIRE_MOV8rm : I<0, Pseudo, (outs GR8 :$dst), (ins i8mem :$src),
779 "#ACQUIRE_MOV PSEUDO!",
780 [(set GR8:$dst, (atomic_load_8 addr:$src))]>;
781 def ACQUIRE_MOV16rm : I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$src),
782 "#ACQUIRE_MOV PSEUDO!",
783 [(set GR16:$dst, (atomic_load_16 addr:$src))]>;
784 def ACQUIRE_MOV32rm : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$src),
785 "#ACQUIRE_MOV PSEUDO!",
786 [(set GR32:$dst, (atomic_load_32 addr:$src))]>;
787 def ACQUIRE_MOV64rm : I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$src),
788 "#ACQUIRE_MOV PSEUDO!",
789 [(set GR64:$dst, (atomic_load_64 addr:$src))]>;
791 def RELEASE_MOV8mr : I<0, Pseudo, (outs), (ins i8mem :$dst, GR8 :$src),
792 "#RELEASE_MOV PSEUDO!",
793 [(atomic_store_8 addr:$dst, GR8 :$src)]>;
794 def RELEASE_MOV16mr : I<0, Pseudo, (outs), (ins i16mem:$dst, GR16:$src),
795 "#RELEASE_MOV PSEUDO!",
796 [(atomic_store_16 addr:$dst, GR16:$src)]>;
797 def RELEASE_MOV32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src),
798 "#RELEASE_MOV PSEUDO!",
799 [(atomic_store_32 addr:$dst, GR32:$src)]>;
800 def RELEASE_MOV64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src),
801 "#RELEASE_MOV PSEUDO!",
802 [(atomic_store_64 addr:$dst, GR64:$src)]>;
804 //===----------------------------------------------------------------------===//
805 // Conditional Move Pseudo Instructions.
806 //===----------------------------------------------------------------------===//
809 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after
810 // instruction selection into a branch sequence.
811 let Uses = [EFLAGS], usesCustomInserter = 1 in {
812 def CMOV_FR32 : I<0, Pseudo,
813 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
814 "#CMOV_FR32 PSEUDO!",
815 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
817 def CMOV_FR64 : I<0, Pseudo,
818 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
819 "#CMOV_FR64 PSEUDO!",
820 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
822 def CMOV_V4F32 : I<0, Pseudo,
823 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
824 "#CMOV_V4F32 PSEUDO!",
826 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
828 def CMOV_V2F64 : I<0, Pseudo,
829 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
830 "#CMOV_V2F64 PSEUDO!",
832 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
834 def CMOV_V2I64 : I<0, Pseudo,
835 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
836 "#CMOV_V2I64 PSEUDO!",
838 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
840 def CMOV_V8F32 : I<0, Pseudo,
841 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
842 "#CMOV_V8F32 PSEUDO!",
844 (v8f32 (X86cmov VR256:$t, VR256:$f, imm:$cond,
846 def CMOV_V4F64 : I<0, Pseudo,
847 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
848 "#CMOV_V4F64 PSEUDO!",
850 (v4f64 (X86cmov VR256:$t, VR256:$f, imm:$cond,
852 def CMOV_V4I64 : I<0, Pseudo,
853 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
854 "#CMOV_V4I64 PSEUDO!",
856 (v4i64 (X86cmov VR256:$t, VR256:$f, imm:$cond,
861 //===----------------------------------------------------------------------===//
862 // DAG Pattern Matching Rules
863 //===----------------------------------------------------------------------===//
865 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
866 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
867 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
868 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
869 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
870 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
871 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
873 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
874 (ADD32ri GR32:$src1, tconstpool:$src2)>;
875 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
876 (ADD32ri GR32:$src1, tjumptable:$src2)>;
877 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
878 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
879 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
880 (ADD32ri GR32:$src1, texternalsym:$src2)>;
881 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
882 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
884 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
885 (MOV32mi addr:$dst, tglobaladdr:$src)>;
886 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
887 (MOV32mi addr:$dst, texternalsym:$src)>;
888 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
889 (MOV32mi addr:$dst, tblockaddress:$src)>;
893 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
894 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
895 // 'movabs' predicate should handle this sort of thing.
896 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
897 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
898 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
899 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
900 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
901 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
902 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
903 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
904 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
905 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>;
907 // In static codegen with small code model, we can get the address of a label
908 // into a register with 'movl'. FIXME: This is a hack, the 'imm' predicate of
909 // the MOV64ri64i32 should accept these.
910 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
911 (MOV64ri64i32 tconstpool :$dst)>, Requires<[SmallCode]>;
912 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
913 (MOV64ri64i32 tjumptable :$dst)>, Requires<[SmallCode]>;
914 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
915 (MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>;
916 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
917 (MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>;
918 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
919 (MOV64ri64i32 tblockaddress:$dst)>, Requires<[SmallCode]>;
921 // In kernel code model, we can get the address of a label
922 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
923 // the MOV64ri32 should accept these.
924 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
925 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
926 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
927 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
928 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
929 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
930 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
931 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
932 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
933 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>;
935 // If we have small model and -static mode, it is safe to store global addresses
936 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
937 // for MOV64mi32 should handle this sort of thing.
938 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
939 (MOV64mi32 addr:$dst, tconstpool:$src)>,
940 Requires<[NearData, IsStatic]>;
941 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
942 (MOV64mi32 addr:$dst, tjumptable:$src)>,
943 Requires<[NearData, IsStatic]>;
944 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
945 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
946 Requires<[NearData, IsStatic]>;
947 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
948 (MOV64mi32 addr:$dst, texternalsym:$src)>,
949 Requires<[NearData, IsStatic]>;
950 def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst),
951 (MOV64mi32 addr:$dst, tblockaddress:$src)>,
952 Requires<[NearData, IsStatic]>;
958 // tls has some funny stuff here...
959 // This corresponds to movabs $foo@tpoff, %rax
960 def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)),
961 (MOV64ri tglobaltlsaddr :$dst)>;
962 // This corresponds to add $foo@tpoff, %rax
963 def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)),
964 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>;
965 // This corresponds to mov foo@tpoff(%rbx), %eax
966 def : Pat<(load (i64 (X86Wrapper tglobaltlsaddr :$dst))),
967 (MOV64rm tglobaltlsaddr :$dst)>;
970 // Direct PC relative function call for small code model. 32-bit displacement
971 // sign extended to 64-bit.
972 def : Pat<(X86call (i64 tglobaladdr:$dst)),
973 (CALL64pcrel32 tglobaladdr:$dst)>;
974 def : Pat<(X86call (i64 texternalsym:$dst)),
975 (CALL64pcrel32 texternalsym:$dst)>;
978 def : Pat<(X86tcret GR32_TC:$dst, imm:$off),
979 (TCRETURNri GR32_TC:$dst, imm:$off)>,
980 Requires<[In32BitMode]>;
982 // FIXME: This is disabled for 32-bit PIC mode because the global base
983 // register which is part of the address mode may be assigned a
984 // callee-saved register.
985 def : Pat<(X86tcret (load addr:$dst), imm:$off),
986 (TCRETURNmi addr:$dst, imm:$off)>,
987 Requires<[In32BitMode, IsNotPIC]>;
989 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
990 (TCRETURNdi texternalsym:$dst, imm:$off)>,
991 Requires<[In32BitMode]>;
993 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
994 (TCRETURNdi texternalsym:$dst, imm:$off)>,
995 Requires<[In32BitMode]>;
997 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
998 (TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>,
999 Requires<[In64BitMode]>;
1001 def : Pat<(X86tcret (load addr:$dst), imm:$off),
1002 (TCRETURNmi64 addr:$dst, imm:$off)>,
1003 Requires<[In64BitMode]>;
1005 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
1006 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>,
1007 Requires<[In64BitMode]>;
1009 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1010 (TCRETURNdi64 texternalsym:$dst, imm:$off)>,
1011 Requires<[In64BitMode]>;
1013 // Normal calls, with various flavors of addresses.
1014 def : Pat<(X86call (i32 tglobaladdr:$dst)),
1015 (CALLpcrel32 tglobaladdr:$dst)>;
1016 def : Pat<(X86call (i32 texternalsym:$dst)),
1017 (CALLpcrel32 texternalsym:$dst)>;
1018 def : Pat<(X86call (i32 imm:$dst)),
1019 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
1023 // TEST R,R is smaller than CMP R,0
1024 def : Pat<(X86cmp GR8:$src1, 0),
1025 (TEST8rr GR8:$src1, GR8:$src1)>;
1026 def : Pat<(X86cmp GR16:$src1, 0),
1027 (TEST16rr GR16:$src1, GR16:$src1)>;
1028 def : Pat<(X86cmp GR32:$src1, 0),
1029 (TEST32rr GR32:$src1, GR32:$src1)>;
1030 def : Pat<(X86cmp GR64:$src1, 0),
1031 (TEST64rr GR64:$src1, GR64:$src1)>;
1033 // Conditional moves with folded loads with operands swapped and conditions
1035 multiclass CMOVmr<PatLeaf InvertedCond, Instruction Inst16, Instruction Inst32,
1036 Instruction Inst64> {
1037 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS),
1038 (Inst16 GR16:$src2, addr:$src1)>;
1039 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS),
1040 (Inst32 GR32:$src2, addr:$src1)>;
1041 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS),
1042 (Inst64 GR64:$src2, addr:$src1)>;
1045 defm : CMOVmr<X86_COND_B , CMOVAE16rm, CMOVAE32rm, CMOVAE64rm>;
1046 defm : CMOVmr<X86_COND_AE, CMOVB16rm , CMOVB32rm , CMOVB64rm>;
1047 defm : CMOVmr<X86_COND_E , CMOVNE16rm, CMOVNE32rm, CMOVNE64rm>;
1048 defm : CMOVmr<X86_COND_NE, CMOVE16rm , CMOVE32rm , CMOVE64rm>;
1049 defm : CMOVmr<X86_COND_BE, CMOVA16rm , CMOVA32rm , CMOVA64rm>;
1050 defm : CMOVmr<X86_COND_A , CMOVBE16rm, CMOVBE32rm, CMOVBE64rm>;
1051 defm : CMOVmr<X86_COND_L , CMOVGE16rm, CMOVGE32rm, CMOVGE64rm>;
1052 defm : CMOVmr<X86_COND_GE, CMOVL16rm , CMOVL32rm , CMOVL64rm>;
1053 defm : CMOVmr<X86_COND_LE, CMOVG16rm , CMOVG32rm , CMOVG64rm>;
1054 defm : CMOVmr<X86_COND_G , CMOVLE16rm, CMOVLE32rm, CMOVLE64rm>;
1055 defm : CMOVmr<X86_COND_P , CMOVNP16rm, CMOVNP32rm, CMOVNP64rm>;
1056 defm : CMOVmr<X86_COND_NP, CMOVP16rm , CMOVP32rm , CMOVP64rm>;
1057 defm : CMOVmr<X86_COND_S , CMOVNS16rm, CMOVNS32rm, CMOVNS64rm>;
1058 defm : CMOVmr<X86_COND_NS, CMOVS16rm , CMOVS32rm , CMOVS64rm>;
1059 defm : CMOVmr<X86_COND_O , CMOVNO16rm, CMOVNO32rm, CMOVNO64rm>;
1060 defm : CMOVmr<X86_COND_NO, CMOVO16rm , CMOVO32rm , CMOVO64rm>;
1062 // zextload bool -> zextload byte
1063 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
1064 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
1065 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
1066 def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1068 // extload bool -> extload byte
1069 // When extloading from 16-bit and smaller memory locations into 64-bit
1070 // registers, use zero-extending loads so that the entire 64-bit register is
1071 // defined, avoiding partial-register updates.
1073 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
1074 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
1075 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
1076 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
1077 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
1078 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
1080 def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1081 def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>;
1082 def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
1083 // For other extloads, use subregs, since the high contents of the register are
1084 // defined after an extload.
1085 def : Pat<(extloadi64i32 addr:$src),
1086 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src),
1089 // anyext. Define these to do an explicit zero-extend to
1090 // avoid partial-register updates.
1091 def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG
1092 (MOVZX32rr8 GR8 :$src), sub_16bit)>;
1093 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
1095 // Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
1096 def : Pat<(i32 (anyext GR16:$src)),
1097 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>;
1099 def : Pat<(i64 (anyext GR8 :$src)), (MOVZX64rr8 GR8 :$src)>;
1100 def : Pat<(i64 (anyext GR16:$src)), (MOVZX64rr16 GR16 :$src)>;
1101 def : Pat<(i64 (anyext GR32:$src)),
1102 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1105 // Any instruction that defines a 32-bit result leaves the high half of the
1106 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
1107 // be copying from a truncate. And x86's cmov doesn't do anything if the
1108 // condition is false. But any other 32-bit operation will zero-extend
1110 def def32 : PatLeaf<(i32 GR32:$src), [{
1111 return N->getOpcode() != ISD::TRUNCATE &&
1112 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
1113 N->getOpcode() != ISD::CopyFromReg &&
1114 N->getOpcode() != X86ISD::CMOV;
1117 // In the case of a 32-bit def that is known to implicitly zero-extend,
1118 // we can use a SUBREG_TO_REG.
1119 def : Pat<(i64 (zext def32:$src)),
1120 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1122 //===----------------------------------------------------------------------===//
1123 // Pattern match OR as ADD
1124 //===----------------------------------------------------------------------===//
1126 // If safe, we prefer to pattern match OR as ADD at isel time. ADD can be
1127 // 3-addressified into an LEA instruction to avoid copies. However, we also
1128 // want to finally emit these instructions as an or at the end of the code
1129 // generator to make the generated code easier to read. To do this, we select
1130 // into "disjoint bits" pseudo ops.
1132 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
1133 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
1134 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1135 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
1137 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
1138 APInt Mask = APInt::getAllOnesValue(BitWidth);
1139 APInt KnownZero0, KnownOne0;
1140 CurDAG->ComputeMaskedBits(N->getOperand(0), Mask, KnownZero0, KnownOne0, 0);
1141 APInt KnownZero1, KnownOne1;
1142 CurDAG->ComputeMaskedBits(N->getOperand(1), Mask, KnownZero1, KnownOne1, 0);
1143 return (~KnownZero0 & ~KnownZero1) == 0;
1147 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
1148 let AddedComplexity = 5 in { // Try this before the selecting to OR
1150 let isConvertibleToThreeAddress = 1,
1151 Constraints = "$src1 = $dst", Defs = [EFLAGS] in {
1152 let isCommutable = 1 in {
1153 def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1154 "", // orw/addw REG, REG
1155 [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>;
1156 def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1157 "", // orl/addl REG, REG
1158 [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>;
1159 def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1160 "", // orq/addq REG, REG
1161 [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>;
1164 // NOTE: These are order specific, we want the ri8 forms to be listed
1165 // first so that they are slightly preferred to the ri forms.
1167 def ADD16ri8_DB : I<0, Pseudo,
1168 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1169 "", // orw/addw REG, imm8
1170 [(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>;
1171 def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1172 "", // orw/addw REG, imm
1173 [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>;
1175 def ADD32ri8_DB : I<0, Pseudo,
1176 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1177 "", // orl/addl REG, imm8
1178 [(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>;
1179 def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1180 "", // orl/addl REG, imm
1181 [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>;
1184 def ADD64ri8_DB : I<0, Pseudo,
1185 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
1186 "", // orq/addq REG, imm8
1187 [(set GR64:$dst, (or_is_add GR64:$src1,
1188 i64immSExt8:$src2))]>;
1189 def ADD64ri32_DB : I<0, Pseudo,
1190 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1191 "", // orq/addq REG, imm
1192 [(set GR64:$dst, (or_is_add GR64:$src1,
1193 i64immSExt32:$src2))]>;
1195 } // AddedComplexity
1198 //===----------------------------------------------------------------------===//
1200 //===----------------------------------------------------------------------===//
1202 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1203 // +128 doesn't, so in this special case use a sub instead of an add.
1204 def : Pat<(add GR16:$src1, 128),
1205 (SUB16ri8 GR16:$src1, -128)>;
1206 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
1207 (SUB16mi8 addr:$dst, -128)>;
1209 def : Pat<(add GR32:$src1, 128),
1210 (SUB32ri8 GR32:$src1, -128)>;
1211 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
1212 (SUB32mi8 addr:$dst, -128)>;
1214 def : Pat<(add GR64:$src1, 128),
1215 (SUB64ri8 GR64:$src1, -128)>;
1216 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1217 (SUB64mi8 addr:$dst, -128)>;
1219 // The same trick applies for 32-bit immediate fields in 64-bit
1221 def : Pat<(add GR64:$src1, 0x0000000080000000),
1222 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1223 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1224 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1226 // To avoid needing to materialize an immediate in a register, use a 32-bit and
1227 // with implicit zero-extension instead of a 64-bit and if the immediate has at
1228 // least 32 bits of leading zeros. If in addition the last 32 bits can be
1229 // represented with a sign extension of a 8 bit constant, use that.
1231 def : Pat<(and GR64:$src, i64immZExt32SExt8:$imm),
1235 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1236 (i32 (GetLo8XForm imm:$imm))),
1239 def : Pat<(and GR64:$src, i64immZExt32:$imm),
1243 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1244 (i32 (GetLo32XForm imm:$imm))),
1248 // r & (2^16-1) ==> movz
1249 def : Pat<(and GR32:$src1, 0xffff),
1250 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
1251 // r & (2^8-1) ==> movz
1252 def : Pat<(and GR32:$src1, 0xff),
1253 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
1256 Requires<[In32BitMode]>;
1257 // r & (2^8-1) ==> movz
1258 def : Pat<(and GR16:$src1, 0xff),
1259 (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG
1260 (i16 (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD)), sub_8bit)),
1262 Requires<[In32BitMode]>;
1264 // r & (2^32-1) ==> movz
1265 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1266 (MOVZX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
1267 // r & (2^16-1) ==> movz
1268 def : Pat<(and GR64:$src, 0xffff),
1269 (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit)))>;
1270 // r & (2^8-1) ==> movz
1271 def : Pat<(and GR64:$src, 0xff),
1272 (MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit)))>;
1273 // r & (2^8-1) ==> movz
1274 def : Pat<(and GR32:$src1, 0xff),
1275 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>,
1276 Requires<[In64BitMode]>;
1277 // r & (2^8-1) ==> movz
1278 def : Pat<(and GR16:$src1, 0xff),
1279 (EXTRACT_SUBREG (MOVZX32rr8 (i8
1280 (EXTRACT_SUBREG GR16:$src1, sub_8bit))), sub_16bit)>,
1281 Requires<[In64BitMode]>;
1284 // sext_inreg patterns
1285 def : Pat<(sext_inreg GR32:$src, i16),
1286 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>;
1287 def : Pat<(sext_inreg GR32:$src, i8),
1288 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1291 Requires<[In32BitMode]>;
1293 def : Pat<(sext_inreg GR16:$src, i8),
1294 (EXTRACT_SUBREG (i32 (MOVSX32rr8 (EXTRACT_SUBREG
1295 (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), sub_8bit))),
1297 Requires<[In32BitMode]>;
1299 def : Pat<(sext_inreg GR64:$src, i32),
1300 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
1301 def : Pat<(sext_inreg GR64:$src, i16),
1302 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>;
1303 def : Pat<(sext_inreg GR64:$src, i8),
1304 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>;
1305 def : Pat<(sext_inreg GR32:$src, i8),
1306 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>,
1307 Requires<[In64BitMode]>;
1308 def : Pat<(sext_inreg GR16:$src, i8),
1309 (EXTRACT_SUBREG (MOVSX32rr8
1310 (EXTRACT_SUBREG GR16:$src, sub_8bit)), sub_16bit)>,
1311 Requires<[In64BitMode]>;
1313 // sext, sext_load, zext, zext_load
1314 def: Pat<(i16 (sext GR8:$src)),
1315 (EXTRACT_SUBREG (MOVSX32rr8 GR8:$src), sub_16bit)>;
1316 def: Pat<(sextloadi16i8 addr:$src),
1317 (EXTRACT_SUBREG (MOVSX32rm8 addr:$src), sub_16bit)>;
1318 def: Pat<(i16 (zext GR8:$src)),
1319 (EXTRACT_SUBREG (MOVZX32rr8 GR8:$src), sub_16bit)>;
1320 def: Pat<(zextloadi16i8 addr:$src),
1321 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>;
1324 def : Pat<(i16 (trunc GR32:$src)),
1325 (EXTRACT_SUBREG GR32:$src, sub_16bit)>;
1326 def : Pat<(i8 (trunc GR32:$src)),
1327 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1329 Requires<[In32BitMode]>;
1330 def : Pat<(i8 (trunc GR16:$src)),
1331 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1333 Requires<[In32BitMode]>;
1334 def : Pat<(i32 (trunc GR64:$src)),
1335 (EXTRACT_SUBREG GR64:$src, sub_32bit)>;
1336 def : Pat<(i16 (trunc GR64:$src)),
1337 (EXTRACT_SUBREG GR64:$src, sub_16bit)>;
1338 def : Pat<(i8 (trunc GR64:$src)),
1339 (EXTRACT_SUBREG GR64:$src, sub_8bit)>;
1340 def : Pat<(i8 (trunc GR32:$src)),
1341 (EXTRACT_SUBREG GR32:$src, sub_8bit)>,
1342 Requires<[In64BitMode]>;
1343 def : Pat<(i8 (trunc GR16:$src)),
1344 (EXTRACT_SUBREG GR16:$src, sub_8bit)>,
1345 Requires<[In64BitMode]>;
1347 // h-register tricks
1348 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
1349 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1351 Requires<[In32BitMode]>;
1352 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
1353 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1355 Requires<[In32BitMode]>;
1356 def : Pat<(srl GR16:$src, (i8 8)),
1359 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1362 Requires<[In32BitMode]>;
1363 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1364 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1367 Requires<[In32BitMode]>;
1368 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1369 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1372 Requires<[In32BitMode]>;
1373 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1374 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1377 Requires<[In32BitMode]>;
1378 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1379 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1382 Requires<[In32BitMode]>;
1384 // h-register tricks.
1385 // For now, be conservative on x86-64 and use an h-register extract only if the
1386 // value is immediately zero-extended or stored, which are somewhat common
1387 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
1388 // from being allocated in the same instruction as the h register, as there's
1389 // currently no way to describe this requirement to the register allocator.
1391 // h-register extract and zero-extend.
1392 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
1396 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1399 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1401 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1403 Requires<[In64BitMode]>;
1404 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1405 (MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1408 Requires<[In64BitMode]>;
1409 def : Pat<(srl GR16:$src, (i8 8)),
1412 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1415 Requires<[In64BitMode]>;
1416 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1418 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1420 Requires<[In64BitMode]>;
1421 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1423 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1425 Requires<[In64BitMode]>;
1426 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
1430 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1433 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
1437 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1441 // h-register extract and store.
1442 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
1445 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1447 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
1450 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1452 Requires<[In64BitMode]>;
1453 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
1456 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1458 Requires<[In64BitMode]>;
1461 // (shl x, 1) ==> (add x, x)
1462 // Note that if x is undef (immediate or otherwise), we could theoretically
1463 // end up with the two uses of x getting different values, producing a result
1464 // where the least significant bit is not 0. However, the probability of this
1465 // happening is considered low enough that this is officially not a
1467 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
1468 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
1469 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
1470 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1472 // Helper imms that check if a mask doesn't change significant shift bits.
1473 def immShift32 : ImmLeaf<i8, [{ return CountTrailingOnes_32(Imm) >= 5; }]>;
1474 def immShift64 : ImmLeaf<i8, [{ return CountTrailingOnes_32(Imm) >= 6; }]>;
1476 // (shl x (and y, 31)) ==> (shl x, y)
1477 def : Pat<(shl GR8:$src1, (and CL, immShift32)),
1478 (SHL8rCL GR8:$src1)>;
1479 def : Pat<(shl GR16:$src1, (and CL, immShift32)),
1480 (SHL16rCL GR16:$src1)>;
1481 def : Pat<(shl GR32:$src1, (and CL, immShift32)),
1482 (SHL32rCL GR32:$src1)>;
1483 def : Pat<(store (shl (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst),
1484 (SHL8mCL addr:$dst)>;
1485 def : Pat<(store (shl (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst),
1486 (SHL16mCL addr:$dst)>;
1487 def : Pat<(store (shl (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst),
1488 (SHL32mCL addr:$dst)>;
1490 def : Pat<(srl GR8:$src1, (and CL, immShift32)),
1491 (SHR8rCL GR8:$src1)>;
1492 def : Pat<(srl GR16:$src1, (and CL, immShift32)),
1493 (SHR16rCL GR16:$src1)>;
1494 def : Pat<(srl GR32:$src1, (and CL, immShift32)),
1495 (SHR32rCL GR32:$src1)>;
1496 def : Pat<(store (srl (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst),
1497 (SHR8mCL addr:$dst)>;
1498 def : Pat<(store (srl (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst),
1499 (SHR16mCL addr:$dst)>;
1500 def : Pat<(store (srl (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst),
1501 (SHR32mCL addr:$dst)>;
1503 def : Pat<(sra GR8:$src1, (and CL, immShift32)),
1504 (SAR8rCL GR8:$src1)>;
1505 def : Pat<(sra GR16:$src1, (and CL, immShift32)),
1506 (SAR16rCL GR16:$src1)>;
1507 def : Pat<(sra GR32:$src1, (and CL, immShift32)),
1508 (SAR32rCL GR32:$src1)>;
1509 def : Pat<(store (sra (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst),
1510 (SAR8mCL addr:$dst)>;
1511 def : Pat<(store (sra (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst),
1512 (SAR16mCL addr:$dst)>;
1513 def : Pat<(store (sra (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst),
1514 (SAR32mCL addr:$dst)>;
1516 // (shl x (and y, 63)) ==> (shl x, y)
1517 def : Pat<(shl GR64:$src1, (and CL, immShift64)),
1518 (SHL64rCL GR64:$src1)>;
1519 def : Pat<(store (shl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1520 (SHL64mCL addr:$dst)>;
1522 def : Pat<(srl GR64:$src1, (and CL, immShift64)),
1523 (SHR64rCL GR64:$src1)>;
1524 def : Pat<(store (srl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1525 (SHR64mCL addr:$dst)>;
1527 def : Pat<(sra GR64:$src1, (and CL, immShift64)),
1528 (SAR64rCL GR64:$src1)>;
1529 def : Pat<(store (sra (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1530 (SAR64mCL addr:$dst)>;
1533 // (anyext (setcc_carry)) -> (setcc_carry)
1534 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1536 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1538 def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))),
1544 //===----------------------------------------------------------------------===//
1545 // EFLAGS-defining Patterns
1546 //===----------------------------------------------------------------------===//
1549 def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>;
1550 def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
1551 def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
1554 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
1555 (ADD8rm GR8:$src1, addr:$src2)>;
1556 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
1557 (ADD16rm GR16:$src1, addr:$src2)>;
1558 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
1559 (ADD32rm GR32:$src1, addr:$src2)>;
1562 def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>;
1563 def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
1564 def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
1565 def : Pat<(add GR16:$src1, i16immSExt8:$src2),
1566 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
1567 def : Pat<(add GR32:$src1, i32immSExt8:$src2),
1568 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
1571 def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>;
1572 def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
1573 def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
1576 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
1577 (SUB8rm GR8:$src1, addr:$src2)>;
1578 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
1579 (SUB16rm GR16:$src1, addr:$src2)>;
1580 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
1581 (SUB32rm GR32:$src1, addr:$src2)>;
1584 def : Pat<(sub GR8:$src1, imm:$src2),
1585 (SUB8ri GR8:$src1, imm:$src2)>;
1586 def : Pat<(sub GR16:$src1, imm:$src2),
1587 (SUB16ri GR16:$src1, imm:$src2)>;
1588 def : Pat<(sub GR32:$src1, imm:$src2),
1589 (SUB32ri GR32:$src1, imm:$src2)>;
1590 def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
1591 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
1592 def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
1593 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
1596 def : Pat<(mul GR16:$src1, GR16:$src2),
1597 (IMUL16rr GR16:$src1, GR16:$src2)>;
1598 def : Pat<(mul GR32:$src1, GR32:$src2),
1599 (IMUL32rr GR32:$src1, GR32:$src2)>;
1602 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
1603 (IMUL16rm GR16:$src1, addr:$src2)>;
1604 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
1605 (IMUL32rm GR32:$src1, addr:$src2)>;
1608 def : Pat<(mul GR16:$src1, imm:$src2),
1609 (IMUL16rri GR16:$src1, imm:$src2)>;
1610 def : Pat<(mul GR32:$src1, imm:$src2),
1611 (IMUL32rri GR32:$src1, imm:$src2)>;
1612 def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
1613 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
1614 def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
1615 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
1617 // reg = mul mem, imm
1618 def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
1619 (IMUL16rmi addr:$src1, imm:$src2)>;
1620 def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
1621 (IMUL32rmi addr:$src1, imm:$src2)>;
1622 def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
1623 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
1624 def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
1625 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
1627 // Patterns for nodes that do not produce flags, for instructions that do.
1630 def : Pat<(add GR64:$src1, GR64:$src2),
1631 (ADD64rr GR64:$src1, GR64:$src2)>;
1632 def : Pat<(add GR64:$src1, i64immSExt8:$src2),
1633 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1634 def : Pat<(add GR64:$src1, i64immSExt32:$src2),
1635 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1636 def : Pat<(add GR64:$src1, (loadi64 addr:$src2)),
1637 (ADD64rm GR64:$src1, addr:$src2)>;
1640 def : Pat<(sub GR64:$src1, GR64:$src2),
1641 (SUB64rr GR64:$src1, GR64:$src2)>;
1642 def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)),
1643 (SUB64rm GR64:$src1, addr:$src2)>;
1644 def : Pat<(sub GR64:$src1, i64immSExt8:$src2),
1645 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1646 def : Pat<(sub GR64:$src1, i64immSExt32:$src2),
1647 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1650 def : Pat<(mul GR64:$src1, GR64:$src2),
1651 (IMUL64rr GR64:$src1, GR64:$src2)>;
1652 def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)),
1653 (IMUL64rm GR64:$src1, addr:$src2)>;
1654 def : Pat<(mul GR64:$src1, i64immSExt8:$src2),
1655 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
1656 def : Pat<(mul GR64:$src1, i64immSExt32:$src2),
1657 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
1658 def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2),
1659 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
1660 def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2),
1661 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
1664 def : Pat<(add GR8 :$src, 1), (INC8r GR8 :$src)>;
1665 def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>, Requires<[In32BitMode]>;
1666 def : Pat<(add GR16:$src, 1), (INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1667 def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>, Requires<[In32BitMode]>;
1668 def : Pat<(add GR32:$src, 1), (INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1669 def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>;
1672 def : Pat<(add GR8 :$src, -1), (DEC8r GR8 :$src)>;
1673 def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
1674 def : Pat<(add GR16:$src, -1), (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1675 def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
1676 def : Pat<(add GR32:$src, -1), (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1677 def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>;
1680 def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
1681 def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
1682 def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
1683 def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>;
1686 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
1687 (OR8rm GR8:$src1, addr:$src2)>;
1688 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
1689 (OR16rm GR16:$src1, addr:$src2)>;
1690 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
1691 (OR32rm GR32:$src1, addr:$src2)>;
1692 def : Pat<(or GR64:$src1, (loadi64 addr:$src2)),
1693 (OR64rm GR64:$src1, addr:$src2)>;
1696 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
1697 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
1698 def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
1699 def : Pat<(or GR16:$src1, i16immSExt8:$src2),
1700 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1701 def : Pat<(or GR32:$src1, i32immSExt8:$src2),
1702 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1703 def : Pat<(or GR64:$src1, i64immSExt8:$src2),
1704 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1705 def : Pat<(or GR64:$src1, i64immSExt32:$src2),
1706 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1709 def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>;
1710 def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
1711 def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
1712 def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>;
1715 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
1716 (XOR8rm GR8:$src1, addr:$src2)>;
1717 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
1718 (XOR16rm GR16:$src1, addr:$src2)>;
1719 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
1720 (XOR32rm GR32:$src1, addr:$src2)>;
1721 def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)),
1722 (XOR64rm GR64:$src1, addr:$src2)>;
1725 def : Pat<(xor GR8:$src1, imm:$src2),
1726 (XOR8ri GR8:$src1, imm:$src2)>;
1727 def : Pat<(xor GR16:$src1, imm:$src2),
1728 (XOR16ri GR16:$src1, imm:$src2)>;
1729 def : Pat<(xor GR32:$src1, imm:$src2),
1730 (XOR32ri GR32:$src1, imm:$src2)>;
1731 def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
1732 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1733 def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
1734 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1735 def : Pat<(xor GR64:$src1, i64immSExt8:$src2),
1736 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1737 def : Pat<(xor GR64:$src1, i64immSExt32:$src2),
1738 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1741 def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>;
1742 def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
1743 def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
1744 def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>;
1747 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
1748 (AND8rm GR8:$src1, addr:$src2)>;
1749 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
1750 (AND16rm GR16:$src1, addr:$src2)>;
1751 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
1752 (AND32rm GR32:$src1, addr:$src2)>;
1753 def : Pat<(and GR64:$src1, (loadi64 addr:$src2)),
1754 (AND64rm GR64:$src1, addr:$src2)>;
1757 def : Pat<(and GR8:$src1, imm:$src2),
1758 (AND8ri GR8:$src1, imm:$src2)>;
1759 def : Pat<(and GR16:$src1, imm:$src2),
1760 (AND16ri GR16:$src1, imm:$src2)>;
1761 def : Pat<(and GR32:$src1, imm:$src2),
1762 (AND32ri GR32:$src1, imm:$src2)>;
1763 def : Pat<(and GR16:$src1, i16immSExt8:$src2),
1764 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
1765 def : Pat<(and GR32:$src1, i32immSExt8:$src2),
1766 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
1767 def : Pat<(and GR64:$src1, i64immSExt8:$src2),
1768 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
1769 def : Pat<(and GR64:$src1, i64immSExt32:$src2),
1770 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>;
1772 // Bit scan instruction patterns to match explicit zero-undef behavior.
1773 def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr GR16:$src)>;
1774 def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr GR32:$src)>;
1775 def : Pat<(cttz_zero_undef GR64:$src), (BSF64rr GR64:$src)>;
1776 def : Pat<(cttz_zero_undef (loadi16 addr:$src)), (BSF16rm addr:$src)>;
1777 def : Pat<(cttz_zero_undef (loadi32 addr:$src)), (BSF32rm addr:$src)>;
1778 def : Pat<(cttz_zero_undef (loadi64 addr:$src)), (BSF64rm addr:$src)>;