1 //===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the various pseudo instructions used by the compiler,
11 // as well as Pat patterns used during instruction selection.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Pattern Matching Support
18 def GetLo32XForm : SDNodeXForm<imm, [{
19 // Transformation function: get the low 32 bits.
20 return getI32Imm((unsigned)N->getZExtValue());
23 def GetLo8XForm : SDNodeXForm<imm, [{
24 // Transformation function: get the low 8 bits.
25 return getI8Imm((uint8_t)N->getZExtValue());
29 //===----------------------------------------------------------------------===//
30 // Random Pseudo Instructions.
32 // PIC base construction. This expands to code that looks like this:
35 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
36 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
40 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
41 // a stack adjustment and the codegen must know that they may modify the stack
42 // pointer before prolog-epilog rewriting occurs.
43 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
44 // sub / add which can clobber EFLAGS.
45 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
46 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
48 [(X86callseq_start timm:$amt)]>,
49 Requires<[In32BitMode]>;
50 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
52 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
53 Requires<[In32BitMode]>;
56 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
57 // a stack adjustment and the codegen must know that they may modify the stack
58 // pointer before prolog-epilog rewriting occurs.
59 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
60 // sub / add which can clobber EFLAGS.
61 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
62 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
64 [(X86callseq_start timm:$amt)]>,
65 Requires<[In64BitMode]>;
66 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
68 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
69 Requires<[In64BitMode]>;
74 // x86-64 va_start lowering magic.
75 let usesCustomInserter = 1 in {
76 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
79 i64imm:$regsavefi, i64imm:$offset,
81 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
82 [(X86vastart_save_xmm_regs GR8:$al,
86 // The VAARG_64 pseudo-instruction takes the address of the va_list,
87 // and places the address of the next argument into a register.
88 let Defs = [EFLAGS] in
89 def VAARG_64 : I<0, Pseudo,
91 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align),
92 "#VAARG_64 $dst, $ap, $size, $mode, $align",
94 (X86vaarg64 addr:$ap, imm:$size, imm:$mode, imm:$align)),
97 // Dynamic stack allocation yields a _chkstk or _alloca call for all Windows
98 // targets. These calls are needed to probe the stack when allocating more than
99 // 4k bytes in one go. Touching the stack at 4K increments is necessary to
100 // ensure that the guard pages used by the OS virtual memory manager are
101 // allocated in correct sequence.
102 // The main point of having separate instruction are extra unmodelled effects
103 // (compared to ordinary calls) like stack pointer change.
105 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
106 def WIN_ALLOCA : I<0, Pseudo, (outs), (ins),
107 "# dynamic stack allocation",
110 // When using segmented stacks these are lowered into instructions which first
111 // check if the current stacklet has enough free memory. If it does, memory is
112 // allocated by bumping the stack pointer. Otherwise memory is allocated from
115 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
116 def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size),
117 "# variable sized alloca for segmented stacks",
119 (X86SegAlloca GR32:$size))]>,
120 Requires<[In32BitMode]>;
122 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
123 def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size),
124 "# variable sized alloca for segmented stacks",
126 (X86SegAlloca GR64:$size))]>,
127 Requires<[In64BitMode]>;
130 // The MSVC runtime contains an _ftol2 routine for converting floating-point
131 // to integer values. It has a strange calling convention: the input is
132 // popped from the x87 stack, and the return value is given in EDX:EAX. No
133 // other registers (aside from flags) are touched.
134 // Microsoft toolchains do not support 80-bit precision, so a WIN_FTOL_80
135 // variant is unnecessary.
137 let Defs = [EAX, EDX, EFLAGS], FPForm = SpecialFP in {
138 def WIN_FTOL_32 : I<0, Pseudo, (outs), (ins RFP32:$src),
140 [(X86WinFTOL RFP32:$src)]>,
141 Requires<[In32BitMode]>;
143 def WIN_FTOL_64 : I<0, Pseudo, (outs), (ins RFP64:$src),
145 [(X86WinFTOL RFP64:$src)]>,
146 Requires<[In32BitMode]>;
149 //===----------------------------------------------------------------------===//
150 // EH Pseudo Instructions
152 let isTerminator = 1, isReturn = 1, isBarrier = 1,
153 hasCtrlDep = 1, isCodeGenOnly = 1 in {
154 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
155 "ret\t#eh_return, addr: $addr",
156 [(X86ehret GR32:$addr)]>;
160 let isTerminator = 1, isReturn = 1, isBarrier = 1,
161 hasCtrlDep = 1, isCodeGenOnly = 1 in {
162 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
163 "ret\t#eh_return, addr: $addr",
164 [(X86ehret GR64:$addr)]>;
168 //===----------------------------------------------------------------------===//
169 // Pseudo instructions used by segmented stacks.
172 // This is lowered into a RET instruction by MCInstLower. We need
173 // this so that we don't have to have a MachineBasicBlock which ends
174 // with a RET and also has successors.
175 let isPseudo = 1 in {
176 def MORESTACK_RET: I<0, Pseudo, (outs), (ins),
179 // This instruction is lowered to a RET followed by a MOV. The two
180 // instructions are not generated on a higher level since then the
181 // verifier sees a MachineBasicBlock ending with a non-terminator.
182 def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins),
186 //===----------------------------------------------------------------------===//
187 // Alias Instructions
188 //===----------------------------------------------------------------------===//
190 // Alias instructions that map movr0 to xor.
191 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
192 // FIXME: Set encoding to pseudo.
193 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
194 isCodeGenOnly = 1 in {
195 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "",
196 [(set GR8:$dst, 0)]>;
198 // We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller
199 // encoding and avoids a partial-register update sometimes, but doing so
200 // at isel time interferes with rematerialization in the current register
201 // allocator. For now, this is rewritten when the instruction is lowered
203 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
205 [(set GR16:$dst, 0)]>, OpSize;
207 // FIXME: Set encoding to pseudo.
208 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "",
209 [(set GR32:$dst, 0)]>;
212 // We want to rewrite MOV64r0 in terms of MOV32r0, because it's sometimes a
213 // smaller encoding, but doing so at isel time interferes with rematerialization
214 // in the current register allocator. For now, this is rewritten when the
215 // instruction is lowered to an MCInst.
216 // FIXME: AddedComplexity gives this a higher priority than MOV64ri32. Remove
217 // when we have a better way to specify isel priority.
218 let Defs = [EFLAGS], isCodeGenOnly=1,
219 AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
220 def MOV64r0 : I<0x31, MRMInitReg, (outs GR64:$dst), (ins), "",
221 [(set GR64:$dst, 0)]>;
223 // Materialize i64 constant where top 32-bits are zero. This could theoretically
224 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
225 // that would make it more difficult to rematerialize.
226 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1,
228 def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
229 "", [(set GR64:$dst, i64immZExt32:$src)]>;
231 // Use sbb to materialize carry bit.
232 let Uses = [EFLAGS], Defs = [EFLAGS], isCodeGenOnly = 1 in {
233 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
234 // However, Pat<> can't replicate the destination reg into the inputs of the
236 // FIXME: Change these to have encoding Pseudo when X86MCCodeEmitter replaces
238 def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins), "",
239 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
240 def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins), "",
241 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>,
243 def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins), "",
244 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
245 def SETB_C64r : RI<0x19, MRMInitReg, (outs GR64:$dst), (ins), "",
246 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
250 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
252 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
254 def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
257 def : Pat<(i16 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
259 def : Pat<(i32 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
261 def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
264 // We canonicalize 'setb' to "(and (sbb reg,reg), 1)" on the hope that the and
265 // will be eliminated and that the sbb can be extended up to a wider type. When
266 // this happens, it is great. However, if we are left with an 8-bit sbb and an
267 // and, we might as well just match it as a setb.
268 def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1),
271 // (add OP, SETB) -> (adc OP, 0)
272 def : Pat<(add (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR8:$op),
273 (ADC8ri GR8:$op, 0)>;
274 def : Pat<(add (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR32:$op),
275 (ADC32ri8 GR32:$op, 0)>;
276 def : Pat<(add (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR64:$op),
277 (ADC64ri8 GR64:$op, 0)>;
279 // (sub OP, SETB) -> (sbb OP, 0)
280 def : Pat<(sub GR8:$op, (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
281 (SBB8ri GR8:$op, 0)>;
282 def : Pat<(sub GR32:$op, (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
283 (SBB32ri8 GR32:$op, 0)>;
284 def : Pat<(sub GR64:$op, (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
285 (SBB64ri8 GR64:$op, 0)>;
287 // (sub OP, SETCC_CARRY) -> (adc OP, 0)
288 def : Pat<(sub GR8:$op, (i8 (X86setcc_c X86_COND_B, EFLAGS))),
289 (ADC8ri GR8:$op, 0)>;
290 def : Pat<(sub GR32:$op, (i32 (X86setcc_c X86_COND_B, EFLAGS))),
291 (ADC32ri8 GR32:$op, 0)>;
292 def : Pat<(sub GR64:$op, (i64 (X86setcc_c X86_COND_B, EFLAGS))),
293 (ADC64ri8 GR64:$op, 0)>;
295 //===----------------------------------------------------------------------===//
296 // String Pseudo Instructions
298 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
299 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
300 [(X86rep_movs i8)]>, REP;
301 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
302 [(X86rep_movs i16)]>, REP, OpSize;
303 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
304 [(X86rep_movs i32)]>, REP;
307 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in
308 def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
309 [(X86rep_movs i64)]>, REP;
312 // FIXME: Should use "(X86rep_stos AL)" as the pattern.
313 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI], isCodeGenOnly = 1 in
314 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
315 [(X86rep_stos i8)]>, REP;
316 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI], isCodeGenOnly = 1 in
317 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
318 [(X86rep_stos i16)]>, REP, OpSize;
319 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI], isCodeGenOnly = 1 in
320 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
321 [(X86rep_stos i32)]>, REP;
323 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI], isCodeGenOnly = 1 in
324 def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
325 [(X86rep_stos i64)]>, REP;
328 //===----------------------------------------------------------------------===//
329 // Thread Local Storage Instructions
333 // All calls clobber the non-callee saved registers. ESP is marked as
334 // a use to prevent stack-pointer assignments that appear immediately
335 // before calls from potentially appearing dead.
336 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
337 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
338 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
339 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
341 def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
343 [(X86tlsaddr tls32addr:$sym)]>,
344 Requires<[In32BitMode]>;
346 // All calls clobber the non-callee saved registers. RSP is marked as
347 // a use to prevent stack-pointer assignments that appear immediately
348 // before calls from potentially appearing dead.
349 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
350 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
351 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
352 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
353 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
355 def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
357 [(X86tlsaddr tls64addr:$sym)]>,
358 Requires<[In64BitMode]>;
360 // Darwin TLS Support
361 // For i386, the address of the thunk is passed on the stack, on return the
362 // address of the variable is in %eax. %ecx is trashed during the function
363 // call. All other registers are preserved.
364 let Defs = [EAX, ECX, EFLAGS],
366 usesCustomInserter = 1 in
367 def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
369 [(X86TLSCall addr:$sym)]>,
370 Requires<[In32BitMode]>;
372 // For x86_64, the address of the thunk is passed in %rdi, on return
373 // the address of the variable is in %rax. All other registers are preserved.
374 let Defs = [RAX, EFLAGS],
376 usesCustomInserter = 1 in
377 def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
379 [(X86TLSCall addr:$sym)]>,
380 Requires<[In64BitMode]>;
383 //===----------------------------------------------------------------------===//
384 // Conditional Move Pseudo Instructions
386 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
387 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
388 // however that requires promoting the operands, and can induce additional
389 // i8 register pressure.
390 let usesCustomInserter = 1, Uses = [EFLAGS] in {
391 def CMOV_GR8 : I<0, Pseudo,
392 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
394 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
395 imm:$cond, EFLAGS))]>;
397 let Predicates = [NoCMov] in {
398 def CMOV_GR32 : I<0, Pseudo,
399 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cond),
400 "#CMOV_GR32* PSEUDO!",
402 (X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>;
403 def CMOV_GR16 : I<0, Pseudo,
404 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cond),
405 "#CMOV_GR16* PSEUDO!",
407 (X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>;
408 def CMOV_RFP32 : I<0, Pseudo,
410 (ins RFP32:$src1, RFP32:$src2, i8imm:$cond),
411 "#CMOV_RFP32 PSEUDO!",
413 (X86cmov RFP32:$src1, RFP32:$src2, imm:$cond,
415 def CMOV_RFP64 : I<0, Pseudo,
417 (ins RFP64:$src1, RFP64:$src2, i8imm:$cond),
418 "#CMOV_RFP64 PSEUDO!",
420 (X86cmov RFP64:$src1, RFP64:$src2, imm:$cond,
422 def CMOV_RFP80 : I<0, Pseudo,
424 (ins RFP80:$src1, RFP80:$src2, i8imm:$cond),
425 "#CMOV_RFP80 PSEUDO!",
427 (X86cmov RFP80:$src1, RFP80:$src2, imm:$cond,
429 } // Predicates = [NoCMov]
430 } // UsesCustomInserter = 1, Uses = [EFLAGS]
433 //===----------------------------------------------------------------------===//
434 // Atomic Instruction Pseudo Instructions
435 //===----------------------------------------------------------------------===//
437 // Atomic exchange, and, or, xor
438 let Constraints = "$val = $dst", Defs = [EFLAGS],
439 usesCustomInserter = 1 in {
441 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
443 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
444 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
446 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
447 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
449 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
450 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
451 "#ATOMNAND8 PSEUDO!",
452 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
454 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
455 "#ATOMAND16 PSEUDO!",
456 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
457 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
459 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
460 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
461 "#ATOMXOR16 PSEUDO!",
462 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
463 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
464 "#ATOMNAND16 PSEUDO!",
465 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
466 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
467 "#ATOMMIN16 PSEUDO!",
468 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
469 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
470 "#ATOMMAX16 PSEUDO!",
471 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
472 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
473 "#ATOMUMIN16 PSEUDO!",
474 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
475 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
476 "#ATOMUMAX16 PSEUDO!",
477 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
480 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
481 "#ATOMAND32 PSEUDO!",
482 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
483 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
485 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
486 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
487 "#ATOMXOR32 PSEUDO!",
488 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
489 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
490 "#ATOMNAND32 PSEUDO!",
491 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
492 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
493 "#ATOMMIN32 PSEUDO!",
494 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
495 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
496 "#ATOMMAX32 PSEUDO!",
497 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
498 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
499 "#ATOMUMIN32 PSEUDO!",
500 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
501 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
502 "#ATOMUMAX32 PSEUDO!",
503 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
507 def ATOMAND64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
508 "#ATOMAND64 PSEUDO!",
509 [(set GR64:$dst, (atomic_load_and_64 addr:$ptr, GR64:$val))]>;
510 def ATOMOR64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
512 [(set GR64:$dst, (atomic_load_or_64 addr:$ptr, GR64:$val))]>;
513 def ATOMXOR64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
514 "#ATOMXOR64 PSEUDO!",
515 [(set GR64:$dst, (atomic_load_xor_64 addr:$ptr, GR64:$val))]>;
516 def ATOMNAND64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
517 "#ATOMNAND64 PSEUDO!",
518 [(set GR64:$dst, (atomic_load_nand_64 addr:$ptr, GR64:$val))]>;
519 def ATOMMIN64: I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val),
520 "#ATOMMIN64 PSEUDO!",
521 [(set GR64:$dst, (atomic_load_min_64 addr:$ptr, GR64:$val))]>;
522 def ATOMMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
523 "#ATOMMAX64 PSEUDO!",
524 [(set GR64:$dst, (atomic_load_max_64 addr:$ptr, GR64:$val))]>;
525 def ATOMUMIN64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
526 "#ATOMUMIN64 PSEUDO!",
527 [(set GR64:$dst, (atomic_load_umin_64 addr:$ptr, GR64:$val))]>;
528 def ATOMUMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
529 "#ATOMUMAX64 PSEUDO!",
530 [(set GR64:$dst, (atomic_load_umax_64 addr:$ptr, GR64:$val))]>;
533 let Constraints = "$val1 = $dst1, $val2 = $dst2",
534 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
535 Uses = [EAX, EBX, ECX, EDX],
536 mayLoad = 1, mayStore = 1,
537 usesCustomInserter = 1 in {
538 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
539 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
540 "#ATOMAND6432 PSEUDO!", []>;
541 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
542 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
543 "#ATOMOR6432 PSEUDO!", []>;
544 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
545 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
546 "#ATOMXOR6432 PSEUDO!", []>;
547 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
548 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
549 "#ATOMNAND6432 PSEUDO!", []>;
550 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
551 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
552 "#ATOMADD6432 PSEUDO!", []>;
553 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
554 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
555 "#ATOMSUB6432 PSEUDO!", []>;
556 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
557 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
558 "#ATOMSWAP6432 PSEUDO!", []>;
561 //===----------------------------------------------------------------------===//
562 // Normal-Instructions-With-Lock-Prefix Pseudo Instructions
563 //===----------------------------------------------------------------------===//
565 // FIXME: Use normal instructions and add lock prefix dynamically.
569 // TODO: Get this to fold the constant into the instruction.
570 let isCodeGenOnly = 1, Defs = [EFLAGS] in
571 def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero),
573 "or{l}\t{$zero, $dst|$dst, $zero}",
574 []>, Requires<[In32BitMode]>, LOCK;
576 let hasSideEffects = 1 in
577 def Int_MemBarrier : I<0, Pseudo, (outs), (ins),
581 // RegOpc corresponds to the mr version of the instruction
582 // ImmOpc corresponds to the mi version of the instruction
583 // ImmOpc8 corresponds to the mi8 version of the instruction
584 // ImmMod corresponds to the instruction format of the mi and mi8 versions
585 multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8,
586 Format ImmMod, string mnemonic> {
587 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1 in {
589 def #NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
590 RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 },
591 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
592 !strconcat("lock\n\t", mnemonic, "{b}\t",
593 "{$src2, $dst|$dst, $src2}"),
595 def #NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
596 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
597 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
598 !strconcat("lock\n\t", mnemonic, "{w}\t",
599 "{$src2, $dst|$dst, $src2}"),
601 def #NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
602 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
603 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
604 !strconcat("lock\n\t", mnemonic, "{l}\t",
605 "{$src2, $dst|$dst, $src2}"),
607 def #NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
608 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
609 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
610 !strconcat("lock\n\t", mnemonic, "{q}\t",
611 "{$src2, $dst|$dst, $src2}"),
614 def #NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
615 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 },
616 ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2),
617 !strconcat("lock\n\t", mnemonic, "{b}\t",
618 "{$src2, $dst|$dst, $src2}"),
621 def #NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
622 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
623 ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2),
624 !strconcat("lock\n\t", mnemonic, "{w}\t",
625 "{$src2, $dst|$dst, $src2}"),
628 def #NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
629 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
630 ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2),
631 !strconcat("lock\n\t", mnemonic, "{l}\t",
632 "{$src2, $dst|$dst, $src2}"),
635 def #NAME#64mi32 : RIi32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
636 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
637 ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2),
638 !strconcat("lock\n\t", mnemonic, "{q}\t",
639 "{$src2, $dst|$dst, $src2}"),
642 def #NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
643 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
644 ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2),
645 !strconcat("lock\n\t", mnemonic, "{w}\t",
646 "{$src2, $dst|$dst, $src2}"),
648 def #NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
649 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
650 ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2),
651 !strconcat("lock\n\t", mnemonic, "{l}\t",
652 "{$src2, $dst|$dst, $src2}"),
654 def #NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
655 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
656 ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2),
657 !strconcat("lock\n\t", mnemonic, "{q}\t",
658 "{$src2, $dst|$dst, $src2}"),
665 defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, "add">;
666 defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, "sub">;
667 defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, "or">;
668 defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, "and">;
669 defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, "xor">;
671 // Optimized codegen when the non-memory output is not used.
672 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1 in {
674 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
676 "inc{b}\t$dst", []>, LOCK;
677 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
679 "inc{w}\t$dst", []>, OpSize, LOCK;
680 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
682 "inc{l}\t$dst", []>, LOCK;
683 def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst),
685 "inc{q}\t$dst", []>, LOCK;
687 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
689 "dec{b}\t$dst", []>, LOCK;
690 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
692 "dec{w}\t$dst", []>, OpSize, LOCK;
693 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
695 "dec{l}\t$dst", []>, LOCK;
696 def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst),
698 "dec{q}\t$dst", []>, LOCK;
701 // Atomic compare and swap.
702 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX],
704 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr),
707 [(X86cas8 addr:$ptr)]>, TB, LOCK;
709 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX],
711 def LCMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$ptr),
714 [(X86cas16 addr:$ptr)]>, TB, LOCK,
715 Requires<[HasCmpxchg16b]>;
717 let Defs = [AL, EFLAGS], Uses = [AL], isCodeGenOnly = 1 in {
718 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
720 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
721 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
724 let Defs = [AX, EFLAGS], Uses = [AX], isCodeGenOnly = 1 in {
725 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
727 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
728 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
731 let Defs = [EAX, EFLAGS], Uses = [EAX], isCodeGenOnly = 1 in {
732 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
734 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
735 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
738 let Defs = [RAX, EFLAGS], Uses = [RAX], isCodeGenOnly = 1 in {
739 def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap),
741 "cmpxchg{q}\t{$swap, $ptr|$ptr, $swap}",
742 [(X86cas addr:$ptr, GR64:$swap, 8)]>, TB, LOCK;
745 // Atomic exchange and add
746 let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1 in {
747 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
749 "xadd{b}\t{$val, $ptr|$ptr, $val}",
750 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
752 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins GR16:$val, i16mem:$ptr),
754 "xadd{w}\t{$val, $ptr|$ptr, $val}",
755 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
757 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins GR32:$val, i32mem:$ptr),
759 "xadd{l}\t{$val, $ptr|$ptr, $val}",
760 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
762 def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins GR64:$val,i64mem:$ptr),
764 "xadd{q}\t{$val, $ptr|$ptr, $val}",
765 [(set GR64:$dst, (atomic_load_add_64 addr:$ptr, GR64:$val))]>,
769 def ACQUIRE_MOV8rm : I<0, Pseudo, (outs GR8 :$dst), (ins i8mem :$src),
770 "#ACQUIRE_MOV PSEUDO!",
771 [(set GR8:$dst, (atomic_load_8 addr:$src))]>;
772 def ACQUIRE_MOV16rm : I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$src),
773 "#ACQUIRE_MOV PSEUDO!",
774 [(set GR16:$dst, (atomic_load_16 addr:$src))]>;
775 def ACQUIRE_MOV32rm : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$src),
776 "#ACQUIRE_MOV PSEUDO!",
777 [(set GR32:$dst, (atomic_load_32 addr:$src))]>;
778 def ACQUIRE_MOV64rm : I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$src),
779 "#ACQUIRE_MOV PSEUDO!",
780 [(set GR64:$dst, (atomic_load_64 addr:$src))]>;
782 def RELEASE_MOV8mr : I<0, Pseudo, (outs), (ins i8mem :$dst, GR8 :$src),
783 "#RELEASE_MOV PSEUDO!",
784 [(atomic_store_8 addr:$dst, GR8 :$src)]>;
785 def RELEASE_MOV16mr : I<0, Pseudo, (outs), (ins i16mem:$dst, GR16:$src),
786 "#RELEASE_MOV PSEUDO!",
787 [(atomic_store_16 addr:$dst, GR16:$src)]>;
788 def RELEASE_MOV32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src),
789 "#RELEASE_MOV PSEUDO!",
790 [(atomic_store_32 addr:$dst, GR32:$src)]>;
791 def RELEASE_MOV64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src),
792 "#RELEASE_MOV PSEUDO!",
793 [(atomic_store_64 addr:$dst, GR64:$src)]>;
795 //===----------------------------------------------------------------------===//
796 // Conditional Move Pseudo Instructions.
797 //===----------------------------------------------------------------------===//
800 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after
801 // instruction selection into a branch sequence.
802 let Uses = [EFLAGS], usesCustomInserter = 1 in {
803 def CMOV_FR32 : I<0, Pseudo,
804 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
805 "#CMOV_FR32 PSEUDO!",
806 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
808 def CMOV_FR64 : I<0, Pseudo,
809 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
810 "#CMOV_FR64 PSEUDO!",
811 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
813 def CMOV_V4F32 : I<0, Pseudo,
814 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
815 "#CMOV_V4F32 PSEUDO!",
817 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
819 def CMOV_V2F64 : I<0, Pseudo,
820 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
821 "#CMOV_V2F64 PSEUDO!",
823 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
825 def CMOV_V2I64 : I<0, Pseudo,
826 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
827 "#CMOV_V2I64 PSEUDO!",
829 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
831 def CMOV_V8F32 : I<0, Pseudo,
832 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
833 "#CMOV_V8F32 PSEUDO!",
835 (v8f32 (X86cmov VR256:$t, VR256:$f, imm:$cond,
837 def CMOV_V4F64 : I<0, Pseudo,
838 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
839 "#CMOV_V4F64 PSEUDO!",
841 (v4f64 (X86cmov VR256:$t, VR256:$f, imm:$cond,
843 def CMOV_V4I64 : I<0, Pseudo,
844 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
845 "#CMOV_V4I64 PSEUDO!",
847 (v4i64 (X86cmov VR256:$t, VR256:$f, imm:$cond,
852 //===----------------------------------------------------------------------===//
853 // DAG Pattern Matching Rules
854 //===----------------------------------------------------------------------===//
856 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
857 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
858 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
859 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
860 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
861 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
862 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
864 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
865 (ADD32ri GR32:$src1, tconstpool:$src2)>;
866 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
867 (ADD32ri GR32:$src1, tjumptable:$src2)>;
868 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
869 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
870 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
871 (ADD32ri GR32:$src1, texternalsym:$src2)>;
872 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
873 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
875 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
876 (MOV32mi addr:$dst, tglobaladdr:$src)>;
877 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
878 (MOV32mi addr:$dst, texternalsym:$src)>;
879 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
880 (MOV32mi addr:$dst, tblockaddress:$src)>;
884 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
885 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
886 // 'movabs' predicate should handle this sort of thing.
887 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
888 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
889 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
890 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
891 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
892 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
893 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
894 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
895 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
896 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>;
898 // In static codegen with small code model, we can get the address of a label
899 // into a register with 'movl'. FIXME: This is a hack, the 'imm' predicate of
900 // the MOV64ri64i32 should accept these.
901 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
902 (MOV64ri64i32 tconstpool :$dst)>, Requires<[SmallCode]>;
903 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
904 (MOV64ri64i32 tjumptable :$dst)>, Requires<[SmallCode]>;
905 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
906 (MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>;
907 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
908 (MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>;
909 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
910 (MOV64ri64i32 tblockaddress:$dst)>, Requires<[SmallCode]>;
912 // In kernel code model, we can get the address of a label
913 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
914 // the MOV64ri32 should accept these.
915 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
916 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
917 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
918 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
919 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
920 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
921 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
922 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
923 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
924 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>;
926 // If we have small model and -static mode, it is safe to store global addresses
927 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
928 // for MOV64mi32 should handle this sort of thing.
929 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
930 (MOV64mi32 addr:$dst, tconstpool:$src)>,
931 Requires<[NearData, IsStatic]>;
932 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
933 (MOV64mi32 addr:$dst, tjumptable:$src)>,
934 Requires<[NearData, IsStatic]>;
935 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
936 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
937 Requires<[NearData, IsStatic]>;
938 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
939 (MOV64mi32 addr:$dst, texternalsym:$src)>,
940 Requires<[NearData, IsStatic]>;
941 def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst),
942 (MOV64mi32 addr:$dst, tblockaddress:$src)>,
943 Requires<[NearData, IsStatic]>;
949 // tls has some funny stuff here...
950 // This corresponds to movabs $foo@tpoff, %rax
951 def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)),
952 (MOV64ri tglobaltlsaddr :$dst)>;
953 // This corresponds to add $foo@tpoff, %rax
954 def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)),
955 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>;
956 // This corresponds to mov foo@tpoff(%rbx), %eax
957 def : Pat<(load (i64 (X86Wrapper tglobaltlsaddr :$dst))),
958 (MOV64rm tglobaltlsaddr :$dst)>;
961 // Direct PC relative function call for small code model. 32-bit displacement
962 // sign extended to 64-bit.
963 def : Pat<(X86call (i64 tglobaladdr:$dst)),
964 (CALL64pcrel32 tglobaladdr:$dst)>;
965 def : Pat<(X86call (i64 texternalsym:$dst)),
966 (CALL64pcrel32 texternalsym:$dst)>;
969 def : Pat<(X86tcret GR32_TC:$dst, imm:$off),
970 (TCRETURNri GR32_TC:$dst, imm:$off)>,
971 Requires<[In32BitMode]>;
973 // FIXME: This is disabled for 32-bit PIC mode because the global base
974 // register which is part of the address mode may be assigned a
975 // callee-saved register.
976 def : Pat<(X86tcret (load addr:$dst), imm:$off),
977 (TCRETURNmi addr:$dst, imm:$off)>,
978 Requires<[In32BitMode, IsNotPIC]>;
980 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
981 (TCRETURNdi texternalsym:$dst, imm:$off)>,
982 Requires<[In32BitMode]>;
984 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
985 (TCRETURNdi texternalsym:$dst, imm:$off)>,
986 Requires<[In32BitMode]>;
988 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
989 (TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>,
990 Requires<[In64BitMode]>;
992 def : Pat<(X86tcret (load addr:$dst), imm:$off),
993 (TCRETURNmi64 addr:$dst, imm:$off)>,
994 Requires<[In64BitMode]>;
996 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
997 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>,
998 Requires<[In64BitMode]>;
1000 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1001 (TCRETURNdi64 texternalsym:$dst, imm:$off)>,
1002 Requires<[In64BitMode]>;
1004 // Normal calls, with various flavors of addresses.
1005 def : Pat<(X86call (i32 tglobaladdr:$dst)),
1006 (CALLpcrel32 tglobaladdr:$dst)>;
1007 def : Pat<(X86call (i32 texternalsym:$dst)),
1008 (CALLpcrel32 texternalsym:$dst)>;
1009 def : Pat<(X86call (i32 imm:$dst)),
1010 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
1014 // TEST R,R is smaller than CMP R,0
1015 def : Pat<(X86cmp GR8:$src1, 0),
1016 (TEST8rr GR8:$src1, GR8:$src1)>;
1017 def : Pat<(X86cmp GR16:$src1, 0),
1018 (TEST16rr GR16:$src1, GR16:$src1)>;
1019 def : Pat<(X86cmp GR32:$src1, 0),
1020 (TEST32rr GR32:$src1, GR32:$src1)>;
1021 def : Pat<(X86cmp GR64:$src1, 0),
1022 (TEST64rr GR64:$src1, GR64:$src1)>;
1024 // Conditional moves with folded loads with operands swapped and conditions
1026 multiclass CMOVmr<PatLeaf InvertedCond, Instruction Inst16, Instruction Inst32,
1027 Instruction Inst64> {
1028 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS),
1029 (Inst16 GR16:$src2, addr:$src1)>;
1030 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS),
1031 (Inst32 GR32:$src2, addr:$src1)>;
1032 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS),
1033 (Inst64 GR64:$src2, addr:$src1)>;
1036 defm : CMOVmr<X86_COND_B , CMOVAE16rm, CMOVAE32rm, CMOVAE64rm>;
1037 defm : CMOVmr<X86_COND_AE, CMOVB16rm , CMOVB32rm , CMOVB64rm>;
1038 defm : CMOVmr<X86_COND_E , CMOVNE16rm, CMOVNE32rm, CMOVNE64rm>;
1039 defm : CMOVmr<X86_COND_NE, CMOVE16rm , CMOVE32rm , CMOVE64rm>;
1040 defm : CMOVmr<X86_COND_BE, CMOVA16rm , CMOVA32rm , CMOVA64rm>;
1041 defm : CMOVmr<X86_COND_A , CMOVBE16rm, CMOVBE32rm, CMOVBE64rm>;
1042 defm : CMOVmr<X86_COND_L , CMOVGE16rm, CMOVGE32rm, CMOVGE64rm>;
1043 defm : CMOVmr<X86_COND_GE, CMOVL16rm , CMOVL32rm , CMOVL64rm>;
1044 defm : CMOVmr<X86_COND_LE, CMOVG16rm , CMOVG32rm , CMOVG64rm>;
1045 defm : CMOVmr<X86_COND_G , CMOVLE16rm, CMOVLE32rm, CMOVLE64rm>;
1046 defm : CMOVmr<X86_COND_P , CMOVNP16rm, CMOVNP32rm, CMOVNP64rm>;
1047 defm : CMOVmr<X86_COND_NP, CMOVP16rm , CMOVP32rm , CMOVP64rm>;
1048 defm : CMOVmr<X86_COND_S , CMOVNS16rm, CMOVNS32rm, CMOVNS64rm>;
1049 defm : CMOVmr<X86_COND_NS, CMOVS16rm , CMOVS32rm , CMOVS64rm>;
1050 defm : CMOVmr<X86_COND_O , CMOVNO16rm, CMOVNO32rm, CMOVNO64rm>;
1051 defm : CMOVmr<X86_COND_NO, CMOVO16rm , CMOVO32rm , CMOVO64rm>;
1053 // zextload bool -> zextload byte
1054 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
1055 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
1056 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
1057 def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1059 // extload bool -> extload byte
1060 // When extloading from 16-bit and smaller memory locations into 64-bit
1061 // registers, use zero-extending loads so that the entire 64-bit register is
1062 // defined, avoiding partial-register updates.
1064 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
1065 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
1066 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
1067 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
1068 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
1069 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
1071 def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1072 def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>;
1073 def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
1074 // For other extloads, use subregs, since the high contents of the register are
1075 // defined after an extload.
1076 def : Pat<(extloadi64i32 addr:$src),
1077 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src),
1080 // anyext. Define these to do an explicit zero-extend to
1081 // avoid partial-register updates.
1082 def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG
1083 (MOVZX32rr8 GR8 :$src), sub_16bit)>;
1084 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
1086 // Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
1087 def : Pat<(i32 (anyext GR16:$src)),
1088 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>;
1090 def : Pat<(i64 (anyext GR8 :$src)), (MOVZX64rr8 GR8 :$src)>;
1091 def : Pat<(i64 (anyext GR16:$src)), (MOVZX64rr16 GR16 :$src)>;
1092 def : Pat<(i64 (anyext GR32:$src)),
1093 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1096 // Any instruction that defines a 32-bit result leaves the high half of the
1097 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
1098 // be copying from a truncate. And x86's cmov doesn't do anything if the
1099 // condition is false. But any other 32-bit operation will zero-extend
1101 def def32 : PatLeaf<(i32 GR32:$src), [{
1102 return N->getOpcode() != ISD::TRUNCATE &&
1103 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
1104 N->getOpcode() != ISD::CopyFromReg &&
1105 N->getOpcode() != X86ISD::CMOV;
1108 // In the case of a 32-bit def that is known to implicitly zero-extend,
1109 // we can use a SUBREG_TO_REG.
1110 def : Pat<(i64 (zext def32:$src)),
1111 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1113 //===----------------------------------------------------------------------===//
1114 // Pattern match OR as ADD
1115 //===----------------------------------------------------------------------===//
1117 // If safe, we prefer to pattern match OR as ADD at isel time. ADD can be
1118 // 3-addressified into an LEA instruction to avoid copies. However, we also
1119 // want to finally emit these instructions as an or at the end of the code
1120 // generator to make the generated code easier to read. To do this, we select
1121 // into "disjoint bits" pseudo ops.
1123 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
1124 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
1125 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1126 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
1128 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
1129 APInt Mask = APInt::getAllOnesValue(BitWidth);
1130 APInt KnownZero0, KnownOne0;
1131 CurDAG->ComputeMaskedBits(N->getOperand(0), Mask, KnownZero0, KnownOne0, 0);
1132 APInt KnownZero1, KnownOne1;
1133 CurDAG->ComputeMaskedBits(N->getOperand(1), Mask, KnownZero1, KnownOne1, 0);
1134 return (~KnownZero0 & ~KnownZero1) == 0;
1138 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
1139 let AddedComplexity = 5 in { // Try this before the selecting to OR
1141 let isConvertibleToThreeAddress = 1,
1142 Constraints = "$src1 = $dst", Defs = [EFLAGS] in {
1143 let isCommutable = 1 in {
1144 def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1145 "", // orw/addw REG, REG
1146 [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>;
1147 def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1148 "", // orl/addl REG, REG
1149 [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>;
1150 def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1151 "", // orq/addq REG, REG
1152 [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>;
1155 // NOTE: These are order specific, we want the ri8 forms to be listed
1156 // first so that they are slightly preferred to the ri forms.
1158 def ADD16ri8_DB : I<0, Pseudo,
1159 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1160 "", // orw/addw REG, imm8
1161 [(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>;
1162 def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1163 "", // orw/addw REG, imm
1164 [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>;
1166 def ADD32ri8_DB : I<0, Pseudo,
1167 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1168 "", // orl/addl REG, imm8
1169 [(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>;
1170 def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1171 "", // orl/addl REG, imm
1172 [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>;
1175 def ADD64ri8_DB : I<0, Pseudo,
1176 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
1177 "", // orq/addq REG, imm8
1178 [(set GR64:$dst, (or_is_add GR64:$src1,
1179 i64immSExt8:$src2))]>;
1180 def ADD64ri32_DB : I<0, Pseudo,
1181 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1182 "", // orq/addq REG, imm
1183 [(set GR64:$dst, (or_is_add GR64:$src1,
1184 i64immSExt32:$src2))]>;
1186 } // AddedComplexity
1189 //===----------------------------------------------------------------------===//
1191 //===----------------------------------------------------------------------===//
1193 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1194 // +128 doesn't, so in this special case use a sub instead of an add.
1195 def : Pat<(add GR16:$src1, 128),
1196 (SUB16ri8 GR16:$src1, -128)>;
1197 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
1198 (SUB16mi8 addr:$dst, -128)>;
1200 def : Pat<(add GR32:$src1, 128),
1201 (SUB32ri8 GR32:$src1, -128)>;
1202 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
1203 (SUB32mi8 addr:$dst, -128)>;
1205 def : Pat<(add GR64:$src1, 128),
1206 (SUB64ri8 GR64:$src1, -128)>;
1207 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1208 (SUB64mi8 addr:$dst, -128)>;
1210 // The same trick applies for 32-bit immediate fields in 64-bit
1212 def : Pat<(add GR64:$src1, 0x0000000080000000),
1213 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1214 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1215 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1217 // To avoid needing to materialize an immediate in a register, use a 32-bit and
1218 // with implicit zero-extension instead of a 64-bit and if the immediate has at
1219 // least 32 bits of leading zeros. If in addition the last 32 bits can be
1220 // represented with a sign extension of a 8 bit constant, use that.
1222 def : Pat<(and GR64:$src, i64immZExt32SExt8:$imm),
1226 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1227 (i32 (GetLo8XForm imm:$imm))),
1230 def : Pat<(and GR64:$src, i64immZExt32:$imm),
1234 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1235 (i32 (GetLo32XForm imm:$imm))),
1239 // r & (2^16-1) ==> movz
1240 def : Pat<(and GR32:$src1, 0xffff),
1241 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
1242 // r & (2^8-1) ==> movz
1243 def : Pat<(and GR32:$src1, 0xff),
1244 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
1247 Requires<[In32BitMode]>;
1248 // r & (2^8-1) ==> movz
1249 def : Pat<(and GR16:$src1, 0xff),
1250 (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG
1251 (i16 (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD)), sub_8bit)),
1253 Requires<[In32BitMode]>;
1255 // r & (2^32-1) ==> movz
1256 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1257 (MOVZX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
1258 // r & (2^16-1) ==> movz
1259 def : Pat<(and GR64:$src, 0xffff),
1260 (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit)))>;
1261 // r & (2^8-1) ==> movz
1262 def : Pat<(and GR64:$src, 0xff),
1263 (MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit)))>;
1264 // r & (2^8-1) ==> movz
1265 def : Pat<(and GR32:$src1, 0xff),
1266 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>,
1267 Requires<[In64BitMode]>;
1268 // r & (2^8-1) ==> movz
1269 def : Pat<(and GR16:$src1, 0xff),
1270 (EXTRACT_SUBREG (MOVZX32rr8 (i8
1271 (EXTRACT_SUBREG GR16:$src1, sub_8bit))), sub_16bit)>,
1272 Requires<[In64BitMode]>;
1275 // sext_inreg patterns
1276 def : Pat<(sext_inreg GR32:$src, i16),
1277 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>;
1278 def : Pat<(sext_inreg GR32:$src, i8),
1279 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1282 Requires<[In32BitMode]>;
1284 def : Pat<(sext_inreg GR16:$src, i8),
1285 (EXTRACT_SUBREG (i32 (MOVSX32rr8 (EXTRACT_SUBREG
1286 (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), sub_8bit))),
1288 Requires<[In32BitMode]>;
1290 def : Pat<(sext_inreg GR64:$src, i32),
1291 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
1292 def : Pat<(sext_inreg GR64:$src, i16),
1293 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>;
1294 def : Pat<(sext_inreg GR64:$src, i8),
1295 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>;
1296 def : Pat<(sext_inreg GR32:$src, i8),
1297 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>,
1298 Requires<[In64BitMode]>;
1299 def : Pat<(sext_inreg GR16:$src, i8),
1300 (EXTRACT_SUBREG (MOVSX32rr8
1301 (EXTRACT_SUBREG GR16:$src, sub_8bit)), sub_16bit)>,
1302 Requires<[In64BitMode]>;
1304 // sext, sext_load, zext, zext_load
1305 def: Pat<(i16 (sext GR8:$src)),
1306 (EXTRACT_SUBREG (MOVSX32rr8 GR8:$src), sub_16bit)>;
1307 def: Pat<(sextloadi16i8 addr:$src),
1308 (EXTRACT_SUBREG (MOVSX32rm8 addr:$src), sub_16bit)>;
1309 def: Pat<(i16 (zext GR8:$src)),
1310 (EXTRACT_SUBREG (MOVZX32rr8 GR8:$src), sub_16bit)>;
1311 def: Pat<(zextloadi16i8 addr:$src),
1312 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>;
1315 def : Pat<(i16 (trunc GR32:$src)),
1316 (EXTRACT_SUBREG GR32:$src, sub_16bit)>;
1317 def : Pat<(i8 (trunc GR32:$src)),
1318 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1320 Requires<[In32BitMode]>;
1321 def : Pat<(i8 (trunc GR16:$src)),
1322 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1324 Requires<[In32BitMode]>;
1325 def : Pat<(i32 (trunc GR64:$src)),
1326 (EXTRACT_SUBREG GR64:$src, sub_32bit)>;
1327 def : Pat<(i16 (trunc GR64:$src)),
1328 (EXTRACT_SUBREG GR64:$src, sub_16bit)>;
1329 def : Pat<(i8 (trunc GR64:$src)),
1330 (EXTRACT_SUBREG GR64:$src, sub_8bit)>;
1331 def : Pat<(i8 (trunc GR32:$src)),
1332 (EXTRACT_SUBREG GR32:$src, sub_8bit)>,
1333 Requires<[In64BitMode]>;
1334 def : Pat<(i8 (trunc GR16:$src)),
1335 (EXTRACT_SUBREG GR16:$src, sub_8bit)>,
1336 Requires<[In64BitMode]>;
1338 // h-register tricks
1339 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
1340 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1342 Requires<[In32BitMode]>;
1343 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
1344 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1346 Requires<[In32BitMode]>;
1347 def : Pat<(srl GR16:$src, (i8 8)),
1350 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1353 Requires<[In32BitMode]>;
1354 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1355 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1358 Requires<[In32BitMode]>;
1359 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1360 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1363 Requires<[In32BitMode]>;
1364 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1365 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1368 Requires<[In32BitMode]>;
1369 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1370 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1373 Requires<[In32BitMode]>;
1375 // h-register tricks.
1376 // For now, be conservative on x86-64 and use an h-register extract only if the
1377 // value is immediately zero-extended or stored, which are somewhat common
1378 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
1379 // from being allocated in the same instruction as the h register, as there's
1380 // currently no way to describe this requirement to the register allocator.
1382 // h-register extract and zero-extend.
1383 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
1387 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1390 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1392 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1394 Requires<[In64BitMode]>;
1395 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1396 (MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1399 Requires<[In64BitMode]>;
1400 def : Pat<(srl GR16:$src, (i8 8)),
1403 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1406 Requires<[In64BitMode]>;
1407 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1409 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1411 Requires<[In64BitMode]>;
1412 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1414 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1416 Requires<[In64BitMode]>;
1417 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
1421 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1424 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
1428 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1432 // h-register extract and store.
1433 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
1436 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1438 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
1441 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1443 Requires<[In64BitMode]>;
1444 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
1447 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1449 Requires<[In64BitMode]>;
1452 // (shl x, 1) ==> (add x, x)
1453 // Note that if x is undef (immediate or otherwise), we could theoretically
1454 // end up with the two uses of x getting different values, producing a result
1455 // where the least significant bit is not 0. However, the probability of this
1456 // happening is considered low enough that this is officially not a
1458 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
1459 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
1460 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
1461 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1463 // Helper imms that check if a mask doesn't change significant shift bits.
1464 def immShift32 : ImmLeaf<i8, [{ return CountTrailingOnes_32(Imm) >= 5; }]>;
1465 def immShift64 : ImmLeaf<i8, [{ return CountTrailingOnes_32(Imm) >= 6; }]>;
1467 // (shl x (and y, 31)) ==> (shl x, y)
1468 def : Pat<(shl GR8:$src1, (and CL, immShift32)),
1469 (SHL8rCL GR8:$src1)>;
1470 def : Pat<(shl GR16:$src1, (and CL, immShift32)),
1471 (SHL16rCL GR16:$src1)>;
1472 def : Pat<(shl GR32:$src1, (and CL, immShift32)),
1473 (SHL32rCL GR32:$src1)>;
1474 def : Pat<(store (shl (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst),
1475 (SHL8mCL addr:$dst)>;
1476 def : Pat<(store (shl (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst),
1477 (SHL16mCL addr:$dst)>;
1478 def : Pat<(store (shl (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst),
1479 (SHL32mCL addr:$dst)>;
1481 def : Pat<(srl GR8:$src1, (and CL, immShift32)),
1482 (SHR8rCL GR8:$src1)>;
1483 def : Pat<(srl GR16:$src1, (and CL, immShift32)),
1484 (SHR16rCL GR16:$src1)>;
1485 def : Pat<(srl GR32:$src1, (and CL, immShift32)),
1486 (SHR32rCL GR32:$src1)>;
1487 def : Pat<(store (srl (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst),
1488 (SHR8mCL addr:$dst)>;
1489 def : Pat<(store (srl (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst),
1490 (SHR16mCL addr:$dst)>;
1491 def : Pat<(store (srl (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst),
1492 (SHR32mCL addr:$dst)>;
1494 def : Pat<(sra GR8:$src1, (and CL, immShift32)),
1495 (SAR8rCL GR8:$src1)>;
1496 def : Pat<(sra GR16:$src1, (and CL, immShift32)),
1497 (SAR16rCL GR16:$src1)>;
1498 def : Pat<(sra GR32:$src1, (and CL, immShift32)),
1499 (SAR32rCL GR32:$src1)>;
1500 def : Pat<(store (sra (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst),
1501 (SAR8mCL addr:$dst)>;
1502 def : Pat<(store (sra (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst),
1503 (SAR16mCL addr:$dst)>;
1504 def : Pat<(store (sra (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst),
1505 (SAR32mCL addr:$dst)>;
1507 // (shl x (and y, 63)) ==> (shl x, y)
1508 def : Pat<(shl GR64:$src1, (and CL, immShift64)),
1509 (SHL64rCL GR64:$src1)>;
1510 def : Pat<(store (shl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1511 (SHL64mCL addr:$dst)>;
1513 def : Pat<(srl GR64:$src1, (and CL, immShift64)),
1514 (SHR64rCL GR64:$src1)>;
1515 def : Pat<(store (srl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1516 (SHR64mCL addr:$dst)>;
1518 def : Pat<(sra GR64:$src1, (and CL, immShift64)),
1519 (SAR64rCL GR64:$src1)>;
1520 def : Pat<(store (sra (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1521 (SAR64mCL addr:$dst)>;
1524 // (anyext (setcc_carry)) -> (setcc_carry)
1525 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1527 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1529 def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))),
1535 //===----------------------------------------------------------------------===//
1536 // EFLAGS-defining Patterns
1537 //===----------------------------------------------------------------------===//
1540 def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>;
1541 def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
1542 def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
1545 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
1546 (ADD8rm GR8:$src1, addr:$src2)>;
1547 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
1548 (ADD16rm GR16:$src1, addr:$src2)>;
1549 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
1550 (ADD32rm GR32:$src1, addr:$src2)>;
1553 def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>;
1554 def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
1555 def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
1556 def : Pat<(add GR16:$src1, i16immSExt8:$src2),
1557 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
1558 def : Pat<(add GR32:$src1, i32immSExt8:$src2),
1559 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
1562 def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>;
1563 def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
1564 def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
1567 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
1568 (SUB8rm GR8:$src1, addr:$src2)>;
1569 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
1570 (SUB16rm GR16:$src1, addr:$src2)>;
1571 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
1572 (SUB32rm GR32:$src1, addr:$src2)>;
1575 def : Pat<(sub GR8:$src1, imm:$src2),
1576 (SUB8ri GR8:$src1, imm:$src2)>;
1577 def : Pat<(sub GR16:$src1, imm:$src2),
1578 (SUB16ri GR16:$src1, imm:$src2)>;
1579 def : Pat<(sub GR32:$src1, imm:$src2),
1580 (SUB32ri GR32:$src1, imm:$src2)>;
1581 def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
1582 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
1583 def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
1584 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
1587 def : Pat<(mul GR16:$src1, GR16:$src2),
1588 (IMUL16rr GR16:$src1, GR16:$src2)>;
1589 def : Pat<(mul GR32:$src1, GR32:$src2),
1590 (IMUL32rr GR32:$src1, GR32:$src2)>;
1593 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
1594 (IMUL16rm GR16:$src1, addr:$src2)>;
1595 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
1596 (IMUL32rm GR32:$src1, addr:$src2)>;
1599 def : Pat<(mul GR16:$src1, imm:$src2),
1600 (IMUL16rri GR16:$src1, imm:$src2)>;
1601 def : Pat<(mul GR32:$src1, imm:$src2),
1602 (IMUL32rri GR32:$src1, imm:$src2)>;
1603 def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
1604 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
1605 def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
1606 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
1608 // reg = mul mem, imm
1609 def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
1610 (IMUL16rmi addr:$src1, imm:$src2)>;
1611 def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
1612 (IMUL32rmi addr:$src1, imm:$src2)>;
1613 def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
1614 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
1615 def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
1616 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
1618 // Patterns for nodes that do not produce flags, for instructions that do.
1621 def : Pat<(add GR64:$src1, GR64:$src2),
1622 (ADD64rr GR64:$src1, GR64:$src2)>;
1623 def : Pat<(add GR64:$src1, i64immSExt8:$src2),
1624 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1625 def : Pat<(add GR64:$src1, i64immSExt32:$src2),
1626 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1627 def : Pat<(add GR64:$src1, (loadi64 addr:$src2)),
1628 (ADD64rm GR64:$src1, addr:$src2)>;
1631 def : Pat<(sub GR64:$src1, GR64:$src2),
1632 (SUB64rr GR64:$src1, GR64:$src2)>;
1633 def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)),
1634 (SUB64rm GR64:$src1, addr:$src2)>;
1635 def : Pat<(sub GR64:$src1, i64immSExt8:$src2),
1636 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1637 def : Pat<(sub GR64:$src1, i64immSExt32:$src2),
1638 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1641 def : Pat<(mul GR64:$src1, GR64:$src2),
1642 (IMUL64rr GR64:$src1, GR64:$src2)>;
1643 def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)),
1644 (IMUL64rm GR64:$src1, addr:$src2)>;
1645 def : Pat<(mul GR64:$src1, i64immSExt8:$src2),
1646 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
1647 def : Pat<(mul GR64:$src1, i64immSExt32:$src2),
1648 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
1649 def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2),
1650 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
1651 def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2),
1652 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
1655 def : Pat<(add GR8 :$src, 1), (INC8r GR8 :$src)>;
1656 def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>, Requires<[In32BitMode]>;
1657 def : Pat<(add GR16:$src, 1), (INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1658 def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>, Requires<[In32BitMode]>;
1659 def : Pat<(add GR32:$src, 1), (INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1660 def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>;
1663 def : Pat<(add GR8 :$src, -1), (DEC8r GR8 :$src)>;
1664 def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
1665 def : Pat<(add GR16:$src, -1), (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1666 def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
1667 def : Pat<(add GR32:$src, -1), (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1668 def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>;
1671 def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
1672 def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
1673 def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
1674 def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>;
1677 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
1678 (OR8rm GR8:$src1, addr:$src2)>;
1679 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
1680 (OR16rm GR16:$src1, addr:$src2)>;
1681 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
1682 (OR32rm GR32:$src1, addr:$src2)>;
1683 def : Pat<(or GR64:$src1, (loadi64 addr:$src2)),
1684 (OR64rm GR64:$src1, addr:$src2)>;
1687 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
1688 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
1689 def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
1690 def : Pat<(or GR16:$src1, i16immSExt8:$src2),
1691 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1692 def : Pat<(or GR32:$src1, i32immSExt8:$src2),
1693 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1694 def : Pat<(or GR64:$src1, i64immSExt8:$src2),
1695 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1696 def : Pat<(or GR64:$src1, i64immSExt32:$src2),
1697 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1700 def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>;
1701 def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
1702 def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
1703 def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>;
1706 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
1707 (XOR8rm GR8:$src1, addr:$src2)>;
1708 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
1709 (XOR16rm GR16:$src1, addr:$src2)>;
1710 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
1711 (XOR32rm GR32:$src1, addr:$src2)>;
1712 def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)),
1713 (XOR64rm GR64:$src1, addr:$src2)>;
1716 def : Pat<(xor GR8:$src1, imm:$src2),
1717 (XOR8ri GR8:$src1, imm:$src2)>;
1718 def : Pat<(xor GR16:$src1, imm:$src2),
1719 (XOR16ri GR16:$src1, imm:$src2)>;
1720 def : Pat<(xor GR32:$src1, imm:$src2),
1721 (XOR32ri GR32:$src1, imm:$src2)>;
1722 def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
1723 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1724 def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
1725 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1726 def : Pat<(xor GR64:$src1, i64immSExt8:$src2),
1727 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1728 def : Pat<(xor GR64:$src1, i64immSExt32:$src2),
1729 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1732 def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>;
1733 def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
1734 def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
1735 def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>;
1738 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
1739 (AND8rm GR8:$src1, addr:$src2)>;
1740 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
1741 (AND16rm GR16:$src1, addr:$src2)>;
1742 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
1743 (AND32rm GR32:$src1, addr:$src2)>;
1744 def : Pat<(and GR64:$src1, (loadi64 addr:$src2)),
1745 (AND64rm GR64:$src1, addr:$src2)>;
1748 def : Pat<(and GR8:$src1, imm:$src2),
1749 (AND8ri GR8:$src1, imm:$src2)>;
1750 def : Pat<(and GR16:$src1, imm:$src2),
1751 (AND16ri GR16:$src1, imm:$src2)>;
1752 def : Pat<(and GR32:$src1, imm:$src2),
1753 (AND32ri GR32:$src1, imm:$src2)>;
1754 def : Pat<(and GR16:$src1, i16immSExt8:$src2),
1755 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
1756 def : Pat<(and GR32:$src1, i32immSExt8:$src2),
1757 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
1758 def : Pat<(and GR64:$src1, i64immSExt8:$src2),
1759 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
1760 def : Pat<(and GR64:$src1, i64immSExt32:$src2),
1761 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>;
1763 // Bit scan instruction patterns to match explicit zero-undef behavior.
1764 def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr GR16:$src)>;
1765 def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr GR32:$src)>;
1766 def : Pat<(cttz_zero_undef GR64:$src), (BSF64rr GR64:$src)>;
1767 def : Pat<(cttz_zero_undef (loadi16 addr:$src)), (BSF16rm addr:$src)>;
1768 def : Pat<(cttz_zero_undef (loadi32 addr:$src)), (BSF32rm addr:$src)>;
1769 def : Pat<(cttz_zero_undef (loadi64 addr:$src)), (BSF64rm addr:$src)>;