1 //===- X86InstrArithmetic.td - Integer Arithmetic Instrs ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the integer arithmetic instructions in the X86
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // LEA - Load Effective Address
18 let neverHasSideEffects = 1 in
19 def LEA16r : I<0x8D, MRMSrcMem,
20 (outs GR16:$dst), (ins i32mem:$src),
21 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
22 let isReMaterializable = 1 in
23 def LEA32r : I<0x8D, MRMSrcMem,
24 (outs GR32:$dst), (ins i32mem:$src),
25 "lea{l}\t{$src|$dst}, {$dst|$src}",
26 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
28 def LEA64_32r : I<0x8D, MRMSrcMem,
29 (outs GR32:$dst), (ins lea64_32mem:$src),
30 "lea{l}\t{$src|$dst}, {$dst|$src}",
31 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>;
33 let isReMaterializable = 1 in
34 def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
35 "lea{q}\t{$src|$dst}, {$dst|$src}",
36 [(set GR64:$dst, lea64addr:$src)]>;
40 //===----------------------------------------------------------------------===//
41 // Fixed-Register Multiplication and Division Instructions.
44 // Extra precision multiplication
46 // AL is really implied by AX, but the registers in Defs must match the
47 // SDNode results (i8, i32).
48 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
49 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
50 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
51 // This probably ought to be moved to a def : Pat<> if the
52 // syntax can be accepted.
53 [(set AL, (mul AL, GR8:$src)),
54 (implicit EFLAGS)]>; // AL,AH = AL*GR8
56 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
57 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
59 []>, OpSize; // AX,DX = AX*GR16
61 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
62 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
64 []>; // EAX,EDX = EAX*GR32
65 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
66 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
67 "mul{q}\t$src", []>; // RAX,RDX = RAX*GR64
69 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
70 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
72 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
73 // This probably ought to be moved to a def : Pat<> if the
74 // syntax can be accepted.
75 [(set AL, (mul AL, (loadi8 addr:$src))),
76 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
78 let mayLoad = 1, neverHasSideEffects = 1 in {
79 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
80 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
82 []>, OpSize; // AX,DX = AX*[mem16]
84 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
85 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
87 []>; // EAX,EDX = EAX*[mem32]
88 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
89 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
90 "mul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
93 let neverHasSideEffects = 1 in {
94 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
95 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
97 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
98 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
99 OpSize; // AX,DX = AX*GR16
100 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
101 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
102 // EAX,EDX = EAX*GR32
103 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
104 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src), "imul{q}\t$src", []>;
105 // RAX,RDX = RAX*GR64
108 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
109 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
110 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
111 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
112 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
113 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
114 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
115 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
116 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
117 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
118 def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
119 "imul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
121 } // neverHasSideEffects
124 let Defs = [EFLAGS] in {
125 let Constraints = "$src1 = $dst" in {
127 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
128 // Register-Register Signed Integer Multiply
129 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
130 "imul{w}\t{$src2, $dst|$dst, $src2}",
131 [(set GR16:$dst, EFLAGS,
132 (X86smul_flag GR16:$src1, GR16:$src2))]>, TB, OpSize;
133 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
134 "imul{l}\t{$src2, $dst|$dst, $src2}",
135 [(set GR32:$dst, EFLAGS,
136 (X86smul_flag GR32:$src1, GR32:$src2))]>, TB;
137 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
138 (ins GR64:$src1, GR64:$src2),
139 "imul{q}\t{$src2, $dst|$dst, $src2}",
140 [(set GR64:$dst, EFLAGS,
141 (X86smul_flag GR64:$src1, GR64:$src2))]>, TB;
144 // Register-Memory Signed Integer Multiply
145 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
146 (ins GR16:$src1, i16mem:$src2),
147 "imul{w}\t{$src2, $dst|$dst, $src2}",
148 [(set GR16:$dst, EFLAGS,
149 (X86smul_flag GR16:$src1, (load addr:$src2)))]>,
151 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
152 (ins GR32:$src1, i32mem:$src2),
153 "imul{l}\t{$src2, $dst|$dst, $src2}",
154 [(set GR32:$dst, EFLAGS,
155 (X86smul_flag GR32:$src1, (load addr:$src2)))]>, TB;
156 def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
157 (ins GR64:$src1, i64mem:$src2),
158 "imul{q}\t{$src2, $dst|$dst, $src2}",
159 [(set GR64:$dst, EFLAGS,
160 (X86smul_flag GR64:$src1, (load addr:$src2)))]>, TB;
161 } // Constraints = "$src1 = $dst"
165 // Suprisingly enough, these are not two address instructions!
166 let Defs = [EFLAGS] in {
167 // Register-Integer Signed Integer Multiply
168 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
169 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
170 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
171 [(set GR16:$dst, EFLAGS,
172 (X86smul_flag GR16:$src1, imm:$src2))]>, OpSize;
173 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
174 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
175 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
176 [(set GR16:$dst, EFLAGS,
177 (X86smul_flag GR16:$src1, i16immSExt8:$src2))]>,
179 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
180 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
181 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
182 [(set GR32:$dst, EFLAGS,
183 (X86smul_flag GR32:$src1, imm:$src2))]>;
184 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
185 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
186 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
187 [(set GR32:$dst, EFLAGS,
188 (X86smul_flag GR32:$src1, i32immSExt8:$src2))]>;
189 def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
190 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
191 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
192 [(set GR64:$dst, EFLAGS,
193 (X86smul_flag GR64:$src1, i64immSExt32:$src2))]>;
194 def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
195 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
196 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
197 [(set GR64:$dst, EFLAGS,
198 (X86smul_flag GR64:$src1, i64immSExt8:$src2))]>;
201 // Memory-Integer Signed Integer Multiply
202 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
203 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
204 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
205 [(set GR16:$dst, EFLAGS,
206 (X86smul_flag (load addr:$src1), imm:$src2))]>,
208 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
209 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
210 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
211 [(set GR16:$dst, EFLAGS,
212 (X86smul_flag (load addr:$src1),
213 i16immSExt8:$src2))]>, OpSize;
214 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
215 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
216 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
217 [(set GR32:$dst, EFLAGS,
218 (X86smul_flag (load addr:$src1), imm:$src2))]>;
219 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
220 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
221 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
222 [(set GR32:$dst, EFLAGS,
223 (X86smul_flag (load addr:$src1),
224 i32immSExt8:$src2))]>;
225 def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
226 (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
227 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
228 [(set GR64:$dst, EFLAGS,
229 (X86smul_flag (load addr:$src1),
230 i64immSExt32:$src2))]>;
231 def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
232 (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
233 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
234 [(set GR64:$dst, EFLAGS,
235 (X86smul_flag (load addr:$src1),
236 i64immSExt8:$src2))]>;
242 // unsigned division/remainder
243 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
244 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
246 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
247 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
248 "div{w}\t$src", []>, OpSize;
249 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
250 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
252 // RDX:RAX/r64 = RAX,RDX
253 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
254 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src),
258 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
259 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
261 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
262 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
263 "div{w}\t$src", []>, OpSize;
264 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX
265 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
267 // RDX:RAX/[mem64] = RAX,RDX
268 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
269 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src),
273 // Signed division/remainder.
274 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
275 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
276 "idiv{b}\t$src", []>;
277 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
278 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
279 "idiv{w}\t$src", []>, OpSize;
280 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
281 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
282 "idiv{l}\t$src", []>;
283 // RDX:RAX/r64 = RAX,RDX
284 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
285 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src),
286 "idiv{q}\t$src", []>;
288 let mayLoad = 1, mayLoad = 1 in {
289 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
290 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
291 "idiv{b}\t$src", []>;
292 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
293 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
294 "idiv{w}\t$src", []>, OpSize;
295 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX
296 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
297 "idiv{l}\t$src", []>;
298 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in // RDX:RAX/[mem64] = RAX,RDX
299 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src),
300 "idiv{q}\t$src", []>;
303 //===----------------------------------------------------------------------===//
304 // Two address Instructions.
307 // unary instructions
308 let CodeSize = 2 in {
309 let Defs = [EFLAGS] in {
310 let Constraints = "$src1 = $dst" in {
311 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src1),
313 [(set GR8:$dst, (ineg GR8:$src1)),
315 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
317 [(set GR16:$dst, (ineg GR16:$src1)),
318 (implicit EFLAGS)]>, OpSize;
319 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
321 [(set GR32:$dst, (ineg GR32:$src1)),
323 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src1), "neg{q}\t$dst",
324 [(set GR64:$dst, (ineg GR64:$src1)),
326 } // Constraints = "$src1 = $dst"
328 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst),
330 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
332 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst),
334 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
335 (implicit EFLAGS)]>, OpSize;
336 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst),
338 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
340 def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
341 [(store (ineg (loadi64 addr:$dst)), addr:$dst),
346 // Note: NOT does not set EFLAGS!
348 let Constraints = "$src1 = $dst" in {
349 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
350 let AddedComplexity = 15 in {
351 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src1),
353 [(set GR8:$dst, (not GR8:$src1))]>;
354 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
356 [(set GR16:$dst, (not GR16:$src1))]>, OpSize;
357 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
359 [(set GR32:$dst, (not GR32:$src1))]>;
360 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src1), "not{q}\t$dst",
361 [(set GR64:$dst, (not GR64:$src1))]>;
363 } // Constraints = "$src1 = $dst"
365 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst),
367 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
368 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst),
370 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
371 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst),
373 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
374 def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
375 [(store (not (loadi64 addr:$dst)), addr:$dst)]>;
378 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
379 let Defs = [EFLAGS] in {
380 let Constraints = "$src1 = $dst" in {
382 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
384 [(set GR8:$dst, EFLAGS, (X86inc_flag GR8:$src1))]>;
386 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
387 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
389 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))]>,
390 OpSize, Requires<[In32BitMode]>;
391 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
393 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))]>,
394 Requires<[In32BitMode]>;
395 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src1), "inc{q}\t$dst",
396 [(set GR64:$dst, EFLAGS, (X86inc_flag GR64:$src1))]>;
397 } // isConvertibleToThreeAddress = 1, CodeSize = 1
400 // In 64-bit mode, single byte INC and DEC cannot be encoded.
401 let isConvertibleToThreeAddress = 1, CodeSize = 2 in {
402 // Can transform into LEA.
403 def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
405 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))]>,
406 OpSize, Requires<[In64BitMode]>;
407 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
409 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))]>,
410 Requires<[In64BitMode]>;
411 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
413 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))]>,
414 OpSize, Requires<[In64BitMode]>;
415 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
417 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))]>,
418 Requires<[In64BitMode]>;
419 } // isConvertibleToThreeAddress = 1, CodeSize = 2
421 } // Constraints = "$src1 = $dst"
423 let CodeSize = 2 in {
424 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
425 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
427 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
428 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
430 OpSize, Requires<[In32BitMode]>;
431 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
432 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
434 Requires<[In32BitMode]>;
435 def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
436 [(store (add (loadi64 addr:$dst), 1), addr:$dst),
439 // These are duplicates of their 32-bit counterparts. Only needed so X86 knows
440 // how to unfold them.
441 // FIXME: What is this for??
442 def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
443 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
445 OpSize, Requires<[In64BitMode]>;
446 def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
447 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
449 Requires<[In64BitMode]>;
450 def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
451 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
453 OpSize, Requires<[In64BitMode]>;
454 def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
455 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
457 Requires<[In64BitMode]>;
460 let Constraints = "$src1 = $dst" in {
462 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
464 [(set GR8:$dst, EFLAGS, (X86dec_flag GR8:$src1))]>;
465 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
466 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
468 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))]>,
469 OpSize, Requires<[In32BitMode]>;
470 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
472 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))]>,
473 Requires<[In32BitMode]>;
474 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src1), "dec{q}\t$dst",
475 [(set GR64:$dst, EFLAGS, (X86dec_flag GR64:$src1))]>;
477 } // Constraints = "$src1 = $dst"
480 let CodeSize = 2 in {
481 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
482 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
484 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
485 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
487 OpSize, Requires<[In32BitMode]>;
488 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
489 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
491 Requires<[In32BitMode]>;
492 def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
493 [(store (add (loadi64 addr:$dst), -1), addr:$dst),
499 /// X86TypeInfo - This is a bunch of information that describes relevant X86
500 /// information about value types. For example, it can tell you what the
501 /// register class and preferred load to use.
502 class X86TypeInfo<ValueType vt, string instrsuffix, RegisterClass regclass,
503 PatFrag loadnode, X86MemOperand memoperand, ImmType immkind,
504 Operand immoperand, SDPatternOperator immoperator,
505 Operand imm8operand, SDPatternOperator imm8operator,
506 bit hasOddOpcode, bit hasOpSizePrefix, bit hasREX_WPrefix> {
507 /// VT - This is the value type itself.
510 /// InstrSuffix - This is the suffix used on instructions with this type. For
511 /// example, i8 -> "b", i16 -> "w", i32 -> "l", i64 -> "q".
512 string InstrSuffix = instrsuffix;
514 /// RegClass - This is the register class associated with this type. For
515 /// example, i8 -> GR8, i16 -> GR16, i32 -> GR32, i64 -> GR64.
516 RegisterClass RegClass = regclass;
518 /// LoadNode - This is the load node associated with this type. For
519 /// example, i8 -> loadi8, i16 -> loadi16, i32 -> loadi32, i64 -> loadi64.
520 PatFrag LoadNode = loadnode;
522 /// MemOperand - This is the memory operand associated with this type. For
523 /// example, i8 -> i8mem, i16 -> i16mem, i32 -> i32mem, i64 -> i64mem.
524 X86MemOperand MemOperand = memoperand;
526 /// ImmEncoding - This is the encoding of an immediate of this type. For
527 /// example, i8 -> Imm8, i16 -> Imm16, i32 -> Imm32. Note that i64 -> Imm32
528 /// since the immediate fields of i64 instructions is a 32-bit sign extended
530 ImmType ImmEncoding = immkind;
532 /// ImmOperand - This is the operand kind of an immediate of this type. For
533 /// example, i8 -> i8imm, i16 -> i16imm, i32 -> i32imm. Note that i64 ->
534 /// i64i32imm since the immediate fields of i64 instructions is a 32-bit sign
536 Operand ImmOperand = immoperand;
538 /// ImmOperator - This is the operator that should be used to match an
539 /// immediate of this kind in a pattern (e.g. imm, or i64immSExt32).
540 SDPatternOperator ImmOperator = immoperator;
542 /// Imm8Operand - This is the operand kind to use for an imm8 of this type.
543 /// For example, i8 -> <invalid>, i16 -> i16i8imm, i32 -> i32i8imm. This is
544 /// only used for instructions that have a sign-extended imm8 field form.
545 Operand Imm8Operand = imm8operand;
547 /// Imm8Operator - This is the operator that should be used to match an 8-bit
548 /// sign extended immediate of this kind in a pattern (e.g. imm16immSExt8).
549 SDPatternOperator Imm8Operator = imm8operator;
551 /// HasOddOpcode - This bit is true if the instruction should have an odd (as
552 /// opposed to even) opcode. Operations on i8 are usually even, operations on
553 /// other datatypes are odd.
554 bit HasOddOpcode = hasOddOpcode;
556 /// HasOpSizePrefix - This bit is set to true if the instruction should have
557 /// the 0x66 operand size prefix. This is set for i16 types.
558 bit HasOpSizePrefix = hasOpSizePrefix;
560 /// HasREX_WPrefix - This bit is set to true if the instruction should have
561 /// the 0x40 REX prefix. This is set for i64 types.
562 bit HasREX_WPrefix = hasREX_WPrefix;
565 def invalid_node : SDNode<"<<invalid_node>>", SDTIntLeaf,[],"<<invalid_node>>">;
568 def Xi8 : X86TypeInfo<i8 , "b", GR8 , loadi8 , i8mem ,
569 Imm8 , i8imm , imm, i8imm , invalid_node,
571 def Xi16 : X86TypeInfo<i16, "w", GR16, loadi16, i16mem,
572 Imm16, i16imm, imm, i16i8imm, i16immSExt8,
574 def Xi32 : X86TypeInfo<i32, "l", GR32, loadi32, i32mem,
575 Imm32, i32imm, imm, i32i8imm, i32immSExt8,
577 def Xi64 : X86TypeInfo<i64, "q", GR64, loadi64, i64mem,
578 Imm32, i64i32imm, i64immSExt32, i64i8imm, i64immSExt8,
581 /// ITy - This instruction base class takes the type info for the instruction.
583 /// 1. Concatenates together the instruction mnemonic with the appropriate
584 /// suffix letter, a tab, and the arguments.
585 /// 2. Infers whether the instruction should have a 0x66 prefix byte.
586 /// 3. Infers whether the instruction should have a 0x40 REX_W prefix.
587 /// 4. Infers whether the low bit of the opcode should be 0 (for i8 operations)
588 /// or 1 (for i16,i32,i64 operations).
589 class ITy<bits<8> opcode, Format f, X86TypeInfo typeinfo, dag outs, dag ins,
590 string mnemonic, string args, list<dag> pattern>
591 : I<{opcode{7}, opcode{6}, opcode{5}, opcode{4},
592 opcode{3}, opcode{2}, opcode{1}, typeinfo.HasOddOpcode },
594 !strconcat(mnemonic, "{", typeinfo.InstrSuffix, "}\t", args), pattern> {
596 // Infer instruction prefixes from type info.
597 let hasOpSizePrefix = typeinfo.HasOpSizePrefix;
598 let hasREX_WPrefix = typeinfo.HasREX_WPrefix;
601 // BinOpRR - Instructions like "add reg, reg, reg".
602 class BinOpRR<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
604 : ITy<opcode, MRMDestReg, typeinfo,
605 (outs typeinfo.RegClass:$dst),
606 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
607 mnemonic, "{$src2, $dst|$dst, $src2}", pattern>;
609 // BinOpRR_R - Instructions like "add reg, reg, reg", where the pattern has
610 // just a regclass (no eflags) as a result.
611 class BinOpRR_R<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
613 : BinOpRR<opcode, mnemonic, typeinfo,
614 [(set typeinfo.RegClass:$dst,
615 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
617 // BinOpRR_RF - Instructions like "add reg, reg, reg", where the pattern has
618 // both a regclass and EFLAGS as a result.
619 class BinOpRR_RF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
621 : BinOpRR<opcode, mnemonic, typeinfo,
622 [(set typeinfo.RegClass:$dst, EFLAGS,
623 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
625 // BinOpRR_Rev - Instructions like "add reg, reg, reg" (reversed encoding).
626 class BinOpRR_Rev<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo>
627 : ITy<opcode, MRMSrcReg, typeinfo,
628 (outs typeinfo.RegClass:$dst),
629 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
630 mnemonic, "{$src2, $dst|$dst, $src2}", []> {
631 // The disassembler should know about this, but not the asmparser.
632 let isCodeGenOnly = 1;
635 // BinOpRM - Instructions like "add reg, reg, [mem]".
636 class BinOpRM<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
638 : ITy<opcode, MRMSrcMem, typeinfo,
639 (outs typeinfo.RegClass:$dst),
640 (ins typeinfo.RegClass:$src1, typeinfo.MemOperand:$src2),
641 mnemonic, "{$src2, $dst|$dst, $src2}", pattern>;
643 // BinOpRM_R - Instructions like "add reg, reg, [mem]".
644 class BinOpRM_R<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
646 : BinOpRM<opcode, mnemonic, typeinfo,
647 [(set typeinfo.RegClass:$dst,
648 (opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2)))]>;
650 // BinOpRM_RF - Instructions like "add reg, reg, [mem]".
651 class BinOpRM_RF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
653 : BinOpRM<opcode, mnemonic, typeinfo,
654 [(set typeinfo.RegClass:$dst, EFLAGS,
655 (opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2)))]>;
657 // BinOpRI - Instructions like "add reg, reg, imm".
658 class BinOpRI<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
659 Format f, list<dag> pattern>
660 : ITy<opcode, f, typeinfo,
661 (outs typeinfo.RegClass:$dst),
662 (ins typeinfo.RegClass:$src1, typeinfo.ImmOperand:$src2),
663 mnemonic, "{$src2, $dst|$dst, $src2}", pattern> {
664 let ImmT = typeinfo.ImmEncoding;
667 // BinOpRI_R - Instructions like "add reg, reg, imm".
668 class BinOpRI_R<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
669 SDNode opnode, Format f>
670 : BinOpRI<opcode, mnemonic, typeinfo, f,
671 [(set typeinfo.RegClass:$dst,
672 (opnode typeinfo.RegClass:$src1, typeinfo.ImmOperator:$src2))]>;
674 // BinOpRI_RF - Instructions like "add reg, reg, imm".
675 class BinOpRI_RF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
676 SDNode opnode, Format f>
677 : BinOpRI<opcode, mnemonic, typeinfo, f,
678 [(set typeinfo.RegClass:$dst, EFLAGS,
679 (opnode typeinfo.RegClass:$src1, typeinfo.ImmOperator:$src2))]>;
681 // BinOpRI8 - Instructions like "add reg, reg, imm8".
682 class BinOpRI8<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
683 Format f, list<dag> pattern>
684 : ITy<opcode, f, typeinfo,
685 (outs typeinfo.RegClass:$dst),
686 (ins typeinfo.RegClass:$src1, typeinfo.Imm8Operand:$src2),
687 mnemonic, "{$src2, $dst|$dst, $src2}", pattern> {
688 let ImmT = Imm8; // Always 8-bit immediate.
691 // BinOpRI8_R - Instructions like "add reg, reg, imm8".
692 class BinOpRI8_R<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
693 SDNode opnode, Format f>
694 : BinOpRI8<opcode, mnemonic, typeinfo, f,
695 [(set typeinfo.RegClass:$dst,
696 (opnode typeinfo.RegClass:$src1, typeinfo.Imm8Operator:$src2))]>;
698 // BinOpRI8_RF - Instructions like "add reg, reg, imm8".
699 class BinOpRI8_RF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
700 SDNode opnode, Format f>
701 : BinOpRI8<opcode, mnemonic, typeinfo, f,
702 [(set typeinfo.RegClass:$dst, EFLAGS,
703 (opnode typeinfo.RegClass:$src1, typeinfo.Imm8Operator:$src2))]>;
705 // BinOpMR - Instructions like "add [mem], reg".
706 class BinOpMR<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
708 : ITy<opcode, MRMDestMem, typeinfo,
709 (outs), (ins typeinfo.MemOperand:$dst, typeinfo.RegClass:$src),
710 mnemonic, "{$src, $dst|$dst, $src}",
711 [(store (opnode (load addr:$dst), typeinfo.RegClass:$src), addr:$dst),
714 // BinOpMI - Instructions like "add [mem], imm".
715 class BinOpMI<string mnemonic, X86TypeInfo typeinfo,
716 SDNode opnode, Format f>
717 : ITy<0x80, f, typeinfo,
718 (outs), (ins typeinfo.MemOperand:$dst, typeinfo.ImmOperand:$src),
719 mnemonic, "{$src, $dst|$dst, $src}",
720 [(store (opnode (typeinfo.VT (load addr:$dst)),
721 typeinfo.ImmOperator:$src), addr:$dst),
722 (implicit EFLAGS)]> {
723 let ImmT = typeinfo.ImmEncoding;
726 // BinOpMI8 - Instructions like "add [mem], imm8".
727 class BinOpMI8<string mnemonic, X86TypeInfo typeinfo,
728 SDNode opnode, Format f>
729 : ITy<0x82, f, typeinfo,
730 (outs), (ins typeinfo.MemOperand:$dst, typeinfo.Imm8Operand:$src),
731 mnemonic, "{$src, $dst|$dst, $src}",
732 [(store (opnode (load addr:$dst),
733 typeinfo.Imm8Operator:$src), addr:$dst),
734 (implicit EFLAGS)]> {
735 let ImmT = Imm8; // Always 8-bit immediate.
738 // BinOpAI - Instructions like "add %eax, %eax, imm".
739 class BinOpAI<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
741 : ITy<opcode, RawFrm, typeinfo,
742 (outs), (ins typeinfo.ImmOperand:$src),
743 mnemonic, !strconcat("{$src, %", areg.AsmName, "|%",
744 areg.AsmName, ", $src}"), []> {
745 let ImmT = typeinfo.ImmEncoding;
750 /// ArithBinOp_RF - This is an arithmetic binary operator where the pattern is
751 /// defined with "(set GPR:$dst, EFLAGS, (...".
753 /// It would be nice to get rid of the second and third argument here, but
754 /// tblgen can't handle dependent type references aggressively enough: PR8330
755 multiclass ArithBinOp_RF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
756 string mnemonic, Format RegMRM, Format MemMRM,
757 SDNode opnodeflag, SDNode opnode,
758 bit CommutableRR, bit ConvertibleToThreeAddress> {
759 let Defs = [EFLAGS] in {
760 let Constraints = "$src1 = $dst" in {
761 let isCommutable = CommutableRR,
762 isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
763 def #NAME#8rr : BinOpRR_RF<BaseOpc, mnemonic, Xi8 , opnodeflag>;
764 def #NAME#16rr : BinOpRR_RF<BaseOpc, mnemonic, Xi16, opnodeflag>;
765 def #NAME#32rr : BinOpRR_RF<BaseOpc, mnemonic, Xi32, opnodeflag>;
766 def #NAME#64rr : BinOpRR_RF<BaseOpc, mnemonic, Xi64, opnodeflag>;
769 def #NAME#8rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi8>;
770 def #NAME#16rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi16>;
771 def #NAME#32rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi32>;
772 def #NAME#64rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi64>;
774 def #NAME#8rm : BinOpRM_RF<BaseOpc2, mnemonic, Xi8 , opnodeflag>;
775 def #NAME#16rm : BinOpRM_RF<BaseOpc2, mnemonic, Xi16, opnodeflag>;
776 def #NAME#32rm : BinOpRM_RF<BaseOpc2, mnemonic, Xi32, opnodeflag>;
777 def #NAME#64rm : BinOpRM_RF<BaseOpc2, mnemonic, Xi64, opnodeflag>;
779 let isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
780 def #NAME#8ri : BinOpRI_RF<0x80, mnemonic, Xi8 , opnodeflag, RegMRM>;
781 def #NAME#16ri : BinOpRI_RF<0x80, mnemonic, Xi16, opnodeflag, RegMRM>;
782 def #NAME#32ri : BinOpRI_RF<0x80, mnemonic, Xi32, opnodeflag, RegMRM>;
783 def #NAME#64ri32: BinOpRI_RF<0x80, mnemonic, Xi64, opnodeflag, RegMRM>;
785 def #NAME#16ri8 : BinOpRI8_RF<0x82, mnemonic, Xi16, opnodeflag, RegMRM>;
786 def #NAME#32ri8 : BinOpRI8_RF<0x82, mnemonic, Xi32, opnodeflag, RegMRM>;
787 def #NAME#64ri8 : BinOpRI8_RF<0x82, mnemonic, Xi64, opnodeflag, RegMRM>;
789 } // Constraints = "$src1 = $dst"
791 def #NAME#8mr : BinOpMR<BaseOpc, mnemonic, Xi8 , opnode>;
792 def #NAME#16mr : BinOpMR<BaseOpc, mnemonic, Xi16, opnode>;
793 def #NAME#32mr : BinOpMR<BaseOpc, mnemonic, Xi32, opnode>;
794 def #NAME#64mr : BinOpMR<BaseOpc, mnemonic, Xi64, opnode>;
796 def #NAME#8mi : BinOpMI<mnemonic, Xi8 , opnode, MemMRM>;
797 def #NAME#16mi : BinOpMI<mnemonic, Xi16, opnode, MemMRM>;
798 def #NAME#32mi : BinOpMI<mnemonic, Xi32, opnode, MemMRM>;
799 def #NAME#64mi32 : BinOpMI<mnemonic, Xi64, opnode, MemMRM>;
801 def #NAME#16mi8 : BinOpMI8<mnemonic, Xi16, opnode, MemMRM>;
802 def #NAME#32mi8 : BinOpMI8<mnemonic, Xi32, opnode, MemMRM>;
803 def #NAME#64mi8 : BinOpMI8<mnemonic, Xi64, opnode, MemMRM>;
805 def #NAME#8i8 : BinOpAI<BaseOpc4, mnemonic, Xi8 , AL>;
806 def #NAME#16i16 : BinOpAI<BaseOpc4, mnemonic, Xi16, AX>;
807 def #NAME#32i32 : BinOpAI<BaseOpc4, mnemonic, Xi32, EAX>;
808 def #NAME#64i32 : BinOpAI<BaseOpc4, mnemonic, Xi64, RAX>;
812 /// ArithBinOp_R - This is an arithmetic binary operator where the pattern is
813 /// defined with "(set GPR:$dst, (...". It would be really nice to find a way
814 /// to factor this with the other ArithBinOp_*.
816 multiclass ArithBinOp_R<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
817 string mnemonic, Format RegMRM, Format MemMRM,
819 bit CommutableRR, bit ConvertibleToThreeAddress> {
820 let Defs = [EFLAGS] in {
821 let Constraints = "$src1 = $dst" in {
822 let isCommutable = CommutableRR,
823 isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
824 def #NAME#8rr : BinOpRR_R<BaseOpc, mnemonic, Xi8 , opnode>;
825 def #NAME#16rr : BinOpRR_R<BaseOpc, mnemonic, Xi16, opnode>;
826 def #NAME#32rr : BinOpRR_R<BaseOpc, mnemonic, Xi32, opnode>;
827 def #NAME#64rr : BinOpRR_R<BaseOpc, mnemonic, Xi64, opnode>;
830 def #NAME#8rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi8>;
831 def #NAME#16rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi16>;
832 def #NAME#32rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi32>;
833 def #NAME#64rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi64>;
835 def #NAME#8rm : BinOpRM_R<BaseOpc2, mnemonic, Xi8 , opnode>;
836 def #NAME#16rm : BinOpRM_R<BaseOpc2, mnemonic, Xi16, opnode>;
837 def #NAME#32rm : BinOpRM_R<BaseOpc2, mnemonic, Xi32, opnode>;
838 def #NAME#64rm : BinOpRM_R<BaseOpc2, mnemonic, Xi64, opnode>;
840 let isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
841 def #NAME#8ri : BinOpRI_R<0x80, mnemonic, Xi8 , opnode, RegMRM>;
842 def #NAME#16ri : BinOpRI_R<0x80, mnemonic, Xi16, opnode, RegMRM>;
843 def #NAME#32ri : BinOpRI_R<0x80, mnemonic, Xi32, opnode, RegMRM>;
844 def #NAME#64ri32: BinOpRI_R<0x80, mnemonic, Xi64, opnode, RegMRM>;
846 def #NAME#16ri8 : BinOpRI8_R<0x82, mnemonic, Xi16, opnode, RegMRM>;
847 def #NAME#32ri8 : BinOpRI8_R<0x82, mnemonic, Xi32, opnode, RegMRM>;
848 def #NAME#64ri8 : BinOpRI8_R<0x82, mnemonic, Xi64, opnode, RegMRM>;
850 } // Constraints = "$src1 = $dst"
852 def #NAME#8mr : BinOpMR<BaseOpc, mnemonic, Xi8 , opnode>;
853 def #NAME#16mr : BinOpMR<BaseOpc, mnemonic, Xi16, opnode>;
854 def #NAME#32mr : BinOpMR<BaseOpc, mnemonic, Xi32, opnode>;
855 def #NAME#64mr : BinOpMR<BaseOpc, mnemonic, Xi64, opnode>;
857 def #NAME#8mi : BinOpMI<mnemonic, Xi8 , opnode, MemMRM>;
858 def #NAME#16mi : BinOpMI<mnemonic, Xi16, opnode, MemMRM>;
859 def #NAME#32mi : BinOpMI<mnemonic, Xi32, opnode, MemMRM>;
860 def #NAME#64mi32 : BinOpMI<mnemonic, Xi64, opnode, MemMRM>;
862 def #NAME#16mi8 : BinOpMI8<mnemonic, Xi16, opnode, MemMRM>;
863 def #NAME#32mi8 : BinOpMI8<mnemonic, Xi32, opnode, MemMRM>;
864 def #NAME#64mi8 : BinOpMI8<mnemonic, Xi64, opnode, MemMRM>;
866 def #NAME#8i8 : BinOpAI<BaseOpc4, mnemonic, Xi8 , AL>;
867 def #NAME#16i16 : BinOpAI<BaseOpc4, mnemonic, Xi16, AX>;
868 def #NAME#32i32 : BinOpAI<BaseOpc4, mnemonic, Xi32, EAX>;
869 def #NAME#64i32 : BinOpAI<BaseOpc4, mnemonic, Xi64, RAX>;
874 defm AND : ArithBinOp_RF<0x20, 0x22, 0x24, "and", MRM4r, MRM4m,
875 X86and_flag, and, 1, 0>;
876 defm OR : ArithBinOp_RF<0x08, 0x0A, 0x0C, "or", MRM1r, MRM1m,
877 X86or_flag, or, 1, 0>;
878 defm XOR : ArithBinOp_RF<0x30, 0x32, 0x34, "xor", MRM6r, MRM6m,
879 X86xor_flag, xor, 1, 0>;
880 defm ADD : ArithBinOp_RF<0x00, 0x02, 0x04, "add", MRM0r, MRM0m,
881 X86add_flag, add, 1, 1>;
882 defm SUB : ArithBinOp_RF<0x28, 0x2A, 0x2C, "sub", MRM5r, MRM5m,
883 X86sub_flag, sub, 0, 0>;
886 let Uses = [EFLAGS] in {
887 // FIXME: Delete ArithBinOp_R if these switch off adde/sube.
888 defm ADC : ArithBinOp_R<0x10, 0x12, 0x14, "adc", MRM2r, MRM2m, adde, 1, 0>;
889 defm SBB : ArithBinOp_R<0x18, 0x1A, 0x1C, "sbb", MRM3r, MRM3m, sube, 0, 0>;
892 //===----------------------------------------------------------------------===//
893 // Test instructions are just like AND, except they don't generate a result.
895 let Defs = [EFLAGS] in {
896 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
897 def TEST8rr : I<0x84, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
898 "test{b}\t{$src2, $src1|$src1, $src2}",
899 [(set EFLAGS, (X86cmp (and_su GR8:$src1, GR8:$src2), 0))]>;
900 def TEST16rr : I<0x85, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
901 "test{w}\t{$src2, $src1|$src1, $src2}",
902 [(set EFLAGS, (X86cmp (and_su GR16:$src1, GR16:$src2),
905 def TEST32rr : I<0x85, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
906 "test{l}\t{$src2, $src1|$src1, $src2}",
907 [(set EFLAGS, (X86cmp (and_su GR32:$src1, GR32:$src2),
909 def TEST64rr : RI<0x85, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
910 "test{q}\t{$src2, $src1|$src1, $src2}",
911 [(set EFLAGS, (X86cmp (and GR64:$src1, GR64:$src2), 0))]>;
914 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
915 "test{b}\t{$src2, $src1|$src1, $src2}",
916 [(set EFLAGS, (X86cmp (and GR8:$src1, (loadi8 addr:$src2)),
918 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
919 "test{w}\t{$src2, $src1|$src1, $src2}",
920 [(set EFLAGS, (X86cmp (and GR16:$src1,
921 (loadi16 addr:$src2)), 0))]>, OpSize;
922 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
923 "test{l}\t{$src2, $src1|$src1, $src2}",
924 [(set EFLAGS, (X86cmp (and GR32:$src1,
925 (loadi32 addr:$src2)), 0))]>;
926 def TEST64rm : RI<0x85, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
927 "test{q}\t{$src2, $src1|$src1, $src2}",
928 [(set EFLAGS, (X86cmp (and GR64:$src1, (loadi64 addr:$src2)),
931 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
932 (outs), (ins GR8:$src1, i8imm:$src2),
933 "test{b}\t{$src2, $src1|$src1, $src2}",
934 [(set EFLAGS, (X86cmp (and_su GR8:$src1, imm:$src2), 0))]>;
935 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
936 (outs), (ins GR16:$src1, i16imm:$src2),
937 "test{w}\t{$src2, $src1|$src1, $src2}",
938 [(set EFLAGS, (X86cmp (and_su GR16:$src1, imm:$src2), 0))]>,
940 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
941 (outs), (ins GR32:$src1, i32imm:$src2),
942 "test{l}\t{$src2, $src1|$src1, $src2}",
943 [(set EFLAGS, (X86cmp (and_su GR32:$src1, imm:$src2), 0))]>;
944 def TEST64ri32 : RIi32<0xF7, MRM0r, (outs),
945 (ins GR64:$src1, i64i32imm:$src2),
946 "test{q}\t{$src2, $src1|$src1, $src2}",
947 [(set EFLAGS, (X86cmp (and GR64:$src1, i64immSExt32:$src2),
950 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
951 (outs), (ins i8mem:$src1, i8imm:$src2),
952 "test{b}\t{$src2, $src1|$src1, $src2}",
953 [(set EFLAGS, (X86cmp (and (loadi8 addr:$src1), imm:$src2),
955 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
956 (outs), (ins i16mem:$src1, i16imm:$src2),
957 "test{w}\t{$src2, $src1|$src1, $src2}",
958 [(set EFLAGS, (X86cmp (and (loadi16 addr:$src1), imm:$src2),
960 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
961 (outs), (ins i32mem:$src1, i32imm:$src2),
962 "test{l}\t{$src2, $src1|$src1, $src2}",
963 [(set EFLAGS, (X86cmp (and (loadi32 addr:$src1), imm:$src2),
965 def TEST64mi32 : RIi32<0xF7, MRM0m, (outs),
966 (ins i64mem:$src1, i64i32imm:$src2),
967 "test{q}\t{$src2, $src1|$src1, $src2}",
968 [(set EFLAGS, (X86cmp (and (loadi64 addr:$src1),
969 i64immSExt32:$src2), 0))]>;
971 def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src),
972 "test{b}\t{$src, %al|%al, $src}", []>;
973 def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src),
974 "test{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
975 def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src),
976 "test{l}\t{$src, %eax|%eax, $src}", []>;
977 def TEST64i32 : RIi32<0xa9, RawFrm, (outs), (ins i64i32imm:$src),
978 "test{q}\t{$src, %rax|%rax, $src}", []>;
983 //===----------------------------------------------------------------------===//
984 // Integer comparisons
986 let Defs = [EFLAGS] in {
988 def CMP8rr : I<0x38, MRMDestReg,
989 (outs), (ins GR8 :$src1, GR8 :$src2),
990 "cmp{b}\t{$src2, $src1|$src1, $src2}",
991 [(set EFLAGS, (X86cmp GR8:$src1, GR8:$src2))]>;
992 def CMP16rr : I<0x39, MRMDestReg,
993 (outs), (ins GR16:$src1, GR16:$src2),
994 "cmp{w}\t{$src2, $src1|$src1, $src2}",
995 [(set EFLAGS, (X86cmp GR16:$src1, GR16:$src2))]>, OpSize;
996 def CMP32rr : I<0x39, MRMDestReg,
997 (outs), (ins GR32:$src1, GR32:$src2),
998 "cmp{l}\t{$src2, $src1|$src1, $src2}",
999 [(set EFLAGS, (X86cmp GR32:$src1, GR32:$src2))]>;
1000 def CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1001 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1002 [(set EFLAGS, (X86cmp GR64:$src1, GR64:$src2))]>;
1004 def CMP8mr : I<0x38, MRMDestMem,
1005 (outs), (ins i8mem :$src1, GR8 :$src2),
1006 "cmp{b}\t{$src2, $src1|$src1, $src2}",
1007 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), GR8:$src2))]>;
1008 def CMP16mr : I<0x39, MRMDestMem,
1009 (outs), (ins i16mem:$src1, GR16:$src2),
1010 "cmp{w}\t{$src2, $src1|$src1, $src2}",
1011 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), GR16:$src2))]>,
1013 def CMP32mr : I<0x39, MRMDestMem,
1014 (outs), (ins i32mem:$src1, GR32:$src2),
1015 "cmp{l}\t{$src2, $src1|$src1, $src2}",
1016 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), GR32:$src2))]>;
1017 def CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1018 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1019 [(set EFLAGS, (X86cmp (loadi64 addr:$src1), GR64:$src2))]>;
1021 def CMP8rm : I<0x3A, MRMSrcMem,
1022 (outs), (ins GR8 :$src1, i8mem :$src2),
1023 "cmp{b}\t{$src2, $src1|$src1, $src2}",
1024 [(set EFLAGS, (X86cmp GR8:$src1, (loadi8 addr:$src2)))]>;
1025 def CMP16rm : I<0x3B, MRMSrcMem,
1026 (outs), (ins GR16:$src1, i16mem:$src2),
1027 "cmp{w}\t{$src2, $src1|$src1, $src2}",
1028 [(set EFLAGS, (X86cmp GR16:$src1, (loadi16 addr:$src2)))]>,
1030 def CMP32rm : I<0x3B, MRMSrcMem,
1031 (outs), (ins GR32:$src1, i32mem:$src2),
1032 "cmp{l}\t{$src2, $src1|$src1, $src2}",
1033 [(set EFLAGS, (X86cmp GR32:$src1, (loadi32 addr:$src2)))]>;
1034 def CMP64rm : RI<0x3B, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1035 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1036 [(set EFLAGS, (X86cmp GR64:$src1, (loadi64 addr:$src2)))]>;
1038 // These are alternate spellings for use by the disassembler, we mark them as
1039 // code gen only to ensure they aren't matched by the assembler.
1040 let isCodeGenOnly = 1 in {
1041 def CMP8rr_alt : I<0x3A, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
1042 "cmp{b}\t{$src2, $src1|$src1, $src2}", []>;
1043 def CMP16rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
1044 "cmp{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize;
1045 def CMP32rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
1046 "cmp{l}\t{$src2, $src1|$src1, $src2}", []>;
1047 def CMP64rr_alt : RI<0x3B, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
1048 "cmp{q}\t{$src2, $src1|$src1, $src2}", []>;
1051 def CMP8ri : Ii8<0x80, MRM7r,
1052 (outs), (ins GR8:$src1, i8imm:$src2),
1053 "cmp{b}\t{$src2, $src1|$src1, $src2}",
1054 [(set EFLAGS, (X86cmp GR8:$src1, imm:$src2))]>;
1055 def CMP16ri : Ii16<0x81, MRM7r,
1056 (outs), (ins GR16:$src1, i16imm:$src2),
1057 "cmp{w}\t{$src2, $src1|$src1, $src2}",
1058 [(set EFLAGS, (X86cmp GR16:$src1, imm:$src2))]>, OpSize;
1059 def CMP32ri : Ii32<0x81, MRM7r,
1060 (outs), (ins GR32:$src1, i32imm:$src2),
1061 "cmp{l}\t{$src2, $src1|$src1, $src2}",
1062 [(set EFLAGS, (X86cmp GR32:$src1, imm:$src2))]>;
1063 def CMP64ri32 : RIi32<0x81, MRM7r, (outs), (ins GR64:$src1, i64i32imm:$src2),
1064 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1065 [(set EFLAGS, (X86cmp GR64:$src1, i64immSExt32:$src2))]>;
1067 def CMP8mi : Ii8 <0x80, MRM7m,
1068 (outs), (ins i8mem :$src1, i8imm :$src2),
1069 "cmp{b}\t{$src2, $src1|$src1, $src2}",
1070 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), imm:$src2))]>;
1071 def CMP16mi : Ii16<0x81, MRM7m,
1072 (outs), (ins i16mem:$src1, i16imm:$src2),
1073 "cmp{w}\t{$src2, $src1|$src1, $src2}",
1074 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), imm:$src2))]>,
1076 def CMP32mi : Ii32<0x81, MRM7m,
1077 (outs), (ins i32mem:$src1, i32imm:$src2),
1078 "cmp{l}\t{$src2, $src1|$src1, $src2}",
1079 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), imm:$src2))]>;
1080 def CMP64mi32 : RIi32<0x81, MRM7m, (outs),
1081 (ins i64mem:$src1, i64i32imm:$src2),
1082 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1083 [(set EFLAGS, (X86cmp (loadi64 addr:$src1),
1084 i64immSExt32:$src2))]>;
1086 def CMP16ri8 : Ii8<0x83, MRM7r,
1087 (outs), (ins GR16:$src1, i16i8imm:$src2),
1088 "cmp{w}\t{$src2, $src1|$src1, $src2}",
1089 [(set EFLAGS, (X86cmp GR16:$src1, i16immSExt8:$src2))]>,
1091 def CMP32ri8 : Ii8<0x83, MRM7r,
1092 (outs), (ins GR32:$src1, i32i8imm:$src2),
1093 "cmp{l}\t{$src2, $src1|$src1, $src2}",
1094 [(set EFLAGS, (X86cmp GR32:$src1, i32immSExt8:$src2))]>;
1095 def CMP64ri8 : RIi8<0x83, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1096 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1097 [(set EFLAGS, (X86cmp GR64:$src1, i64immSExt8:$src2))]>;
1099 def CMP16mi8 : Ii8<0x83, MRM7m,
1100 (outs), (ins i16mem:$src1, i16i8imm:$src2),
1101 "cmp{w}\t{$src2, $src1|$src1, $src2}",
1102 [(set EFLAGS, (X86cmp (loadi16 addr:$src1),
1103 i16immSExt8:$src2))]>, OpSize;
1104 def CMP32mi8 : Ii8<0x83, MRM7m,
1105 (outs), (ins i32mem:$src1, i32i8imm:$src2),
1106 "cmp{l}\t{$src2, $src1|$src1, $src2}",
1107 [(set EFLAGS, (X86cmp (loadi32 addr:$src1),
1108 i32immSExt8:$src2))]>;
1109 def CMP64mi8 : RIi8<0x83, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1110 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1111 [(set EFLAGS, (X86cmp (loadi64 addr:$src1),
1112 i64immSExt8:$src2))]>;
1114 def CMP8i8 : Ii8<0x3C, RawFrm, (outs), (ins i8imm:$src),
1115 "cmp{b}\t{$src, %al|%al, $src}", []>;
1116 def CMP16i16 : Ii16<0x3D, RawFrm, (outs), (ins i16imm:$src),
1117 "cmp{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1118 def CMP32i32 : Ii32<0x3D, RawFrm, (outs), (ins i32imm:$src),
1119 "cmp{l}\t{$src, %eax|%eax, $src}", []>;
1120 def CMP64i32 : RIi32<0x3D, RawFrm, (outs), (ins i64i32imm:$src),
1121 "cmp{q}\t{$src, %rax|%rax, $src}", []>;
1123 } // Defs = [EFLAGS]