1 // Bitcasts between 512-bit vector types. Return the original type since
2 // no instruction is needed for the conversion
3 let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
49 // Bitcasts between 256-bit vector types. Return the original type since
50 // no instruction is needed for the conversion
51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
83 //===----------------------------------------------------------------------===//
84 // AVX-512 - VECTOR INSERT
87 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
88 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
89 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
90 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
91 []>, EVEX_4V, EVEX_V512;
93 def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
94 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
95 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
96 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
100 let neverHasSideEffects = 1, ExeDomain = SSEPackedDouble in {
101 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
102 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
103 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
104 []>, EVEX_4V, EVEX_V512, VEX_W;
106 def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
107 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
108 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
109 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
111 // -- 32x4 integer form --
112 let neverHasSideEffects = 1 in {
113 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
114 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
115 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
116 []>, EVEX_4V, EVEX_V512;
118 def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
119 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
120 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
121 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
125 let neverHasSideEffects = 1 in {
127 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
128 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
129 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
130 []>, EVEX_4V, EVEX_V512, VEX_W;
132 def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
133 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
134 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
135 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
138 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
139 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
140 (INSERT_get_vinsert128_imm VR512:$ins))>;
141 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
142 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
143 (INSERT_get_vinsert128_imm VR512:$ins))>;
144 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
145 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
146 (INSERT_get_vinsert128_imm VR512:$ins))>;
147 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
148 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
149 (INSERT_get_vinsert128_imm VR512:$ins))>;
151 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
152 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
153 (INSERT_get_vinsert128_imm VR512:$ins))>;
154 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
155 (bc_v4i32 (loadv2i64 addr:$src2)),
156 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
157 (INSERT_get_vinsert128_imm VR512:$ins))>;
158 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
159 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
160 (INSERT_get_vinsert128_imm VR512:$ins))>;
161 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
162 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
163 (INSERT_get_vinsert128_imm VR512:$ins))>;
165 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
166 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
167 (INSERT_get_vinsert256_imm VR512:$ins))>;
168 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
169 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
170 (INSERT_get_vinsert256_imm VR512:$ins))>;
171 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
172 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
173 (INSERT_get_vinsert256_imm VR512:$ins))>;
174 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
175 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
176 (INSERT_get_vinsert256_imm VR512:$ins))>;
178 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
179 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
180 (INSERT_get_vinsert256_imm VR512:$ins))>;
181 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
182 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
183 (INSERT_get_vinsert256_imm VR512:$ins))>;
184 def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
185 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
186 (INSERT_get_vinsert256_imm VR512:$ins))>;
187 def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
188 (bc_v8i32 (loadv4i64 addr:$src2)),
189 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
190 (INSERT_get_vinsert256_imm VR512:$ins))>;
192 // vinsertps - insert f32 to XMM
193 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
194 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
195 "vinsertps{z}\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
196 [(set VR128X:$dst, (X86insrtps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
198 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
199 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
200 "vinsertps{z}\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
201 [(set VR128X:$dst, (X86insrtps VR128X:$src1,
202 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
203 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
205 //===----------------------------------------------------------------------===//
206 // AVX-512 VECTOR EXTRACT
208 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
210 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
211 (ins VR512:$src1, i8imm:$src2),
212 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
213 []>, EVEX, EVEX_V512;
214 def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
215 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
216 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
217 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
220 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
221 (ins VR512:$src1, i8imm:$src2),
222 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
223 []>, EVEX, EVEX_V512, VEX_W;
225 def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
226 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
227 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
228 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
231 let neverHasSideEffects = 1 in {
233 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
234 (ins VR512:$src1, i8imm:$src2),
235 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
236 []>, EVEX, EVEX_V512;
237 def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
238 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
239 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
240 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
243 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
244 (ins VR512:$src1, i8imm:$src2),
245 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
246 []>, EVEX, EVEX_V512, VEX_W;
248 def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
249 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
250 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
251 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
254 def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
255 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
256 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
258 def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
259 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
260 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
262 def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
263 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
264 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
266 def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
267 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
268 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
271 def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
272 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
273 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
275 def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
276 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
277 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
279 def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
280 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
281 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
283 def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
284 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
285 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
287 // A 256-bit subvector extract from the first 512-bit vector position
288 // is a subregister copy that needs no instruction.
289 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
290 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
291 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
292 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
293 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
294 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
295 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
296 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
299 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
300 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
301 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
302 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
303 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
304 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
305 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
306 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
309 // A 128-bit subvector insert to the first 512-bit vector position
310 // is a subregister copy that needs no instruction.
311 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
312 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
313 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
315 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
316 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
317 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
319 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
320 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
321 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
323 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
324 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
325 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
328 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
329 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
330 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
331 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
332 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
333 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
334 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
335 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
337 // vextractps - extract 32 bits from XMM
338 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
339 (ins VR128X:$src1, u32u8imm:$src2),
340 "vextractps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
341 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
344 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
345 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
346 "vextractps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
347 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
350 //===---------------------------------------------------------------------===//
353 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
354 RegisterClass DestRC,
355 RegisterClass SrcRC, X86MemOperand x86memop> {
356 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
357 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
359 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
360 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),[]>, EVEX;
362 let ExeDomain = SSEPackedSingle in {
363 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss{z}", VR512,
365 EVEX_V512, EVEX_CD8<32, CD8VT1>;
368 let ExeDomain = SSEPackedDouble in {
369 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd{z}", VR512,
371 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
374 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
375 (VBROADCASTSSZrm addr:$src)>;
376 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
377 (VBROADCASTSDZrm addr:$src)>;
379 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
380 RegisterClass SrcRC, RegisterClass KRC> {
381 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
382 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
383 []>, EVEX, EVEX_V512;
384 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
385 (ins KRC:$mask, SrcRC:$src),
386 !strconcat(OpcodeStr,
387 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
388 []>, EVEX, EVEX_V512, EVEX_KZ;
391 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
392 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
395 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
396 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
398 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
399 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
401 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
402 (VPBROADCASTDrZrr GR32:$src)>;
403 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
404 (VPBROADCASTQrZrr GR64:$src)>;
406 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
407 X86MemOperand x86memop, PatFrag ld_frag,
408 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
410 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
411 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
413 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
414 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
416 !strconcat(OpcodeStr,
417 "\t{$src, ${dst}{${mask}}{z}|${dst}{${mask}}{z}, $src}"),
419 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
421 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
422 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
424 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
425 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
427 !strconcat(OpcodeStr,
428 "\t{$src, ${dst}{${mask}}{z}|${dst}{${mask}}{z}, $src}"),
429 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
430 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
433 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
434 loadi32, VR512, v16i32, v4i32, VK16WM>,
435 EVEX_V512, EVEX_CD8<32, CD8VT1>;
436 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
437 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
438 EVEX_CD8<64, CD8VT1>;
440 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
441 (VBROADCASTSSZrr VR128X:$src)>;
442 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
443 (VBROADCASTSDZrr VR128X:$src)>;
445 // Provide fallback in case the load node that is used in the patterns above
446 // is used by additional users, which prevents the pattern selection.
447 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
448 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
449 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
450 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
453 let Predicates = [HasAVX512] in {
454 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
456 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
457 addr:$src)), sub_ymm)>;
459 //===----------------------------------------------------------------------===//
460 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
463 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
464 RegisterClass DstRC, RegisterClass KRC,
465 ValueType OpVT, ValueType SrcVT> {
466 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
467 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
471 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
472 VK16, v16i32, v16i1>, EVEX_V512;
473 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
474 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
476 //===----------------------------------------------------------------------===//
479 // -- immediate form --
480 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
481 SDNode OpNode, PatFrag mem_frag,
482 X86MemOperand x86memop, ValueType OpVT> {
483 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
484 (ins RC:$src1, i8imm:$src2),
485 !strconcat(OpcodeStr,
486 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
488 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
490 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
491 (ins x86memop:$src1, i8imm:$src2),
492 !strconcat(OpcodeStr,
493 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
495 (OpVT (OpNode (mem_frag addr:$src1),
496 (i8 imm:$src2))))]>, EVEX;
499 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
500 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
501 let ExeDomain = SSEPackedDouble in
502 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
503 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
505 // -- VPERM - register form --
506 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
507 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
509 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
510 (ins RC:$src1, RC:$src2),
511 !strconcat(OpcodeStr,
512 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
514 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
516 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
517 (ins RC:$src1, x86memop:$src2),
518 !strconcat(OpcodeStr,
519 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
521 (OpVT (X86VPermv RC:$src1,
522 (bitconvert (mem_frag addr:$src2)))))]>, EVEX_4V;
525 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv8i64, i512mem,
526 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
527 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
528 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
529 let ExeDomain = SSEPackedSingle in
530 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv8f64, f512mem,
531 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
532 let ExeDomain = SSEPackedDouble in
533 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
534 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
536 // -- VPERM2I - 3 source operands form --
537 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
538 PatFrag mem_frag, X86MemOperand x86memop,
540 let Constraints = "$src1 = $dst" in {
541 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
542 (ins RC:$src1, RC:$src2, RC:$src3),
543 !strconcat(OpcodeStr,
544 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
546 (OpVT (X86VPermv3 RC:$src1, RC:$src2, RC:$src3)))]>,
549 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
550 (ins RC:$src1, RC:$src2, x86memop:$src3),
551 !strconcat(OpcodeStr,
552 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
554 (OpVT (X86VPermv3 RC:$src1, RC:$src2,
555 (bitconvert (mem_frag addr:$src3)))))]>, EVEX_4V;
558 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem,
559 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
560 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem,
561 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
562 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem,
563 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
564 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
565 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
568 // Mask register copy, including
569 // - copy between mask registers
570 // - load/store mask registers
571 // - copy from GPR to mask register and vice versa
573 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
574 string OpcodeStr, RegisterClass KRC,
575 ValueType vt, X86MemOperand x86memop> {
576 let neverHasSideEffects = 1 in {
577 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
578 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
580 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
581 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
582 [(set KRC:$dst, (vt (load addr:$src)))]>;
584 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
585 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
589 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
591 RegisterClass KRC, RegisterClass GRC> {
592 let neverHasSideEffects = 1 in {
593 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
594 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
595 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
596 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
600 let Predicates = [HasAVX512] in {
601 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
603 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
607 let Predicates = [HasAVX512] in {
608 // GR16 from/to 16-bit mask
609 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
610 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
611 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
612 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
614 // Store kreg in memory
615 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
616 (KMOVWmk addr:$dst, VK16:$src)>;
618 def : Pat<(store (v8i1 VK8:$src), addr:$dst),
619 (KMOVWmk addr:$dst, (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16)))>;
621 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
622 let Predicates = [HasAVX512] in {
623 // GR from/to 8-bit mask without native support
624 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
626 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
628 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
630 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
634 // Mask unary operation
636 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
637 RegisterClass KRC, SDPatternOperator OpNode> {
638 let Predicates = [HasAVX512] in
639 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
640 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
641 [(set KRC:$dst, (OpNode KRC:$src))]>;
644 multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
645 SDPatternOperator OpNode> {
646 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
650 defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
652 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
653 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
654 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
656 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
657 def : Pat<(not VK8:$src),
659 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
661 // Mask binary operation
662 // - KADD, KAND, KANDN, KOR, KXNOR, KXOR
663 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
664 RegisterClass KRC, SDPatternOperator OpNode> {
665 let Predicates = [HasAVX512] in
666 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
667 !strconcat(OpcodeStr,
668 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
669 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
672 multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
673 SDPatternOperator OpNode> {
674 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
678 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
679 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
681 let isCommutable = 1 in {
682 defm KADD : avx512_mask_binop_w<0x4a, "kadd", add>;
683 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
684 let isCommutable = 0 in
685 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
686 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
687 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
688 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
691 multiclass avx512_mask_binop_int<string IntName, string InstName> {
692 let Predicates = [HasAVX512] in
693 def : Pat<(!cast<Intrinsic>("int_x86_"##IntName##"_v16i1")
694 VK16:$src1, VK16:$src2),
695 (!cast<Instruction>(InstName##"Wrr") VK16:$src1, VK16:$src2)>;
698 defm : avx512_mask_binop_int<"kadd", "KADD">;
699 defm : avx512_mask_binop_int<"kand", "KAND">;
700 defm : avx512_mask_binop_int<"kandn", "KANDN">;
701 defm : avx512_mask_binop_int<"kor", "KOR">;
702 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
703 defm : avx512_mask_binop_int<"kxor", "KXOR">;
704 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
705 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
706 let Predicates = [HasAVX512] in
707 def : Pat<(OpNode VK8:$src1, VK8:$src2),
709 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
710 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
713 defm : avx512_binop_pat<and, KANDWrr>;
714 defm : avx512_binop_pat<andn, KANDNWrr>;
715 defm : avx512_binop_pat<or, KORWrr>;
716 defm : avx512_binop_pat<xnor, KXNORWrr>;
717 defm : avx512_binop_pat<xor, KXORWrr>;
720 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
721 RegisterClass KRC1, RegisterClass KRC2> {
722 let Predicates = [HasAVX512] in
723 def rr : I<opc, MRMSrcReg, (outs KRC1:$dst), (ins KRC2:$src1, KRC2:$src2),
724 !strconcat(OpcodeStr,
725 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
728 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
729 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16, VK8>,
730 VEX_4V, VEX_L, OpSize, TB;
733 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
735 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
736 let Predicates = [HasAVX512] in
737 def : Pat<(!cast<Intrinsic>("int_x86_"##IntName##"_v16i1")
738 VK8:$src1, VK8:$src2),
739 (!cast<Instruction>(InstName##"BWrr") VK8:$src1, VK8:$src2)>;
742 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
744 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
746 let Predicates = [HasAVX512], Defs = [EFLAGS] in
747 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
748 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
749 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
752 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
753 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
757 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
758 defm KTEST : avx512_mask_testop_w<0x99, "ktest", X86ktest>;
761 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
763 let Predicates = [HasAVX512] in
764 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
765 !strconcat(OpcodeStr,
766 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
767 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
770 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
772 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
773 VEX, OpSize, TA, VEX_W;
776 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", shl>;
777 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", srl>;
779 // Mask setting all 0s or 1s
780 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
781 let Predicates = [HasAVX512] in
782 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
783 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
784 [(set KRC:$dst, (VT Val))]>;
787 multiclass avx512_mask_setop_w<PatFrag Val> {
788 defm B : avx512_mask_setop<VK8, v8i1, Val>;
789 defm W : avx512_mask_setop<VK16, v16i1, Val>;
792 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
793 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
795 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
796 let Predicates = [HasAVX512] in {
797 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
798 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
800 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
801 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
803 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
804 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
806 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
807 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
809 //===----------------------------------------------------------------------===//
810 // AVX-512 - Aligned and unaligned load and store
813 multiclass avx512_mov_packed<bits<8> opc, RegisterClass RC, RegisterClass KRC,
814 X86MemOperand x86memop, PatFrag ld_frag,
815 string asm, Domain d> {
816 let neverHasSideEffects = 1 in
817 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
818 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>,
820 let canFoldAsLoad = 1 in
821 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
822 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
823 [(set RC:$dst, (ld_frag addr:$src))], d>, EVEX;
824 let Constraints = "$src1 = $dst" in {
825 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
826 (ins RC:$src1, KRC:$mask, RC:$src2),
828 "\t{$src2, ${dst}{${mask}}|${dst}{${mask}}, $src2}"), [], d>,
830 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
831 (ins RC:$src1, KRC:$mask, x86memop:$src2),
833 "\t{$src2, ${dst}{${mask}}|${dst}{${mask}}, $src2}"),
834 [], d>, EVEX, EVEX_K;
838 defm VMOVAPSZ : avx512_mov_packed<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
839 "vmovaps", SSEPackedSingle>,
840 EVEX_V512, EVEX_CD8<32, CD8VF>;
841 defm VMOVAPDZ : avx512_mov_packed<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
842 "vmovapd", SSEPackedDouble>,
843 OpSize, EVEX_V512, VEX_W,
845 defm VMOVUPSZ : avx512_mov_packed<0x10, VR512, VK16WM, f512mem, loadv16f32,
846 "vmovups", SSEPackedSingle>,
847 TB, EVEX_V512, EVEX_CD8<32, CD8VF>;
848 defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64,
849 "vmovupd", SSEPackedDouble>,
850 OpSize, EVEX_V512, VEX_W,
852 def VMOVAPSZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
853 "vmovaps\t{$src, $dst|$dst, $src}",
854 [(alignedstore512 (v16f32 VR512:$src), addr:$dst)],
855 SSEPackedSingle>, EVEX, EVEX_V512, TB,
857 def VMOVAPDZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
858 "vmovapd\t{$src, $dst|$dst, $src}",
859 [(alignedstore512 (v8f64 VR512:$src), addr:$dst)],
860 SSEPackedDouble>, EVEX, EVEX_V512,
861 OpSize, TB, VEX_W, EVEX_CD8<64, CD8VF>;
862 def VMOVUPSZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
863 "vmovups\t{$src, $dst|$dst, $src}",
864 [(store (v16f32 VR512:$src), addr:$dst)],
865 SSEPackedSingle>, EVEX, EVEX_V512, TB,
867 def VMOVUPDZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
868 "vmovupd\t{$src, $dst|$dst, $src}",
869 [(store (v8f64 VR512:$src), addr:$dst)],
870 SSEPackedDouble>, EVEX, EVEX_V512,
871 OpSize, TB, VEX_W, EVEX_CD8<64, CD8VF>;
873 // Use vmovaps/vmovups for AVX-512 integer load/store.
874 // 512-bit load/store
875 def : Pat<(alignedloadv8i64 addr:$src),
876 (VMOVAPSZrm addr:$src)>;
877 def : Pat<(loadv8i64 addr:$src),
878 (VMOVUPSZrm addr:$src)>;
880 def : Pat<(alignedstore512 (v8i64 VR512:$src), addr:$dst),
881 (VMOVAPSZmr addr:$dst, VR512:$src)>;
882 def : Pat<(alignedstore512 (v16i32 VR512:$src), addr:$dst),
883 (VMOVAPSZmr addr:$dst, VR512:$src)>;
885 def : Pat<(store (v8i64 VR512:$src), addr:$dst),
886 (VMOVUPDZmr addr:$dst, VR512:$src)>;
887 def : Pat<(store (v16i32 VR512:$src), addr:$dst),
888 (VMOVUPSZmr addr:$dst, VR512:$src)>;
890 let neverHasSideEffects = 1 in {
891 def VMOVDQA32rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
893 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
895 def VMOVDQA64rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
897 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
898 EVEX, EVEX_V512, VEX_W;
899 let mayStore = 1 in {
900 def VMOVDQA32mr : AVX512BI<0x7F, MRMDestMem, (outs),
901 (ins i512mem:$dst, VR512:$src),
902 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
903 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
904 def VMOVDQA64mr : AVX512BI<0x7F, MRMDestMem, (outs),
905 (ins i512mem:$dst, VR512:$src),
906 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
907 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
910 def VMOVDQA32rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
912 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
913 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
914 def VMOVDQA64rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
916 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
917 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
921 multiclass avx512_mov_int<bits<8> opc, string asm, RegisterClass RC,
923 PatFrag ld_frag, X86MemOperand x86memop> {
924 let neverHasSideEffects = 1 in
925 def rr : AVX512XSI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
926 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>,
928 let canFoldAsLoad = 1 in
929 def rm : AVX512XSI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
930 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
931 [(set RC:$dst, (ld_frag addr:$src))]>,
933 let Constraints = "$src1 = $dst" in {
934 def rrk : AVX512XSI<opc, MRMSrcReg, (outs RC:$dst),
935 (ins RC:$src1, KRC:$mask, RC:$src2),
937 "\t{$src2, ${dst}{${mask}}|${dst}{${mask}}, $src2}"), []>,
939 def rmk : AVX512XSI<opc, MRMSrcMem, (outs RC:$dst),
940 (ins RC:$src1, KRC:$mask, x86memop:$src2),
942 "\t{$src2, ${dst}{${mask}}|${dst}{${mask}}, $src2}"),
947 defm VMOVDQU32 : avx512_mov_int<0x6F, "vmovdqu32", VR512, VK16WM, memopv16i32, i512mem>,
948 EVEX_V512, EVEX_CD8<32, CD8VF>;
949 defm VMOVDQU64 : avx512_mov_int<0x6F, "vmovdqu64", VR512, VK8WM, memopv8i64, i512mem>,
950 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;