1 // Bitcasts between 512-bit vector types. Return the original type since
2 // no instruction is needed for the conversion
3 let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
49 // Bitcasts between 256-bit vector types. Return the original type since
50 // no instruction is needed for the conversion
51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
84 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
87 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
88 isPseudo = 1, Predicates = [HasAVX512] in {
89 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
90 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
93 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
94 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
95 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
96 def : Pat<(v16f32 immAllZerosV), (AVX512_512_SET0)>;
98 //===----------------------------------------------------------------------===//
99 // AVX-512 - VECTOR INSERT
102 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
103 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
104 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
105 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
106 []>, EVEX_4V, EVEX_V512;
108 def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
109 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
110 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
111 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
114 // -- 64x4 fp form --
115 let neverHasSideEffects = 1, ExeDomain = SSEPackedDouble in {
116 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
117 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
118 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
119 []>, EVEX_4V, EVEX_V512, VEX_W;
121 def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
122 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
123 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
124 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
126 // -- 32x4 integer form --
127 let neverHasSideEffects = 1 in {
128 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
129 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
130 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
131 []>, EVEX_4V, EVEX_V512;
133 def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
134 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
135 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
136 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
140 let neverHasSideEffects = 1 in {
142 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
143 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
144 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
145 []>, EVEX_4V, EVEX_V512, VEX_W;
147 def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
148 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
149 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
150 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
153 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
154 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
155 (INSERT_get_vinsert128_imm VR512:$ins))>;
156 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
157 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
158 (INSERT_get_vinsert128_imm VR512:$ins))>;
159 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
160 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
161 (INSERT_get_vinsert128_imm VR512:$ins))>;
162 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
163 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
164 (INSERT_get_vinsert128_imm VR512:$ins))>;
166 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
167 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
168 (INSERT_get_vinsert128_imm VR512:$ins))>;
169 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
170 (bc_v4i32 (loadv2i64 addr:$src2)),
171 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
172 (INSERT_get_vinsert128_imm VR512:$ins))>;
173 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
174 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
175 (INSERT_get_vinsert128_imm VR512:$ins))>;
176 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
177 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
178 (INSERT_get_vinsert128_imm VR512:$ins))>;
180 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
181 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
182 (INSERT_get_vinsert256_imm VR512:$ins))>;
183 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
184 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
185 (INSERT_get_vinsert256_imm VR512:$ins))>;
186 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
187 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
188 (INSERT_get_vinsert256_imm VR512:$ins))>;
189 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
190 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
191 (INSERT_get_vinsert256_imm VR512:$ins))>;
193 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
194 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
195 (INSERT_get_vinsert256_imm VR512:$ins))>;
196 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
197 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
198 (INSERT_get_vinsert256_imm VR512:$ins))>;
199 def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
200 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
201 (INSERT_get_vinsert256_imm VR512:$ins))>;
202 def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
203 (bc_v8i32 (loadv4i64 addr:$src2)),
204 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
205 (INSERT_get_vinsert256_imm VR512:$ins))>;
207 // vinsertps - insert f32 to XMM
208 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
209 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
210 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
211 [(set VR128X:$dst, (X86insrtps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
213 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
214 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
215 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
216 [(set VR128X:$dst, (X86insrtps VR128X:$src1,
217 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
218 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
220 //===----------------------------------------------------------------------===//
221 // AVX-512 VECTOR EXTRACT
223 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
225 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
226 (ins VR512:$src1, i8imm:$src2),
227 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
228 []>, EVEX, EVEX_V512;
229 def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
230 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
231 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
232 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
235 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
236 (ins VR512:$src1, i8imm:$src2),
237 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
238 []>, EVEX, EVEX_V512, VEX_W;
240 def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
241 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
242 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
243 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
246 let neverHasSideEffects = 1 in {
248 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
249 (ins VR512:$src1, i8imm:$src2),
250 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
251 []>, EVEX, EVEX_V512;
252 def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
253 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
254 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
255 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
258 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
259 (ins VR512:$src1, i8imm:$src2),
260 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
261 []>, EVEX, EVEX_V512, VEX_W;
263 def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
264 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
265 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
266 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
269 def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
270 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
271 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
273 def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
274 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
275 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
277 def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
278 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
279 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
281 def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
282 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
283 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
286 def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
287 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
288 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
290 def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
291 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
292 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
294 def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
295 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
296 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
298 def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
299 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
300 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
302 // A 256-bit subvector extract from the first 512-bit vector position
303 // is a subregister copy that needs no instruction.
304 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
305 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
306 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
307 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
308 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
309 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
310 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
311 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
314 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
315 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
316 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
317 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
318 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
319 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
320 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
321 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
324 // A 128-bit subvector insert to the first 512-bit vector position
325 // is a subregister copy that needs no instruction.
326 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
327 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
328 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
330 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
331 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
332 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
334 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
335 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
336 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
338 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
339 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
340 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
343 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
344 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
345 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
346 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
347 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
348 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
349 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
350 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
352 // vextractps - extract 32 bits from XMM
353 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
354 (ins VR128X:$src1, u32u8imm:$src2),
355 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
356 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
359 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
360 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
361 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
362 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
365 //===---------------------------------------------------------------------===//
368 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
369 RegisterClass DestRC,
370 RegisterClass SrcRC, X86MemOperand x86memop> {
371 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
372 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
374 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
375 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),[]>, EVEX;
377 let ExeDomain = SSEPackedSingle in {
378 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
380 EVEX_V512, EVEX_CD8<32, CD8VT1>;
383 let ExeDomain = SSEPackedDouble in {
384 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
386 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
389 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
390 (VBROADCASTSSZrm addr:$src)>;
391 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
392 (VBROADCASTSDZrm addr:$src)>;
394 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
395 (VBROADCASTSSZrm addr:$src)>;
396 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
397 (VBROADCASTSDZrm addr:$src)>;
399 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
400 RegisterClass SrcRC, RegisterClass KRC> {
401 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
402 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
403 []>, EVEX, EVEX_V512;
404 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
405 (ins KRC:$mask, SrcRC:$src),
406 !strconcat(OpcodeStr,
407 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
408 []>, EVEX, EVEX_V512, EVEX_KZ;
411 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
412 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
415 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
416 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
418 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
419 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
421 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
422 (VPBROADCASTDrZrr GR32:$src)>;
423 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
424 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
425 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
426 (VPBROADCASTQrZrr GR64:$src)>;
427 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
428 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
430 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
431 (VPBROADCASTDrZrr GR32:$src)>;
432 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
433 (VPBROADCASTQrZrr GR64:$src)>;
435 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
436 X86MemOperand x86memop, PatFrag ld_frag,
437 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
439 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
440 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
442 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
443 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
445 !strconcat(OpcodeStr,
446 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
448 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
451 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
452 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
454 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
455 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
457 !strconcat(OpcodeStr,
458 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
459 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
460 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
464 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
465 loadi32, VR512, v16i32, v4i32, VK16WM>,
466 EVEX_V512, EVEX_CD8<32, CD8VT1>;
467 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
468 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
469 EVEX_CD8<64, CD8VT1>;
471 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
472 (VPBROADCASTDZrr VR128X:$src)>;
473 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
474 (VPBROADCASTQZrr VR128X:$src)>;
476 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
477 (VBROADCASTSSZrr VR128X:$src)>;
478 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
479 (VBROADCASTSDZrr VR128X:$src)>;
481 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
482 (VBROADCASTSSZrr VR128X:$src)>;
483 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
484 (VBROADCASTSDZrr VR128X:$src)>;
486 // Provide fallback in case the load node that is used in the patterns above
487 // is used by additional users, which prevents the pattern selection.
488 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
489 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
490 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
491 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
494 let Predicates = [HasAVX512] in {
495 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
497 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
498 addr:$src)), sub_ymm)>;
500 //===----------------------------------------------------------------------===//
501 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
504 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
505 RegisterClass DstRC, RegisterClass KRC,
506 ValueType OpVT, ValueType SrcVT> {
507 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
508 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
512 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
513 VK16, v16i32, v16i1>, EVEX_V512;
514 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
515 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
517 //===----------------------------------------------------------------------===//
520 // -- immediate form --
521 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
522 SDNode OpNode, PatFrag mem_frag,
523 X86MemOperand x86memop, ValueType OpVT> {
524 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
525 (ins RC:$src1, i8imm:$src2),
526 !strconcat(OpcodeStr,
527 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
529 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
531 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
532 (ins x86memop:$src1, i8imm:$src2),
533 !strconcat(OpcodeStr,
534 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
536 (OpVT (OpNode (mem_frag addr:$src1),
537 (i8 imm:$src2))))]>, EVEX;
540 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
541 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
542 let ExeDomain = SSEPackedDouble in
543 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
544 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
546 // -- VPERM - register form --
547 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
548 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
550 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
551 (ins RC:$src1, RC:$src2),
552 !strconcat(OpcodeStr,
553 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
555 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
557 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
558 (ins RC:$src1, x86memop:$src2),
559 !strconcat(OpcodeStr,
560 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
562 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
566 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
567 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
568 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
569 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
570 let ExeDomain = SSEPackedSingle in
571 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
572 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
573 let ExeDomain = SSEPackedDouble in
574 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
575 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
577 // -- VPERM2I - 3 source operands form --
578 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
579 PatFrag mem_frag, X86MemOperand x86memop,
581 let Constraints = "$src1 = $dst" in {
582 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
583 (ins RC:$src1, RC:$src2, RC:$src3),
584 !strconcat(OpcodeStr,
585 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
587 (OpVT (X86VPermv3 RC:$src1, RC:$src2, RC:$src3)))]>,
590 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
591 (ins RC:$src1, RC:$src2, x86memop:$src3),
592 !strconcat(OpcodeStr,
593 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
595 (OpVT (X86VPermv3 RC:$src1, RC:$src2,
596 (mem_frag addr:$src3))))]>, EVEX_4V;
599 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem,
600 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
601 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem,
602 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
603 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem,
604 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
605 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
606 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
608 //===----------------------------------------------------------------------===//
609 // AVX-512 - BLEND using mask
611 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, Intrinsic Int,
612 RegisterClass KRC, RegisterClass RC,
613 X86MemOperand x86memop, PatFrag mem_frag,
614 SDNode OpNode, ValueType vt> {
615 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
616 (ins KRC:$mask, RC:$src1, RC:$src2),
617 !strconcat(OpcodeStr,
618 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
619 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
620 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
621 let isCodeGenOnly = 1 in
622 def rr_Int : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
623 (ins KRC:$mask, RC:$src1, RC:$src2),
624 !strconcat(OpcodeStr,
625 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
626 [(set RC:$dst, (Int KRC:$mask, (vt RC:$src2),
627 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
630 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
631 (ins KRC:$mask, RC:$src1, x86memop:$src2),
632 !strconcat(OpcodeStr,
633 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
637 let isCodeGenOnly = 1 in
638 def rm_Int : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
639 (ins KRC:$mask, RC:$src1, x86memop:$src2),
640 !strconcat(OpcodeStr,
641 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
642 [(set RC:$dst, (Int KRC:$mask, (vt RC:$src1),
643 (mem_frag addr:$src2)))]>,
648 let ExeDomain = SSEPackedSingle in
649 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
650 int_x86_avx512_mask_blend_ps_512,
651 VK16WM, VR512, f512mem,
652 memopv16f32, vselect, v16f32>,
653 EVEX_CD8<32, CD8VF>, EVEX_V512;
654 let ExeDomain = SSEPackedDouble in
655 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
656 int_x86_avx512_mask_blend_pd_512,
657 VK8WM, VR512, f512mem,
658 memopv8f64, vselect, v8f64>,
659 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
661 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
662 int_x86_avx512_mask_blend_d_512,
663 VK16WM, VR512, f512mem,
664 memopv16i32, vselect, v16i32>,
665 EVEX_CD8<32, CD8VF>, EVEX_V512;
667 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
668 int_x86_avx512_mask_blend_q_512,
669 VK8WM, VR512, f512mem,
670 memopv8i64, vselect, v8i64>,
671 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
673 let Predicates = [HasAVX512] in {
674 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
675 (v8f32 VR256X:$src2))),
677 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
678 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
679 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
681 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
682 (v8i32 VR256X:$src2))),
684 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
685 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
686 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
688 //===----------------------------------------------------------------------===//
689 // Compare Instructions
690 //===----------------------------------------------------------------------===//
692 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
693 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
694 Operand CC, SDNode OpNode, ValueType VT,
695 PatFrag ld_frag, string asm, string asm_alt> {
696 def rr : AVX512Ii8<0xC2, MRMSrcReg,
697 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
698 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
699 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
700 def rm : AVX512Ii8<0xC2, MRMSrcMem,
701 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
702 [(set VK1:$dst, (OpNode (VT RC:$src1),
703 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
704 let neverHasSideEffects = 1 in {
705 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
706 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
707 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
708 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
709 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
710 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
714 let Predicates = [HasAVX512] in {
715 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
716 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
717 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
719 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
720 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
721 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
725 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
726 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
727 SDNode OpNode, ValueType vt> {
728 def rr : AVX512BI<opc, MRMSrcReg,
729 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
730 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
731 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
732 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
733 def rm : AVX512BI<opc, MRMSrcMem,
734 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
735 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
736 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
737 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
740 defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
741 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512;
742 defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
743 memopv8i64, X86pcmpeqm, v8i64>, T8, EVEX_V512, VEX_W;
745 defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
746 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512;
747 defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
748 memopv8i64, X86pcmpgtm, v8i64>, T8, EVEX_V512, VEX_W;
750 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
751 (COPY_TO_REGCLASS (VPCMPGTDZrr
752 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
753 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
755 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
756 (COPY_TO_REGCLASS (VPCMPEQDZrr
757 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
758 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
760 multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
761 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
762 SDNode OpNode, ValueType vt, Operand CC, string asm,
764 def rri : AVX512AIi8<opc, MRMSrcReg,
765 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
766 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
767 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
768 def rmi : AVX512AIi8<opc, MRMSrcMem,
769 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
770 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
771 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
772 // Accept explicit immediate argument form instead of comparison code.
773 let neverHasSideEffects = 1 in {
774 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
775 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
776 asm_alt, [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
777 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
778 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
779 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
783 defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv16i32,
784 X86cmpm, v16i32, AVXCC,
785 "vpcmp${cc}d\t{$src2, $src1, $dst|$dst, $src1, $src2}",
786 "vpcmpd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
787 EVEX_V512, EVEX_CD8<32, CD8VF>;
788 defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv16i32,
789 X86cmpmu, v16i32, AVXCC,
790 "vpcmp${cc}ud\t{$src2, $src1, $dst|$dst, $src1, $src2}",
791 "vpcmpud\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
792 EVEX_V512, EVEX_CD8<32, CD8VF>;
794 defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64,
795 X86cmpm, v8i64, AVXCC,
796 "vpcmp${cc}q\t{$src2, $src1, $dst|$dst, $src1, $src2}",
797 "vpcmpq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
798 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
799 defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64,
800 X86cmpmu, v8i64, AVXCC,
801 "vpcmp${cc}uq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
802 "vpcmpuq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
803 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
805 // avx512_cmp_packed - sse 1 & 2 compare packed instructions
806 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
807 X86MemOperand x86memop, ValueType vt,
808 string suffix, Domain d> {
809 def rri : AVX512PIi8<0xC2, MRMSrcReg,
810 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
811 !strconcat("vcmp${cc}", suffix,
812 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
813 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
814 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
815 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc, i32imm:$sae),
816 !strconcat("vcmp${cc}", suffix,
817 "\t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
819 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
820 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
821 !strconcat("vcmp", suffix,
822 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
824 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
826 // Accept explicit immediate argument form instead of comparison code.
827 let neverHasSideEffects = 1 in {
828 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
829 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
830 !strconcat("vcmp", suffix,
831 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
832 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
833 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
834 !strconcat("vcmp", suffix,
835 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
839 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
840 "ps", SSEPackedSingle>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VF>;
841 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
842 "pd", SSEPackedDouble>, OpSize, EVEX_4V, VEX_W, EVEX_V512,
845 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
846 (COPY_TO_REGCLASS (VCMPPSZrri
847 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
848 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
850 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
851 (COPY_TO_REGCLASS (VPCMPDZrri
852 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
853 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
855 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
856 (COPY_TO_REGCLASS (VPCMPUDZrri
857 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
858 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
861 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
862 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
864 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
865 (I8Imm imm:$cc), (i32 0)), GR16)>;
867 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
868 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
870 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
871 (I8Imm imm:$cc), (i32 0)), GR8)>;
873 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
874 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
876 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
877 (I8Imm imm:$cc)), GR16)>;
879 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
880 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
882 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
883 (I8Imm imm:$cc)), GR8)>;
885 // Mask register copy, including
886 // - copy between mask registers
887 // - load/store mask registers
888 // - copy from GPR to mask register and vice versa
890 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
891 string OpcodeStr, RegisterClass KRC,
892 ValueType vt, X86MemOperand x86memop> {
893 let neverHasSideEffects = 1 in {
894 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
895 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
897 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
898 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
899 [(set KRC:$dst, (vt (load addr:$src)))]>;
901 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
902 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
906 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
908 RegisterClass KRC, RegisterClass GRC> {
909 let neverHasSideEffects = 1 in {
910 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
911 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
912 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
913 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
917 let Predicates = [HasAVX512] in {
918 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
920 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
924 let Predicates = [HasAVX512] in {
925 // GR16 from/to 16-bit mask
926 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
927 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
928 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
929 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
931 // Store kreg in memory
932 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
933 (KMOVWmk addr:$dst, VK16:$src)>;
935 def : Pat<(store VK8:$src, addr:$dst),
936 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
938 def : Pat<(i1 (load addr:$src)),
939 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
941 def : Pat<(v8i1 (load addr:$src)),
942 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
944 def : Pat<(i1 (trunc (i32 GR32:$src))),
945 (COPY_TO_REGCLASS (KMOVWkr $src), VK1)>;
947 def : Pat<(i1 (trunc (i8 GR8:$src))),
949 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)), VK1)>;
951 def : Pat<(i32 (zext VK1:$src)), (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16))>;
952 def : Pat<(i8 (zext VK1:$src)),
954 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_8bit)>;
956 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
957 let Predicates = [HasAVX512] in {
958 // GR from/to 8-bit mask without native support
959 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
961 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
963 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
965 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
968 def : Pat<(i1 (extractelt VK16:$src, (iPTR 0))),
969 (COPY_TO_REGCLASS VK16:$src, VK1)>;
970 def : Pat<(i1 (extractelt VK8:$src, (iPTR 0))),
971 (COPY_TO_REGCLASS VK8:$src, VK1)>;
975 // Mask unary operation
977 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
978 RegisterClass KRC, SDPatternOperator OpNode> {
979 let Predicates = [HasAVX512] in
980 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
981 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
982 [(set KRC:$dst, (OpNode KRC:$src))]>;
985 multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
986 SDPatternOperator OpNode> {
987 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
991 defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
993 multiclass avx512_mask_unop_int<string IntName, string InstName> {
994 let Predicates = [HasAVX512] in
995 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
997 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
998 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1000 defm : avx512_mask_unop_int<"knot", "KNOT">;
1002 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1003 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1004 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1006 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1007 def : Pat<(not VK8:$src),
1009 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1011 // Mask binary operation
1012 // - KAND, KANDN, KOR, KXNOR, KXOR
1013 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1014 RegisterClass KRC, SDPatternOperator OpNode> {
1015 let Predicates = [HasAVX512] in
1016 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1017 !strconcat(OpcodeStr,
1018 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1019 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1022 multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
1023 SDPatternOperator OpNode> {
1024 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1028 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1029 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1031 let isCommutable = 1 in {
1032 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
1033 let isCommutable = 0 in
1034 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
1035 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
1036 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
1037 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
1040 def : Pat<(xor VK1:$src1, VK1:$src2),
1041 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1042 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1044 def : Pat<(or VK1:$src1, VK1:$src2),
1045 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1046 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1048 def : Pat<(not VK1:$src),
1049 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src, VK16),
1050 (COPY_TO_REGCLASS (VCMPSSZrr (f32 (IMPLICIT_DEF)),
1051 (f32 (IMPLICIT_DEF)), (i8 0)), VK16)), VK1)>;
1053 def : Pat<(and VK1:$src1, VK1:$src2),
1054 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1055 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1057 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1058 let Predicates = [HasAVX512] in
1059 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1060 (i16 GR16:$src1), (i16 GR16:$src2)),
1061 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1062 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1063 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1066 defm : avx512_mask_binop_int<"kand", "KAND">;
1067 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1068 defm : avx512_mask_binop_int<"kor", "KOR">;
1069 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1070 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1072 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1073 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1074 let Predicates = [HasAVX512] in
1075 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1077 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1078 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1081 defm : avx512_binop_pat<and, KANDWrr>;
1082 defm : avx512_binop_pat<andn, KANDNWrr>;
1083 defm : avx512_binop_pat<or, KORWrr>;
1084 defm : avx512_binop_pat<xnor, KXNORWrr>;
1085 defm : avx512_binop_pat<xor, KXORWrr>;
1088 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1089 RegisterClass KRC> {
1090 let Predicates = [HasAVX512] in
1091 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1092 !strconcat(OpcodeStr,
1093 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1096 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1097 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1098 VEX_4V, VEX_L, OpSize, TB;
1101 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1102 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1103 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1104 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1107 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1108 let Predicates = [HasAVX512] in
1109 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1110 (i16 GR16:$src1), (i16 GR16:$src2)),
1111 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1112 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1113 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1115 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1118 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1120 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1121 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1122 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1123 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1126 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1127 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1131 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1133 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1134 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1135 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1138 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1140 let Predicates = [HasAVX512] in
1141 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1142 !strconcat(OpcodeStr,
1143 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
1144 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1147 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1149 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1150 VEX, OpSize, TA, VEX_W;
1153 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1154 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1156 // Mask setting all 0s or 1s
1157 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1158 let Predicates = [HasAVX512] in
1159 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1160 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1161 [(set KRC:$dst, (VT Val))]>;
1164 multiclass avx512_mask_setop_w<PatFrag Val> {
1165 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1166 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1169 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1170 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1172 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1173 let Predicates = [HasAVX512] in {
1174 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1175 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1177 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1178 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1180 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1181 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1183 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1184 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1186 //===----------------------------------------------------------------------===//
1187 // AVX-512 - Aligned and unaligned load and store
1190 multiclass avx512_mov_packed<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1191 X86MemOperand x86memop, PatFrag ld_frag,
1192 string asm, Domain d> {
1193 let neverHasSideEffects = 1 in
1194 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1195 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>,
1197 let canFoldAsLoad = 1 in
1198 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1199 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1200 [(set RC:$dst, (ld_frag addr:$src))], d>, EVEX;
1201 let Constraints = "$src1 = $dst" in {
1202 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1203 (ins RC:$src1, KRC:$mask, RC:$src2),
1205 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1207 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1208 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1210 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1211 [], d>, EVEX, EVEX_K;
1215 defm VMOVAPSZ : avx512_mov_packed<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1216 "vmovaps", SSEPackedSingle>,
1217 EVEX_V512, EVEX_CD8<32, CD8VF>;
1218 defm VMOVAPDZ : avx512_mov_packed<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1219 "vmovapd", SSEPackedDouble>,
1220 OpSize, EVEX_V512, VEX_W,
1221 EVEX_CD8<64, CD8VF>;
1222 defm VMOVUPSZ : avx512_mov_packed<0x10, VR512, VK16WM, f512mem, loadv16f32,
1223 "vmovups", SSEPackedSingle>,
1224 EVEX_V512, EVEX_CD8<32, CD8VF>;
1225 defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64,
1226 "vmovupd", SSEPackedDouble>,
1227 OpSize, EVEX_V512, VEX_W,
1228 EVEX_CD8<64, CD8VF>;
1229 def VMOVAPSZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1230 "vmovaps\t{$src, $dst|$dst, $src}",
1231 [(alignedstore512 (v16f32 VR512:$src), addr:$dst)],
1232 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1233 def VMOVAPDZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1234 "vmovapd\t{$src, $dst|$dst, $src}",
1235 [(alignedstore512 (v8f64 VR512:$src), addr:$dst)],
1236 SSEPackedDouble>, EVEX, EVEX_V512,
1237 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1238 def VMOVUPSZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1239 "vmovups\t{$src, $dst|$dst, $src}",
1240 [(store (v16f32 VR512:$src), addr:$dst)],
1241 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1242 def VMOVUPDZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1243 "vmovupd\t{$src, $dst|$dst, $src}",
1244 [(store (v8f64 VR512:$src), addr:$dst)],
1245 SSEPackedDouble>, EVEX, EVEX_V512,
1246 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1248 let neverHasSideEffects = 1 in {
1249 def VMOVDQA32rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1251 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1253 def VMOVDQA64rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1255 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1256 EVEX, EVEX_V512, VEX_W;
1257 let mayStore = 1 in {
1258 def VMOVDQA32mr : AVX512BI<0x7F, MRMDestMem, (outs),
1259 (ins i512mem:$dst, VR512:$src),
1260 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1261 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1262 def VMOVDQA64mr : AVX512BI<0x7F, MRMDestMem, (outs),
1263 (ins i512mem:$dst, VR512:$src),
1264 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1265 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1267 let mayLoad = 1 in {
1268 def VMOVDQA32rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1270 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1271 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1272 def VMOVDQA64rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1274 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1275 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1279 // 512-bit aligned load/store
1280 def : Pat<(alignedloadv8i64 addr:$src), (VMOVDQA64rm addr:$src)>;
1281 def : Pat<(alignedloadv16i32 addr:$src), (VMOVDQA32rm addr:$src)>;
1283 def : Pat<(alignedstore512 (v8i64 VR512:$src), addr:$dst),
1284 (VMOVDQA64mr addr:$dst, VR512:$src)>;
1285 def : Pat<(alignedstore512 (v16i32 VR512:$src), addr:$dst),
1286 (VMOVDQA32mr addr:$dst, VR512:$src)>;
1288 multiclass avx512_mov_int<bits<8> load_opc, bits<8> store_opc, string asm,
1289 RegisterClass RC, RegisterClass KRC,
1290 PatFrag ld_frag, X86MemOperand x86memop> {
1291 let neverHasSideEffects = 1 in
1292 def rr : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1293 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>, EVEX;
1294 let canFoldAsLoad = 1 in
1295 def rm : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1296 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1297 [(set RC:$dst, (ld_frag addr:$src))]>, EVEX;
1299 def mr : AVX512XSI<store_opc, MRMDestMem, (outs),
1300 (ins x86memop:$dst, VR512:$src),
1301 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>, EVEX;
1302 let Constraints = "$src1 = $dst" in {
1303 def rrk : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst),
1304 (ins RC:$src1, KRC:$mask, RC:$src2),
1306 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), []>,
1308 def rmk : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst),
1309 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1311 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1316 defm VMOVDQU32 : avx512_mov_int<0x6F, 0x7F, "vmovdqu32", VR512, VK16WM,
1317 memopv16i32, i512mem>,
1318 EVEX_V512, EVEX_CD8<32, CD8VF>;
1319 defm VMOVDQU64 : avx512_mov_int<0x6F, 0x7F, "vmovdqu64", VR512, VK8WM,
1320 memopv8i64, i512mem>,
1321 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1323 // 512-bit unaligned load/store
1324 def : Pat<(loadv8i64 addr:$src), (VMOVDQU64rm addr:$src)>;
1325 def : Pat<(loadv16i32 addr:$src), (VMOVDQU32rm addr:$src)>;
1327 def : Pat<(store (v8i64 VR512:$src), addr:$dst),
1328 (VMOVDQU64mr addr:$dst, VR512:$src)>;
1329 def : Pat<(store (v16i32 VR512:$src), addr:$dst),
1330 (VMOVDQU32mr addr:$dst, VR512:$src)>;
1332 let AddedComplexity = 20 in {
1333 def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1334 (v16f32 VR512:$src2))),
1335 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1336 def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1337 (v8f64 VR512:$src2))),
1338 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1339 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1340 (v16i32 VR512:$src2))),
1341 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1342 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1343 (v8i64 VR512:$src2))),
1344 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1346 // Move Int Doubleword to Packed Double Int
1348 def VMOVDI2PDIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1349 "vmovd\t{$src, $dst|$dst, $src}",
1351 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1353 def VMOVDI2PDIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1354 "vmovd\t{$src, $dst|$dst, $src}",
1356 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1357 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1358 def VMOV64toPQIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1359 "vmovq\t{$src, $dst|$dst, $src}",
1361 (v2i64 (scalar_to_vector GR64:$src)))],
1362 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
1363 let isCodeGenOnly = 1 in {
1364 def VMOV64toSDZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1365 "vmovq\t{$src, $dst|$dst, $src}",
1366 [(set FR64:$dst, (bitconvert GR64:$src))],
1367 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1368 def VMOVSDto64Zrr : AVX512SI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1369 "vmovq\t{$src, $dst|$dst, $src}",
1370 [(set GR64:$dst, (bitconvert FR64:$src))],
1371 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1373 def VMOVSDto64Zmr : AVX512SI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1374 "vmovq\t{$src, $dst|$dst, $src}",
1375 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1376 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1377 EVEX_CD8<64, CD8VT1>;
1379 // Move Int Doubleword to Single Scalar
1381 let isCodeGenOnly = 1 in {
1382 def VMOVDI2SSZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1383 "vmovd\t{$src, $dst|$dst, $src}",
1384 [(set FR32X:$dst, (bitconvert GR32:$src))],
1385 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1387 def VMOVDI2SSZrm : AVX512SI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1388 "vmovd\t{$src, $dst|$dst, $src}",
1389 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1390 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1393 // Move Packed Doubleword Int to Packed Double Int
1395 def VMOVPDI2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1396 "vmovd\t{$src, $dst|$dst, $src}",
1397 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1398 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1400 def VMOVPDI2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1401 (ins i32mem:$dst, VR128X:$src),
1402 "vmovd\t{$src, $dst|$dst, $src}",
1403 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1404 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1405 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1407 // Move Packed Doubleword Int first element to Doubleword Int
1409 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1410 "vmovq\t{$src, $dst|$dst, $src}",
1411 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1413 IIC_SSE_MOVD_ToGP>, TB, OpSize, EVEX, VEX_LIG, VEX_W,
1414 Requires<[HasAVX512, In64BitMode]>;
1416 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
1417 (ins i64mem:$dst, VR128X:$src),
1418 "vmovq\t{$src, $dst|$dst, $src}",
1419 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1420 addr:$dst)], IIC_SSE_MOVDQ>,
1421 EVEX, OpSize, VEX_LIG, VEX_W, TB, EVEX_CD8<64, CD8VT1>,
1422 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1424 // Move Scalar Single to Double Int
1426 let isCodeGenOnly = 1 in {
1427 def VMOVSS2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst),
1429 "vmovd\t{$src, $dst|$dst, $src}",
1430 [(set GR32:$dst, (bitconvert FR32X:$src))],
1431 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1432 def VMOVSS2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1433 (ins i32mem:$dst, FR32X:$src),
1434 "vmovd\t{$src, $dst|$dst, $src}",
1435 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1436 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1439 // Move Quadword Int to Packed Quadword Int
1441 def VMOVQI2PQIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst),
1443 "vmovq\t{$src, $dst|$dst, $src}",
1445 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1446 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1448 //===----------------------------------------------------------------------===//
1449 // AVX-512 MOVSS, MOVSD
1450 //===----------------------------------------------------------------------===//
1452 multiclass avx512_move_scalar <string asm, RegisterClass RC,
1453 SDNode OpNode, ValueType vt,
1454 X86MemOperand x86memop, PatFrag mem_pat> {
1455 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1456 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1457 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1458 (scalar_to_vector RC:$src2))))],
1459 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1460 let Constraints = "$src1 = $dst" in
1461 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
1462 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
1464 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
1465 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
1466 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1467 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1468 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1470 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1471 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1472 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1476 let ExeDomain = SSEPackedSingle in
1477 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
1478 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1480 let ExeDomain = SSEPackedDouble in
1481 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
1482 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1484 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
1485 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
1486 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
1488 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
1489 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
1490 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
1492 // For the disassembler
1493 let isCodeGenOnly = 1 in {
1494 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1495 (ins VR128X:$src1, FR32X:$src2),
1496 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1498 XS, EVEX_4V, VEX_LIG;
1499 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1500 (ins VR128X:$src1, FR64X:$src2),
1501 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1503 XD, EVEX_4V, VEX_LIG, VEX_W;
1506 let Predicates = [HasAVX512] in {
1507 let AddedComplexity = 15 in {
1508 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1509 // MOVS{S,D} to the lower bits.
1510 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1511 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1512 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1513 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1514 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1515 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1516 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1517 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1519 // Move low f32 and clear high bits.
1520 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1521 (SUBREG_TO_REG (i32 0),
1522 (VMOVSSZrr (v4f32 (V_SET0)),
1523 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1524 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1525 (SUBREG_TO_REG (i32 0),
1526 (VMOVSSZrr (v4i32 (V_SET0)),
1527 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1530 let AddedComplexity = 20 in {
1531 // MOVSSrm zeros the high parts of the register; represent this
1532 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1533 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1534 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1535 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1536 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1537 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1538 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1540 // MOVSDrm zeros the high parts of the register; represent this
1541 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1542 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1543 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1544 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1545 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1546 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1547 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1548 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1549 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1550 def : Pat<(v2f64 (X86vzload addr:$src)),
1551 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1553 // Represent the same patterns above but in the form they appear for
1555 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1556 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
1557 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
1558 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1559 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1560 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1561 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1562 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1563 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1565 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1566 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1567 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1568 FR32X:$src)), sub_xmm)>;
1569 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1570 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1571 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1572 FR64X:$src)), sub_xmm)>;
1573 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1574 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
1575 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
1577 // Move low f64 and clear high bits.
1578 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1579 (SUBREG_TO_REG (i32 0),
1580 (VMOVSDZrr (v2f64 (V_SET0)),
1581 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1583 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1584 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1585 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1587 // Extract and store.
1588 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1590 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1591 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1593 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1595 // Shuffle with VMOVSS
1596 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1597 (VMOVSSZrr (v4i32 VR128X:$src1),
1598 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1599 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1600 (VMOVSSZrr (v4f32 VR128X:$src1),
1601 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1604 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1605 (SUBREG_TO_REG (i32 0),
1606 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1607 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1609 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1610 (SUBREG_TO_REG (i32 0),
1611 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1612 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1615 // Shuffle with VMOVSD
1616 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1617 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1618 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1619 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1620 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1621 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1622 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1623 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1626 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1627 (SUBREG_TO_REG (i32 0),
1628 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1629 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1631 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1632 (SUBREG_TO_REG (i32 0),
1633 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1634 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1637 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1638 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1639 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1640 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1641 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1642 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1643 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1644 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1647 let AddedComplexity = 15 in
1648 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1650 "vmovq\t{$src, $dst|$dst, $src}",
1651 [(set VR128X:$dst, (v2i64 (X86vzmovl
1652 (v2i64 VR128X:$src))))],
1653 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1655 let AddedComplexity = 20 in
1656 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1658 "vmovq\t{$src, $dst|$dst, $src}",
1659 [(set VR128X:$dst, (v2i64 (X86vzmovl
1660 (loadv2i64 addr:$src))))],
1661 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1662 EVEX_CD8<8, CD8VT8>;
1664 let Predicates = [HasAVX512] in {
1665 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1666 let AddedComplexity = 20 in {
1667 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1668 (VMOVDI2PDIZrm addr:$src)>;
1669 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
1670 (VMOV64toPQIZrr GR64:$src)>;
1671 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
1672 (VMOVDI2PDIZrr GR32:$src)>;
1674 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1675 (VMOVDI2PDIZrm addr:$src)>;
1676 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1677 (VMOVDI2PDIZrm addr:$src)>;
1678 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1679 (VMOVZPQILo2PQIZrm addr:$src)>;
1680 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1681 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1682 def : Pat<(v2i64 (X86vzload addr:$src)),
1683 (VMOVZPQILo2PQIZrm addr:$src)>;
1686 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1687 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1688 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1689 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1690 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1691 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1692 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1695 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
1696 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1698 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
1699 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1701 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
1702 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1704 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
1705 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1707 //===----------------------------------------------------------------------===//
1708 // AVX-512 - Integer arithmetic
1710 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1711 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1712 X86MemOperand x86memop, PatFrag scalar_mfrag,
1713 X86MemOperand x86scalar_mop, string BrdcstStr,
1714 OpndItins itins, bit IsCommutable = 0> {
1715 let isCommutable = IsCommutable in
1716 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1717 (ins RC:$src1, RC:$src2),
1718 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1719 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1721 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1722 (ins RC:$src1, x86memop:$src2),
1723 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1724 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
1726 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1727 (ins RC:$src1, x86scalar_mop:$src2),
1728 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1729 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1730 [(set RC:$dst, (OpNode RC:$src1,
1731 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1732 itins.rm>, EVEX_4V, EVEX_B;
1734 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr,
1735 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
1736 PatFrag memop_frag, X86MemOperand x86memop,
1738 bit IsCommutable = 0> {
1739 let isCommutable = IsCommutable in
1740 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1741 (ins RC:$src1, RC:$src2),
1742 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1743 []>, EVEX_4V, VEX_W;
1744 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1745 (ins RC:$src1, x86memop:$src2),
1746 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1747 []>, EVEX_4V, VEX_W;
1750 defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VR512, memopv16i32,
1751 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1752 EVEX_V512, EVEX_CD8<32, CD8VF>;
1754 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VR512, memopv16i32,
1755 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 0>,
1756 EVEX_V512, EVEX_CD8<32, CD8VF>;
1758 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VR512, memopv16i32,
1759 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1760 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1762 defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VR512, memopv8i64,
1763 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 1>,
1764 EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
1766 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VR512, memopv8i64,
1767 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1768 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1770 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32,
1771 VR512, memopv8i64, i512mem, SSE_INTALU_ITINS_P, 1>, T8,
1772 EVEX_V512, EVEX_CD8<64, CD8VF>;
1774 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32,
1775 VR512, memopv8i64, i512mem, SSE_INTMUL_ITINS_P, 1>, EVEX_V512,
1776 EVEX_CD8<64, CD8VF>;
1778 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
1779 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1781 defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VR512, memopv16i32,
1782 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1783 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1784 defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VR512, memopv8i64,
1785 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1786 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1788 defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VR512, memopv16i32,
1789 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1790 EVEX_V512, EVEX_CD8<32, CD8VF>;
1791 defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VR512, memopv8i64,
1792 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1793 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1795 defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VR512, memopv16i32,
1796 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1797 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1798 defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VR512, memopv8i64,
1799 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1800 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1802 defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VR512, memopv16i32,
1803 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1804 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1805 defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VR512, memopv8i64,
1806 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1807 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1809 //===----------------------------------------------------------------------===//
1810 // AVX-512 - Unpack Instructions
1811 //===----------------------------------------------------------------------===//
1813 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
1814 PatFrag mem_frag, RegisterClass RC,
1815 X86MemOperand x86memop, string asm,
1817 def rr : AVX512PI<opc, MRMSrcReg,
1818 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1820 (vt (OpNode RC:$src1, RC:$src2)))],
1822 def rm : AVX512PI<opc, MRMSrcMem,
1823 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1825 (vt (OpNode RC:$src1,
1826 (bitconvert (mem_frag addr:$src2)))))],
1830 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
1831 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1832 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1833 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
1834 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1835 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1836 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
1837 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1838 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1839 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
1840 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1841 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1843 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
1844 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1845 X86MemOperand x86memop> {
1846 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1847 (ins RC:$src1, RC:$src2),
1848 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1849 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1850 IIC_SSE_UNPCK>, EVEX_4V;
1851 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1852 (ins RC:$src1, x86memop:$src2),
1853 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1854 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
1855 (bitconvert (memop_frag addr:$src2)))))],
1856 IIC_SSE_UNPCK>, EVEX_4V;
1858 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
1859 VR512, memopv16i32, i512mem>, EVEX_V512,
1860 EVEX_CD8<32, CD8VF>;
1861 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
1862 VR512, memopv8i64, i512mem>, EVEX_V512,
1863 VEX_W, EVEX_CD8<64, CD8VF>;
1864 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
1865 VR512, memopv16i32, i512mem>, EVEX_V512,
1866 EVEX_CD8<32, CD8VF>;
1867 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
1868 VR512, memopv8i64, i512mem>, EVEX_V512,
1869 VEX_W, EVEX_CD8<64, CD8VF>;
1870 //===----------------------------------------------------------------------===//
1874 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
1875 SDNode OpNode, PatFrag mem_frag,
1876 X86MemOperand x86memop, ValueType OpVT> {
1877 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
1878 (ins RC:$src1, i8imm:$src2),
1879 !strconcat(OpcodeStr,
1880 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1882 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
1884 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
1885 (ins x86memop:$src1, i8imm:$src2),
1886 !strconcat(OpcodeStr,
1887 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1889 (OpVT (OpNode (mem_frag addr:$src1),
1890 (i8 imm:$src2))))]>, EVEX;
1893 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
1894 i512mem, v16i32>, OpSize, EVEX_V512, EVEX_CD8<32, CD8VF>;
1896 let ExeDomain = SSEPackedSingle in
1897 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
1898 memopv16f32, i512mem, v16f32>, OpSize, TA, EVEX_V512,
1899 EVEX_CD8<32, CD8VF>;
1900 let ExeDomain = SSEPackedDouble in
1901 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
1902 memopv8f64, i512mem, v8f64>, OpSize, TA, EVEX_V512,
1903 VEX_W, EVEX_CD8<32, CD8VF>;
1905 def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1906 (VPERMILPSZri VR512:$src1, imm:$imm)>;
1907 def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1908 (VPERMILPDZri VR512:$src1, imm:$imm)>;
1910 //===----------------------------------------------------------------------===//
1911 // AVX-512 Logical Instructions
1912 //===----------------------------------------------------------------------===//
1914 defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VR512, memopv16i32,
1915 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1916 EVEX_V512, EVEX_CD8<32, CD8VF>;
1917 defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VR512, memopv8i64,
1918 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1919 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1920 defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VR512, memopv16i32,
1921 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1922 EVEX_V512, EVEX_CD8<32, CD8VF>;
1923 defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VR512, memopv8i64,
1924 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1925 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1926 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VR512, memopv16i32,
1927 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1928 EVEX_V512, EVEX_CD8<32, CD8VF>;
1929 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VR512, memopv8i64,
1930 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1931 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1932 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VR512,
1933 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1934 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1935 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VR512, memopv8i64,
1936 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 0>,
1937 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1939 //===----------------------------------------------------------------------===//
1940 // AVX-512 FP arithmetic
1941 //===----------------------------------------------------------------------===//
1943 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1945 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
1946 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
1947 EVEX_CD8<32, CD8VT1>;
1948 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
1949 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
1950 EVEX_CD8<64, CD8VT1>;
1953 let isCommutable = 1 in {
1954 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
1955 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
1956 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
1957 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
1959 let isCommutable = 0 in {
1960 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
1961 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
1964 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1965 RegisterClass RC, ValueType vt,
1966 X86MemOperand x86memop, PatFrag mem_frag,
1967 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
1969 Domain d, OpndItins itins, bit commutable> {
1970 let isCommutable = commutable in
1971 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1972 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1973 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
1975 let mayLoad = 1 in {
1976 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1977 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1978 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
1979 itins.rm, d>, EVEX_4V, TB;
1980 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
1981 (ins RC:$src1, x86scalar_mop:$src2),
1982 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1983 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1984 [(set RC:$dst, (OpNode RC:$src1,
1985 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1986 itins.rm, d>, EVEX_4V, EVEX_B, TB;
1990 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VR512, v16f32, f512mem,
1991 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1992 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1994 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VR512, v8f64, f512mem,
1995 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1996 SSE_ALU_ITINS_P.d, 1>,
1997 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1999 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VR512, v16f32, f512mem,
2000 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2001 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2002 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VR512, v8f64, f512mem,
2003 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2004 SSE_ALU_ITINS_P.d, 1>,
2005 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
2007 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VR512, v16f32, f512mem,
2008 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2009 SSE_ALU_ITINS_P.s, 1>,
2010 EVEX_V512, EVEX_CD8<32, CD8VF>;
2011 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VR512, v16f32, f512mem,
2012 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2013 SSE_ALU_ITINS_P.s, 1>,
2014 EVEX_V512, EVEX_CD8<32, CD8VF>;
2016 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VR512, v8f64, f512mem,
2017 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2018 SSE_ALU_ITINS_P.d, 1>,
2019 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
2020 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VR512, v8f64, f512mem,
2021 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2022 SSE_ALU_ITINS_P.d, 1>,
2023 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
2025 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VR512, v16f32, f512mem,
2026 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2027 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2028 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VR512, v16f32, f512mem,
2029 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2030 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2032 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VR512, v8f64, f512mem,
2033 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2034 SSE_ALU_ITINS_P.d, 0>,
2035 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
2036 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VR512, v8f64, f512mem,
2037 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2038 SSE_ALU_ITINS_P.d, 0>,
2039 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
2041 //===----------------------------------------------------------------------===//
2042 // AVX-512 VPTESTM instructions
2043 //===----------------------------------------------------------------------===//
2045 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2046 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
2047 SDNode OpNode, ValueType vt> {
2048 def rr : AVX5128I<opc, MRMSrcReg,
2049 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
2050 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2051 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))]>, EVEX_4V;
2052 def rm : AVX5128I<opc, MRMSrcMem,
2053 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
2054 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2055 [(set KRC:$dst, (OpNode (vt RC:$src1),
2056 (bitconvert (memop_frag addr:$src2))))]>, EVEX_4V;
2059 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
2060 memopv16i32, X86testm, v16i32>, EVEX_V512,
2061 EVEX_CD8<32, CD8VF>;
2062 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
2063 memopv8i64, X86testm, v8i64>, EVEX_V512, VEX_W,
2064 EVEX_CD8<64, CD8VF>;
2066 //===----------------------------------------------------------------------===//
2067 // AVX-512 Shift instructions
2068 //===----------------------------------------------------------------------===//
2069 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
2070 string OpcodeStr, SDNode OpNode, RegisterClass RC,
2071 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
2072 RegisterClass KRC> {
2073 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2074 (ins RC:$src1, i8imm:$src2),
2075 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2076 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
2077 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2078 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2079 (ins KRC:$mask, RC:$src1, i8imm:$src2),
2080 !strconcat(OpcodeStr,
2081 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2082 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2083 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2084 (ins x86memop:$src1, i8imm:$src2),
2085 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2086 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
2087 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2088 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2089 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
2090 !strconcat(OpcodeStr,
2091 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2092 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2095 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2096 RegisterClass RC, ValueType vt, ValueType SrcVT,
2097 PatFrag bc_frag, RegisterClass KRC> {
2098 // src2 is always 128-bit
2099 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2100 (ins RC:$src1, VR128X:$src2),
2101 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2102 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
2103 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2104 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2105 (ins KRC:$mask, RC:$src1, VR128X:$src2),
2106 !strconcat(OpcodeStr,
2107 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2108 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2109 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2110 (ins RC:$src1, i128mem:$src2),
2111 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2112 [(set RC:$dst, (vt (OpNode RC:$src1,
2113 (bc_frag (memopv2i64 addr:$src2)))))],
2114 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2115 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2116 (ins KRC:$mask, RC:$src1, i128mem:$src2),
2117 !strconcat(OpcodeStr,
2118 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2119 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2122 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
2123 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2124 EVEX_V512, EVEX_CD8<32, CD8VF>;
2125 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
2126 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2127 EVEX_CD8<32, CD8VQ>;
2129 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
2130 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2131 EVEX_CD8<64, CD8VF>, VEX_W;
2132 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
2133 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2134 EVEX_CD8<64, CD8VQ>, VEX_W;
2136 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
2137 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
2138 EVEX_CD8<32, CD8VF>;
2139 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
2140 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2141 EVEX_CD8<32, CD8VQ>;
2143 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
2144 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2145 EVEX_CD8<64, CD8VF>, VEX_W;
2146 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
2147 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2148 EVEX_CD8<64, CD8VQ>, VEX_W;
2150 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
2151 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2152 EVEX_V512, EVEX_CD8<32, CD8VF>;
2153 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
2154 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2155 EVEX_CD8<32, CD8VQ>;
2157 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
2158 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2159 EVEX_CD8<64, CD8VF>, VEX_W;
2160 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
2161 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2162 EVEX_CD8<64, CD8VQ>, VEX_W;
2164 //===-------------------------------------------------------------------===//
2165 // Variable Bit Shifts
2166 //===-------------------------------------------------------------------===//
2167 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
2168 RegisterClass RC, ValueType vt,
2169 X86MemOperand x86memop, PatFrag mem_frag> {
2170 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
2171 (ins RC:$src1, RC:$src2),
2172 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2174 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
2176 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
2177 (ins RC:$src1, x86memop:$src2),
2178 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2180 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
2184 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
2185 i512mem, memopv16i32>, EVEX_V512,
2186 EVEX_CD8<32, CD8VF>;
2187 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
2188 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2189 EVEX_CD8<64, CD8VF>;
2190 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
2191 i512mem, memopv16i32>, EVEX_V512,
2192 EVEX_CD8<32, CD8VF>;
2193 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
2194 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2195 EVEX_CD8<64, CD8VF>;
2196 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
2197 i512mem, memopv16i32>, EVEX_V512,
2198 EVEX_CD8<32, CD8VF>;
2199 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
2200 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2201 EVEX_CD8<64, CD8VF>;
2203 //===----------------------------------------------------------------------===//
2204 // AVX-512 - MOVDDUP
2205 //===----------------------------------------------------------------------===//
2207 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
2208 X86MemOperand x86memop, PatFrag memop_frag> {
2209 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2210 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2211 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
2212 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2213 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2215 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
2218 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
2219 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
2220 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
2221 (VMOVDDUPZrm addr:$src)>;
2223 //===---------------------------------------------------------------------===//
2224 // Replicate Single FP - MOVSHDUP and MOVSLDUP
2225 //===---------------------------------------------------------------------===//
2226 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
2227 ValueType vt, RegisterClass RC, PatFrag mem_frag,
2228 X86MemOperand x86memop> {
2229 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2230 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2231 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
2233 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2234 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2235 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
2238 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
2239 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2240 EVEX_CD8<32, CD8VF>;
2241 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
2242 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2243 EVEX_CD8<32, CD8VF>;
2245 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
2246 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
2247 (VMOVSHDUPZrm addr:$src)>;
2248 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
2249 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
2250 (VMOVSLDUPZrm addr:$src)>;
2252 //===----------------------------------------------------------------------===//
2253 // Move Low to High and High to Low packed FP Instructions
2254 //===----------------------------------------------------------------------===//
2255 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
2256 (ins VR128X:$src1, VR128X:$src2),
2257 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2258 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2259 IIC_SSE_MOV_LH>, EVEX_4V;
2260 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2261 (ins VR128X:$src1, VR128X:$src2),
2262 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2263 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2264 IIC_SSE_MOV_LH>, EVEX_4V;
2266 let Predicates = [HasAVX512] in {
2268 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2269 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2270 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2271 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
2274 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2275 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2278 //===----------------------------------------------------------------------===//
2279 // FMA - Fused Multiply Operations
2281 let Constraints = "$src1 = $dst" in {
2282 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2283 RegisterClass RC, X86MemOperand x86memop,
2284 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2285 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2286 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2287 (ins RC:$src1, RC:$src2, RC:$src3),
2288 !strconcat(OpcodeStr,"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2289 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2292 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2293 (ins RC:$src1, RC:$src2, x86memop:$src3),
2294 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2295 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2296 (mem_frag addr:$src3))))]>;
2297 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2298 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2299 !strconcat(OpcodeStr, "\t{${src3}", BrdcstStr,
2300 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2301 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2302 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2304 } // Constraints = "$src1 = $dst"
2306 let ExeDomain = SSEPackedSingle in {
2307 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2308 memopv16f32, f32mem, loadf32, "{1to16}",
2309 X86Fmadd, v16f32>, EVEX_V512,
2310 EVEX_CD8<32, CD8VF>;
2311 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2312 memopv16f32, f32mem, loadf32, "{1to16}",
2313 X86Fmsub, v16f32>, EVEX_V512,
2314 EVEX_CD8<32, CD8VF>;
2315 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2316 memopv16f32, f32mem, loadf32, "{1to16}",
2317 X86Fmaddsub, v16f32>,
2318 EVEX_V512, EVEX_CD8<32, CD8VF>;
2319 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2320 memopv16f32, f32mem, loadf32, "{1to16}",
2321 X86Fmsubadd, v16f32>,
2322 EVEX_V512, EVEX_CD8<32, CD8VF>;
2323 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2324 memopv16f32, f32mem, loadf32, "{1to16}",
2325 X86Fnmadd, v16f32>, EVEX_V512,
2326 EVEX_CD8<32, CD8VF>;
2327 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2328 memopv16f32, f32mem, loadf32, "{1to16}",
2329 X86Fnmsub, v16f32>, EVEX_V512,
2330 EVEX_CD8<32, CD8VF>;
2332 let ExeDomain = SSEPackedDouble in {
2333 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2334 memopv8f64, f64mem, loadf64, "{1to8}",
2335 X86Fmadd, v8f64>, EVEX_V512,
2336 VEX_W, EVEX_CD8<64, CD8VF>;
2337 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2338 memopv8f64, f64mem, loadf64, "{1to8}",
2339 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2340 EVEX_CD8<64, CD8VF>;
2341 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2342 memopv8f64, f64mem, loadf64, "{1to8}",
2343 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2344 EVEX_CD8<64, CD8VF>;
2345 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2346 memopv8f64, f64mem, loadf64, "{1to8}",
2347 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2348 EVEX_CD8<64, CD8VF>;
2349 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2350 memopv8f64, f64mem, loadf64, "{1to8}",
2351 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2352 EVEX_CD8<64, CD8VF>;
2353 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2354 memopv8f64, f64mem, loadf64, "{1to8}",
2355 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2356 EVEX_CD8<64, CD8VF>;
2359 let Constraints = "$src1 = $dst" in {
2360 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2361 RegisterClass RC, X86MemOperand x86memop,
2362 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2363 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2365 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2366 (ins RC:$src1, RC:$src3, x86memop:$src2),
2367 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2368 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2369 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2370 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2371 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2372 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2373 [(set RC:$dst, (OpNode RC:$src1,
2374 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2376 } // Constraints = "$src1 = $dst"
2379 let ExeDomain = SSEPackedSingle in {
2380 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2381 memopv16f32, f32mem, loadf32, "{1to16}",
2382 X86Fmadd, v16f32>, EVEX_V512,
2383 EVEX_CD8<32, CD8VF>;
2384 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2385 memopv16f32, f32mem, loadf32, "{1to16}",
2386 X86Fmsub, v16f32>, EVEX_V512,
2387 EVEX_CD8<32, CD8VF>;
2388 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
2389 memopv16f32, f32mem, loadf32, "{1to16}",
2390 X86Fmaddsub, v16f32>,
2391 EVEX_V512, EVEX_CD8<32, CD8VF>;
2392 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
2393 memopv16f32, f32mem, loadf32, "{1to16}",
2394 X86Fmsubadd, v16f32>,
2395 EVEX_V512, EVEX_CD8<32, CD8VF>;
2396 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
2397 memopv16f32, f32mem, loadf32, "{1to16}",
2398 X86Fnmadd, v16f32>, EVEX_V512,
2399 EVEX_CD8<32, CD8VF>;
2400 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
2401 memopv16f32, f32mem, loadf32, "{1to16}",
2402 X86Fnmsub, v16f32>, EVEX_V512,
2403 EVEX_CD8<32, CD8VF>;
2405 let ExeDomain = SSEPackedDouble in {
2406 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
2407 memopv8f64, f64mem, loadf64, "{1to8}",
2408 X86Fmadd, v8f64>, EVEX_V512,
2409 VEX_W, EVEX_CD8<64, CD8VF>;
2410 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
2411 memopv8f64, f64mem, loadf64, "{1to8}",
2412 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2413 EVEX_CD8<64, CD8VF>;
2414 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
2415 memopv8f64, f64mem, loadf64, "{1to8}",
2416 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2417 EVEX_CD8<64, CD8VF>;
2418 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
2419 memopv8f64, f64mem, loadf64, "{1to8}",
2420 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2421 EVEX_CD8<64, CD8VF>;
2422 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
2423 memopv8f64, f64mem, loadf64, "{1to8}",
2424 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2425 EVEX_CD8<64, CD8VF>;
2426 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
2427 memopv8f64, f64mem, loadf64, "{1to8}",
2428 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2429 EVEX_CD8<64, CD8VF>;
2433 let Constraints = "$src1 = $dst" in {
2434 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2435 RegisterClass RC, ValueType OpVT,
2436 X86MemOperand x86memop, Operand memop,
2438 let isCommutable = 1 in
2439 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2440 (ins RC:$src1, RC:$src2, RC:$src3),
2441 !strconcat(OpcodeStr,
2442 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2444 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
2446 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2447 (ins RC:$src1, RC:$src2, f128mem:$src3),
2448 !strconcat(OpcodeStr,
2449 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2451 (OpVT (OpNode RC:$src2, RC:$src1,
2452 (mem_frag addr:$src3))))]>;
2455 } // Constraints = "$src1 = $dst"
2457 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
2458 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2459 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
2460 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2461 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
2462 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2463 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
2464 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2465 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
2466 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2467 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
2468 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2469 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
2470 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2471 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
2472 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2474 //===----------------------------------------------------------------------===//
2475 // AVX-512 Scalar convert from sign integer to float/double
2476 //===----------------------------------------------------------------------===//
2478 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2479 X86MemOperand x86memop, string asm> {
2480 let neverHasSideEffects = 1 in {
2481 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
2482 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2485 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
2486 (ins DstRC:$src1, x86memop:$src),
2487 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2489 } // neverHasSideEffects = 1
2491 let Predicates = [HasAVX512] in {
2492 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
2493 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2494 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
2495 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2496 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
2497 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2498 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
2499 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2501 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
2502 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2503 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
2504 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2505 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
2506 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2507 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
2508 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2510 def : Pat<(f32 (sint_to_fp GR32:$src)),
2511 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2512 def : Pat<(f32 (sint_to_fp GR64:$src)),
2513 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2514 def : Pat<(f64 (sint_to_fp GR32:$src)),
2515 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2516 def : Pat<(f64 (sint_to_fp GR64:$src)),
2517 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2519 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
2520 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2521 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
2522 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2523 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
2524 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2525 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
2526 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2528 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
2529 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2530 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
2531 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2532 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
2533 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2534 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
2535 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2537 def : Pat<(f32 (uint_to_fp GR32:$src)),
2538 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2539 def : Pat<(f32 (uint_to_fp GR64:$src)),
2540 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2541 def : Pat<(f64 (uint_to_fp GR32:$src)),
2542 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2543 def : Pat<(f64 (uint_to_fp GR64:$src)),
2544 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2547 //===----------------------------------------------------------------------===//
2548 // AVX-512 Scalar convert from float/double to integer
2549 //===----------------------------------------------------------------------===//
2550 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2551 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
2553 let neverHasSideEffects = 1 in {
2554 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2555 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2556 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
2557 Requires<[HasAVX512]>;
2559 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
2560 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
2561 Requires<[HasAVX512]>;
2562 } // neverHasSideEffects = 1
2564 let Predicates = [HasAVX512] in {
2565 // Convert float/double to signed/unsigned int 32/64
2566 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
2567 ssmem, sse_load_f32, "cvtss2si">,
2568 XS, EVEX_CD8<32, CD8VT1>;
2569 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
2570 ssmem, sse_load_f32, "cvtss2si">,
2571 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
2572 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
2573 ssmem, sse_load_f32, "cvtss2usi">,
2574 XS, EVEX_CD8<32, CD8VT1>;
2575 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2576 int_x86_avx512_cvtss2usi64, ssmem,
2577 sse_load_f32, "cvtss2usi">, XS, VEX_W,
2578 EVEX_CD8<32, CD8VT1>;
2579 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
2580 sdmem, sse_load_f64, "cvtsd2si">,
2581 XD, EVEX_CD8<64, CD8VT1>;
2582 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
2583 sdmem, sse_load_f64, "cvtsd2si">,
2584 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2585 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
2586 sdmem, sse_load_f64, "cvtsd2usi">,
2587 XD, EVEX_CD8<64, CD8VT1>;
2588 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2589 int_x86_avx512_cvtsd2usi64, sdmem,
2590 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
2591 EVEX_CD8<64, CD8VT1>;
2593 let isCodeGenOnly = 1 in {
2594 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2595 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
2596 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2597 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2598 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
2599 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2600 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2601 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
2602 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2603 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2604 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
2605 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2607 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2608 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
2609 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2610 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2611 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
2612 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2613 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2614 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
2615 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2616 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2617 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
2618 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2619 } // isCodeGenOnly = 1
2621 // Convert float/double to signed/unsigned int 32/64 with truncation
2622 let isCodeGenOnly = 1 in {
2623 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
2624 ssmem, sse_load_f32, "cvttss2si">,
2625 XS, EVEX_CD8<32, CD8VT1>;
2626 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2627 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
2628 "cvttss2si">, XS, VEX_W,
2629 EVEX_CD8<32, CD8VT1>;
2630 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
2631 sdmem, sse_load_f64, "cvttsd2si">, XD,
2632 EVEX_CD8<64, CD8VT1>;
2633 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2634 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
2635 "cvttsd2si">, XD, VEX_W,
2636 EVEX_CD8<64, CD8VT1>;
2637 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2638 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
2639 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
2640 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2641 int_x86_avx512_cvttss2usi64, ssmem,
2642 sse_load_f32, "cvttss2usi">, XS, VEX_W,
2643 EVEX_CD8<32, CD8VT1>;
2644 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2645 int_x86_avx512_cvttsd2usi,
2646 sdmem, sse_load_f64, "cvttsd2usi">, XD,
2647 EVEX_CD8<64, CD8VT1>;
2648 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2649 int_x86_avx512_cvttsd2usi64, sdmem,
2650 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
2651 EVEX_CD8<64, CD8VT1>;
2652 } // isCodeGenOnly = 1
2654 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2655 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
2657 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2658 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2659 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
2660 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2661 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2662 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
2665 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
2666 loadf32, "cvttss2si">, XS,
2667 EVEX_CD8<32, CD8VT1>;
2668 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
2669 loadf32, "cvttss2usi">, XS,
2670 EVEX_CD8<32, CD8VT1>;
2671 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
2672 loadf32, "cvttss2si">, XS, VEX_W,
2673 EVEX_CD8<32, CD8VT1>;
2674 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
2675 loadf32, "cvttss2usi">, XS, VEX_W,
2676 EVEX_CD8<32, CD8VT1>;
2677 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
2678 loadf64, "cvttsd2si">, XD,
2679 EVEX_CD8<64, CD8VT1>;
2680 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
2681 loadf64, "cvttsd2usi">, XD,
2682 EVEX_CD8<64, CD8VT1>;
2683 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
2684 loadf64, "cvttsd2si">, XD, VEX_W,
2685 EVEX_CD8<64, CD8VT1>;
2686 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
2687 loadf64, "cvttsd2usi">, XD, VEX_W,
2688 EVEX_CD8<64, CD8VT1>;
2690 //===----------------------------------------------------------------------===//
2691 // AVX-512 Convert form float to double and back
2692 //===----------------------------------------------------------------------===//
2693 let neverHasSideEffects = 1 in {
2694 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
2695 (ins FR32X:$src1, FR32X:$src2),
2696 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2697 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
2699 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
2700 (ins FR32X:$src1, f32mem:$src2),
2701 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2702 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
2703 EVEX_CD8<32, CD8VT1>;
2705 // Convert scalar double to scalar single
2706 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
2707 (ins FR64X:$src1, FR64X:$src2),
2708 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2709 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
2711 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
2712 (ins FR64X:$src1, f64mem:$src2),
2713 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2714 []>, EVEX_4V, VEX_LIG, VEX_W,
2715 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
2718 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
2719 Requires<[HasAVX512]>;
2720 def : Pat<(fextend (loadf32 addr:$src)),
2721 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
2723 def : Pat<(extloadf32 addr:$src),
2724 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
2725 Requires<[HasAVX512, OptForSize]>;
2727 def : Pat<(extloadf32 addr:$src),
2728 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
2729 Requires<[HasAVX512, OptForSpeed]>;
2731 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
2732 Requires<[HasAVX512]>;
2734 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
2735 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2736 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2738 let neverHasSideEffects = 1 in {
2739 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2740 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2742 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2743 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
2744 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
2745 [], d>, EVEX, EVEX_B;
2747 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2748 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2750 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2751 } // neverHasSideEffects = 1
2754 multiclass avx512_vcvtt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
2755 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2756 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2758 let neverHasSideEffects = 1 in {
2759 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2760 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2762 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2764 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2765 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2767 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2768 } // neverHasSideEffects = 1
2772 defm VCVTPD2PSZ : avx512_vcvt_fp<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
2773 memopv8f64, f512mem, v8f32, v8f64,
2774 SSEPackedSingle>, EVEX_V512, VEX_W, OpSize,
2775 EVEX_CD8<64, CD8VF>;
2777 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
2778 memopv4f64, f256mem, v8f64, v8f32,
2779 SSEPackedDouble>, EVEX_V512, EVEX_CD8<32, CD8VH>;
2780 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2781 (VCVTPS2PDZrm addr:$src)>;
2783 //===----------------------------------------------------------------------===//
2784 // AVX-512 Vector convert from sign integer to float/double
2785 //===----------------------------------------------------------------------===//
2787 defm VCVTDQ2PSZ : avx512_vcvt_fp<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
2788 memopv8i64, i512mem, v16f32, v16i32,
2789 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2791 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
2792 memopv4i64, i256mem, v8f64, v8i32,
2793 SSEPackedDouble>, EVEX_V512, XS,
2794 EVEX_CD8<32, CD8VH>;
2796 defm VCVTTPS2DQZ : avx512_vcvtt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
2797 memopv16f32, f512mem, v16i32, v16f32,
2798 SSEPackedSingle>, EVEX_V512, XS,
2799 EVEX_CD8<32, CD8VF>;
2801 defm VCVTTPD2DQZ : avx512_vcvtt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
2802 memopv8f64, f512mem, v8i32, v8f64,
2803 SSEPackedDouble>, EVEX_V512, OpSize, VEX_W,
2804 EVEX_CD8<64, CD8VF>;
2806 defm VCVTTPS2UDQZ : avx512_vcvtt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
2807 memopv16f32, f512mem, v16i32, v16f32,
2808 SSEPackedSingle>, EVEX_V512,
2809 EVEX_CD8<32, CD8VF>;
2811 // cvttps2udq (src, 0, mask-all-ones, sae-current)
2812 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
2813 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
2814 (VCVTTPS2UDQZrr VR512:$src)>;
2816 defm VCVTTPD2UDQZ : avx512_vcvtt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
2817 memopv8f64, f512mem, v8i32, v8f64,
2818 SSEPackedDouble>, EVEX_V512, VEX_W,
2819 EVEX_CD8<64, CD8VF>;
2821 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
2822 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
2823 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
2824 (VCVTTPD2UDQZrr VR512:$src)>;
2826 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
2827 memopv4i64, f256mem, v8f64, v8i32,
2828 SSEPackedDouble>, EVEX_V512, XS,
2829 EVEX_CD8<32, CD8VH>;
2831 defm VCVTUDQ2PSZ : avx512_vcvt_fp<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
2832 memopv16i32, f512mem, v16f32, v16i32,
2833 SSEPackedSingle>, EVEX_V512, XD,
2834 EVEX_CD8<32, CD8VF>;
2836 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
2837 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
2838 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
2841 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
2842 (v16f32 immAllZerosV), (i16 -1), imm:$rc)),
2843 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
2846 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
2847 RegisterClass DstRC, PatFrag mem_frag,
2848 X86MemOperand x86memop, Domain d> {
2849 let neverHasSideEffects = 1 in {
2850 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2851 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2853 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
2854 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
2855 [], d>, EVEX, EVEX_B;
2857 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2858 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2860 } // neverHasSideEffects = 1
2863 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
2864 memopv16f32, f512mem, SSEPackedSingle>, OpSize,
2865 EVEX_V512, EVEX_CD8<32, CD8VF>;
2866 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
2867 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
2868 EVEX_V512, EVEX_CD8<64, CD8VF>;
2870 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
2871 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
2872 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
2874 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
2875 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
2876 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
2878 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
2879 memopv16f32, f512mem, SSEPackedSingle>,
2880 EVEX_V512, EVEX_CD8<32, CD8VF>;
2881 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
2882 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
2883 EVEX_V512, EVEX_CD8<64, CD8VF>;
2885 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
2886 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
2887 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
2889 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
2890 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
2891 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
2893 let Predicates = [HasAVX512] in {
2894 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
2895 (VCVTPD2PSZrm addr:$src)>;
2896 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2897 (VCVTPS2PDZrm addr:$src)>;
2900 //===----------------------------------------------------------------------===//
2901 // Half precision conversion instructions
2902 //===----------------------------------------------------------------------===//
2903 multiclass avx512_f16c_ph2ps<RegisterClass destRC, RegisterClass srcRC,
2904 X86MemOperand x86memop, Intrinsic Int> {
2905 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
2906 "vcvtph2ps\t{$src, $dst|$dst, $src}",
2907 [(set destRC:$dst, (Int srcRC:$src))]>, EVEX;
2908 let neverHasSideEffects = 1, mayLoad = 1 in
2909 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
2910 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
2913 multiclass avx512_f16c_ps2ph<RegisterClass destRC, RegisterClass srcRC,
2914 X86MemOperand x86memop, Intrinsic Int> {
2915 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
2916 (ins srcRC:$src1, i32i8imm:$src2),
2917 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2918 [(set destRC:$dst, (Int srcRC:$src1, imm:$src2))]>, EVEX;
2919 let neverHasSideEffects = 1, mayStore = 1 in
2920 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
2921 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
2922 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
2925 defm VCVTPH2PSZ : avx512_f16c_ph2ps<VR512, VR256X, f256mem,
2926 int_x86_avx512_vcvtph2ps_512>, EVEX_V512,
2927 EVEX_CD8<32, CD8VH>;
2928 defm VCVTPS2PHZ : avx512_f16c_ps2ph<VR256X, VR512, f256mem,
2929 int_x86_avx512_vcvtps2ph_512>, EVEX_V512,
2930 EVEX_CD8<32, CD8VH>;
2932 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
2933 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
2934 "ucomiss">, TB, EVEX, VEX_LIG,
2935 EVEX_CD8<32, CD8VT1>;
2936 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
2937 "ucomisd">, TB, OpSize, EVEX,
2938 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2939 let Pattern = []<dag> in {
2940 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
2941 "comiss">, TB, EVEX, VEX_LIG,
2942 EVEX_CD8<32, CD8VT1>;
2943 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
2944 "comisd">, TB, OpSize, EVEX,
2945 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2947 let isCodeGenOnly = 1 in {
2948 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
2949 load, "ucomiss">, TB, EVEX, VEX_LIG,
2950 EVEX_CD8<32, CD8VT1>;
2951 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
2952 load, "ucomisd">, TB, OpSize, EVEX,
2953 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2955 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
2956 load, "comiss">, TB, EVEX, VEX_LIG,
2957 EVEX_CD8<32, CD8VT1>;
2958 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
2959 load, "comisd">, TB, OpSize, EVEX,
2960 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2964 /// avx512_unop_p - AVX-512 unops in packed form.
2965 multiclass avx512_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2966 def PSZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2967 !strconcat(OpcodeStr,
2968 "ps\t{$src, $dst|$dst, $src}"),
2969 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))]>,
2971 def PSZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f256mem:$src),
2972 !strconcat(OpcodeStr,
2973 "ps\t{$src, $dst|$dst, $src}"),
2974 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
2975 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2976 def PDZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2977 !strconcat(OpcodeStr,
2978 "pd\t{$src, $dst|$dst, $src}"),
2979 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))]>,
2980 EVEX, EVEX_V512, VEX_W;
2981 def PDZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2982 !strconcat(OpcodeStr,
2983 "pd\t{$src, $dst|$dst, $src}"),
2984 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
2985 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2988 /// avx512_fp_unop_p_int - AVX-512 intrinsics unops in packed forms.
2989 multiclass avx512_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2990 Intrinsic V16F32Int, Intrinsic V8F64Int> {
2991 let isCodeGenOnly = 1 in {
2992 def PSZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2993 !strconcat(OpcodeStr,
2994 "ps\t{$src, $dst|$dst, $src}"),
2995 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
2997 def PSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2998 !strconcat(OpcodeStr,
2999 "ps\t{$src, $dst|$dst, $src}"),
3001 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
3002 EVEX_V512, EVEX_CD8<32, CD8VF>;
3003 def PDZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3004 !strconcat(OpcodeStr,
3005 "pd\t{$src, $dst|$dst, $src}"),
3006 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
3007 EVEX, EVEX_V512, VEX_W;
3008 def PDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3009 !strconcat(OpcodeStr,
3010 "pd\t{$src, $dst|$dst, $src}"),
3012 (V8F64Int (memopv8f64 addr:$src)))]>,
3013 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3014 } // isCodeGenOnly = 1
3017 /// avx512_fp_unop_s - AVX-512 unops in scalar form.
3018 multiclass avx512_fp_unop_s<bits<8> opc, string OpcodeStr> {
3019 let hasSideEffects = 0 in {
3020 def SSZr : AVX5128I<opc, MRMSrcReg, (outs FR32X:$dst),
3021 (ins FR32X:$src1, FR32X:$src2),
3022 !strconcat(OpcodeStr,
3023 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3025 let mayLoad = 1 in {
3026 def SSZm : AVX5128I<opc, MRMSrcMem, (outs FR32X:$dst),
3027 (ins FR32X:$src1, f32mem:$src2),
3028 !strconcat(OpcodeStr,
3029 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3030 []>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3031 let isCodeGenOnly = 1 in
3032 def SSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
3033 (ins VR128X:$src1, ssmem:$src2),
3034 !strconcat(OpcodeStr,
3035 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3036 []>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3038 def SDZr : AVX5128I<opc, MRMSrcReg, (outs FR64X:$dst),
3039 (ins FR64X:$src1, FR64X:$src2),
3040 !strconcat(OpcodeStr,
3041 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3043 let mayLoad = 1 in {
3044 def SDZm : AVX5128I<opc, MRMSrcMem, (outs FR64X:$dst),
3045 (ins FR64X:$src1, f64mem:$src2),
3046 !strconcat(OpcodeStr,
3047 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3048 EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3049 let isCodeGenOnly = 1 in
3050 def SDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
3051 (ins VR128X:$src1, sdmem:$src2),
3052 !strconcat(OpcodeStr,
3053 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3054 []>, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3059 defm VRCP14 : avx512_fp_unop_s<0x4D, "vrcp14">,
3060 avx512_fp_unop_p<0x4C, "vrcp14", X86frcp>,
3061 avx512_fp_unop_p_int<0x4C, "vrcp14",
3062 int_x86_avx512_rcp14_ps_512, int_x86_avx512_rcp14_pd_512>;
3064 defm VRSQRT14 : avx512_fp_unop_s<0x4F, "vrsqrt14">,
3065 avx512_fp_unop_p<0x4E, "vrsqrt14", X86frsqrt>,
3066 avx512_fp_unop_p_int<0x4E, "vrsqrt14",
3067 int_x86_avx512_rsqrt14_ps_512, int_x86_avx512_rsqrt14_pd_512>;
3069 def : Pat<(int_x86_avx512_rsqrt14_ss VR128X:$src),
3070 (COPY_TO_REGCLASS (VRSQRT14SSZr (f32 (IMPLICIT_DEF)),
3071 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3073 def : Pat<(int_x86_avx512_rsqrt14_ss sse_load_f32:$src),
3074 (VRSQRT14SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3076 def : Pat<(int_x86_avx512_rcp14_ss VR128X:$src),
3077 (COPY_TO_REGCLASS (VRCP14SSZr (f32 (IMPLICIT_DEF)),
3078 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3080 def : Pat<(int_x86_avx512_rcp14_ss sse_load_f32:$src),
3081 (VRCP14SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3083 let AddedComplexity = 20, Predicates = [HasERI] in {
3084 defm VRCP28 : avx512_fp_unop_s<0xCB, "vrcp28">,
3085 avx512_fp_unop_p<0xCA, "vrcp28", X86frcp>,
3086 avx512_fp_unop_p_int<0xCA, "vrcp28",
3087 int_x86_avx512_rcp28_ps_512, int_x86_avx512_rcp28_pd_512>;
3089 defm VRSQRT28 : avx512_fp_unop_s<0xCD, "vrsqrt28">,
3090 avx512_fp_unop_p<0xCC, "vrsqrt28", X86frsqrt>,
3091 avx512_fp_unop_p_int<0xCC, "vrsqrt28",
3092 int_x86_avx512_rsqrt28_ps_512, int_x86_avx512_rsqrt28_pd_512>;
3095 let Predicates = [HasERI] in {
3096 def : Pat<(int_x86_avx512_rsqrt28_ss VR128X:$src),
3097 (COPY_TO_REGCLASS (VRSQRT28SSZr (f32 (IMPLICIT_DEF)),
3098 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3100 def : Pat<(int_x86_avx512_rsqrt28_ss sse_load_f32:$src),
3101 (VRSQRT28SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3103 def : Pat<(int_x86_avx512_rcp28_ss VR128X:$src),
3104 (COPY_TO_REGCLASS (VRCP28SSZr (f32 (IMPLICIT_DEF)),
3105 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3107 def : Pat<(int_x86_avx512_rcp28_ss sse_load_f32:$src),
3108 (VRCP28SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3110 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3111 Intrinsic V16F32Int, Intrinsic V8F64Int,
3112 OpndItins itins_s, OpndItins itins_d> {
3113 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3114 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3115 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
3119 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3120 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3122 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
3123 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
3125 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3126 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3127 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
3131 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3132 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3133 [(set VR512:$dst, (OpNode
3134 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
3135 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
3137 let isCodeGenOnly = 1 in {
3138 def PSZr_Int : AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3139 !strconcat(OpcodeStr,
3140 "ps\t{$src, $dst|$dst, $src}"),
3141 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
3143 def PSZm_Int : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3144 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3146 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
3147 EVEX_V512, EVEX_CD8<32, CD8VF>;
3148 def PDZr_Int : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3149 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3150 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
3151 EVEX, EVEX_V512, VEX_W;
3152 def PDZm_Int : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3153 !strconcat(OpcodeStr,
3154 "pd\t{$src, $dst|$dst, $src}"),
3155 [(set VR512:$dst, (V8F64Int (memopv8f64 addr:$src)))]>,
3156 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3157 } // isCodeGenOnly = 1
3160 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
3161 Intrinsic F32Int, Intrinsic F64Int,
3162 OpndItins itins_s, OpndItins itins_d> {
3163 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
3164 (ins FR32X:$src1, FR32X:$src2),
3165 !strconcat(OpcodeStr,
3166 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3167 [], itins_s.rr>, XS, EVEX_4V;
3168 let isCodeGenOnly = 1 in
3169 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3170 (ins VR128X:$src1, VR128X:$src2),
3171 !strconcat(OpcodeStr,
3172 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3174 (F32Int VR128X:$src1, VR128X:$src2))],
3175 itins_s.rr>, XS, EVEX_4V;
3176 let mayLoad = 1 in {
3177 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
3178 (ins FR32X:$src1, f32mem:$src2),
3179 !strconcat(OpcodeStr,
3180 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3181 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3182 let isCodeGenOnly = 1 in
3183 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3184 (ins VR128X:$src1, ssmem:$src2),
3185 !strconcat(OpcodeStr,
3186 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3188 (F32Int VR128X:$src1, sse_load_f32:$src2))],
3189 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3191 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
3192 (ins FR64X:$src1, FR64X:$src2),
3193 !strconcat(OpcodeStr,
3194 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3196 let isCodeGenOnly = 1 in
3197 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3198 (ins VR128X:$src1, VR128X:$src2),
3199 !strconcat(OpcodeStr,
3200 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3202 (F64Int VR128X:$src1, VR128X:$src2))],
3203 itins_s.rr>, XD, EVEX_4V, VEX_W;
3204 let mayLoad = 1 in {
3205 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
3206 (ins FR64X:$src1, f64mem:$src2),
3207 !strconcat(OpcodeStr,
3208 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3209 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3210 let isCodeGenOnly = 1 in
3211 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3212 (ins VR128X:$src1, sdmem:$src2),
3213 !strconcat(OpcodeStr,
3214 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3216 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
3217 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3222 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
3223 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
3224 SSE_SQRTSS, SSE_SQRTSD>,
3225 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
3226 int_x86_avx512_sqrt_ps_512, int_x86_avx512_sqrt_pd_512,
3227 SSE_SQRTPS, SSE_SQRTPD>;
3229 let Predicates = [HasAVX512] in {
3230 def : Pat<(f32 (fsqrt FR32X:$src)),
3231 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3232 def : Pat<(f32 (fsqrt (load addr:$src))),
3233 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3234 Requires<[OptForSize]>;
3235 def : Pat<(f64 (fsqrt FR64X:$src)),
3236 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
3237 def : Pat<(f64 (fsqrt (load addr:$src))),
3238 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
3239 Requires<[OptForSize]>;
3241 def : Pat<(f32 (X86frsqrt FR32X:$src)),
3242 (VRSQRT14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3243 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3244 (VRSQRT14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3245 Requires<[OptForSize]>;
3247 def : Pat<(f32 (X86frcp FR32X:$src)),
3248 (VRCP14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3249 def : Pat<(f32 (X86frcp (load addr:$src))),
3250 (VRCP14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3251 Requires<[OptForSize]>;
3253 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
3254 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
3255 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3257 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3258 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3260 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
3261 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
3262 (COPY_TO_REGCLASS VR128X:$src, FR64)),
3264 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3265 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3269 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
3270 X86MemOperand x86memop, RegisterClass RC,
3271 PatFrag mem_frag32, PatFrag mem_frag64,
3272 Intrinsic V4F32Int, Intrinsic V2F64Int,
3274 let ExeDomain = SSEPackedSingle in {
3275 // Intrinsic operation, reg.
3276 // Vector intrinsic operation, reg
3277 def PSr : AVX512AIi8<opcps, MRMSrcReg,
3278 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3279 !strconcat(OpcodeStr,
3280 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3281 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
3283 // Vector intrinsic operation, mem
3284 def PSm : AVX512AIi8<opcps, MRMSrcMem,
3285 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3286 !strconcat(OpcodeStr,
3287 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3289 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
3290 EVEX_CD8<32, VForm>;
3291 } // ExeDomain = SSEPackedSingle
3293 let ExeDomain = SSEPackedDouble in {
3294 // Vector intrinsic operation, reg
3295 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
3296 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3297 !strconcat(OpcodeStr,
3298 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3299 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
3301 // Vector intrinsic operation, mem
3302 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
3303 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3304 !strconcat(OpcodeStr,
3305 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3307 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
3308 EVEX_CD8<64, VForm>;
3309 } // ExeDomain = SSEPackedDouble
3312 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3316 let ExeDomain = GenericDomain in {
3318 let hasSideEffects = 0 in
3319 def SSr : AVX512AIi8<opcss, MRMSrcReg,
3320 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
3321 !strconcat(OpcodeStr,
3322 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3325 // Intrinsic operation, reg.
3326 let isCodeGenOnly = 1 in
3327 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
3328 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3329 !strconcat(OpcodeStr,
3330 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3331 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
3333 // Intrinsic operation, mem.
3334 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
3335 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
3336 !strconcat(OpcodeStr,
3337 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3338 [(set VR128X:$dst, (F32Int VR128X:$src1,
3339 sse_load_f32:$src2, imm:$src3))]>,
3340 EVEX_CD8<32, CD8VT1>;
3343 let hasSideEffects = 0 in
3344 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
3345 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
3346 !strconcat(OpcodeStr,
3347 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3350 // Intrinsic operation, reg.
3351 let isCodeGenOnly = 1 in
3352 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
3353 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3354 !strconcat(OpcodeStr,
3355 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3356 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
3359 // Intrinsic operation, mem.
3360 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
3361 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
3362 !strconcat(OpcodeStr,
3363 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3365 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
3366 VEX_W, EVEX_CD8<64, CD8VT1>;
3367 } // ExeDomain = GenericDomain
3370 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
3371 X86MemOperand x86memop, RegisterClass RC,
3372 PatFrag mem_frag, Domain d> {
3373 let ExeDomain = d in {
3374 // Intrinsic operation, reg.
3375 // Vector intrinsic operation, reg
3376 def r : AVX512AIi8<opc, MRMSrcReg,
3377 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3378 !strconcat(OpcodeStr,
3379 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3382 // Vector intrinsic operation, mem
3383 def m : AVX512AIi8<opc, MRMSrcMem,
3384 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3385 !strconcat(OpcodeStr,
3386 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3392 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
3393 memopv16f32, SSEPackedSingle>, EVEX_V512,
3394 EVEX_CD8<32, CD8VF>;
3396 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
3397 imm:$src2, (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1),
3399 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
3402 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
3403 memopv8f64, SSEPackedDouble>, EVEX_V512,
3404 VEX_W, EVEX_CD8<64, CD8VF>;
3406 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
3407 imm:$src2, (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1),
3409 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
3411 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
3412 Operand x86memop, RegisterClass RC, Domain d> {
3413 let ExeDomain = d in {
3414 def r : AVX512AIi8<opc, MRMSrcReg,
3415 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
3416 !strconcat(OpcodeStr,
3417 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3420 def m : AVX512AIi8<opc, MRMSrcMem,
3421 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
3422 !strconcat(OpcodeStr,
3423 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3428 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
3429 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
3431 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
3432 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
3434 def : Pat<(ffloor FR32X:$src),
3435 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
3436 def : Pat<(f64 (ffloor FR64X:$src)),
3437 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
3438 def : Pat<(f32 (fnearbyint FR32X:$src)),
3439 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
3440 def : Pat<(f64 (fnearbyint FR64X:$src)),
3441 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
3442 def : Pat<(f32 (fceil FR32X:$src)),
3443 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
3444 def : Pat<(f64 (fceil FR64X:$src)),
3445 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
3446 def : Pat<(f32 (frint FR32X:$src)),
3447 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
3448 def : Pat<(f64 (frint FR64X:$src)),
3449 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
3450 def : Pat<(f32 (ftrunc FR32X:$src)),
3451 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
3452 def : Pat<(f64 (ftrunc FR64X:$src)),
3453 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
3455 def : Pat<(v16f32 (ffloor VR512:$src)),
3456 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
3457 def : Pat<(v16f32 (fnearbyint VR512:$src)),
3458 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
3459 def : Pat<(v16f32 (fceil VR512:$src)),
3460 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
3461 def : Pat<(v16f32 (frint VR512:$src)),
3462 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
3463 def : Pat<(v16f32 (ftrunc VR512:$src)),
3464 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
3466 def : Pat<(v8f64 (ffloor VR512:$src)),
3467 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
3468 def : Pat<(v8f64 (fnearbyint VR512:$src)),
3469 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
3470 def : Pat<(v8f64 (fceil VR512:$src)),
3471 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
3472 def : Pat<(v8f64 (frint VR512:$src)),
3473 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
3474 def : Pat<(v8f64 (ftrunc VR512:$src)),
3475 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
3477 //-------------------------------------------------
3478 // Integer truncate and extend operations
3479 //-------------------------------------------------
3481 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
3482 RegisterClass dstRC, RegisterClass srcRC,
3483 RegisterClass KRC, X86MemOperand x86memop> {
3484 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3486 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
3489 def krr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3490 (ins KRC:$mask, srcRC:$src),
3491 !strconcat(OpcodeStr,
3492 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3495 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
3496 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3499 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
3500 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3501 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
3502 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3503 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
3504 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3505 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
3506 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3507 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
3508 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3509 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
3510 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3511 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
3512 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3513 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
3514 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3515 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
3516 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3517 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
3518 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3519 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
3520 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3521 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
3522 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3523 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
3524 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3525 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
3526 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3527 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
3528 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3530 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
3531 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
3532 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
3533 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
3534 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
3536 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3537 (VPMOVDBkrr VK16WM:$mask, VR512:$src)>;
3538 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3539 (VPMOVDWkrr VK16WM:$mask, VR512:$src)>;
3540 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3541 (VPMOVQWkrr VK8WM:$mask, VR512:$src)>;
3542 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3543 (VPMOVQDkrr VK8WM:$mask, VR512:$src)>;
3546 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass DstRC,
3547 RegisterClass SrcRC, SDNode OpNode, PatFrag mem_frag,
3548 X86MemOperand x86memop, ValueType OpVT, ValueType InVT> {
3550 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
3552 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3553 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
3554 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
3555 (ins x86memop:$src),
3556 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
3558 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
3562 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VR512, VR128X, X86vzext,
3563 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3565 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VR512, VR128X, X86vzext,
3566 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3568 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VR512, VR256X, X86vzext,
3569 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3570 EVEX_CD8<16, CD8VH>;
3571 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VR512, VR128X, X86vzext,
3572 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3573 EVEX_CD8<16, CD8VQ>;
3574 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VR512, VR256X, X86vzext,
3575 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3576 EVEX_CD8<32, CD8VH>;
3578 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VR512, VR128X, X86vsext,
3579 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3581 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VR512, VR128X, X86vsext,
3582 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3584 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VR512, VR256X, X86vsext,
3585 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3586 EVEX_CD8<16, CD8VH>;
3587 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VR512, VR128X, X86vsext,
3588 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3589 EVEX_CD8<16, CD8VQ>;
3590 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VR512, VR256X, X86vsext,
3591 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3592 EVEX_CD8<32, CD8VH>;
3594 //===----------------------------------------------------------------------===//
3595 // GATHER - SCATTER Operations
3597 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3598 RegisterClass RC, X86MemOperand memop> {
3600 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
3601 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
3602 (ins RC:$src1, KRC:$mask, memop:$src2),
3603 !strconcat(OpcodeStr,
3604 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3607 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
3608 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3609 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
3610 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3612 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
3613 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3614 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
3615 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3617 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
3618 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3619 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
3620 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3622 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
3623 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3624 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
3625 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3627 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3628 RegisterClass RC, X86MemOperand memop> {
3629 let mayStore = 1, Constraints = "$mask = $mask_wb" in
3630 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
3631 (ins memop:$dst, KRC:$mask, RC:$src2),
3632 !strconcat(OpcodeStr,
3633 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3637 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
3638 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3639 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
3640 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3642 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
3643 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3644 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
3645 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3647 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
3648 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3649 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
3650 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3652 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
3653 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3654 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
3655 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3657 //===----------------------------------------------------------------------===//
3658 // VSHUFPS - VSHUFPD Operations
3660 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
3661 ValueType vt, string OpcodeStr, PatFrag mem_frag,
3663 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
3664 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3665 !strconcat(OpcodeStr,
3666 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3667 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
3668 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3669 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
3670 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
3671 (ins RC:$src1, RC:$src2, i8imm:$src3),
3672 !strconcat(OpcodeStr,
3673 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3674 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
3675 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3676 EVEX_4V, Sched<[WriteShuffle]>;
3679 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
3680 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3681 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
3682 SSEPackedDouble>, OpSize, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3684 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3685 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3686 def : Pat<(v16i32 (X86Shufp VR512:$src1,
3687 (memopv16i32 addr:$src2), (i8 imm:$imm))),
3688 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3690 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3691 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3692 def : Pat<(v8i64 (X86Shufp VR512:$src1,
3693 (memopv8i64 addr:$src2), (i8 imm:$imm))),
3694 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3696 multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
3697 X86MemOperand x86memop> {
3698 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
3699 (ins RC:$src1, RC:$src2, i8imm:$src3),
3700 !strconcat(OpcodeStr,
3701 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3704 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
3705 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3706 !strconcat(OpcodeStr,
3707 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3710 defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
3711 EVEX_V512, EVEX_CD8<32, CD8VF>;
3712 defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
3713 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3715 def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3716 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3717 def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3718 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3719 def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3720 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3721 def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3722 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3724 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, RegisterClass RC,
3725 X86MemOperand x86memop> {
3726 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3727 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3729 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
3730 (ins x86memop:$src),
3731 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3735 defm VPABSD : avx512_vpabs<0x1E, "vpabsd", VR512, i512mem>, EVEX_V512,
3736 EVEX_CD8<32, CD8VF>;
3737 defm VPABSQ : avx512_vpabs<0x1F, "vpabsq", VR512, i512mem>, EVEX_V512, VEX_W,
3738 EVEX_CD8<64, CD8VF>;
3740 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
3741 RegisterClass RC, RegisterClass KRC,
3742 X86MemOperand x86memop,
3743 X86MemOperand x86scalar_mop, string BrdcstStr> {
3744 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3746 !strconcat(OpcodeStr, "\t{$src, ${dst} |${dst}, $src}"),
3748 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3749 (ins x86memop:$src),
3750 !strconcat(OpcodeStr, "\t{$src, ${dst}|${dst}, $src}"),
3752 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3753 (ins x86scalar_mop:$src),
3754 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
3755 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
3757 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3758 (ins KRC:$mask, RC:$src),
3759 !strconcat(OpcodeStr,
3760 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3762 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3763 (ins KRC:$mask, x86memop:$src),
3764 !strconcat(OpcodeStr,
3765 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3767 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3768 (ins KRC:$mask, x86scalar_mop:$src),
3769 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
3770 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
3772 []>, EVEX, EVEX_KZ, EVEX_B;
3774 let Constraints = "$src1 = $dst" in {
3775 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3776 (ins RC:$src1, KRC:$mask, RC:$src2),
3777 !strconcat(OpcodeStr,
3778 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3780 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3781 (ins RC:$src1, KRC:$mask, x86memop:$src2),
3782 !strconcat(OpcodeStr,
3783 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3785 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3786 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
3787 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
3788 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
3789 []>, EVEX, EVEX_K, EVEX_B;
3793 let Predicates = [HasCDI] in {
3794 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
3795 i512mem, i32mem, "{1to16}">,
3796 EVEX_V512, EVEX_CD8<32, CD8VF>;
3799 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
3800 i512mem, i64mem, "{1to8}">,
3801 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3805 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
3807 (VPCONFLICTDrrk VR512:$src1,
3808 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
3810 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
3812 (VPCONFLICTQrrk VR512:$src1,
3813 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;