1 // Group template arguments that can be derived from the vector type (EltNum x
2 // EltVT). These are things like the register class for the writemask, etc.
3 // The idea is to pass one of these as the template argument rather than the
4 // individual arguments.
5 // The template is also used for scalar types, in this case numelts is 1.
6 class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,
9 ValueType EltVT = eltvt;
10 int NumElts = numelts;
12 // Corresponding mask register class.
13 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
15 // Corresponding write-mask register class.
16 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
18 // The GPR register class that can hold the write mask. Use GR8 for fewer
19 // than 8 elements. Use shift-right and equal to work around the lack of
22 !cast<RegisterClass>("GR" #
23 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
25 // Suffix used in the instruction mnemonic.
26 string Suffix = suffix;
28 // VTName is a string name for vector VT. For vector types it will be
29 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
30 // It is a little bit complex for scalar types, where NumElts = 1.
31 // In this case we build v4f32 or v2f64
32 string VTName = "v" # !if (!eq (NumElts, 1),
33 !if (!eq (EltVT.Size, 32), 4,
34 !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT;
37 ValueType VT = !cast<ValueType>(VTName);
39 string EltTypeName = !cast<string>(EltVT);
40 // Size of the element type in bits, e.g. 32 for v16i32.
41 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
42 int EltSize = EltVT.Size;
44 // "i" for integer types and "f" for floating-point types
45 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
47 // Size of RC in bits, e.g. 512 for VR512.
50 // The corresponding memory operand, e.g. i512mem for VR512.
51 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
52 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
55 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
56 // due to load promotion during legalization
57 PatFrag LdFrag = !cast<PatFrag>("load" #
58 !if (!eq (TypeVariantName, "i"),
59 !if (!eq (Size, 128), "v2i64",
60 !if (!eq (Size, 256), "v4i64",
62 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
64 // Load patterns used for memory operands. We only have this defined in
65 // case of i64 element types for sub-512 integer vectors. For now, keep
66 // MemOpFrag undefined in these cases.
68 !if (!eq (NumElts#EltTypeName, "1f32"), !cast<PatFrag>("memopfsf32"),
69 !if (!eq (NumElts#EltTypeName, "1f64"), !cast<PatFrag>("memopfsf64"),
70 !if (!eq (TypeVariantName, "f"), !cast<PatFrag>("memop" # VTName),
71 !if (!eq (EltTypeName, "i64"), !cast<PatFrag>("memop" # VTName),
72 !if (!eq (VTName, "v16i32"), !cast<PatFrag>("memop" # VTName), ?)))));
74 // The corresponding float type, e.g. v16f32 for v16i32
75 // Note: For EltSize < 32, FloatVT is illegal and TableGen
76 // fails to compile, so we choose FloatVT = VT
77 ValueType FloatVT = !cast<ValueType>(
78 !if (!eq (!srl(EltSize,5),0),
80 !if (!eq(TypeVariantName, "i"),
81 "v" # NumElts # "f" # EltSize,
84 // The string to specify embedded broadcast in assembly.
85 string BroadcastStr = "{1to" # NumElts # "}";
87 // 8-bit compressed displacement tuple/subvector format. This is only
88 // defined for NumElts <= 8.
89 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
90 !cast<CD8VForm>("CD8VT" # NumElts), ?);
92 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
93 !if (!eq (Size, 256), sub_ymm, ?));
95 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
96 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
99 // A vector type of the same width with element type i32. This is used to
100 // create the canonical constant zero node ImmAllZerosV.
101 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
102 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
105 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
106 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
107 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
108 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
109 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
110 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
112 // "x" in v32i8x_info means RC = VR256X
113 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
114 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
115 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
116 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
117 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
118 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
120 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
121 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
122 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
123 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
124 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
125 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
127 // We map scalar types to the smallest (128-bit) vector type
128 // with the appropriate element type. This allows to use the same masking logic.
129 def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;
130 def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;
132 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
133 X86VectorVTInfo i128> {
134 X86VectorVTInfo info512 = i512;
135 X86VectorVTInfo info256 = i256;
136 X86VectorVTInfo info128 = i128;
139 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
141 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
143 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
145 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
147 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
149 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
152 // This multiclass generates the masking variants from the non-masking
153 // variant. It only provides the assembly pieces for the masking variants.
154 // It assumes custom ISel patterns for masking which can be provided as
155 // template arguments.
156 multiclass AVX512_maskable_custom<bits<8> O, Format F,
158 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
160 string AttSrcAsm, string IntelSrcAsm,
162 list<dag> MaskingPattern,
163 list<dag> ZeroMaskingPattern,
165 string MaskingConstraint = "",
166 InstrItinClass itin = NoItinerary,
167 bit IsCommutable = 0> {
168 let isCommutable = IsCommutable in
169 def NAME: AVX512<O, F, Outs, Ins,
170 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
171 "$dst "#Round#", "#IntelSrcAsm#"}",
174 // Prefer over VMOV*rrk Pat<>
175 let AddedComplexity = 20 in
176 def NAME#k: AVX512<O, F, Outs, MaskingIns,
177 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}"#Round#"|"#
178 "$dst {${mask}}"#Round#", "#IntelSrcAsm#"}",
179 MaskingPattern, itin>,
181 // In case of the 3src subclass this is overridden with a let.
182 string Constraints = MaskingConstraint;
184 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
185 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
186 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}"#Round#"|"#
187 "$dst {${mask}} {z}"#Round#", "#IntelSrcAsm#"}",
194 // Common base class of AVX512_maskable and AVX512_maskable_3src.
195 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
197 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
199 string AttSrcAsm, string IntelSrcAsm,
200 dag RHS, dag MaskingRHS,
201 SDNode Select = vselect, string Round = "",
202 string MaskingConstraint = "",
203 InstrItinClass itin = NoItinerary,
204 bit IsCommutable = 0> :
205 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
206 AttSrcAsm, IntelSrcAsm,
207 [(set _.RC:$dst, RHS)],
208 [(set _.RC:$dst, MaskingRHS)],
210 (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
211 Round, MaskingConstraint, NoItinerary, IsCommutable>;
213 // This multiclass generates the unconditional/non-masking, the masking and
214 // the zero-masking variant of the vector instruction. In the masking case, the
215 // perserved vector elements come from a new dummy input operand tied to $dst.
216 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
217 dag Outs, dag Ins, string OpcodeStr,
218 string AttSrcAsm, string IntelSrcAsm,
219 dag RHS, string Round = "",
220 InstrItinClass itin = NoItinerary,
221 bit IsCommutable = 0> :
222 AVX512_maskable_common<O, F, _, Outs, Ins,
223 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
224 !con((ins _.KRCWM:$mask), Ins),
225 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
226 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect,
227 Round, "$src0 = $dst", itin, IsCommutable>;
229 // This multiclass generates the unconditional/non-masking, the masking and
230 // the zero-masking variant of the scalar instruction.
231 multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
232 dag Outs, dag Ins, string OpcodeStr,
233 string AttSrcAsm, string IntelSrcAsm,
234 dag RHS, string Round = "",
235 InstrItinClass itin = NoItinerary,
236 bit IsCommutable = 0> :
237 AVX512_maskable_common<O, F, _, Outs, Ins,
238 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
239 !con((ins _.KRCWM:$mask), Ins),
240 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
241 (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select,
242 Round, "$src0 = $dst", itin, IsCommutable>;
244 // Similar to AVX512_maskable but in this case one of the source operands
245 // ($src1) is already tied to $dst so we just use that for the preserved
246 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
248 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
249 dag Outs, dag NonTiedIns, string OpcodeStr,
250 string AttSrcAsm, string IntelSrcAsm,
252 AVX512_maskable_common<O, F, _, Outs,
253 !con((ins _.RC:$src1), NonTiedIns),
254 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
255 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
256 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
257 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
260 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
263 string AttSrcAsm, string IntelSrcAsm,
265 AVX512_maskable_custom<O, F, Outs, Ins,
266 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
267 !con((ins _.KRCWM:$mask), Ins),
268 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [], "",
271 // Bitcasts between 512-bit vector types. Return the original type since
272 // no instruction is needed for the conversion
273 let Predicates = [HasAVX512] in {
274 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
275 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
276 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
277 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
278 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
279 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
280 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
281 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
282 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
283 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
284 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
285 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
286 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
287 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
288 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
289 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
290 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
291 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
292 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
293 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
294 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
295 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
296 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
297 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
298 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
299 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
300 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
301 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
302 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
303 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
304 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
306 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
307 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
308 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
309 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
310 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
311 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
312 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
313 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
314 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
315 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
316 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
317 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
318 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
319 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
320 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
321 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
322 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
323 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
324 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
325 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
326 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
327 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
328 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
329 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
330 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
331 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
332 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
333 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
334 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
335 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
337 // Bitcasts between 256-bit vector types. Return the original type since
338 // no instruction is needed for the conversion
339 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
340 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
341 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
342 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
343 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
344 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
345 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
346 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
347 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
348 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
349 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
350 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
351 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
352 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
353 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
354 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
355 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
356 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
357 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
358 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
359 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
360 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
361 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
362 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
363 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
364 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
365 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
366 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
367 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
368 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
372 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
375 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
376 isPseudo = 1, Predicates = [HasAVX512] in {
377 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
378 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
381 let Predicates = [HasAVX512] in {
382 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
383 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
384 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
387 //===----------------------------------------------------------------------===//
388 // AVX-512 - VECTOR INSERT
391 multiclass vinsert_for_size_no_alt<int Opcode,
392 X86VectorVTInfo From, X86VectorVTInfo To,
393 PatFrag vinsert_insert,
394 SDNodeXForm INSERT_get_vinsert_imm> {
395 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
396 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
397 (ins VR512:$src1, From.RC:$src2, u8imm:$src3),
398 "vinsert" # From.EltTypeName # "x" # From.NumElts #
399 "\t{$src3, $src2, $src1, $dst|"
400 "$dst, $src1, $src2, $src3}",
401 [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
402 (From.VT From.RC:$src2),
407 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
408 (ins VR512:$src1, From.MemOp:$src2, u8imm:$src3),
409 "vinsert" # From.EltTypeName # "x" # From.NumElts #
410 "\t{$src3, $src2, $src1, $dst|"
411 "$dst, $src1, $src2, $src3}",
413 EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, From.CD8TupleForm>;
417 multiclass vinsert_for_size<int Opcode,
418 X86VectorVTInfo From, X86VectorVTInfo To,
419 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
420 PatFrag vinsert_insert,
421 SDNodeXForm INSERT_get_vinsert_imm> :
422 vinsert_for_size_no_alt<Opcode, From, To,
423 vinsert_insert, INSERT_get_vinsert_imm> {
424 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
425 // vinserti32x4. Only add this if 64x2 and friends are not supported
426 // natively via AVX512DQ.
427 let Predicates = [NoDQI] in
428 def : Pat<(vinsert_insert:$ins
429 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
430 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
431 VR512:$src1, From.RC:$src2,
432 (INSERT_get_vinsert_imm VR512:$ins)))>;
435 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
436 ValueType EltVT64, int Opcode256> {
437 defm NAME # "32x4" : vinsert_for_size<Opcode128,
438 X86VectorVTInfo< 4, EltVT32, VR128X>,
439 X86VectorVTInfo<16, EltVT32, VR512>,
440 X86VectorVTInfo< 2, EltVT64, VR128X>,
441 X86VectorVTInfo< 8, EltVT64, VR512>,
443 INSERT_get_vinsert128_imm>;
444 let Predicates = [HasDQI] in
445 defm NAME # "64x2" : vinsert_for_size_no_alt<Opcode128,
446 X86VectorVTInfo< 2, EltVT64, VR128X>,
447 X86VectorVTInfo< 8, EltVT64, VR512>,
449 INSERT_get_vinsert128_imm>, VEX_W;
450 defm NAME # "64x4" : vinsert_for_size<Opcode256,
451 X86VectorVTInfo< 4, EltVT64, VR256X>,
452 X86VectorVTInfo< 8, EltVT64, VR512>,
453 X86VectorVTInfo< 8, EltVT32, VR256>,
454 X86VectorVTInfo<16, EltVT32, VR512>,
456 INSERT_get_vinsert256_imm>, VEX_W;
457 let Predicates = [HasDQI] in
458 defm NAME # "32x8" : vinsert_for_size_no_alt<Opcode256,
459 X86VectorVTInfo< 8, EltVT32, VR256X>,
460 X86VectorVTInfo<16, EltVT32, VR512>,
462 INSERT_get_vinsert256_imm>;
465 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
466 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
468 // vinsertps - insert f32 to XMM
469 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
470 (ins VR128X:$src1, VR128X:$src2, u8imm:$src3),
471 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
472 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
474 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
475 (ins VR128X:$src1, f32mem:$src2, u8imm:$src3),
476 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
477 [(set VR128X:$dst, (X86insertps VR128X:$src1,
478 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
479 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
481 //===----------------------------------------------------------------------===//
482 // AVX-512 VECTOR EXTRACT
485 multiclass vextract_for_size<int Opcode,
486 X86VectorVTInfo From, X86VectorVTInfo To,
487 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
488 PatFrag vextract_extract,
489 SDNodeXForm EXTRACT_get_vextract_imm> {
490 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
491 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
492 (ins VR512:$src1, u8imm:$idx),
493 "vextract" # To.EltTypeName # "x4",
494 "$idx, $src1", "$src1, $idx",
495 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
497 AVX512AIi8Base, EVEX, EVEX_V512;
499 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
500 (ins To.MemOp:$dst, VR512:$src1, u8imm:$src2),
501 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
502 "$dst, $src1, $src2}",
503 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
506 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
508 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
509 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
511 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
513 // A 128/256-bit subvector extract from the first 512-bit vector position is
514 // a subregister copy that needs no instruction.
515 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
517 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
519 // And for the alternative types.
520 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
522 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
524 // Intrinsic call with masking.
525 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
527 VR512:$src1, (iPTR imm:$idx), To.RC:$src0, GR8:$mask),
528 (!cast<Instruction>(NAME # To.EltSize # "x4rrk") To.RC:$src0,
529 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
530 VR512:$src1, imm:$idx)>;
532 // Intrinsic call with zero-masking.
533 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
535 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, GR8:$mask),
536 (!cast<Instruction>(NAME # To.EltSize # "x4rrkz")
537 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
538 VR512:$src1, imm:$idx)>;
540 // Intrinsic call without masking.
541 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
543 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
544 (!cast<Instruction>(NAME # To.EltSize # "x4rr")
545 VR512:$src1, imm:$idx)>;
548 multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
549 ValueType EltVT64, int Opcode64> {
550 defm NAME # "32x4" : vextract_for_size<Opcode32,
551 X86VectorVTInfo<16, EltVT32, VR512>,
552 X86VectorVTInfo< 4, EltVT32, VR128X>,
553 X86VectorVTInfo< 8, EltVT64, VR512>,
554 X86VectorVTInfo< 2, EltVT64, VR128X>,
556 EXTRACT_get_vextract128_imm>;
557 defm NAME # "64x4" : vextract_for_size<Opcode64,
558 X86VectorVTInfo< 8, EltVT64, VR512>,
559 X86VectorVTInfo< 4, EltVT64, VR256X>,
560 X86VectorVTInfo<16, EltVT32, VR512>,
561 X86VectorVTInfo< 8, EltVT32, VR256>,
563 EXTRACT_get_vextract256_imm>, VEX_W;
566 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
567 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
569 // A 128-bit subvector insert to the first 512-bit vector position
570 // is a subregister copy that needs no instruction.
571 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
572 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
573 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
575 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
576 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
577 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
579 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
580 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
581 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
583 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
584 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
585 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
588 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
589 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
590 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
591 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
592 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
593 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
594 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
595 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
597 // vextractps - extract 32 bits from XMM
598 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
599 (ins VR128X:$src1, u8imm:$src2),
600 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
601 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
604 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
605 (ins f32mem:$dst, VR128X:$src1, u8imm:$src2),
606 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
607 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
608 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
610 //===---------------------------------------------------------------------===//
613 multiclass avx512_fp_broadcast<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
614 ValueType svt, X86VectorVTInfo _> {
615 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
616 (ins SrcRC:$src), "vbroadcast"## !subst("p", "s", _.Suffix),
617 "$src", "$src", (_.VT (OpNode (svt SrcRC:$src)))>,
621 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
622 (ins _.ScalarMemOp:$src),
623 "vbroadcast"##!subst("p", "s", _.Suffix), "$src", "$src",
624 (_.VT (OpNode (_.ScalarLdFrag addr:$src)))>,
629 multiclass avx512_fp_broadcast_vl<bits<8> opc, SDNode OpNode,
630 AVX512VLVectorVTInfo _> {
631 defm Z : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info512>,
634 let Predicates = [HasVLX] in {
635 defm Z256 : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info256>,
640 let ExeDomain = SSEPackedSingle in {
641 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, X86VBroadcast,
642 avx512vl_f32_info>, EVEX_CD8<32, CD8VT1>;
643 let Predicates = [HasVLX] in {
644 defm VBROADCASTSSZ128 : avx512_fp_broadcast<0x18, X86VBroadcast, VR128X,
645 v4f32, v4f32x_info>, EVEX_V128,
646 EVEX_CD8<32, CD8VT1>;
650 let ExeDomain = SSEPackedDouble in {
651 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, X86VBroadcast,
652 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VT1>;
655 // avx512_broadcast_pat introduces patterns for broadcast with a scalar argument.
656 // Later, we can canonize broadcast instructions before ISel phase and
657 // eliminate additional patterns on ISel.
658 // SrcRC_v and SrcRC_s are RegisterClasses for vector and scalar
659 // representations of source
660 multiclass avx512_broadcast_pat<string InstName, SDNode OpNode,
661 X86VectorVTInfo _, RegisterClass SrcRC_v,
662 RegisterClass SrcRC_s> {
663 def : Pat<(_.VT (OpNode (_.EltVT SrcRC_s:$src))),
664 (!cast<Instruction>(InstName##"r")
665 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
667 let AddedComplexity = 30 in {
668 def : Pat<(_.VT (vselect _.KRCWM:$mask,
669 (OpNode (_.EltVT SrcRC_s:$src)), _.RC:$src0)),
670 (!cast<Instruction>(InstName##"rk") _.RC:$src0, _.KRCWM:$mask,
671 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
673 def : Pat<(_.VT(vselect _.KRCWM:$mask,
674 (OpNode (_.EltVT SrcRC_s:$src)), _.ImmAllZerosV)),
675 (!cast<Instruction>(InstName##"rkz") _.KRCWM:$mask,
676 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
680 defm : avx512_broadcast_pat<"VBROADCASTSSZ", X86VBroadcast, v16f32_info,
682 defm : avx512_broadcast_pat<"VBROADCASTSDZ", X86VBroadcast, v8f64_info,
685 let Predicates = [HasVLX] in {
686 defm : avx512_broadcast_pat<"VBROADCASTSSZ256", X86VBroadcast,
687 v8f32x_info, VR128X, FR32X>;
688 defm : avx512_broadcast_pat<"VBROADCASTSSZ128", X86VBroadcast,
689 v4f32x_info, VR128X, FR32X>;
690 defm : avx512_broadcast_pat<"VBROADCASTSDZ256", X86VBroadcast,
691 v4f64x_info, VR128X, FR64X>;
694 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
695 (VBROADCASTSSZm addr:$src)>;
696 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
697 (VBROADCASTSDZm addr:$src)>;
699 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
700 (VBROADCASTSSZm addr:$src)>;
701 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
702 (VBROADCASTSDZm addr:$src)>;
704 multiclass avx512_int_broadcast_reg<bits<8> opc, X86VectorVTInfo _,
705 RegisterClass SrcRC> {
706 defm r : AVX512_maskable_in_asm<opc, MRMSrcReg, _, (outs _.RC:$dst),
707 (ins SrcRC:$src), "vpbroadcast"##_.Suffix,
708 "$src", "$src", []>, T8PD, EVEX;
711 multiclass avx512_int_broadcast_reg_vl<bits<8> opc, AVX512VLVectorVTInfo _,
712 RegisterClass SrcRC, Predicate prd> {
713 let Predicates = [prd] in
714 defm Z : avx512_int_broadcast_reg<opc, _.info512, SrcRC>, EVEX_V512;
715 let Predicates = [prd, HasVLX] in {
716 defm Z256 : avx512_int_broadcast_reg<opc, _.info256, SrcRC>, EVEX_V256;
717 defm Z128 : avx512_int_broadcast_reg<opc, _.info128, SrcRC>, EVEX_V128;
721 defm VPBROADCASTBr : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info, GR32,
723 defm VPBROADCASTWr : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info, GR32,
725 defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, GR32,
727 defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, GR64,
730 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
731 (VPBROADCASTDrZrkz VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
733 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
734 (VPBROADCASTQrZrkz VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
736 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
737 (VPBROADCASTDrZr GR32:$src)>;
738 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
739 (VPBROADCASTDrZrkz VK16WM:$mask, GR32:$src)>;
740 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
741 (VPBROADCASTQrZr GR64:$src)>;
742 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
743 (VPBROADCASTQrZrkz VK8WM:$mask, GR64:$src)>;
745 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
746 (VPBROADCASTDrZr GR32:$src)>;
747 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
748 (VPBROADCASTQrZr GR64:$src)>;
750 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
751 (v16i32 immAllZerosV), (i16 GR16:$mask))),
752 (VPBROADCASTDrZrkz (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
753 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
754 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
755 (VPBROADCASTQrZrkz (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
757 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
758 X86MemOperand x86memop, PatFrag ld_frag,
759 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
761 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
762 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
764 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
765 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
767 !strconcat(OpcodeStr,
768 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
770 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
773 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
774 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
776 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
777 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
779 !strconcat(OpcodeStr,
780 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
781 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
782 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
786 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
787 loadi32, VR512, v16i32, v4i32, VK16WM>,
788 EVEX_V512, EVEX_CD8<32, CD8VT1>;
789 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
790 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
791 EVEX_CD8<64, CD8VT1>;
793 multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
794 X86MemOperand x86memop, PatFrag ld_frag,
797 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
798 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
800 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
802 !strconcat(OpcodeStr,
803 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
808 defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
809 i128mem, loadv2i64, VK16WM>,
810 EVEX_V512, EVEX_CD8<32, CD8VT4>;
811 defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
812 i256mem, loadv4i64, VK16WM>, VEX_W,
813 EVEX_V512, EVEX_CD8<64, CD8VT4>;
815 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
816 (VPBROADCASTDZrr VR128X:$src)>;
817 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
818 (VPBROADCASTQZrr VR128X:$src)>;
820 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
821 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
822 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
823 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
825 def : Pat<(v16i32 (X86VBroadcast (v16i32 VR512:$src))),
826 (VPBROADCASTDZrr (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
827 def : Pat<(v8i64 (X86VBroadcast (v8i64 VR512:$src))),
828 (VPBROADCASTQZrr (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
830 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
831 (VBROADCASTSSZr VR128X:$src)>;
832 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
833 (VBROADCASTSDZr VR128X:$src)>;
835 // Provide fallback in case the load node that is used in the patterns above
836 // is used by additional users, which prevents the pattern selection.
837 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
838 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
839 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
840 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
843 let Predicates = [HasAVX512] in {
844 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
846 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
847 addr:$src)), sub_ymm)>;
849 //===----------------------------------------------------------------------===//
850 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
853 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
855 let Predicates = [HasCDI] in
856 def Zrr : AVX512XS8I<opc, MRMSrcReg, (outs VR512:$dst), (ins KRC:$src),
857 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
858 []>, EVEX, EVEX_V512;
860 let Predicates = [HasCDI, HasVLX] in {
861 def Z128rr : AVX512XS8I<opc, MRMSrcReg, (outs VR128:$dst), (ins KRC:$src),
862 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
863 []>, EVEX, EVEX_V128;
864 def Z256rr : AVX512XS8I<opc, MRMSrcReg, (outs VR256:$dst), (ins KRC:$src),
865 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
866 []>, EVEX, EVEX_V256;
870 let Predicates = [HasCDI] in {
871 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
873 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
877 //===----------------------------------------------------------------------===//
880 // -- immediate form --
881 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
883 let ExeDomain = _.ExeDomain in {
884 def ri : AVX512AIi8<opc, MRMSrcReg, (outs _.RC:$dst),
885 (ins _.RC:$src1, u8imm:$src2),
886 !strconcat(OpcodeStr,
887 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
889 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>,
891 def mi : AVX512AIi8<opc, MRMSrcMem, (outs _.RC:$dst),
892 (ins _.MemOp:$src1, u8imm:$src2),
893 !strconcat(OpcodeStr,
894 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
896 (_.VT (OpNode (_.MemOpFrag addr:$src1),
898 EVEX, EVEX_CD8<_.EltSize, CD8VF>;
902 multiclass avx512_permil<bits<8> OpcImm, bits<8> OpcVar, X86VectorVTInfo _,
903 X86VectorVTInfo Ctrl> :
904 avx512_perm_imm<OpcImm, "vpermil" # _.Suffix, X86VPermilpi, _> {
905 let ExeDomain = _.ExeDomain in {
906 def rr : AVX5128I<OpcVar, MRMSrcReg, (outs _.RC:$dst),
907 (ins _.RC:$src1, _.RC:$src2),
908 !strconcat("vpermil" # _.Suffix,
909 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
911 (_.VT (X86VPermilpv _.RC:$src1,
912 (Ctrl.VT Ctrl.RC:$src2))))]>,
914 def rm : AVX5128I<OpcVar, MRMSrcMem, (outs _.RC:$dst),
915 (ins _.RC:$src1, Ctrl.MemOp:$src2),
916 !strconcat("vpermil" # _.Suffix,
917 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
919 (_.VT (X86VPermilpv _.RC:$src1,
920 (Ctrl.VT (Ctrl.MemOpFrag addr:$src2)))))]>,
925 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", X86VPermi, v8i64_info>,
927 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", X86VPermi, v8f64_info>,
930 defm VPERMILPSZ : avx512_permil<0x04, 0x0C, v16f32_info, v16i32_info>,
932 defm VPERMILPDZ : avx512_permil<0x05, 0x0D, v8f64_info, v8i64_info>,
935 def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
936 (VPERMILPSZri VR512:$src1, imm:$imm)>;
937 def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
938 (VPERMILPDZri VR512:$src1, imm:$imm)>;
940 // -- VPERM - register form --
941 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
942 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
944 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
945 (ins RC:$src1, RC:$src2),
946 !strconcat(OpcodeStr,
947 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
949 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
951 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
952 (ins RC:$src1, x86memop:$src2),
953 !strconcat(OpcodeStr,
954 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
956 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
960 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
961 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
962 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
963 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
964 let ExeDomain = SSEPackedSingle in
965 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
966 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
967 let ExeDomain = SSEPackedDouble in
968 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
969 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
971 // -- VPERM2I - 3 source operands form --
972 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
973 PatFrag mem_frag, X86MemOperand x86memop,
974 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
975 let Constraints = "$src1 = $dst" in {
976 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
977 (ins RC:$src1, RC:$src2, RC:$src3),
978 !strconcat(OpcodeStr,
979 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
981 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
984 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
985 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
986 !strconcat(OpcodeStr,
987 "\t{$src3, $src2, $dst {${mask}}|"
988 "$dst {${mask}}, $src2, $src3}"),
989 [(set RC:$dst, (OpVT (vselect KRC:$mask,
990 (OpNode RC:$src1, RC:$src2,
995 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
996 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
997 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
998 !strconcat(OpcodeStr,
999 "\t{$src3, $src2, $dst {${mask}} {z} |",
1000 "$dst {${mask}} {z}, $src2, $src3}"),
1001 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1002 (OpNode RC:$src1, RC:$src2,
1005 (v16i32 immAllZerosV))))))]>,
1008 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1009 (ins RC:$src1, RC:$src2, x86memop:$src3),
1010 !strconcat(OpcodeStr,
1011 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
1013 (OpVT (OpNode RC:$src1, RC:$src2,
1014 (mem_frag addr:$src3))))]>, EVEX_4V;
1016 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1017 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
1018 !strconcat(OpcodeStr,
1019 "\t{$src3, $src2, $dst {${mask}}|"
1020 "$dst {${mask}}, $src2, $src3}"),
1022 (OpVT (vselect KRC:$mask,
1023 (OpNode RC:$src1, RC:$src2,
1024 (mem_frag addr:$src3)),
1028 let AddedComplexity = 10 in // Prefer over the rrkz variant
1029 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1030 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
1031 !strconcat(OpcodeStr,
1032 "\t{$src3, $src2, $dst {${mask}} {z}|"
1033 "$dst {${mask}} {z}, $src2, $src3}"),
1035 (OpVT (vselect KRC:$mask,
1036 (OpNode RC:$src1, RC:$src2,
1037 (mem_frag addr:$src3)),
1039 (v16i32 immAllZerosV))))))]>,
1043 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32,
1044 i512mem, X86VPermiv3, v16i32, VK16WM>,
1045 EVEX_V512, EVEX_CD8<32, CD8VF>;
1046 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64,
1047 i512mem, X86VPermiv3, v8i64, VK8WM>,
1048 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1049 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32,
1050 i512mem, X86VPermiv3, v16f32, VK16WM>,
1051 EVEX_V512, EVEX_CD8<32, CD8VF>;
1052 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64,
1053 i512mem, X86VPermiv3, v8f64, VK8WM>,
1054 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1056 multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
1057 PatFrag mem_frag, X86MemOperand x86memop,
1058 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
1059 ValueType MaskVT, RegisterClass MRC> :
1060 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
1062 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
1063 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
1064 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
1066 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
1067 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
1068 (!cast<Instruction>(NAME#rrk) VR512:$src1,
1069 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
1072 defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, memopv16i32, i512mem,
1073 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
1074 EVEX_V512, EVEX_CD8<32, CD8VF>;
1075 defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, memopv8i64, i512mem,
1076 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
1077 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1078 defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, memopv16f32, i512mem,
1079 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
1080 EVEX_V512, EVEX_CD8<32, CD8VF>;
1081 defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, memopv8f64, i512mem,
1082 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
1083 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1085 //===----------------------------------------------------------------------===//
1086 // AVX-512 - BLEND using mask
1088 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1089 let ExeDomain = _.ExeDomain in {
1090 def rr : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1091 (ins _.RC:$src1, _.RC:$src2),
1092 !strconcat(OpcodeStr,
1093 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1095 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1096 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1097 !strconcat(OpcodeStr,
1098 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1099 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1100 (_.VT _.RC:$src2)))]>, EVEX_4V, EVEX_K;
1101 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1102 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1103 !strconcat(OpcodeStr,
1104 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1105 []>, EVEX_4V, EVEX_KZ;
1106 let mayLoad = 1 in {
1107 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1108 (ins _.RC:$src1, _.MemOp:$src2),
1109 !strconcat(OpcodeStr,
1110 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1111 []>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
1112 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1113 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1114 !strconcat(OpcodeStr,
1115 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1116 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1117 (_.VT (bitconvert (_.LdFrag addr:$src2)))))]>,
1118 EVEX_4V, EVEX_K, EVEX_CD8<_.EltSize, CD8VF>;
1119 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1120 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1121 !strconcat(OpcodeStr,
1122 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1123 []>, EVEX_4V, EVEX_KZ, EVEX_CD8<_.EltSize, CD8VF>;
1127 multiclass avx512_blendmask_rmb<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1129 def rmbk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1130 (ins _.KRCWM:$mask, _.RC:$src1, _.ScalarMemOp:$src2),
1131 !strconcat(OpcodeStr,
1132 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1133 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1134 [(set _.RC:$dst,(X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1135 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))]>,
1136 EVEX_4V, EVEX_K, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1138 def rmb : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1139 (ins _.RC:$src1, _.ScalarMemOp:$src2),
1140 !strconcat(OpcodeStr,
1141 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1142 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1143 []>, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1147 multiclass blendmask_dq <bits<8> opc, string OpcodeStr,
1148 AVX512VLVectorVTInfo VTInfo> {
1149 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>,
1150 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1152 let Predicates = [HasVLX] in {
1153 defm Z256 : avx512_blendmask<opc, OpcodeStr, VTInfo.info256>,
1154 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1155 defm Z128 : avx512_blendmask<opc, OpcodeStr, VTInfo.info128>,
1156 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1160 multiclass blendmask_bw <bits<8> opc, string OpcodeStr,
1161 AVX512VLVectorVTInfo VTInfo> {
1162 let Predicates = [HasBWI] in
1163 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1165 let Predicates = [HasBWI, HasVLX] in {
1166 defm Z256 : avx512_blendmask <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1167 defm Z128 : avx512_blendmask <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1172 defm VBLENDMPS : blendmask_dq <0x65, "vblendmps", avx512vl_f32_info>;
1173 defm VBLENDMPD : blendmask_dq <0x65, "vblendmpd", avx512vl_f64_info>, VEX_W;
1174 defm VPBLENDMD : blendmask_dq <0x64, "vpblendmd", avx512vl_i32_info>;
1175 defm VPBLENDMQ : blendmask_dq <0x64, "vpblendmq", avx512vl_i64_info>, VEX_W;
1176 defm VPBLENDMB : blendmask_bw <0x66, "vpblendmb", avx512vl_i8_info>;
1177 defm VPBLENDMW : blendmask_bw <0x66, "vpblendmw", avx512vl_i16_info>, VEX_W;
1180 let Predicates = [HasAVX512] in {
1181 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1182 (v8f32 VR256X:$src2))),
1184 (v16f32 (VBLENDMPSZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1185 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1186 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1188 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1189 (v8i32 VR256X:$src2))),
1191 (v16i32 (VPBLENDMDZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1192 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1193 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1195 //===----------------------------------------------------------------------===//
1196 // Compare Instructions
1197 //===----------------------------------------------------------------------===//
1199 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1200 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1201 SDNode OpNode, ValueType VT,
1202 PatFrag ld_frag, string Suffix> {
1203 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1204 (outs VK1:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1205 !strconcat("vcmp${cc}", Suffix,
1206 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1207 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
1208 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1209 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1210 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1211 !strconcat("vcmp${cc}", Suffix,
1212 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1213 [(set VK1:$dst, (OpNode (VT RC:$src1),
1214 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1215 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1216 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
1217 (outs VK1:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc),
1218 !strconcat("vcmp", Suffix,
1219 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1220 [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1222 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
1223 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, u8imm:$cc),
1224 !strconcat("vcmp", Suffix,
1225 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1226 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1230 let Predicates = [HasAVX512] in {
1231 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, X86cmpms, f32, loadf32, "ss">,
1233 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, X86cmpms, f64, loadf64, "sd">,
1237 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1238 X86VectorVTInfo _> {
1239 def rr : AVX512BI<opc, MRMSrcReg,
1240 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1241 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1242 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1243 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1245 def rm : AVX512BI<opc, MRMSrcMem,
1246 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1247 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1248 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1249 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1250 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1251 def rrk : AVX512BI<opc, MRMSrcReg,
1252 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1253 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1254 "$dst {${mask}}, $src1, $src2}"),
1255 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1256 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1257 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1259 def rmk : AVX512BI<opc, MRMSrcMem,
1260 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1261 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1262 "$dst {${mask}}, $src1, $src2}"),
1263 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1264 (OpNode (_.VT _.RC:$src1),
1266 (_.LdFrag addr:$src2))))))],
1267 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1270 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1271 X86VectorVTInfo _> :
1272 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1273 let mayLoad = 1 in {
1274 def rmb : AVX512BI<opc, MRMSrcMem,
1275 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1276 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1277 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1278 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1279 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1280 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1281 def rmbk : AVX512BI<opc, MRMSrcMem,
1282 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1283 _.ScalarMemOp:$src2),
1284 !strconcat(OpcodeStr,
1285 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1286 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1287 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1288 (OpNode (_.VT _.RC:$src1),
1290 (_.ScalarLdFrag addr:$src2)))))],
1291 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1295 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1296 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1297 let Predicates = [prd] in
1298 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1301 let Predicates = [prd, HasVLX] in {
1302 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1304 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1309 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1310 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1312 let Predicates = [prd] in
1313 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1316 let Predicates = [prd, HasVLX] in {
1317 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1319 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1324 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1325 avx512vl_i8_info, HasBWI>,
1328 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1329 avx512vl_i16_info, HasBWI>,
1330 EVEX_CD8<16, CD8VF>;
1332 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1333 avx512vl_i32_info, HasAVX512>,
1334 EVEX_CD8<32, CD8VF>;
1336 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1337 avx512vl_i64_info, HasAVX512>,
1338 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1340 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1341 avx512vl_i8_info, HasBWI>,
1344 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1345 avx512vl_i16_info, HasBWI>,
1346 EVEX_CD8<16, CD8VF>;
1348 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1349 avx512vl_i32_info, HasAVX512>,
1350 EVEX_CD8<32, CD8VF>;
1352 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1353 avx512vl_i64_info, HasAVX512>,
1354 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1356 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1357 (COPY_TO_REGCLASS (VPCMPGTDZrr
1358 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1359 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1361 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1362 (COPY_TO_REGCLASS (VPCMPEQDZrr
1363 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1364 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1366 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1367 X86VectorVTInfo _> {
1368 def rri : AVX512AIi8<opc, MRMSrcReg,
1369 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1370 !strconcat("vpcmp${cc}", Suffix,
1371 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1372 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1374 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1376 def rmi : AVX512AIi8<opc, MRMSrcMem,
1377 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1378 !strconcat("vpcmp${cc}", Suffix,
1379 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1380 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1381 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1383 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1384 def rrik : AVX512AIi8<opc, MRMSrcReg,
1385 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1387 !strconcat("vpcmp${cc}", Suffix,
1388 "\t{$src2, $src1, $dst {${mask}}|",
1389 "$dst {${mask}}, $src1, $src2}"),
1390 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1391 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1393 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1395 def rmik : AVX512AIi8<opc, MRMSrcMem,
1396 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1398 !strconcat("vpcmp${cc}", Suffix,
1399 "\t{$src2, $src1, $dst {${mask}}|",
1400 "$dst {${mask}}, $src1, $src2}"),
1401 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1402 (OpNode (_.VT _.RC:$src1),
1403 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1405 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1407 // Accept explicit immediate argument form instead of comparison code.
1408 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1409 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1410 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1411 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1412 "$dst, $src1, $src2, $cc}"),
1413 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1415 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1416 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1417 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1418 "$dst, $src1, $src2, $cc}"),
1419 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1420 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1421 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1423 !strconcat("vpcmp", Suffix,
1424 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1425 "$dst {${mask}}, $src1, $src2, $cc}"),
1426 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1428 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1429 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1431 !strconcat("vpcmp", Suffix,
1432 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1433 "$dst {${mask}}, $src1, $src2, $cc}"),
1434 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1438 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1439 X86VectorVTInfo _> :
1440 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1441 def rmib : AVX512AIi8<opc, MRMSrcMem,
1442 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1444 !strconcat("vpcmp${cc}", Suffix,
1445 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1446 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1447 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1448 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1450 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1451 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1452 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1453 _.ScalarMemOp:$src2, AVXCC:$cc),
1454 !strconcat("vpcmp${cc}", Suffix,
1455 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1456 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1457 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1458 (OpNode (_.VT _.RC:$src1),
1459 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1461 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1463 // Accept explicit immediate argument form instead of comparison code.
1464 let isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 1 in {
1465 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1466 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1468 !strconcat("vpcmp", Suffix,
1469 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1470 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1471 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1472 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1473 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1474 _.ScalarMemOp:$src2, u8imm:$cc),
1475 !strconcat("vpcmp", Suffix,
1476 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1477 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1478 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1482 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1483 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1484 let Predicates = [prd] in
1485 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1487 let Predicates = [prd, HasVLX] in {
1488 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1489 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1493 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1494 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1495 let Predicates = [prd] in
1496 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1499 let Predicates = [prd, HasVLX] in {
1500 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1502 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1507 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1508 HasBWI>, EVEX_CD8<8, CD8VF>;
1509 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1510 HasBWI>, EVEX_CD8<8, CD8VF>;
1512 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1513 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1514 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1515 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1517 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1518 HasAVX512>, EVEX_CD8<32, CD8VF>;
1519 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1520 HasAVX512>, EVEX_CD8<32, CD8VF>;
1522 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1523 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1524 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1525 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1527 // avx512_cmp_packed - compare packed instructions
1528 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
1529 X86MemOperand x86memop, ValueType vt,
1530 string suffix, Domain d> {
1531 def rri : AVX512PIi8<0xC2, MRMSrcReg,
1532 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1533 !strconcat("vcmp${cc}", suffix,
1534 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1535 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
1536 let hasSideEffects = 0 in
1537 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
1538 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1539 !strconcat("vcmp${cc}", suffix,
1540 "\t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
1542 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
1543 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1544 !strconcat("vcmp${cc}", suffix,
1545 "\t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1547 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
1549 // Accept explicit immediate argument form instead of comparison code.
1550 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1551 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
1552 (outs KRC:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc),
1553 !strconcat("vcmp", suffix,
1554 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1556 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
1557 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, u8imm:$cc),
1558 !strconcat("vcmp", suffix,
1559 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1563 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
1564 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
1565 EVEX_CD8<32, CD8VF>;
1566 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
1567 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
1568 EVEX_CD8<64, CD8VF>;
1570 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1571 (COPY_TO_REGCLASS (VCMPPSZrri
1572 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1573 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1575 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1576 (COPY_TO_REGCLASS (VPCMPDZrri
1577 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1578 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1580 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1581 (COPY_TO_REGCLASS (VPCMPUDZrri
1582 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1583 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1586 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1587 (v16f32 VR512:$src2), i8immZExt5:$cc, (i16 -1),
1589 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
1590 (I8Imm imm:$cc)), GR16)>;
1592 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1593 (v8f64 VR512:$src2), i8immZExt5:$cc, (i8 -1),
1595 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
1596 (I8Imm imm:$cc)), GR8)>;
1598 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1599 (v16f32 VR512:$src2), i8immZExt5:$cc, (i16 -1),
1601 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1602 (I8Imm imm:$cc)), GR16)>;
1604 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1605 (v8f64 VR512:$src2), i8immZExt5:$cc, (i8 -1),
1607 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1608 (I8Imm imm:$cc)), GR8)>;
1610 // Mask register copy, including
1611 // - copy between mask registers
1612 // - load/store mask registers
1613 // - copy from GPR to mask register and vice versa
1615 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1616 string OpcodeStr, RegisterClass KRC,
1617 ValueType vvt, ValueType ivt, X86MemOperand x86memop> {
1618 let hasSideEffects = 0 in {
1619 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1620 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1622 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1623 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1624 [(set KRC:$dst, (vvt (bitconvert (ivt (load addr:$src)))))]>;
1626 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1627 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1631 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1633 RegisterClass KRC, RegisterClass GRC> {
1634 let hasSideEffects = 0 in {
1635 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1636 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1637 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1638 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1642 let Predicates = [HasDQI] in
1643 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8,
1645 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1648 let Predicates = [HasAVX512] in
1649 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16,
1651 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1654 let Predicates = [HasBWI] in {
1655 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1, i32,
1656 i32mem>, VEX, PD, VEX_W;
1657 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1661 let Predicates = [HasBWI] in {
1662 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64,
1663 i64mem>, VEX, PS, VEX_W;
1664 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1668 // GR from/to mask register
1669 let Predicates = [HasDQI] in {
1670 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1671 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1672 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1673 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1675 let Predicates = [HasAVX512] in {
1676 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1677 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1678 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1679 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1681 let Predicates = [HasBWI] in {
1682 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1683 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1685 let Predicates = [HasBWI] in {
1686 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1687 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1691 let Predicates = [HasDQI] in {
1692 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1693 (KMOVBmk addr:$dst, VK8:$src)>;
1695 let Predicates = [HasAVX512] in {
1696 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1697 (KMOVWmk addr:$dst, VK16:$src)>;
1698 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1699 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1700 def : Pat<(i1 (load addr:$src)),
1701 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
1702 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1703 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1705 let Predicates = [HasBWI] in {
1706 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1707 (KMOVDmk addr:$dst, VK32:$src)>;
1709 let Predicates = [HasBWI] in {
1710 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1711 (KMOVQmk addr:$dst, VK64:$src)>;
1714 let Predicates = [HasAVX512] in {
1715 def : Pat<(i1 (trunc (i64 GR64:$src))),
1716 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1719 def : Pat<(i1 (trunc (i32 GR32:$src))),
1720 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1722 def : Pat<(i1 (trunc (i8 GR8:$src))),
1724 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1726 def : Pat<(i1 (trunc (i16 GR16:$src))),
1728 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1731 def : Pat<(i32 (zext VK1:$src)),
1732 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1733 def : Pat<(i8 (zext VK1:$src)),
1736 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1737 def : Pat<(i64 (zext VK1:$src)),
1738 (AND64ri8 (SUBREG_TO_REG (i64 0),
1739 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1740 def : Pat<(i16 (zext VK1:$src)),
1742 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1744 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1745 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1746 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1747 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1749 let Predicates = [HasBWI] in {
1750 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1751 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1752 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1753 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1757 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1758 let Predicates = [HasAVX512] in {
1759 // GR from/to 8-bit mask without native support
1760 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1762 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1764 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1766 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1769 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1770 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1771 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1772 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1774 let Predicates = [HasBWI] in {
1775 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1776 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1777 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1778 (COPY_TO_REGCLASS VK64:$src, VK1)>;
1781 // Mask unary operation
1783 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1784 RegisterClass KRC, SDPatternOperator OpNode,
1786 let Predicates = [prd] in
1787 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1788 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1789 [(set KRC:$dst, (OpNode KRC:$src))]>;
1792 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1793 SDPatternOperator OpNode> {
1794 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1796 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1797 HasAVX512>, VEX, PS;
1798 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1799 HasBWI>, VEX, PD, VEX_W;
1800 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1801 HasBWI>, VEX, PS, VEX_W;
1804 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
1806 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1807 let Predicates = [HasAVX512] in
1808 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1810 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1811 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1813 defm : avx512_mask_unop_int<"knot", "KNOT">;
1815 let Predicates = [HasDQI] in
1816 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1817 let Predicates = [HasAVX512] in
1818 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1819 let Predicates = [HasBWI] in
1820 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1821 let Predicates = [HasBWI] in
1822 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1824 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1825 let Predicates = [HasAVX512] in {
1826 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1827 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1829 def : Pat<(not VK8:$src),
1831 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1834 // Mask binary operation
1835 // - KAND, KANDN, KOR, KXNOR, KXOR
1836 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1837 RegisterClass KRC, SDPatternOperator OpNode,
1839 let Predicates = [prd] in
1840 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1841 !strconcat(OpcodeStr,
1842 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1843 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1846 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1847 SDPatternOperator OpNode> {
1848 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1849 HasDQI>, VEX_4V, VEX_L, PD;
1850 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1851 HasAVX512>, VEX_4V, VEX_L, PS;
1852 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1853 HasBWI>, VEX_4V, VEX_L, VEX_W, PD;
1854 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1855 HasBWI>, VEX_4V, VEX_L, VEX_W, PS;
1858 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1859 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1861 let isCommutable = 1 in {
1862 defm KAND : avx512_mask_binop_all<0x41, "kand", and>;
1863 defm KOR : avx512_mask_binop_all<0x45, "kor", or>;
1864 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>;
1865 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>;
1867 let isCommutable = 0 in
1868 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
1870 def : Pat<(xor VK1:$src1, VK1:$src2),
1871 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1872 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1874 def : Pat<(or VK1:$src1, VK1:$src2),
1875 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1876 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1878 def : Pat<(and VK1:$src1, VK1:$src2),
1879 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1880 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1882 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1883 let Predicates = [HasAVX512] in
1884 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1885 (i16 GR16:$src1), (i16 GR16:$src2)),
1886 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1887 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1888 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1891 defm : avx512_mask_binop_int<"kand", "KAND">;
1892 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1893 defm : avx512_mask_binop_int<"kor", "KOR">;
1894 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1895 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1897 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1898 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1899 let Predicates = [HasAVX512] in
1900 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1902 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1903 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1906 defm : avx512_binop_pat<and, KANDWrr>;
1907 defm : avx512_binop_pat<andn, KANDNWrr>;
1908 defm : avx512_binop_pat<or, KORWrr>;
1909 defm : avx512_binop_pat<xnor, KXNORWrr>;
1910 defm : avx512_binop_pat<xor, KXORWrr>;
1913 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1914 RegisterClass KRC> {
1915 let Predicates = [HasAVX512] in
1916 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1917 !strconcat(OpcodeStr,
1918 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1921 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1922 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1926 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1927 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1928 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1929 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1932 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1933 let Predicates = [HasAVX512] in
1934 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1935 (i16 GR16:$src1), (i16 GR16:$src2)),
1936 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1937 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1938 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1940 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1943 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1945 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1946 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1947 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1948 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1951 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1952 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1956 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1958 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1959 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1960 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1963 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1965 let Predicates = [HasAVX512] in
1966 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, u8imm:$imm),
1967 !strconcat(OpcodeStr,
1968 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
1969 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1972 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1974 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1978 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1979 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1981 // Mask setting all 0s or 1s
1982 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1983 let Predicates = [HasAVX512] in
1984 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1985 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1986 [(set KRC:$dst, (VT Val))]>;
1989 multiclass avx512_mask_setop_w<PatFrag Val> {
1990 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1991 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1994 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1995 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1997 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1998 let Predicates = [HasAVX512] in {
1999 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
2000 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
2001 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
2002 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
2003 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
2005 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
2006 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
2008 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
2009 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
2011 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
2012 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
2014 let Predicates = [HasVLX] in {
2015 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
2016 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
2017 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2018 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
2019 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2020 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
2021 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2022 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
2025 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
2026 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
2028 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
2029 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
2030 //===----------------------------------------------------------------------===//
2031 // AVX-512 - Aligned and unaligned load and store
2034 multiclass avx512_load<bits<8> opc, string OpcodeStr, PatFrag ld_frag,
2035 RegisterClass KRC, RegisterClass RC,
2036 ValueType vt, ValueType zvt, X86MemOperand memop,
2037 Domain d, bit IsReMaterializable = 1> {
2038 let hasSideEffects = 0 in {
2039 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2040 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
2042 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
2043 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2044 "${dst} {${mask}} {z}, $src}"), [], d>, EVEX, EVEX_KZ;
2046 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
2047 SchedRW = [WriteLoad] in
2048 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins memop:$src),
2049 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2050 [(set RC:$dst, (vt (bitconvert (ld_frag addr:$src))))],
2053 let AddedComplexity = 20 in {
2054 let Constraints = "$src0 = $dst", hasSideEffects = 0 in {
2055 let hasSideEffects = 0 in
2056 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
2057 (ins RC:$src0, KRC:$mask, RC:$src1),
2058 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2059 "${dst} {${mask}}, $src1}"),
2060 [(set RC:$dst, (vt (vselect KRC:$mask,
2064 let mayLoad = 1, SchedRW = [WriteLoad] in
2065 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
2066 (ins RC:$src0, KRC:$mask, memop:$src1),
2067 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2068 "${dst} {${mask}}, $src1}"),
2071 (vt (bitconvert (ld_frag addr:$src1))),
2075 let mayLoad = 1, SchedRW = [WriteLoad] in
2076 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
2077 (ins KRC:$mask, memop:$src),
2078 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2079 "${dst} {${mask}} {z}, $src}"),
2082 (vt (bitconvert (ld_frag addr:$src))),
2083 (vt (bitconvert (zvt immAllZerosV))))))],
2088 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat,
2089 string elty, string elsz, string vsz512,
2090 string vsz256, string vsz128, Domain d,
2091 Predicate prd, bit IsReMaterializable = 1> {
2092 let Predicates = [prd] in
2093 defm Z : avx512_load<opc, OpcodeStr,
2094 !cast<PatFrag>(ld_pat##"v"##vsz512##elty##elsz),
2095 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
2096 !cast<ValueType>("v"##vsz512##elty##elsz), v16i32,
2097 !cast<X86MemOperand>(elty##"512mem"), d,
2098 IsReMaterializable>, EVEX_V512;
2100 let Predicates = [prd, HasVLX] in {
2101 defm Z256 : avx512_load<opc, OpcodeStr,
2102 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
2103 "v"##vsz256##elty##elsz, "v4i64")),
2104 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
2105 !cast<ValueType>("v"##vsz256##elty##elsz), v8i32,
2106 !cast<X86MemOperand>(elty##"256mem"), d,
2107 IsReMaterializable>, EVEX_V256;
2109 defm Z128 : avx512_load<opc, OpcodeStr,
2110 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
2111 "v"##vsz128##elty##elsz, "v2i64")),
2112 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
2113 !cast<ValueType>("v"##vsz128##elty##elsz), v4i32,
2114 !cast<X86MemOperand>(elty##"128mem"), d,
2115 IsReMaterializable>, EVEX_V128;
2120 multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2121 ValueType OpVT, RegisterClass KRC, RegisterClass RC,
2122 X86MemOperand memop, Domain d> {
2123 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2124 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
2125 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>,
2127 let Constraints = "$src1 = $dst" in
2128 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
2129 (ins RC:$src1, KRC:$mask, RC:$src2),
2130 !strconcat(OpcodeStr,
2131 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
2133 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
2134 (ins KRC:$mask, RC:$src),
2135 !strconcat(OpcodeStr,
2136 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
2137 [], d>, EVEX, EVEX_KZ;
2139 let mayStore = 1 in {
2140 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2141 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2142 [(st_frag (OpVT RC:$src), addr:$dst)], d>, EVEX;
2143 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2144 (ins memop:$dst, KRC:$mask, RC:$src),
2145 !strconcat(OpcodeStr,
2146 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
2147 [], d>, EVEX, EVEX_K;
2152 multiclass avx512_store_vl<bits<8> opc, string OpcodeStr, string st_pat,
2153 string st_suff_512, string st_suff_256,
2154 string st_suff_128, string elty, string elsz,
2155 string vsz512, string vsz256, string vsz128,
2156 Domain d, Predicate prd> {
2157 let Predicates = [prd] in
2158 defm Z : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_512),
2159 !cast<ValueType>("v"##vsz512##elty##elsz),
2160 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
2161 !cast<X86MemOperand>(elty##"512mem"), d>, EVEX_V512;
2163 let Predicates = [prd, HasVLX] in {
2164 defm Z256 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_256),
2165 !cast<ValueType>("v"##vsz256##elty##elsz),
2166 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
2167 !cast<X86MemOperand>(elty##"256mem"), d>, EVEX_V256;
2169 defm Z128 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_128),
2170 !cast<ValueType>("v"##vsz128##elty##elsz),
2171 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
2172 !cast<X86MemOperand>(elty##"128mem"), d>, EVEX_V128;
2176 defm VMOVAPS : avx512_load_vl<0x28, "vmovaps", "alignedload", "f", "32",
2177 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2178 avx512_store_vl<0x29, "vmovaps", "alignedstore",
2179 "512", "256", "", "f", "32", "16", "8", "4",
2180 SSEPackedSingle, HasAVX512>,
2181 PS, EVEX_CD8<32, CD8VF>;
2183 defm VMOVAPD : avx512_load_vl<0x28, "vmovapd", "alignedload", "f", "64",
2184 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2185 avx512_store_vl<0x29, "vmovapd", "alignedstore",
2186 "512", "256", "", "f", "64", "8", "4", "2",
2187 SSEPackedDouble, HasAVX512>,
2188 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2190 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", "load", "f", "32",
2191 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2192 avx512_store_vl<0x11, "vmovups", "store", "", "", "", "f", "32",
2193 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2194 PS, EVEX_CD8<32, CD8VF>;
2196 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", "load", "f", "64",
2197 "8", "4", "2", SSEPackedDouble, HasAVX512, 0>,
2198 avx512_store_vl<0x11, "vmovupd", "store", "", "", "", "f", "64",
2199 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2200 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2202 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2203 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2204 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2206 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2207 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2208 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2210 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2211 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2212 (VMOVAPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2214 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2215 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2216 (VMOVAPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2218 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2219 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2220 (VMOVAPDZrm addr:$ptr)>;
2222 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2223 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
2224 (VMOVAPSZrm addr:$ptr)>;
2226 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2228 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2230 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2232 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2235 def: Pat<(int_x86_avx512_mask_store_ps_512 addr:$ptr, (v16f32 VR512:$src),
2237 (VMOVAPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2239 def: Pat<(int_x86_avx512_mask_store_pd_512 addr:$ptr, (v8f64 VR512:$src),
2241 (VMOVAPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2244 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src)),
2245 (VMOVUPSZmrk addr:$ptr,
2246 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2247 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2249 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2250 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmkz
2251 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2253 def: Pat<(masked_store addr:$ptr, VK16WM:$mask, (v16f32 VR512:$src)),
2254 (VMOVUPSZmrk addr:$ptr, VK16WM:$mask, VR512:$src)>;
2256 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8f64 VR512:$src)),
2257 (VMOVUPDZmrk addr:$ptr, VK8WM:$mask, VR512:$src)>;
2259 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask, undef)),
2260 (VMOVUPSZrmkz VK16WM:$mask, addr:$ptr)>;
2262 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask,
2263 (bc_v16f32 (v16i32 immAllZerosV)))),
2264 (VMOVUPSZrmkz VK16WM:$mask, addr:$ptr)>;
2266 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask, (v16f32 VR512:$src0))),
2267 (VMOVUPSZrmk VR512:$src0, VK16WM:$mask, addr:$ptr)>;
2269 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2270 (VMOVUPDZrmkz VK8WM:$mask, addr:$ptr)>;
2272 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask,
2273 (bc_v8f64 (v16i32 immAllZerosV)))),
2274 (VMOVUPDZrmkz VK8WM:$mask, addr:$ptr)>;
2276 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask, (v8f64 VR512:$src0))),
2277 (VMOVUPDZrmk VR512:$src0, VK8WM:$mask, addr:$ptr)>;
2279 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src0))),
2280 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmk
2281 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src0, sub_ymm),
2282 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2284 defm VMOVDQA32 : avx512_load_vl<0x6F, "vmovdqa32", "alignedload", "i", "32",
2285 "16", "8", "4", SSEPackedInt, HasAVX512>,
2286 avx512_store_vl<0x7F, "vmovdqa32", "alignedstore",
2287 "512", "256", "", "i", "32", "16", "8", "4",
2288 SSEPackedInt, HasAVX512>,
2289 PD, EVEX_CD8<32, CD8VF>;
2291 defm VMOVDQA64 : avx512_load_vl<0x6F, "vmovdqa64", "alignedload", "i", "64",
2292 "8", "4", "2", SSEPackedInt, HasAVX512>,
2293 avx512_store_vl<0x7F, "vmovdqa64", "alignedstore",
2294 "512", "256", "", "i", "64", "8", "4", "2",
2295 SSEPackedInt, HasAVX512>,
2296 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2298 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", "load", "i", "8",
2299 "64", "32", "16", SSEPackedInt, HasBWI>,
2300 avx512_store_vl<0x7F, "vmovdqu8", "store", "", "", "",
2301 "i", "8", "64", "32", "16", SSEPackedInt,
2302 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2304 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", "load", "i", "16",
2305 "32", "16", "8", SSEPackedInt, HasBWI>,
2306 avx512_store_vl<0x7F, "vmovdqu16", "store", "", "", "",
2307 "i", "16", "32", "16", "8", SSEPackedInt,
2308 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2310 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", "load", "i", "32",
2311 "16", "8", "4", SSEPackedInt, HasAVX512>,
2312 avx512_store_vl<0x7F, "vmovdqu32", "store", "", "", "",
2313 "i", "32", "16", "8", "4", SSEPackedInt,
2314 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2316 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", "load", "i", "64",
2317 "8", "4", "2", SSEPackedInt, HasAVX512>,
2318 avx512_store_vl<0x7F, "vmovdqu64", "store", "", "", "",
2319 "i", "64", "8", "4", "2", SSEPackedInt,
2320 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2322 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2323 (v16i32 immAllZerosV), GR16:$mask)),
2324 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2326 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2327 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2328 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2330 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2332 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2334 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2336 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2339 let AddedComplexity = 20 in {
2340 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2341 (bc_v8i64 (v16i32 immAllZerosV)))),
2342 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2344 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2345 (v8i64 VR512:$src))),
2346 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2349 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2350 (v16i32 immAllZerosV))),
2351 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2353 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2354 (v16i32 VR512:$src))),
2355 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2358 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, (v16i32 immAllZerosV))),
2359 (VMOVDQU32Zrmkz VK16WM:$mask, addr:$ptr)>;
2361 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, undef)),
2362 (VMOVDQU32Zrmkz VK16WM:$mask, addr:$ptr)>;
2364 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, (v16i32 VR512:$src0))),
2365 (VMOVDQU32Zrmk VR512:$src0, VK16WM:$mask, addr:$ptr)>;
2367 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask,
2368 (bc_v8i64 (v16i32 immAllZerosV)))),
2369 (VMOVDQU64Zrmkz VK8WM:$mask, addr:$ptr)>;
2371 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2372 (VMOVDQU64Zrmkz VK8WM:$mask, addr:$ptr)>;
2374 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask, (v8i64 VR512:$src0))),
2375 (VMOVDQU64Zrmk VR512:$src0, VK8WM:$mask, addr:$ptr)>;
2377 def: Pat<(masked_store addr:$ptr, VK16WM:$mask, (v16i32 VR512:$src)),
2378 (VMOVDQU32Zmrk addr:$ptr, VK16WM:$mask, VR512:$src)>;
2380 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i64 VR512:$src)),
2381 (VMOVDQU64Zmrk addr:$ptr, VK8WM:$mask, VR512:$src)>;
2384 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2385 (VMOVDQU32Z256mrk addr:$ptr, VK8WM:$mask, VR256:$src)>;
2388 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2389 (VMOVDQU32Zmrk addr:$ptr,
2390 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2391 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2393 def: Pat<(v8i32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2394 (v8i32 (EXTRACT_SUBREG (v16i32 (VMOVDQU32Zrmkz
2395 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2398 // Move Int Doubleword to Packed Double Int
2400 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2401 "vmovd\t{$src, $dst|$dst, $src}",
2403 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2405 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2406 "vmovd\t{$src, $dst|$dst, $src}",
2408 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2409 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2410 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2411 "vmovq\t{$src, $dst|$dst, $src}",
2413 (v2i64 (scalar_to_vector GR64:$src)))],
2414 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2415 let isCodeGenOnly = 1 in {
2416 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2417 "vmovq\t{$src, $dst|$dst, $src}",
2418 [(set FR64:$dst, (bitconvert GR64:$src))],
2419 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2420 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2421 "vmovq\t{$src, $dst|$dst, $src}",
2422 [(set GR64:$dst, (bitconvert FR64:$src))],
2423 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2425 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2426 "vmovq\t{$src, $dst|$dst, $src}",
2427 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2428 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2429 EVEX_CD8<64, CD8VT1>;
2431 // Move Int Doubleword to Single Scalar
2433 let isCodeGenOnly = 1 in {
2434 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2435 "vmovd\t{$src, $dst|$dst, $src}",
2436 [(set FR32X:$dst, (bitconvert GR32:$src))],
2437 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2439 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2440 "vmovd\t{$src, $dst|$dst, $src}",
2441 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2442 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2445 // Move doubleword from xmm register to r/m32
2447 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2448 "vmovd\t{$src, $dst|$dst, $src}",
2449 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2450 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2452 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2453 (ins i32mem:$dst, VR128X:$src),
2454 "vmovd\t{$src, $dst|$dst, $src}",
2455 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2456 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2457 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2459 // Move quadword from xmm1 register to r/m64
2461 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2462 "vmovq\t{$src, $dst|$dst, $src}",
2463 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2465 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2466 Requires<[HasAVX512, In64BitMode]>;
2468 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2469 (ins i64mem:$dst, VR128X:$src),
2470 "vmovq\t{$src, $dst|$dst, $src}",
2471 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2472 addr:$dst)], IIC_SSE_MOVDQ>,
2473 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2474 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2476 // Move Scalar Single to Double Int
2478 let isCodeGenOnly = 1 in {
2479 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2481 "vmovd\t{$src, $dst|$dst, $src}",
2482 [(set GR32:$dst, (bitconvert FR32X:$src))],
2483 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2484 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2485 (ins i32mem:$dst, FR32X:$src),
2486 "vmovd\t{$src, $dst|$dst, $src}",
2487 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2488 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2491 // Move Quadword Int to Packed Quadword Int
2493 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2495 "vmovq\t{$src, $dst|$dst, $src}",
2497 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2498 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2500 //===----------------------------------------------------------------------===//
2501 // AVX-512 MOVSS, MOVSD
2502 //===----------------------------------------------------------------------===//
2504 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2505 SDNode OpNode, ValueType vt,
2506 X86MemOperand x86memop, PatFrag mem_pat> {
2507 let hasSideEffects = 0 in {
2508 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2509 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2510 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2511 (scalar_to_vector RC:$src2))))],
2512 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2513 let Constraints = "$src1 = $dst" in
2514 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2515 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2517 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2518 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2519 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2520 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2521 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2523 let mayStore = 1 in {
2524 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2525 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2526 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2528 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2529 !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2530 [], IIC_SSE_MOV_S_MR>,
2531 EVEX, VEX_LIG, EVEX_K;
2533 } //hasSideEffects = 0
2536 let ExeDomain = SSEPackedSingle in
2537 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2538 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2540 let ExeDomain = SSEPackedDouble in
2541 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2542 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2544 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2545 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2546 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2548 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2549 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2550 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2552 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2553 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2554 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2556 // For the disassembler
2557 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2558 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2559 (ins VR128X:$src1, FR32X:$src2),
2560 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2562 XS, EVEX_4V, VEX_LIG;
2563 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2564 (ins VR128X:$src1, FR64X:$src2),
2565 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2567 XD, EVEX_4V, VEX_LIG, VEX_W;
2570 let Predicates = [HasAVX512] in {
2571 let AddedComplexity = 15 in {
2572 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2573 // MOVS{S,D} to the lower bits.
2574 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2575 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2576 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2577 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2578 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2579 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2580 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2581 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2583 // Move low f32 and clear high bits.
2584 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2585 (SUBREG_TO_REG (i32 0),
2586 (VMOVSSZrr (v4f32 (V_SET0)),
2587 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2588 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2589 (SUBREG_TO_REG (i32 0),
2590 (VMOVSSZrr (v4i32 (V_SET0)),
2591 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2594 let AddedComplexity = 20 in {
2595 // MOVSSrm zeros the high parts of the register; represent this
2596 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2597 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2598 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2599 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2600 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2601 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2602 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2604 // MOVSDrm zeros the high parts of the register; represent this
2605 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2606 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2607 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2608 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2609 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2610 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2611 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2612 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2613 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2614 def : Pat<(v2f64 (X86vzload addr:$src)),
2615 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2617 // Represent the same patterns above but in the form they appear for
2619 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2620 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
2621 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
2622 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2623 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2624 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2625 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2626 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2627 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2629 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2630 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2631 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2632 FR32X:$src)), sub_xmm)>;
2633 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2634 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2635 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2636 FR64X:$src)), sub_xmm)>;
2637 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2638 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
2639 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
2641 // Move low f64 and clear high bits.
2642 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2643 (SUBREG_TO_REG (i32 0),
2644 (VMOVSDZrr (v2f64 (V_SET0)),
2645 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2647 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2648 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2649 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2651 // Extract and store.
2652 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2654 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2655 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2657 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2659 // Shuffle with VMOVSS
2660 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2661 (VMOVSSZrr (v4i32 VR128X:$src1),
2662 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2663 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2664 (VMOVSSZrr (v4f32 VR128X:$src1),
2665 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2668 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2669 (SUBREG_TO_REG (i32 0),
2670 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2671 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2673 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2674 (SUBREG_TO_REG (i32 0),
2675 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2676 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2679 // Shuffle with VMOVSD
2680 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2681 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2682 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2683 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2684 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2685 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2686 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2687 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2690 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2691 (SUBREG_TO_REG (i32 0),
2692 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2693 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2695 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2696 (SUBREG_TO_REG (i32 0),
2697 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2698 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2701 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2702 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2703 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2704 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2705 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2706 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2707 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2708 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2711 let AddedComplexity = 15 in
2712 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2714 "vmovq\t{$src, $dst|$dst, $src}",
2715 [(set VR128X:$dst, (v2i64 (X86vzmovl
2716 (v2i64 VR128X:$src))))],
2717 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2719 let AddedComplexity = 20 in
2720 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2722 "vmovq\t{$src, $dst|$dst, $src}",
2723 [(set VR128X:$dst, (v2i64 (X86vzmovl
2724 (loadv2i64 addr:$src))))],
2725 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2726 EVEX_CD8<8, CD8VT8>;
2728 let Predicates = [HasAVX512] in {
2729 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2730 let AddedComplexity = 20 in {
2731 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2732 (VMOVDI2PDIZrm addr:$src)>;
2733 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2734 (VMOV64toPQIZrr GR64:$src)>;
2735 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2736 (VMOVDI2PDIZrr GR32:$src)>;
2738 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2739 (VMOVDI2PDIZrm addr:$src)>;
2740 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2741 (VMOVDI2PDIZrm addr:$src)>;
2742 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2743 (VMOVZPQILo2PQIZrm addr:$src)>;
2744 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2745 (VMOVZPQILo2PQIZrr VR128X:$src)>;
2746 def : Pat<(v2i64 (X86vzload addr:$src)),
2747 (VMOVZPQILo2PQIZrm addr:$src)>;
2750 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2751 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2752 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2753 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2754 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2755 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2756 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2759 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2760 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2762 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2763 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2765 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2766 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2768 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2769 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2771 //===----------------------------------------------------------------------===//
2772 // AVX-512 - Non-temporals
2773 //===----------------------------------------------------------------------===//
2774 let SchedRW = [WriteLoad] in {
2775 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2776 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2777 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2778 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2779 EVEX_CD8<64, CD8VF>;
2781 let Predicates = [HasAVX512, HasVLX] in {
2782 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2784 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2785 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2786 EVEX_CD8<64, CD8VF>;
2788 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2790 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2791 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2792 EVEX_CD8<64, CD8VF>;
2796 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2797 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2798 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2799 let SchedRW = [WriteStore], mayStore = 1,
2800 AddedComplexity = 400 in
2801 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2802 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2803 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2806 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2807 string elty, string elsz, string vsz512,
2808 string vsz256, string vsz128, Domain d,
2809 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2810 let Predicates = [prd] in
2811 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2812 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2813 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2816 let Predicates = [prd, HasVLX] in {
2817 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2818 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2819 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2822 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2823 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2824 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2829 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2830 "i", "64", "8", "4", "2", SSEPackedInt,
2831 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2833 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2834 "f", "64", "8", "4", "2", SSEPackedDouble,
2835 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2837 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2838 "f", "32", "16", "8", "4", SSEPackedSingle,
2839 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2841 //===----------------------------------------------------------------------===//
2842 // AVX-512 - Integer arithmetic
2844 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2845 X86VectorVTInfo _, OpndItins itins,
2846 bit IsCommutable = 0> {
2847 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
2848 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
2849 "$src2, $src1", "$src1, $src2",
2850 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
2851 "", itins.rr, IsCommutable>,
2852 AVX512BIBase, EVEX_4V;
2855 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2856 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
2857 "$src2, $src1", "$src1, $src2",
2858 (_.VT (OpNode _.RC:$src1,
2859 (bitconvert (_.LdFrag addr:$src2)))),
2861 AVX512BIBase, EVEX_4V;
2864 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
2865 X86VectorVTInfo _, OpndItins itins,
2866 bit IsCommutable = 0> :
2867 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
2869 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2870 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
2871 "${src2}"##_.BroadcastStr##", $src1",
2872 "$src1, ${src2}"##_.BroadcastStr,
2873 (_.VT (OpNode _.RC:$src1,
2875 (_.ScalarLdFrag addr:$src2)))),
2877 AVX512BIBase, EVEX_4V, EVEX_B;
2880 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2881 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2882 Predicate prd, bit IsCommutable = 0> {
2883 let Predicates = [prd] in
2884 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2885 IsCommutable>, EVEX_V512;
2887 let Predicates = [prd, HasVLX] in {
2888 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2889 IsCommutable>, EVEX_V256;
2890 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2891 IsCommutable>, EVEX_V128;
2895 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2896 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2897 Predicate prd, bit IsCommutable = 0> {
2898 let Predicates = [prd] in
2899 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2900 IsCommutable>, EVEX_V512;
2902 let Predicates = [prd, HasVLX] in {
2903 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2904 IsCommutable>, EVEX_V256;
2905 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2906 IsCommutable>, EVEX_V128;
2910 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
2911 OpndItins itins, Predicate prd,
2912 bit IsCommutable = 0> {
2913 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
2914 itins, prd, IsCommutable>,
2915 VEX_W, EVEX_CD8<64, CD8VF>;
2918 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
2919 OpndItins itins, Predicate prd,
2920 bit IsCommutable = 0> {
2921 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
2922 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
2925 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
2926 OpndItins itins, Predicate prd,
2927 bit IsCommutable = 0> {
2928 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
2929 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
2932 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
2933 OpndItins itins, Predicate prd,
2934 bit IsCommutable = 0> {
2935 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
2936 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
2939 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
2940 SDNode OpNode, OpndItins itins, Predicate prd,
2941 bit IsCommutable = 0> {
2942 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr, OpNode, itins, prd,
2945 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr, OpNode, itins, prd,
2949 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
2950 SDNode OpNode, OpndItins itins, Predicate prd,
2951 bit IsCommutable = 0> {
2952 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr, OpNode, itins, prd,
2955 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr, OpNode, itins, prd,
2959 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
2960 bits<8> opc_d, bits<8> opc_q,
2961 string OpcodeStr, SDNode OpNode,
2962 OpndItins itins, bit IsCommutable = 0> {
2963 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
2964 itins, HasAVX512, IsCommutable>,
2965 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
2966 itins, HasBWI, IsCommutable>;
2969 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
2970 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
2971 PatFrag memop_frag, X86MemOperand x86memop,
2972 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
2973 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
2974 let isCommutable = IsCommutable in
2976 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2977 (ins RC:$src1, RC:$src2),
2978 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2980 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2981 (ins KRC:$mask, RC:$src1, RC:$src2),
2982 !strconcat(OpcodeStr,
2983 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2984 [], itins.rr>, EVEX_4V, EVEX_K;
2985 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2986 (ins KRC:$mask, RC:$src1, RC:$src2),
2987 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}} {z}" ,
2988 "|$dst {${mask}} {z}, $src1, $src2}"),
2989 [], itins.rr>, EVEX_4V, EVEX_KZ;
2991 let mayLoad = 1 in {
2992 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2993 (ins RC:$src1, x86memop:$src2),
2994 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2996 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2997 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2998 !strconcat(OpcodeStr,
2999 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
3000 [], itins.rm>, EVEX_4V, EVEX_K;
3001 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3002 (ins KRC:$mask, RC:$src1, x86memop:$src2),
3003 !strconcat(OpcodeStr,
3004 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
3005 [], itins.rm>, EVEX_4V, EVEX_KZ;
3006 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3007 (ins RC:$src1, x86scalar_mop:$src2),
3008 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
3009 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
3010 [], itins.rm>, EVEX_4V, EVEX_B;
3011 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3012 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
3013 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
3014 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
3016 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
3017 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3018 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
3019 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
3020 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
3022 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
3026 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
3027 SSE_INTALU_ITINS_P, 1>;
3028 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
3029 SSE_INTALU_ITINS_P, 0>;
3030 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmull", mul,
3031 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3032 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmull", mul,
3033 SSE_INTALU_ITINS_P, HasBWI, 1>;
3034 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmull", mul,
3035 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
3037 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
3038 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
3039 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
3040 EVEX_CD8<64, CD8VF>, VEX_W;
3042 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
3043 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
3044 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
3046 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
3047 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
3049 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
3050 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3051 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
3052 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
3053 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3054 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
3056 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxs", X86smax,
3057 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3058 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxs", X86smax,
3059 SSE_INTALU_ITINS_P, HasBWI, 1>;
3060 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", X86smax,
3061 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3063 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxu", X86umax,
3064 SSE_INTALU_ITINS_P, HasBWI, 1>;
3065 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxu", X86umax,
3066 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3067 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", X86umax,
3068 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3070 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpmins", X86smin,
3071 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3072 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpmins", X86smin,
3073 SSE_INTALU_ITINS_P, HasBWI, 1>;
3074 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", X86smin,
3075 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3077 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminu", X86umin,
3078 SSE_INTALU_ITINS_P, HasBWI, 1>;
3079 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminu", X86umin,
3080 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3081 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", X86umin,
3082 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3084 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
3085 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3086 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
3087 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
3088 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3089 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
3090 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
3091 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3092 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
3093 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
3094 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3095 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
3096 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
3097 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3098 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
3099 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
3100 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3101 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
3102 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
3103 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3104 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
3105 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
3106 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3107 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
3108 //===----------------------------------------------------------------------===//
3109 // AVX-512 - Unpack Instructions
3110 //===----------------------------------------------------------------------===//
3112 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
3113 PatFrag mem_frag, RegisterClass RC,
3114 X86MemOperand x86memop, string asm,
3116 def rr : AVX512PI<opc, MRMSrcReg,
3117 (outs RC:$dst), (ins RC:$src1, RC:$src2),
3119 (vt (OpNode RC:$src1, RC:$src2)))],
3121 def rm : AVX512PI<opc, MRMSrcMem,
3122 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3124 (vt (OpNode RC:$src1,
3125 (bitconvert (mem_frag addr:$src2)))))],
3129 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
3130 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3131 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3132 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
3133 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3134 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3135 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
3136 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3137 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3138 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
3139 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3140 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3142 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
3143 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
3144 X86MemOperand x86memop> {
3145 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3146 (ins RC:$src1, RC:$src2),
3147 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3148 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
3149 IIC_SSE_UNPCK>, EVEX_4V;
3150 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3151 (ins RC:$src1, x86memop:$src2),
3152 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3153 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
3154 (bitconvert (memop_frag addr:$src2)))))],
3155 IIC_SSE_UNPCK>, EVEX_4V;
3157 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
3158 VR512, memopv16i32, i512mem>, EVEX_V512,
3159 EVEX_CD8<32, CD8VF>;
3160 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
3161 VR512, memopv8i64, i512mem>, EVEX_V512,
3162 VEX_W, EVEX_CD8<64, CD8VF>;
3163 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
3164 VR512, memopv16i32, i512mem>, EVEX_V512,
3165 EVEX_CD8<32, CD8VF>;
3166 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
3167 VR512, memopv8i64, i512mem>, EVEX_V512,
3168 VEX_W, EVEX_CD8<64, CD8VF>;
3169 //===----------------------------------------------------------------------===//
3173 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
3174 SDNode OpNode, PatFrag mem_frag,
3175 X86MemOperand x86memop, ValueType OpVT> {
3176 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
3177 (ins RC:$src1, u8imm:$src2),
3178 !strconcat(OpcodeStr,
3179 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3181 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
3183 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
3184 (ins x86memop:$src1, u8imm:$src2),
3185 !strconcat(OpcodeStr,
3186 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3188 (OpVT (OpNode (mem_frag addr:$src1),
3189 (i8 imm:$src2))))]>, EVEX;
3192 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
3193 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
3195 //===----------------------------------------------------------------------===//
3196 // AVX-512 Logical Instructions
3197 //===----------------------------------------------------------------------===//
3199 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
3200 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3201 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
3202 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3203 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
3204 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3205 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
3206 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3208 //===----------------------------------------------------------------------===//
3209 // AVX-512 FP arithmetic
3210 //===----------------------------------------------------------------------===//
3212 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3214 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
3215 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
3216 EVEX_CD8<32, CD8VT1>;
3217 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
3218 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
3219 EVEX_CD8<64, CD8VT1>;
3222 let isCommutable = 1 in {
3223 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
3224 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
3225 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
3226 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
3228 let isCommutable = 0 in {
3229 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
3230 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
3233 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3234 X86VectorVTInfo _, bit IsCommutable> {
3235 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3236 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3237 "$src2, $src1", "$src1, $src2",
3238 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
3239 let mayLoad = 1 in {
3240 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3241 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3242 "$src2, $src1", "$src1, $src2",
3243 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3244 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3245 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3246 "${src2}"##_.BroadcastStr##", $src1",
3247 "$src1, ${src2}"##_.BroadcastStr,
3248 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3249 (_.ScalarLdFrag addr:$src2))))>,
3254 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3255 bit IsCommutable = 0> {
3256 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3257 IsCommutable>, EVEX_V512, PS,
3258 EVEX_CD8<32, CD8VF>;
3259 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3260 IsCommutable>, EVEX_V512, PD, VEX_W,
3261 EVEX_CD8<64, CD8VF>;
3263 // Define only if AVX512VL feature is present.
3264 let Predicates = [HasVLX] in {
3265 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3266 IsCommutable>, EVEX_V128, PS,
3267 EVEX_CD8<32, CD8VF>;
3268 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3269 IsCommutable>, EVEX_V256, PS,
3270 EVEX_CD8<32, CD8VF>;
3271 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3272 IsCommutable>, EVEX_V128, PD, VEX_W,
3273 EVEX_CD8<64, CD8VF>;
3274 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3275 IsCommutable>, EVEX_V256, PD, VEX_W,
3276 EVEX_CD8<64, CD8VF>;
3280 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>;
3281 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>;
3282 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>;
3283 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>;
3284 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>;
3285 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>;
3287 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
3288 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3289 (i16 -1), FROUND_CURRENT)),
3290 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
3292 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
3293 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3294 (i8 -1), FROUND_CURRENT)),
3295 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
3297 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
3298 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3299 (i16 -1), FROUND_CURRENT)),
3300 (VMINPSZrr VR512:$src1, VR512:$src2)>;
3302 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
3303 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3304 (i8 -1), FROUND_CURRENT)),
3305 (VMINPDZrr VR512:$src1, VR512:$src2)>;
3306 //===----------------------------------------------------------------------===//
3307 // AVX-512 VPTESTM instructions
3308 //===----------------------------------------------------------------------===//
3310 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3311 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
3312 SDNode OpNode, ValueType vt> {
3313 def rr : AVX512PI<opc, MRMSrcReg,
3314 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
3315 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3316 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
3317 SSEPackedInt>, EVEX_4V;
3318 def rm : AVX512PI<opc, MRMSrcMem,
3319 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
3320 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3321 [(set KRC:$dst, (OpNode (vt RC:$src1),
3322 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
3325 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
3326 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
3327 EVEX_CD8<32, CD8VF>;
3328 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
3329 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
3330 EVEX_CD8<64, CD8VF>;
3332 let Predicates = [HasCDI] in {
3333 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
3334 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
3335 EVEX_CD8<32, CD8VF>;
3336 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
3337 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
3338 EVEX_CD8<64, CD8VF>;
3341 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3342 (v16i32 VR512:$src2), (i16 -1))),
3343 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3345 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3346 (v8i64 VR512:$src2), (i8 -1))),
3347 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3349 //===----------------------------------------------------------------------===//
3350 // AVX-512 Shift instructions
3351 //===----------------------------------------------------------------------===//
3352 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3353 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3354 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
3355 (ins _.RC:$src1, u8imm:$src2), OpcodeStr,
3356 "$src2, $src1", "$src1, $src2",
3357 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
3358 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIi8Base, EVEX_4V;
3359 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3360 (ins _.MemOp:$src1, u8imm:$src2), OpcodeStr,
3361 "$src2, $src1", "$src1, $src2",
3362 (_.VT (OpNode (_.MemOpFrag addr:$src1), (i8 imm:$src2))),
3363 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIi8Base, EVEX_4V;
3366 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3367 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3368 // src2 is always 128-bit
3369 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3370 (ins _.RC:$src1, VR128X:$src2), OpcodeStr,
3371 "$src2, $src1", "$src1, $src2",
3372 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))),
3373 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V;
3374 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3375 (ins _.RC:$src1, i128mem:$src2), OpcodeStr,
3376 "$src2, $src1", "$src1, $src2",
3377 (_.VT (OpNode _.RC:$src1, (bc_frag (memopv2i64 addr:$src2)))),
3378 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase, EVEX_4V;
3381 multiclass avx512_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3382 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3383 defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag, _>, EVEX_V512;
3386 multiclass avx512_shift_types<bits<8> opcd, bits<8> opcq, string OpcodeStr,
3388 defm D : avx512_shift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,
3389 v16i32_info>, EVEX_CD8<32, CD8VQ>;
3390 defm Q : avx512_shift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,
3391 v8i64_info>, EVEX_CD8<64, CD8VQ>, VEX_W;
3394 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
3396 EVEX_V512, EVEX_CD8<32, CD8VF>;
3397 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
3398 v8i64_info>, EVEX_V512,
3399 EVEX_CD8<64, CD8VF>, VEX_W;
3401 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
3402 v16i32_info>, EVEX_V512,
3403 EVEX_CD8<32, CD8VF>;
3404 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
3405 v8i64_info>, EVEX_V512,
3406 EVEX_CD8<64, CD8VF>, VEX_W;
3408 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
3410 EVEX_V512, EVEX_CD8<32, CD8VF>;
3411 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
3412 v8i64_info>, EVEX_V512,
3413 EVEX_CD8<64, CD8VF>, VEX_W;
3415 defm VPSLL : avx512_shift_types<0xF2, 0xF3, "vpsll", X86vshl>;
3416 defm VPSRA : avx512_shift_types<0xE2, 0xE2, "vpsra", X86vsra>;
3417 defm VPSRL : avx512_shift_types<0xD2, 0xD3, "vpsrl", X86vsrl>;
3419 //===-------------------------------------------------------------------===//
3420 // Variable Bit Shifts
3421 //===-------------------------------------------------------------------===//
3422 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3423 X86VectorVTInfo _> {
3424 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3425 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3426 "$src2, $src1", "$src1, $src2",
3427 (_.VT (OpNode _.RC:$src1, (_.VT _.RC:$src2))),
3428 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX5128IBase, EVEX_4V;
3429 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3430 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3431 "$src2, $src1", "$src1, $src2",
3432 (_.VT (OpNode _.RC:$src1, (_.MemOpFrag addr:$src2))),
3433 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_4V;
3436 multiclass avx512_var_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3437 AVX512VLVectorVTInfo _> {
3438 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3441 multiclass avx512_var_shift_types<bits<8> opc, string OpcodeStr,
3443 defm D : avx512_var_shift_sizes<opc, OpcodeStr#"d", OpNode,
3444 avx512vl_i32_info>, EVEX_CD8<32, CD8VQ>;
3445 defm Q : avx512_var_shift_sizes<opc, OpcodeStr#"q", OpNode,
3446 avx512vl_i64_info>, EVEX_CD8<64, CD8VQ>, VEX_W;
3449 defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl>;
3450 defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra>;
3451 defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl>;
3453 //===----------------------------------------------------------------------===//
3454 // AVX-512 - MOVDDUP
3455 //===----------------------------------------------------------------------===//
3457 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3458 X86MemOperand x86memop, PatFrag memop_frag> {
3459 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3460 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3461 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3462 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3463 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3465 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3468 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
3469 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3470 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3471 (VMOVDDUPZrm addr:$src)>;
3473 //===---------------------------------------------------------------------===//
3474 // Replicate Single FP - MOVSHDUP and MOVSLDUP
3475 //===---------------------------------------------------------------------===//
3476 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3477 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3478 X86MemOperand x86memop> {
3479 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3480 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3481 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3483 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3484 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3485 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3488 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3489 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3490 EVEX_CD8<32, CD8VF>;
3491 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3492 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3493 EVEX_CD8<32, CD8VF>;
3495 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3496 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
3497 (VMOVSHDUPZrm addr:$src)>;
3498 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3499 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
3500 (VMOVSLDUPZrm addr:$src)>;
3502 //===----------------------------------------------------------------------===//
3503 // Move Low to High and High to Low packed FP Instructions
3504 //===----------------------------------------------------------------------===//
3505 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3506 (ins VR128X:$src1, VR128X:$src2),
3507 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3508 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3509 IIC_SSE_MOV_LH>, EVEX_4V;
3510 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3511 (ins VR128X:$src1, VR128X:$src2),
3512 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3513 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3514 IIC_SSE_MOV_LH>, EVEX_4V;
3516 let Predicates = [HasAVX512] in {
3518 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3519 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3520 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3521 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
3524 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3525 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3528 //===----------------------------------------------------------------------===//
3529 // FMA - Fused Multiply Operations
3532 let Constraints = "$src1 = $dst" in {
3533 // Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
3534 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
3535 SDPatternOperator OpNode = null_frag> {
3536 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3537 (ins _.RC:$src2, _.RC:$src3),
3538 OpcodeStr, "$src3, $src2", "$src2, $src3",
3539 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
3543 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
3544 (ins _.RC:$src2, _.MemOp:$src3),
3545 OpcodeStr, "$src3, $src2", "$src2, $src3",
3546 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (_.LdFrag addr:$src3)))>,
3549 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
3550 (ins _.RC:$src2, _.ScalarMemOp:$src3),
3551 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"), !strconcat("$src2, ${src3}", _.BroadcastStr ),
3552 (OpNode _.RC:$src1, _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))>,
3553 AVX512FMA3Base, EVEX_B;
3555 } // Constraints = "$src1 = $dst"
3557 multiclass avx512_fma3p_forms<bits<8> opc213, bits<8> opc231,
3558 string OpcodeStr, X86VectorVTInfo VTI,
3559 SDPatternOperator OpNode> {
3560 defm v213r : avx512_fma3p_rm<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
3561 VTI, OpNode>, EVEX_CD8<VTI.EltSize, CD8VF>;
3563 defm v231r : avx512_fma3p_rm<opc231, !strconcat(OpcodeStr, "231", VTI.Suffix),
3564 VTI>, EVEX_CD8<VTI.EltSize, CD8VF>;
3567 multiclass avx512_fma3p<bits<8> opc213, bits<8> opc231,
3569 SDPatternOperator OpNode> {
3570 let ExeDomain = SSEPackedSingle in {
3571 defm NAME##PSZ : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3572 v16f32_info, OpNode>, EVEX_V512;
3573 defm NAME##PSZ256 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3574 v8f32x_info, OpNode>, EVEX_V256;
3575 defm NAME##PSZ128 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3576 v4f32x_info, OpNode>, EVEX_V128;
3578 let ExeDomain = SSEPackedDouble in {
3579 defm NAME##PDZ : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3580 v8f64_info, OpNode>, EVEX_V512, VEX_W;
3581 defm NAME##PDZ256 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3582 v4f64x_info, OpNode>, EVEX_V256, VEX_W;
3583 defm NAME##PDZ128 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3584 v2f64x_info, OpNode>, EVEX_V128, VEX_W;
3588 defm VFMADD : avx512_fma3p<0xA8, 0xB8, "vfmadd", X86Fmadd>;
3589 defm VFMSUB : avx512_fma3p<0xAA, 0xBA, "vfmsub", X86Fmsub>;
3590 defm VFMADDSUB : avx512_fma3p<0xA6, 0xB6, "vfmaddsub", X86Fmaddsub>;
3591 defm VFMSUBADD : avx512_fma3p<0xA7, 0xB7, "vfmsubadd", X86Fmsubadd>;
3592 defm VFNMADD : avx512_fma3p<0xAC, 0xBC, "vfnmadd", X86Fnmadd>;
3593 defm VFNMSUB : avx512_fma3p<0xAE, 0xBE, "vfnmsub", X86Fnmsub>;
3595 let Constraints = "$src1 = $dst" in {
3596 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
3597 X86VectorVTInfo _> {
3599 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3600 (ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2),
3601 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
3602 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.MemOpFrag addr:$src2),
3604 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3605 (ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2),
3606 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr,
3607 ", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"),
3609 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3610 (_.ScalarLdFrag addr:$src2))),
3611 _.RC:$src3))]>, EVEX_B;
3613 } // Constraints = "$src1 = $dst"
3616 multiclass avx512_fma3p_m132_f<bits<8> opc,
3620 let ExeDomain = SSEPackedSingle in {
3621 defm NAME##PSZ : avx512_fma3p_m132<opc, OpcodeStr##ps,
3622 OpNode,v16f32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3623 defm NAME##PSZ256 : avx512_fma3p_m132<opc, OpcodeStr##ps,
3624 OpNode, v8f32x_info>, EVEX_V256, EVEX_CD8<32, CD8VF>;
3625 defm NAME##PSZ128 : avx512_fma3p_m132<opc, OpcodeStr##ps,
3626 OpNode, v4f32x_info>, EVEX_V128, EVEX_CD8<32, CD8VF>;
3628 let ExeDomain = SSEPackedDouble in {
3629 defm NAME##PDZ : avx512_fma3p_m132<opc, OpcodeStr##pd,
3630 OpNode, v8f64_info>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VF>;
3631 defm NAME##PDZ256 : avx512_fma3p_m132<opc, OpcodeStr##pd,
3632 OpNode, v4f64x_info>, EVEX_V256, VEX_W, EVEX_CD8<32, CD8VF>;
3633 defm NAME##PDZ128 : avx512_fma3p_m132<opc, OpcodeStr##pd,
3634 OpNode, v2f64x_info>, EVEX_V128, VEX_W, EVEX_CD8<32, CD8VF>;
3638 defm VFMADD132 : avx512_fma3p_m132_f<0x98, "vfmadd132", X86Fmadd>;
3639 defm VFMSUB132 : avx512_fma3p_m132_f<0x9A, "vfmsub132", X86Fmsub>;
3640 defm VFMADDSUB132 : avx512_fma3p_m132_f<0x96, "vfmaddsub132", X86Fmaddsub>;
3641 defm VFMSUBADD132 : avx512_fma3p_m132_f<0x97, "vfmsubadd132", X86Fmsubadd>;
3642 defm VFNMADD132 : avx512_fma3p_m132_f<0x9C, "vfnmadd132", X86Fnmadd>;
3643 defm VFNMSUB132 : avx512_fma3p_m132_f<0x9E, "vfnmsub132", X86Fnmsub>;
3647 let Constraints = "$src1 = $dst" in {
3648 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3649 RegisterClass RC, ValueType OpVT,
3650 X86MemOperand x86memop, Operand memop,
3652 let isCommutable = 1 in
3653 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
3654 (ins RC:$src1, RC:$src2, RC:$src3),
3655 !strconcat(OpcodeStr,
3656 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3658 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
3660 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3661 (ins RC:$src1, RC:$src2, f128mem:$src3),
3662 !strconcat(OpcodeStr,
3663 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3665 (OpVT (OpNode RC:$src2, RC:$src1,
3666 (mem_frag addr:$src3))))]>;
3669 } // Constraints = "$src1 = $dst"
3671 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
3672 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3673 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
3674 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3675 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
3676 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3677 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
3678 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3679 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
3680 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3681 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
3682 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3683 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
3684 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3685 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
3686 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3688 //===----------------------------------------------------------------------===//
3689 // AVX-512 Scalar convert from sign integer to float/double
3690 //===----------------------------------------------------------------------===//
3692 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3693 X86MemOperand x86memop, string asm> {
3694 let hasSideEffects = 0 in {
3695 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
3696 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3699 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
3700 (ins DstRC:$src1, x86memop:$src),
3701 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3703 } // hasSideEffects = 0
3705 let Predicates = [HasAVX512] in {
3706 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
3707 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3708 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
3709 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3710 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
3711 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3712 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
3713 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3715 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
3716 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3717 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
3718 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3719 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
3720 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3721 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
3722 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3724 def : Pat<(f32 (sint_to_fp GR32:$src)),
3725 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3726 def : Pat<(f32 (sint_to_fp GR64:$src)),
3727 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3728 def : Pat<(f64 (sint_to_fp GR32:$src)),
3729 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3730 def : Pat<(f64 (sint_to_fp GR64:$src)),
3731 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3733 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
3734 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3735 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
3736 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3737 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
3738 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3739 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
3740 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3742 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
3743 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3744 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
3745 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3746 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
3747 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3748 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
3749 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3751 def : Pat<(f32 (uint_to_fp GR32:$src)),
3752 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3753 def : Pat<(f32 (uint_to_fp GR64:$src)),
3754 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3755 def : Pat<(f64 (uint_to_fp GR32:$src)),
3756 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3757 def : Pat<(f64 (uint_to_fp GR64:$src)),
3758 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3761 //===----------------------------------------------------------------------===//
3762 // AVX-512 Scalar convert from float/double to integer
3763 //===----------------------------------------------------------------------===//
3764 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3765 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
3767 let hasSideEffects = 0 in {
3768 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3769 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3770 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
3771 Requires<[HasAVX512]>;
3773 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
3774 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
3775 Requires<[HasAVX512]>;
3776 } // hasSideEffects = 0
3778 let Predicates = [HasAVX512] in {
3779 // Convert float/double to signed/unsigned int 32/64
3780 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
3781 ssmem, sse_load_f32, "cvtss2si">,
3782 XS, EVEX_CD8<32, CD8VT1>;
3783 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
3784 ssmem, sse_load_f32, "cvtss2si">,
3785 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3786 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
3787 ssmem, sse_load_f32, "cvtss2usi">,
3788 XS, EVEX_CD8<32, CD8VT1>;
3789 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3790 int_x86_avx512_cvtss2usi64, ssmem,
3791 sse_load_f32, "cvtss2usi">, XS, VEX_W,
3792 EVEX_CD8<32, CD8VT1>;
3793 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
3794 sdmem, sse_load_f64, "cvtsd2si">,
3795 XD, EVEX_CD8<64, CD8VT1>;
3796 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
3797 sdmem, sse_load_f64, "cvtsd2si">,
3798 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3799 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
3800 sdmem, sse_load_f64, "cvtsd2usi">,
3801 XD, EVEX_CD8<64, CD8VT1>;
3802 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3803 int_x86_avx512_cvtsd2usi64, sdmem,
3804 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
3805 EVEX_CD8<64, CD8VT1>;
3807 let isCodeGenOnly = 1 in {
3808 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3809 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3810 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3811 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3812 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3813 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3814 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3815 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3816 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3817 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3818 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3819 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3821 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3822 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3823 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3824 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3825 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3826 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3827 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3828 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3829 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3830 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3831 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3832 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3833 } // isCodeGenOnly = 1
3835 // Convert float/double to signed/unsigned int 32/64 with truncation
3836 let isCodeGenOnly = 1 in {
3837 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3838 ssmem, sse_load_f32, "cvttss2si">,
3839 XS, EVEX_CD8<32, CD8VT1>;
3840 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3841 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3842 "cvttss2si">, XS, VEX_W,
3843 EVEX_CD8<32, CD8VT1>;
3844 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3845 sdmem, sse_load_f64, "cvttsd2si">, XD,
3846 EVEX_CD8<64, CD8VT1>;
3847 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3848 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3849 "cvttsd2si">, XD, VEX_W,
3850 EVEX_CD8<64, CD8VT1>;
3851 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3852 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3853 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3854 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3855 int_x86_avx512_cvttss2usi64, ssmem,
3856 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3857 EVEX_CD8<32, CD8VT1>;
3858 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3859 int_x86_avx512_cvttsd2usi,
3860 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3861 EVEX_CD8<64, CD8VT1>;
3862 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3863 int_x86_avx512_cvttsd2usi64, sdmem,
3864 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3865 EVEX_CD8<64, CD8VT1>;
3866 } // isCodeGenOnly = 1
3868 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3869 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3871 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3872 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3873 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3874 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3875 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3876 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3879 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
3880 loadf32, "cvttss2si">, XS,
3881 EVEX_CD8<32, CD8VT1>;
3882 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
3883 loadf32, "cvttss2usi">, XS,
3884 EVEX_CD8<32, CD8VT1>;
3885 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
3886 loadf32, "cvttss2si">, XS, VEX_W,
3887 EVEX_CD8<32, CD8VT1>;
3888 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
3889 loadf32, "cvttss2usi">, XS, VEX_W,
3890 EVEX_CD8<32, CD8VT1>;
3891 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
3892 loadf64, "cvttsd2si">, XD,
3893 EVEX_CD8<64, CD8VT1>;
3894 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
3895 loadf64, "cvttsd2usi">, XD,
3896 EVEX_CD8<64, CD8VT1>;
3897 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
3898 loadf64, "cvttsd2si">, XD, VEX_W,
3899 EVEX_CD8<64, CD8VT1>;
3900 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
3901 loadf64, "cvttsd2usi">, XD, VEX_W,
3902 EVEX_CD8<64, CD8VT1>;
3904 //===----------------------------------------------------------------------===//
3905 // AVX-512 Convert form float to double and back
3906 //===----------------------------------------------------------------------===//
3907 let hasSideEffects = 0 in {
3908 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3909 (ins FR32X:$src1, FR32X:$src2),
3910 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3911 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3913 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3914 (ins FR32X:$src1, f32mem:$src2),
3915 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3916 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3917 EVEX_CD8<32, CD8VT1>;
3919 // Convert scalar double to scalar single
3920 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3921 (ins FR64X:$src1, FR64X:$src2),
3922 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3923 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3925 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3926 (ins FR64X:$src1, f64mem:$src2),
3927 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3928 []>, EVEX_4V, VEX_LIG, VEX_W,
3929 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3932 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3933 Requires<[HasAVX512]>;
3934 def : Pat<(fextend (loadf32 addr:$src)),
3935 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3937 def : Pat<(extloadf32 addr:$src),
3938 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3939 Requires<[HasAVX512, OptForSize]>;
3941 def : Pat<(extloadf32 addr:$src),
3942 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3943 Requires<[HasAVX512, OptForSpeed]>;
3945 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3946 Requires<[HasAVX512]>;
3948 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
3949 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3950 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3952 let hasSideEffects = 0 in {
3953 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3954 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3956 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3957 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3958 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
3959 [], d>, EVEX, EVEX_B, EVEX_RC;
3961 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3962 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3964 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3965 } // hasSideEffects = 0
3968 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
3969 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3970 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3972 let hasSideEffects = 0 in {
3973 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3974 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3976 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3978 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3979 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3981 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3982 } // hasSideEffects = 0
3985 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
3986 memopv8f64, f512mem, v8f32, v8f64,
3987 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
3988 EVEX_CD8<64, CD8VF>;
3990 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3991 memopv4f64, f256mem, v8f64, v8f32,
3992 SSEPackedDouble>, EVEX_V512, PS,
3993 EVEX_CD8<32, CD8VH>;
3994 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3995 (VCVTPS2PDZrm addr:$src)>;
3997 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3998 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3999 (VCVTPD2PSZrr VR512:$src)>;
4001 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
4002 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
4003 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
4005 //===----------------------------------------------------------------------===//
4006 // AVX-512 Vector convert from sign integer to float/double
4007 //===----------------------------------------------------------------------===//
4009 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
4010 memopv8i64, i512mem, v16f32, v16i32,
4011 SSEPackedSingle>, EVEX_V512, PS,
4012 EVEX_CD8<32, CD8VF>;
4014 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
4015 memopv4i64, i256mem, v8f64, v8i32,
4016 SSEPackedDouble>, EVEX_V512, XS,
4017 EVEX_CD8<32, CD8VH>;
4019 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
4020 memopv16f32, f512mem, v16i32, v16f32,
4021 SSEPackedSingle>, EVEX_V512, XS,
4022 EVEX_CD8<32, CD8VF>;
4024 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
4025 memopv8f64, f512mem, v8i32, v8f64,
4026 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
4027 EVEX_CD8<64, CD8VF>;
4029 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
4030 memopv16f32, f512mem, v16i32, v16f32,
4031 SSEPackedSingle>, EVEX_V512, PS,
4032 EVEX_CD8<32, CD8VF>;
4034 // cvttps2udq (src, 0, mask-all-ones, sae-current)
4035 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
4036 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
4037 (VCVTTPS2UDQZrr VR512:$src)>;
4039 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
4040 memopv8f64, f512mem, v8i32, v8f64,
4041 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
4042 EVEX_CD8<64, CD8VF>;
4044 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
4045 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
4046 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
4047 (VCVTTPD2UDQZrr VR512:$src)>;
4049 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
4050 memopv4i64, f256mem, v8f64, v8i32,
4051 SSEPackedDouble>, EVEX_V512, XS,
4052 EVEX_CD8<32, CD8VH>;
4054 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
4055 memopv16i32, f512mem, v16f32, v16i32,
4056 SSEPackedSingle>, EVEX_V512, XD,
4057 EVEX_CD8<32, CD8VF>;
4059 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
4060 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
4061 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
4063 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
4064 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
4065 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
4067 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
4068 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
4069 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
4071 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
4072 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
4073 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
4075 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
4076 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
4077 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
4079 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
4080 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
4081 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
4082 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
4083 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4084 (VCVTDQ2PDZrr VR256X:$src)>;
4085 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
4086 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
4087 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
4088 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
4089 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4090 (VCVTUDQ2PDZrr VR256X:$src)>;
4092 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
4093 RegisterClass DstRC, PatFrag mem_frag,
4094 X86MemOperand x86memop, Domain d> {
4095 let hasSideEffects = 0 in {
4096 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4097 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4099 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4100 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
4101 [], d>, EVEX, EVEX_B, EVEX_RC;
4103 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4104 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4106 } // hasSideEffects = 0
4109 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
4110 memopv16f32, f512mem, SSEPackedSingle>, PD,
4111 EVEX_V512, EVEX_CD8<32, CD8VF>;
4112 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
4113 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
4114 EVEX_V512, EVEX_CD8<64, CD8VF>;
4116 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
4117 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4118 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
4120 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
4121 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4122 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
4124 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
4125 memopv16f32, f512mem, SSEPackedSingle>,
4126 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4127 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
4128 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
4129 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
4131 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
4132 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4133 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
4135 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
4136 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4137 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
4139 let Predicates = [HasAVX512] in {
4140 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
4141 (VCVTPD2PSZrm addr:$src)>;
4142 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
4143 (VCVTPS2PDZrm addr:$src)>;
4146 //===----------------------------------------------------------------------===//
4147 // Half precision conversion instructions
4148 //===----------------------------------------------------------------------===//
4149 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
4150 X86MemOperand x86memop> {
4151 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
4152 "vcvtph2ps\t{$src, $dst|$dst, $src}",
4154 let hasSideEffects = 0, mayLoad = 1 in
4155 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
4156 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
4159 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
4160 X86MemOperand x86memop> {
4161 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
4162 (ins srcRC:$src1, i32u8imm:$src2),
4163 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4165 let hasSideEffects = 0, mayStore = 1 in
4166 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
4167 (ins x86memop:$dst, srcRC:$src1, i32u8imm:$src2),
4168 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
4171 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
4172 EVEX_CD8<32, CD8VH>;
4173 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
4174 EVEX_CD8<32, CD8VH>;
4176 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
4177 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
4178 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
4180 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
4181 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
4182 (VCVTPH2PSZrr VR256X:$src)>;
4184 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
4185 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
4186 "ucomiss">, PS, EVEX, VEX_LIG,
4187 EVEX_CD8<32, CD8VT1>;
4188 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
4189 "ucomisd">, PD, EVEX,
4190 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4191 let Pattern = []<dag> in {
4192 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
4193 "comiss">, PS, EVEX, VEX_LIG,
4194 EVEX_CD8<32, CD8VT1>;
4195 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
4196 "comisd">, PD, EVEX,
4197 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4199 let isCodeGenOnly = 1 in {
4200 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
4201 load, "ucomiss">, PS, EVEX, VEX_LIG,
4202 EVEX_CD8<32, CD8VT1>;
4203 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
4204 load, "ucomisd">, PD, EVEX,
4205 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4207 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
4208 load, "comiss">, PS, EVEX, VEX_LIG,
4209 EVEX_CD8<32, CD8VT1>;
4210 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
4211 load, "comisd">, PD, EVEX,
4212 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4216 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
4217 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4218 X86MemOperand x86memop> {
4219 let hasSideEffects = 0 in {
4220 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4221 (ins RC:$src1, RC:$src2),
4222 !strconcat(OpcodeStr,
4223 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4224 let mayLoad = 1 in {
4225 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4226 (ins RC:$src1, x86memop:$src2),
4227 !strconcat(OpcodeStr,
4228 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4233 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
4234 EVEX_CD8<32, CD8VT1>;
4235 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
4236 VEX_W, EVEX_CD8<64, CD8VT1>;
4237 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
4238 EVEX_CD8<32, CD8VT1>;
4239 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
4240 VEX_W, EVEX_CD8<64, CD8VT1>;
4242 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
4243 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4244 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4245 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4247 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
4248 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4249 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4250 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4252 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
4253 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4254 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4255 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4257 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
4258 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4259 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4260 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4262 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
4263 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
4264 X86VectorVTInfo _> {
4265 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4266 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4267 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
4268 let mayLoad = 1 in {
4269 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4270 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4272 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
4273 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4274 (ins _.ScalarMemOp:$src), OpcodeStr,
4275 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4277 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4282 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4283 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
4284 EVEX_V512, EVEX_CD8<32, CD8VF>;
4285 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
4286 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4288 // Define only if AVX512VL feature is present.
4289 let Predicates = [HasVLX] in {
4290 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4291 OpNode, v4f32x_info>,
4292 EVEX_V128, EVEX_CD8<32, CD8VF>;
4293 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4294 OpNode, v8f32x_info>,
4295 EVEX_V256, EVEX_CD8<32, CD8VF>;
4296 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4297 OpNode, v2f64x_info>,
4298 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
4299 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4300 OpNode, v4f64x_info>,
4301 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
4305 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
4306 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
4308 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
4309 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4310 (VRSQRT14PSZr VR512:$src)>;
4311 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
4312 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4313 (VRSQRT14PDZr VR512:$src)>;
4315 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
4316 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4317 (VRCP14PSZr VR512:$src)>;
4318 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
4319 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4320 (VRCP14PDZr VR512:$src)>;
4322 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
4323 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
4326 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4327 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4328 "$src2, $src1", "$src1, $src2",
4329 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4330 (i32 FROUND_CURRENT))>;
4332 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4333 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4334 "$src2, $src1", "$src1, $src2",
4335 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4336 (i32 FROUND_NO_EXC)), "{sae}">, EVEX_B;
4338 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4339 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
4340 "$src2, $src1", "$src1, $src2",
4341 (OpNode (_.VT _.RC:$src1),
4342 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
4343 (i32 FROUND_CURRENT))>;
4346 multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4347 defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
4348 EVEX_CD8<32, CD8VT1>;
4349 defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>,
4350 EVEX_CD8<64, CD8VT1>, VEX_W;
4353 let hasSideEffects = 0, Predicates = [HasERI] in {
4354 defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V;
4355 defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V;
4357 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
4359 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4362 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4363 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4364 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
4366 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4367 (ins _.RC:$src), OpcodeStr,
4369 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC)),
4372 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4373 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4375 (bitconvert (_.LdFrag addr:$src))),
4376 (i32 FROUND_CURRENT))>;
4378 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4379 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4381 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
4382 (i32 FROUND_CURRENT))>, EVEX_B;
4385 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4386 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
4387 EVEX_CD8<32, CD8VF>;
4388 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
4389 VEX_W, EVEX_CD8<32, CD8VF>;
4392 let Predicates = [HasERI], hasSideEffects = 0 in {
4394 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX, EVEX_V512, T8PD;
4395 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX, EVEX_V512, T8PD;
4396 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX, EVEX_V512, T8PD;
4399 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
4400 SDNode OpNode, X86VectorVTInfo _>{
4401 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4402 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4403 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
4404 let mayLoad = 1 in {
4405 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4406 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4408 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
4410 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4411 (ins _.ScalarMemOp:$src), OpcodeStr,
4412 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4414 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4419 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
4420 Intrinsic F32Int, Intrinsic F64Int,
4421 OpndItins itins_s, OpndItins itins_d> {
4422 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
4423 (ins FR32X:$src1, FR32X:$src2),
4424 !strconcat(OpcodeStr,
4425 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4426 [], itins_s.rr>, XS, EVEX_4V;
4427 let isCodeGenOnly = 1 in
4428 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4429 (ins VR128X:$src1, VR128X:$src2),
4430 !strconcat(OpcodeStr,
4431 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4433 (F32Int VR128X:$src1, VR128X:$src2))],
4434 itins_s.rr>, XS, EVEX_4V;
4435 let mayLoad = 1 in {
4436 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
4437 (ins FR32X:$src1, f32mem:$src2),
4438 !strconcat(OpcodeStr,
4439 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4440 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4441 let isCodeGenOnly = 1 in
4442 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4443 (ins VR128X:$src1, ssmem:$src2),
4444 !strconcat(OpcodeStr,
4445 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4447 (F32Int VR128X:$src1, sse_load_f32:$src2))],
4448 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4450 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
4451 (ins FR64X:$src1, FR64X:$src2),
4452 !strconcat(OpcodeStr,
4453 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4455 let isCodeGenOnly = 1 in
4456 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4457 (ins VR128X:$src1, VR128X:$src2),
4458 !strconcat(OpcodeStr,
4459 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4461 (F64Int VR128X:$src1, VR128X:$src2))],
4462 itins_s.rr>, XD, EVEX_4V, VEX_W;
4463 let mayLoad = 1 in {
4464 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
4465 (ins FR64X:$src1, f64mem:$src2),
4466 !strconcat(OpcodeStr,
4467 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4468 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4469 let isCodeGenOnly = 1 in
4470 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4471 (ins VR128X:$src1, sdmem:$src2),
4472 !strconcat(OpcodeStr,
4473 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4475 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
4476 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4480 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
4482 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
4484 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
4485 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
4487 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4488 // Define only if AVX512VL feature is present.
4489 let Predicates = [HasVLX] in {
4490 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4491 OpNode, v4f32x_info>,
4492 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
4493 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4494 OpNode, v8f32x_info>,
4495 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
4496 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4497 OpNode, v2f64x_info>,
4498 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4499 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4500 OpNode, v4f64x_info>,
4501 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4505 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>;
4507 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
4508 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
4509 SSE_SQRTSS, SSE_SQRTSD>;
4511 let Predicates = [HasAVX512] in {
4512 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
4513 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
4514 (VSQRTPSZr VR512:$src1)>;
4515 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
4516 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
4517 (VSQRTPDZr VR512:$src1)>;
4519 def : Pat<(f32 (fsqrt FR32X:$src)),
4520 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4521 def : Pat<(f32 (fsqrt (load addr:$src))),
4522 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
4523 Requires<[OptForSize]>;
4524 def : Pat<(f64 (fsqrt FR64X:$src)),
4525 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
4526 def : Pat<(f64 (fsqrt (load addr:$src))),
4527 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
4528 Requires<[OptForSize]>;
4530 def : Pat<(f32 (X86frsqrt FR32X:$src)),
4531 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4532 def : Pat<(f32 (X86frsqrt (load addr:$src))),
4533 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4534 Requires<[OptForSize]>;
4536 def : Pat<(f32 (X86frcp FR32X:$src)),
4537 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4538 def : Pat<(f32 (X86frcp (load addr:$src))),
4539 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4540 Requires<[OptForSize]>;
4542 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
4543 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
4544 (COPY_TO_REGCLASS VR128X:$src, FR32)),
4546 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
4547 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
4549 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
4550 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
4551 (COPY_TO_REGCLASS VR128X:$src, FR64)),
4553 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
4554 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
4558 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
4559 X86MemOperand x86memop, RegisterClass RC,
4560 PatFrag mem_frag, Domain d> {
4561 let ExeDomain = d in {
4562 // Intrinsic operation, reg.
4563 // Vector intrinsic operation, reg
4564 def r : AVX512AIi8<opc, MRMSrcReg,
4565 (outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
4566 !strconcat(OpcodeStr,
4567 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4570 // Vector intrinsic operation, mem
4571 def m : AVX512AIi8<opc, MRMSrcMem,
4572 (outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
4573 !strconcat(OpcodeStr,
4574 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4580 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
4581 memopv16f32, SSEPackedSingle>, EVEX_V512,
4582 EVEX_CD8<32, CD8VF>;
4584 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
4585 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
4587 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
4590 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
4591 memopv8f64, SSEPackedDouble>, EVEX_V512,
4592 VEX_W, EVEX_CD8<64, CD8VF>;
4594 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
4595 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
4597 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
4599 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
4600 Operand x86memop, RegisterClass RC, Domain d> {
4601 let ExeDomain = d in {
4602 def r : AVX512AIi8<opc, MRMSrcReg,
4603 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32u8imm:$src3),
4604 !strconcat(OpcodeStr,
4605 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4608 def m : AVX512AIi8<opc, MRMSrcMem,
4609 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32u8imm:$src3),
4610 !strconcat(OpcodeStr,
4611 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4616 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
4617 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
4619 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
4620 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
4622 def : Pat<(ffloor FR32X:$src),
4623 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
4624 def : Pat<(f64 (ffloor FR64X:$src)),
4625 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
4626 def : Pat<(f32 (fnearbyint FR32X:$src)),
4627 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
4628 def : Pat<(f64 (fnearbyint FR64X:$src)),
4629 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
4630 def : Pat<(f32 (fceil FR32X:$src)),
4631 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
4632 def : Pat<(f64 (fceil FR64X:$src)),
4633 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
4634 def : Pat<(f32 (frint FR32X:$src)),
4635 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
4636 def : Pat<(f64 (frint FR64X:$src)),
4637 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
4638 def : Pat<(f32 (ftrunc FR32X:$src)),
4639 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
4640 def : Pat<(f64 (ftrunc FR64X:$src)),
4641 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
4643 def : Pat<(v16f32 (ffloor VR512:$src)),
4644 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
4645 def : Pat<(v16f32 (fnearbyint VR512:$src)),
4646 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
4647 def : Pat<(v16f32 (fceil VR512:$src)),
4648 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
4649 def : Pat<(v16f32 (frint VR512:$src)),
4650 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
4651 def : Pat<(v16f32 (ftrunc VR512:$src)),
4652 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
4654 def : Pat<(v8f64 (ffloor VR512:$src)),
4655 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
4656 def : Pat<(v8f64 (fnearbyint VR512:$src)),
4657 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
4658 def : Pat<(v8f64 (fceil VR512:$src)),
4659 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
4660 def : Pat<(v8f64 (frint VR512:$src)),
4661 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
4662 def : Pat<(v8f64 (ftrunc VR512:$src)),
4663 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
4665 //-------------------------------------------------
4666 // Integer truncate and extend operations
4667 //-------------------------------------------------
4669 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
4670 RegisterClass dstRC, RegisterClass srcRC,
4671 RegisterClass KRC, X86MemOperand x86memop> {
4672 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4674 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
4677 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4678 (ins KRC:$mask, srcRC:$src),
4679 !strconcat(OpcodeStr,
4680 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
4683 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4684 (ins KRC:$mask, srcRC:$src),
4685 !strconcat(OpcodeStr,
4686 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4689 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
4690 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4693 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4694 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4695 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4699 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4700 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4701 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4702 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4703 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4704 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4705 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4706 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4707 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4708 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4709 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4710 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4711 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4712 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4713 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4714 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4715 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4716 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4717 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4718 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4719 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4720 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4721 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4722 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4723 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4724 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4725 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4726 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4727 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4728 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4730 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4731 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4732 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4733 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4734 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4736 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4737 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
4738 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4739 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
4740 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4741 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
4742 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4743 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
4746 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4747 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4748 PatFrag mem_frag, X86MemOperand x86memop,
4749 ValueType OpVT, ValueType InVT> {
4751 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4753 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4754 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
4756 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4757 (ins KRC:$mask, SrcRC:$src),
4758 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4761 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4762 (ins KRC:$mask, SrcRC:$src),
4763 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4766 let mayLoad = 1 in {
4767 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4768 (ins x86memop:$src),
4769 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
4771 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4774 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4775 (ins KRC:$mask, x86memop:$src),
4776 !strconcat(OpcodeStr,"\t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4780 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4781 (ins KRC:$mask, x86memop:$src),
4782 !strconcat(OpcodeStr,"\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4788 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
4789 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4791 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
4792 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4794 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
4795 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4796 EVEX_CD8<16, CD8VH>;
4797 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
4798 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4799 EVEX_CD8<16, CD8VQ>;
4800 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
4801 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4802 EVEX_CD8<32, CD8VH>;
4804 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
4805 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4807 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
4808 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4810 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
4811 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4812 EVEX_CD8<16, CD8VH>;
4813 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
4814 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4815 EVEX_CD8<16, CD8VQ>;
4816 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
4817 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4818 EVEX_CD8<32, CD8VH>;
4820 //===----------------------------------------------------------------------===//
4821 // GATHER - SCATTER Operations
4823 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4824 RegisterClass RC, X86MemOperand memop> {
4826 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4827 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4828 (ins RC:$src1, KRC:$mask, memop:$src2),
4829 !strconcat(OpcodeStr,
4830 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4834 let ExeDomain = SSEPackedDouble in {
4835 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4836 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4837 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4838 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4841 let ExeDomain = SSEPackedSingle in {
4842 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4843 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4844 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4845 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4848 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4849 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4850 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4851 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4853 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4854 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4855 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4856 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4858 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4859 RegisterClass RC, X86MemOperand memop> {
4860 let mayStore = 1, Constraints = "$mask = $mask_wb" in
4861 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4862 (ins memop:$dst, KRC:$mask, RC:$src2),
4863 !strconcat(OpcodeStr,
4864 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4868 let ExeDomain = SSEPackedDouble in {
4869 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4870 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4871 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4872 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4875 let ExeDomain = SSEPackedSingle in {
4876 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4877 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4878 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4879 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4882 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4883 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4884 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4885 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4887 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4888 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4889 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4890 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4893 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4894 RegisterClass KRC, X86MemOperand memop> {
4895 let Predicates = [HasPFI], hasSideEffects = 1 in
4896 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4897 !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"),
4901 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4902 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4904 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4905 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4907 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4908 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4910 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4911 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4913 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4914 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4916 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4917 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4919 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4920 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4922 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4923 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4925 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4926 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4928 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
4929 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4931 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
4932 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4934 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
4935 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4937 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
4938 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4940 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
4941 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4943 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
4944 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4946 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
4947 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4948 //===----------------------------------------------------------------------===//
4949 // VSHUFPS - VSHUFPD Operations
4951 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
4952 ValueType vt, string OpcodeStr, PatFrag mem_frag,
4954 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
4955 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
4956 !strconcat(OpcodeStr,
4957 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4958 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
4959 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4960 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
4961 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
4962 (ins RC:$src1, RC:$src2, u8imm:$src3),
4963 !strconcat(OpcodeStr,
4964 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4965 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
4966 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4967 EVEX_4V, Sched<[WriteShuffle]>;
4970 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
4971 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4972 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
4973 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4975 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4976 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4977 def : Pat<(v16i32 (X86Shufp VR512:$src1,
4978 (memopv16i32 addr:$src2), (i8 imm:$imm))),
4979 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4981 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4982 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4983 def : Pat<(v8i64 (X86Shufp VR512:$src1,
4984 (memopv8i64 addr:$src2), (i8 imm:$imm))),
4985 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4987 multiclass avx512_valign<X86VectorVTInfo _> {
4988 defm rri : AVX512_maskable<0x03, MRMSrcReg, _, (outs _.RC:$dst),
4989 (ins _.RC:$src1, _.RC:$src2, u8imm:$src3),
4991 "$src3, $src2, $src1", "$src1, $src2, $src3",
4992 (_.VT (X86VAlign _.RC:$src2, _.RC:$src1,
4994 AVX512AIi8Base, EVEX_4V;
4996 // Also match valign of packed floats.
4997 def : Pat<(_.FloatVT (X86VAlign _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
4998 (!cast<Instruction>(NAME##rri) _.RC:$src2, _.RC:$src1, imm:$imm)>;
5001 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs _.RC:$dst),
5002 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$src3),
5003 !strconcat("valign"##_.Suffix,
5004 "\t{$src3, $src2, $src1, $dst|"
5005 "$dst, $src1, $src2, $src3}"),
5008 defm VALIGND : avx512_valign<v16i32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
5009 defm VALIGNQ : avx512_valign<v8i64_info>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
5011 // Helper fragments to match sext vXi1 to vXiY.
5012 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
5013 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
5015 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
5016 RegisterClass KRC, RegisterClass RC,
5017 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
5019 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
5020 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5022 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5023 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
5025 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5026 !strconcat(OpcodeStr,
5027 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5029 let mayLoad = 1 in {
5030 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5031 (ins x86memop:$src),
5032 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5034 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5035 (ins KRC:$mask, x86memop:$src),
5036 !strconcat(OpcodeStr,
5037 "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
5039 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5040 (ins KRC:$mask, x86memop:$src),
5041 !strconcat(OpcodeStr,
5042 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5044 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5045 (ins x86scalar_mop:$src),
5046 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5047 ", $dst|$dst, ${src}", BrdcstStr, "}"),
5049 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5050 (ins KRC:$mask, x86scalar_mop:$src),
5051 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5052 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
5053 []>, EVEX, EVEX_B, EVEX_K;
5054 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5055 (ins KRC:$mask, x86scalar_mop:$src),
5056 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5057 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
5059 []>, EVEX, EVEX_B, EVEX_KZ;
5063 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
5064 i512mem, i32mem, "{1to16}">, EVEX_V512,
5065 EVEX_CD8<32, CD8VF>;
5066 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
5067 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
5068 EVEX_CD8<64, CD8VF>;
5071 (bc_v16i32 (v16i1sextv16i32)),
5072 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
5073 (VPABSDZrr VR512:$src)>;
5075 (bc_v8i64 (v8i1sextv8i64)),
5076 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
5077 (VPABSQZrr VR512:$src)>;
5079 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
5080 (v16i32 immAllZerosV), (i16 -1))),
5081 (VPABSDZrr VR512:$src)>;
5082 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
5083 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
5084 (VPABSQZrr VR512:$src)>;
5086 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
5087 RegisterClass RC, RegisterClass KRC,
5088 X86MemOperand x86memop,
5089 X86MemOperand x86scalar_mop, string BrdcstStr> {
5090 let hasSideEffects = 0 in {
5091 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5093 !strconcat(OpcodeStr, "\t{$src, ${dst} |${dst}, $src}"),
5096 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5097 (ins x86memop:$src),
5098 !strconcat(OpcodeStr, "\t{$src, ${dst}|${dst}, $src}"),
5101 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5102 (ins x86scalar_mop:$src),
5103 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5104 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
5106 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5107 (ins KRC:$mask, RC:$src),
5108 !strconcat(OpcodeStr,
5109 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5112 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5113 (ins KRC:$mask, x86memop:$src),
5114 !strconcat(OpcodeStr,
5115 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5118 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5119 (ins KRC:$mask, x86scalar_mop:$src),
5120 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5121 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
5123 []>, EVEX, EVEX_KZ, EVEX_B;
5125 let Constraints = "$src1 = $dst" in {
5126 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5127 (ins RC:$src1, KRC:$mask, RC:$src2),
5128 !strconcat(OpcodeStr,
5129 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5132 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5133 (ins RC:$src1, KRC:$mask, x86memop:$src2),
5134 !strconcat(OpcodeStr,
5135 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5138 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5139 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
5140 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
5141 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
5142 []>, EVEX, EVEX_K, EVEX_B;
5147 let Predicates = [HasCDI] in {
5148 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
5149 i512mem, i32mem, "{1to16}">,
5150 EVEX_V512, EVEX_CD8<32, CD8VF>;
5153 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
5154 i512mem, i64mem, "{1to8}">,
5155 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5159 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
5161 (VPCONFLICTDrrk VR512:$src1,
5162 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5164 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
5166 (VPCONFLICTQrrk VR512:$src1,
5167 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5169 let Predicates = [HasCDI] in {
5170 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
5171 i512mem, i32mem, "{1to16}">,
5172 EVEX_V512, EVEX_CD8<32, CD8VF>;
5175 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
5176 i512mem, i64mem, "{1to8}">,
5177 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5181 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
5183 (VPLZCNTDrrk VR512:$src1,
5184 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5186 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
5188 (VPLZCNTQrrk VR512:$src1,
5189 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5191 def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))),
5192 (VPLZCNTDrm addr:$src)>;
5193 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
5194 (VPLZCNTDrr VR512:$src)>;
5195 def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))),
5196 (VPLZCNTQrm addr:$src)>;
5197 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
5198 (VPLZCNTQrr VR512:$src)>;
5200 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5201 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5202 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
5204 def : Pat<(store VK1:$src, addr:$dst),
5205 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
5207 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
5208 (truncstore node:$val, node:$ptr), [{
5209 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
5212 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
5213 (MOV8mr addr:$dst, GR8:$src)>;
5215 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
5216 def rr : AVX512XS8I<opc, MRMDestReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
5217 !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
5218 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
5221 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
5222 string OpcodeStr, Predicate prd> {
5223 let Predicates = [prd] in
5224 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5226 let Predicates = [prd, HasVLX] in {
5227 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5228 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5232 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
5233 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
5235 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
5237 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
5239 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
5243 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;
5245 //===----------------------------------------------------------------------===//
5246 // AVX-512 - COMPRESS and EXPAND
5248 multiclass compress_by_vec_width<bits<8> opc, X86VectorVTInfo _,
5250 def rrkz : AVX5128I<opc, MRMDestReg, (outs _.RC:$dst),
5251 (ins _.KRCWM:$mask, _.RC:$src),
5252 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5253 [(set _.RC:$dst, (_.VT (X86compress _.KRCWM:$mask, _.RC:$src,
5254 _.ImmAllZerosV)))]>, EVEX_KZ;
5256 let Constraints = "$src0 = $dst" in
5257 def rrk : AVX5128I<opc, MRMDestReg, (outs _.RC:$dst),
5258 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src),
5259 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5260 [(set _.RC:$dst, (_.VT (X86compress _.KRCWM:$mask, _.RC:$src,
5261 _.RC:$src0)))]>, EVEX_K;
5263 let mayStore = 1 in {
5264 def mrk : AVX5128I<opc, MRMDestMem, (outs),
5265 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
5266 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5267 [(store (_.VT (X86compress _.KRCWM:$mask, _.RC:$src, undef)),
5269 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
5273 multiclass compress_by_elt_width<bits<8> opc, string OpcodeStr,
5274 AVX512VLVectorVTInfo VTInfo> {
5275 defm Z : compress_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5277 let Predicates = [HasVLX] in {
5278 defm Z256 : compress_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5279 defm Z128 : compress_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5283 defm VPCOMPRESSD : compress_by_elt_width <0x8B, "vpcompressd", avx512vl_i32_info>,
5285 defm VPCOMPRESSQ : compress_by_elt_width <0x8B, "vpcompressq", avx512vl_i64_info>,
5287 defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", avx512vl_f32_info>,
5289 defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", avx512vl_f64_info>,
5293 multiclass expand_by_vec_width<bits<8> opc, X86VectorVTInfo _,
5295 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
5296 (ins _.KRCWM:$mask, _.RC:$src),
5297 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5298 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask, (_.VT _.RC:$src),
5299 _.ImmAllZerosV)))]>, EVEX_KZ;
5301 let Constraints = "$src0 = $dst" in
5302 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
5303 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src),
5304 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5305 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5306 (_.VT _.RC:$src), _.RC:$src0)))]>, EVEX_K;
5308 let mayLoad = 1, Constraints = "$src0 = $dst" in
5309 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
5310 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src),
5311 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5312 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5314 (_.LdFrag addr:$src))),
5316 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
5319 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
5320 (ins _.KRCWM:$mask, _.MemOp:$src),
5321 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5322 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5323 (_.VT (bitconvert (_.LdFrag addr:$src))),
5324 _.ImmAllZerosV)))]>,
5325 EVEX_KZ, EVEX_CD8<_.EltSize, CD8VT1>;
5329 multiclass expand_by_elt_width<bits<8> opc, string OpcodeStr,
5330 AVX512VLVectorVTInfo VTInfo> {
5331 defm Z : expand_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5333 let Predicates = [HasVLX] in {
5334 defm Z256 : expand_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5335 defm Z128 : expand_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5339 defm VPEXPANDD : expand_by_elt_width <0x89, "vpexpandd", avx512vl_i32_info>,
5341 defm VPEXPANDQ : expand_by_elt_width <0x89, "vpexpandq", avx512vl_i64_info>,
5343 defm VEXPANDPS : expand_by_elt_width <0x88, "vexpandps", avx512vl_f32_info>,
5345 defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", avx512vl_f64_info>,