1 // Bitcasts between 512-bit vector types. Return the original type since
2 // no instruction is needed for the conversion
3 let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
49 // Bitcasts between 256-bit vector types. Return the original type since
50 // no instruction is needed for the conversion
51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
84 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
87 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
88 isPseudo = 1, Predicates = [HasAVX512] in {
89 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
90 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
93 let Predicates = [HasAVX512] in {
94 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
95 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
96 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
99 //===----------------------------------------------------------------------===//
100 // AVX-512 - VECTOR INSERT
103 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
104 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
105 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
106 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
107 []>, EVEX_4V, EVEX_V512;
109 def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
110 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
111 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
112 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
115 // -- 64x4 fp form --
116 let hasSideEffects = 0, ExeDomain = SSEPackedDouble in {
117 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
118 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
119 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
120 []>, EVEX_4V, EVEX_V512, VEX_W;
122 def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
123 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
124 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
125 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
127 // -- 32x4 integer form --
128 let hasSideEffects = 0 in {
129 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
130 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
131 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
132 []>, EVEX_4V, EVEX_V512;
134 def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
135 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
136 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
137 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
141 let hasSideEffects = 0 in {
143 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
144 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
145 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
146 []>, EVEX_4V, EVEX_V512, VEX_W;
148 def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
149 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
150 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
151 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
154 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
155 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
156 (INSERT_get_vinsert128_imm VR512:$ins))>;
157 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
158 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
159 (INSERT_get_vinsert128_imm VR512:$ins))>;
160 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
161 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
162 (INSERT_get_vinsert128_imm VR512:$ins))>;
163 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
164 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
165 (INSERT_get_vinsert128_imm VR512:$ins))>;
167 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
168 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
169 (INSERT_get_vinsert128_imm VR512:$ins))>;
170 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
171 (bc_v4i32 (loadv2i64 addr:$src2)),
172 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
173 (INSERT_get_vinsert128_imm VR512:$ins))>;
174 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
175 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
176 (INSERT_get_vinsert128_imm VR512:$ins))>;
177 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
178 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
179 (INSERT_get_vinsert128_imm VR512:$ins))>;
181 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
182 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
183 (INSERT_get_vinsert256_imm VR512:$ins))>;
184 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
185 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
186 (INSERT_get_vinsert256_imm VR512:$ins))>;
187 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
188 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
189 (INSERT_get_vinsert256_imm VR512:$ins))>;
190 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
191 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
192 (INSERT_get_vinsert256_imm VR512:$ins))>;
194 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
195 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
196 (INSERT_get_vinsert256_imm VR512:$ins))>;
197 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
198 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
199 (INSERT_get_vinsert256_imm VR512:$ins))>;
200 def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
201 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
202 (INSERT_get_vinsert256_imm VR512:$ins))>;
203 def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
204 (bc_v8i32 (loadv4i64 addr:$src2)),
205 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
206 (INSERT_get_vinsert256_imm VR512:$ins))>;
208 // vinsertps - insert f32 to XMM
209 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
210 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
211 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
212 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
214 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
215 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
216 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
217 [(set VR128X:$dst, (X86insertps VR128X:$src1,
218 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
219 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
221 //===----------------------------------------------------------------------===//
222 // AVX-512 VECTOR EXTRACT
224 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
226 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
227 (ins VR512:$src1, i8imm:$src2),
228 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
229 []>, EVEX, EVEX_V512;
230 def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
231 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
232 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
233 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
236 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
237 (ins VR512:$src1, i8imm:$src2),
238 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
239 []>, EVEX, EVEX_V512, VEX_W;
241 def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
242 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
243 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
244 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
247 let hasSideEffects = 0 in {
249 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
250 (ins VR512:$src1, i8imm:$src2),
251 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
252 []>, EVEX, EVEX_V512;
253 def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
254 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
255 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
256 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
259 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
260 (ins VR512:$src1, i8imm:$src2),
261 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
262 []>, EVEX, EVEX_V512, VEX_W;
264 def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
265 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
266 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
267 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
270 def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
271 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
272 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
274 def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
275 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
276 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
278 def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
279 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
280 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
282 def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
283 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
284 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
287 def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
288 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
289 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
291 def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
292 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
293 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
295 def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
296 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
297 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
299 def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
300 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
301 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
303 // A 256-bit subvector extract from the first 512-bit vector position
304 // is a subregister copy that needs no instruction.
305 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
306 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
307 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
308 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
309 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
310 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
311 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
312 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
315 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
316 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
317 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
318 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
319 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
320 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
321 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
322 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
325 // A 128-bit subvector insert to the first 512-bit vector position
326 // is a subregister copy that needs no instruction.
327 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
328 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
329 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
331 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
332 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
333 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
335 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
336 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
337 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
339 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
340 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
341 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
344 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
345 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
346 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
347 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
348 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
349 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
350 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
351 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
353 // vextractps - extract 32 bits from XMM
354 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
355 (ins VR128X:$src1, u32u8imm:$src2),
356 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
357 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
360 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
361 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
362 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
363 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
364 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
366 //===---------------------------------------------------------------------===//
369 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
370 RegisterClass DestRC,
371 RegisterClass SrcRC, X86MemOperand x86memop> {
372 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
373 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
375 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
376 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),[]>, EVEX;
378 let ExeDomain = SSEPackedSingle in {
379 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
381 EVEX_V512, EVEX_CD8<32, CD8VT1>;
384 let ExeDomain = SSEPackedDouble in {
385 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
387 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
390 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
391 (VBROADCASTSSZrm addr:$src)>;
392 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
393 (VBROADCASTSDZrm addr:$src)>;
395 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
396 (VBROADCASTSSZrm addr:$src)>;
397 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
398 (VBROADCASTSDZrm addr:$src)>;
400 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
401 RegisterClass SrcRC, RegisterClass KRC> {
402 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
403 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
404 []>, EVEX, EVEX_V512;
405 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
406 (ins KRC:$mask, SrcRC:$src),
407 !strconcat(OpcodeStr,
408 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
409 []>, EVEX, EVEX_V512, EVEX_KZ;
412 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
413 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
416 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
417 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
419 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
420 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
422 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
423 (VPBROADCASTDrZrr GR32:$src)>;
424 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
425 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
426 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
427 (VPBROADCASTQrZrr GR64:$src)>;
428 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
429 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
431 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
432 (VPBROADCASTDrZrr GR32:$src)>;
433 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
434 (VPBROADCASTQrZrr GR64:$src)>;
436 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
437 (v16i32 immAllZerosV), (i16 GR16:$mask))),
438 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
439 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
440 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
441 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
443 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
444 X86MemOperand x86memop, PatFrag ld_frag,
445 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
447 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
448 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
450 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
451 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
453 !strconcat(OpcodeStr,
454 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
456 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
459 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
460 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
462 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
463 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
465 !strconcat(OpcodeStr,
466 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
467 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
468 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
472 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
473 loadi32, VR512, v16i32, v4i32, VK16WM>,
474 EVEX_V512, EVEX_CD8<32, CD8VT1>;
475 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
476 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
477 EVEX_CD8<64, CD8VT1>;
479 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
480 (VPBROADCASTDZrr VR128X:$src)>;
481 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
482 (VPBROADCASTQZrr VR128X:$src)>;
484 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
485 (VBROADCASTSSZrr VR128X:$src)>;
486 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
487 (VBROADCASTSDZrr VR128X:$src)>;
489 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
490 (VBROADCASTSSZrr VR128X:$src)>;
491 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
492 (VBROADCASTSDZrr VR128X:$src)>;
494 // Provide fallback in case the load node that is used in the patterns above
495 // is used by additional users, which prevents the pattern selection.
496 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
497 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
498 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
499 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
502 let Predicates = [HasAVX512] in {
503 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
505 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
506 addr:$src)), sub_ymm)>;
508 //===----------------------------------------------------------------------===//
509 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
512 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
513 RegisterClass DstRC, RegisterClass KRC,
514 ValueType OpVT, ValueType SrcVT> {
515 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
516 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
520 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
521 VK16, v16i32, v16i1>, EVEX_V512;
522 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
523 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
525 //===----------------------------------------------------------------------===//
528 // -- immediate form --
529 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
530 SDNode OpNode, PatFrag mem_frag,
531 X86MemOperand x86memop, ValueType OpVT> {
532 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
533 (ins RC:$src1, i8imm:$src2),
534 !strconcat(OpcodeStr,
535 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
537 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
539 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
540 (ins x86memop:$src1, i8imm:$src2),
541 !strconcat(OpcodeStr,
542 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
544 (OpVT (OpNode (mem_frag addr:$src1),
545 (i8 imm:$src2))))]>, EVEX;
548 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
549 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
550 let ExeDomain = SSEPackedDouble in
551 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
552 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
554 // -- VPERM - register form --
555 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
556 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
558 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
559 (ins RC:$src1, RC:$src2),
560 !strconcat(OpcodeStr,
561 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
563 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
565 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
566 (ins RC:$src1, x86memop:$src2),
567 !strconcat(OpcodeStr,
568 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
570 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
574 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
575 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
576 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
577 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
578 let ExeDomain = SSEPackedSingle in
579 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
580 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
581 let ExeDomain = SSEPackedDouble in
582 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
583 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
585 // -- VPERM2I - 3 source operands form --
586 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
587 PatFrag mem_frag, X86MemOperand x86memop,
588 SDNode OpNode, ValueType OpVT> {
589 let Constraints = "$src1 = $dst" in {
590 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
591 (ins RC:$src1, RC:$src2, RC:$src3),
592 !strconcat(OpcodeStr,
593 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
595 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
598 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
599 (ins RC:$src1, RC:$src2, x86memop:$src3),
600 !strconcat(OpcodeStr,
601 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
603 (OpVT (OpNode RC:$src1, RC:$src2,
604 (mem_frag addr:$src3))))]>, EVEX_4V;
607 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem,
608 X86VPermiv3, v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
609 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem,
610 X86VPermiv3, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
611 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem,
612 X86VPermiv3, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
613 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
614 X86VPermiv3, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
616 defm VPERMT2D : avx512_perm_3src<0x7E, "vpermt2d", VR512, memopv16i32, i512mem,
617 X86VPermv3, v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
618 defm VPERMT2Q : avx512_perm_3src<0x7E, "vpermt2q", VR512, memopv8i64, i512mem,
619 X86VPermv3, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
620 defm VPERMT2PS : avx512_perm_3src<0x7F, "vpermt2ps", VR512, memopv16f32, i512mem,
621 X86VPermv3, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
622 defm VPERMT2PD : avx512_perm_3src<0x7F, "vpermt2pd", VR512, memopv8f64, i512mem,
623 X86VPermv3, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
624 //===----------------------------------------------------------------------===//
625 // AVX-512 - BLEND using mask
627 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
628 RegisterClass KRC, RegisterClass RC,
629 X86MemOperand x86memop, PatFrag mem_frag,
630 SDNode OpNode, ValueType vt> {
631 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
632 (ins KRC:$mask, RC:$src1, RC:$src2),
633 !strconcat(OpcodeStr,
634 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
635 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
636 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
638 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
639 (ins KRC:$mask, RC:$src1, x86memop:$src2),
640 !strconcat(OpcodeStr,
641 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
642 []>, EVEX_4V, EVEX_K;
645 let ExeDomain = SSEPackedSingle in
646 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
647 VK16WM, VR512, f512mem,
648 memopv16f32, vselect, v16f32>,
649 EVEX_CD8<32, CD8VF>, EVEX_V512;
650 let ExeDomain = SSEPackedDouble in
651 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
652 VK8WM, VR512, f512mem,
653 memopv8f64, vselect, v8f64>,
654 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
656 def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
657 (v16f32 VR512:$src2), (i16 GR16:$mask))),
658 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
659 VR512:$src1, VR512:$src2)>;
661 def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
662 (v8f64 VR512:$src2), (i8 GR8:$mask))),
663 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
664 VR512:$src1, VR512:$src2)>;
666 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
667 VK16WM, VR512, f512mem,
668 memopv16i32, vselect, v16i32>,
669 EVEX_CD8<32, CD8VF>, EVEX_V512;
671 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
672 VK8WM, VR512, f512mem,
673 memopv8i64, vselect, v8i64>,
674 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
676 def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
677 (v16i32 VR512:$src2), (i16 GR16:$mask))),
678 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
679 VR512:$src1, VR512:$src2)>;
681 def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
682 (v8i64 VR512:$src2), (i8 GR8:$mask))),
683 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
684 VR512:$src1, VR512:$src2)>;
686 let Predicates = [HasAVX512] in {
687 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
688 (v8f32 VR256X:$src2))),
690 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
691 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
692 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
694 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
695 (v8i32 VR256X:$src2))),
697 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
698 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
699 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
701 //===----------------------------------------------------------------------===//
702 // Compare Instructions
703 //===----------------------------------------------------------------------===//
705 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
706 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
707 Operand CC, SDNode OpNode, ValueType VT,
708 PatFrag ld_frag, string asm, string asm_alt> {
709 def rr : AVX512Ii8<0xC2, MRMSrcReg,
710 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
711 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
712 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
713 def rm : AVX512Ii8<0xC2, MRMSrcMem,
714 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
715 [(set VK1:$dst, (OpNode (VT RC:$src1),
716 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
717 let isAsmParserOnly = 1, hasSideEffects = 0 in {
718 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
719 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
720 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
721 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
722 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
723 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
727 let Predicates = [HasAVX512] in {
728 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
729 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
730 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
732 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
733 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
734 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
738 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
739 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
740 SDNode OpNode, ValueType vt> {
741 def rr : AVX512BI<opc, MRMSrcReg,
742 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
743 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
744 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
745 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
746 def rm : AVX512BI<opc, MRMSrcMem,
747 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
748 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
749 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
750 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
753 defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
754 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512,
756 defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
757 memopv8i64, X86pcmpeqm, v8i64>, T8PD, EVEX_V512,
758 VEX_W, EVEX_CD8<64, CD8VF>;
760 defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
761 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512,
763 defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
764 memopv8i64, X86pcmpgtm, v8i64>, T8PD, EVEX_V512,
765 VEX_W, EVEX_CD8<64, CD8VF>;
767 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
768 (COPY_TO_REGCLASS (VPCMPGTDZrr
769 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
770 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
772 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
773 (COPY_TO_REGCLASS (VPCMPEQDZrr
774 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
775 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
777 multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
778 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
779 SDNode OpNode, ValueType vt, Operand CC, string asm,
781 def rri : AVX512AIi8<opc, MRMSrcReg,
782 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
783 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
784 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
785 def rmi : AVX512AIi8<opc, MRMSrcMem,
786 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
787 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
788 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
789 // Accept explicit immediate argument form instead of comparison code.
790 let isAsmParserOnly = 1, hasSideEffects = 0 in {
791 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
792 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
793 asm_alt, [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
794 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
795 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
796 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
800 defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv16i32,
801 X86cmpm, v16i32, AVXCC,
802 "vpcmp${cc}d\t{$src2, $src1, $dst|$dst, $src1, $src2}",
803 "vpcmpd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
804 EVEX_V512, EVEX_CD8<32, CD8VF>;
805 defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv16i32,
806 X86cmpmu, v16i32, AVXCC,
807 "vpcmp${cc}ud\t{$src2, $src1, $dst|$dst, $src1, $src2}",
808 "vpcmpud\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
809 EVEX_V512, EVEX_CD8<32, CD8VF>;
811 defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64,
812 X86cmpm, v8i64, AVXCC,
813 "vpcmp${cc}q\t{$src2, $src1, $dst|$dst, $src1, $src2}",
814 "vpcmpq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
815 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
816 defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64,
817 X86cmpmu, v8i64, AVXCC,
818 "vpcmp${cc}uq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
819 "vpcmpuq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
820 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
822 // avx512_cmp_packed - sse 1 & 2 compare packed instructions
823 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
824 X86MemOperand x86memop, ValueType vt,
825 string suffix, Domain d> {
826 def rri : AVX512PIi8<0xC2, MRMSrcReg,
827 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
828 !strconcat("vcmp${cc}", suffix,
829 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
830 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
831 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
832 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
833 !strconcat("vcmp${cc}", suffix,
834 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
836 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
837 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
838 !strconcat("vcmp${cc}", suffix,
839 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
841 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
843 // Accept explicit immediate argument form instead of comparison code.
844 let isAsmParserOnly = 1, hasSideEffects = 0 in {
845 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
846 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
847 !strconcat("vcmp", suffix,
848 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
849 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
850 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
851 !strconcat("vcmp", suffix,
852 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
856 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
857 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
859 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
860 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
863 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
864 (COPY_TO_REGCLASS (VCMPPSZrri
865 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
866 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
868 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
869 (COPY_TO_REGCLASS (VPCMPDZrri
870 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
871 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
873 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
874 (COPY_TO_REGCLASS (VPCMPUDZrri
875 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
876 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
879 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
880 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
882 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
883 (I8Imm imm:$cc)), GR16)>;
885 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
886 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
888 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
889 (I8Imm imm:$cc)), GR8)>;
891 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
892 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
894 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
895 (I8Imm imm:$cc)), GR16)>;
897 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
898 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
900 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
901 (I8Imm imm:$cc)), GR8)>;
903 // Mask register copy, including
904 // - copy between mask registers
905 // - load/store mask registers
906 // - copy from GPR to mask register and vice versa
908 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
909 string OpcodeStr, RegisterClass KRC,
910 ValueType vt, X86MemOperand x86memop> {
911 let hasSideEffects = 0 in {
912 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
913 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
915 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
916 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
917 [(set KRC:$dst, (vt (load addr:$src)))]>;
919 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
920 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
924 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
926 RegisterClass KRC, RegisterClass GRC> {
927 let hasSideEffects = 0 in {
928 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
929 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
930 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
931 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
935 let Predicates = [HasAVX512] in {
936 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
938 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
942 let Predicates = [HasAVX512] in {
943 // GR16 from/to 16-bit mask
944 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
945 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
946 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
947 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
949 // Store kreg in memory
950 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
951 (KMOVWmk addr:$dst, VK16:$src)>;
953 def : Pat<(store VK8:$src, addr:$dst),
954 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
956 def : Pat<(i1 (load addr:$src)),
957 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
959 def : Pat<(v8i1 (load addr:$src)),
960 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
962 def : Pat<(i1 (trunc (i32 GR32:$src))),
963 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
965 def : Pat<(i1 (trunc (i8 GR8:$src))),
967 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
969 def : Pat<(i1 (trunc (i16 GR16:$src))),
971 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
974 def : Pat<(i32 (zext VK1:$src)),
975 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
976 def : Pat<(i8 (zext VK1:$src)),
979 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
980 def : Pat<(i64 (zext VK1:$src)),
981 (AND64ri8 (SUBREG_TO_REG (i64 0),
982 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
983 def : Pat<(i16 (zext VK1:$src)),
985 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
987 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
988 (COPY_TO_REGCLASS VK1:$src, VK16)>;
989 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
990 (COPY_TO_REGCLASS VK1:$src, VK8)>;
992 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
993 let Predicates = [HasAVX512] in {
994 // GR from/to 8-bit mask without native support
995 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
997 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
999 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1001 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1004 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1005 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1006 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1007 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1011 // Mask unary operation
1013 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1014 RegisterClass KRC, SDPatternOperator OpNode> {
1015 let Predicates = [HasAVX512] in
1016 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1017 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1018 [(set KRC:$dst, (OpNode KRC:$src))]>;
1021 multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
1022 SDPatternOperator OpNode> {
1023 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1027 defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
1029 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1030 let Predicates = [HasAVX512] in
1031 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1033 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1034 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1036 defm : avx512_mask_unop_int<"knot", "KNOT">;
1038 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1039 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1040 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1042 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1043 def : Pat<(not VK8:$src),
1045 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1047 // Mask binary operation
1048 // - KAND, KANDN, KOR, KXNOR, KXOR
1049 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1050 RegisterClass KRC, SDPatternOperator OpNode> {
1051 let Predicates = [HasAVX512] in
1052 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1053 !strconcat(OpcodeStr,
1054 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1055 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1058 multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
1059 SDPatternOperator OpNode> {
1060 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1064 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1065 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1067 let isCommutable = 1 in {
1068 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
1069 let isCommutable = 0 in
1070 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
1071 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
1072 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
1073 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
1076 def : Pat<(xor VK1:$src1, VK1:$src2),
1077 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1078 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1080 def : Pat<(or VK1:$src1, VK1:$src2),
1081 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1082 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1084 def : Pat<(and VK1:$src1, VK1:$src2),
1085 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1086 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1088 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1089 let Predicates = [HasAVX512] in
1090 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1091 (i16 GR16:$src1), (i16 GR16:$src2)),
1092 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1093 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1094 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1097 defm : avx512_mask_binop_int<"kand", "KAND">;
1098 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1099 defm : avx512_mask_binop_int<"kor", "KOR">;
1100 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1101 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1103 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1104 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1105 let Predicates = [HasAVX512] in
1106 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1108 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1109 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1112 defm : avx512_binop_pat<and, KANDWrr>;
1113 defm : avx512_binop_pat<andn, KANDNWrr>;
1114 defm : avx512_binop_pat<or, KORWrr>;
1115 defm : avx512_binop_pat<xnor, KXNORWrr>;
1116 defm : avx512_binop_pat<xor, KXORWrr>;
1119 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1120 RegisterClass KRC> {
1121 let Predicates = [HasAVX512] in
1122 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1123 !strconcat(OpcodeStr,
1124 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1127 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1128 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1132 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1133 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1134 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1135 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1138 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1139 let Predicates = [HasAVX512] in
1140 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1141 (i16 GR16:$src1), (i16 GR16:$src2)),
1142 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1143 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1144 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1146 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1149 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1151 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1152 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1153 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"),
1154 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1157 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1158 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1162 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1164 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1165 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1166 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1169 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1171 let Predicates = [HasAVX512] in
1172 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1173 !strconcat(OpcodeStr,
1174 " \t{$imm, $src, $dst|$dst, $src, $imm}"),
1175 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1178 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1180 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1184 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1185 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1187 // Mask setting all 0s or 1s
1188 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1189 let Predicates = [HasAVX512] in
1190 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1191 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1192 [(set KRC:$dst, (VT Val))]>;
1195 multiclass avx512_mask_setop_w<PatFrag Val> {
1196 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1197 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1200 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1201 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1203 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1204 let Predicates = [HasAVX512] in {
1205 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1206 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1207 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1208 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1209 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1211 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1212 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1214 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1215 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1217 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1218 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1220 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1221 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1223 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1224 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1225 //===----------------------------------------------------------------------===//
1226 // AVX-512 - Aligned and unaligned load and store
1229 multiclass avx512_load<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1230 X86MemOperand x86memop, PatFrag ld_frag,
1231 string asm, Domain d,
1232 ValueType vt, bit IsReMaterializable = 1> {
1233 let hasSideEffects = 0 in {
1234 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1235 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), [], d>,
1237 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
1239 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1240 [], d>, EVEX, EVEX_KZ;
1242 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
1243 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1244 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1245 [(set (vt RC:$dst), (ld_frag addr:$src))], d>, EVEX;
1246 let Constraints = "$src1 = $dst", hasSideEffects = 0 in {
1247 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1248 (ins RC:$src1, KRC:$mask, RC:$src2),
1250 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1253 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1254 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1256 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1257 [], d>, EVEX, EVEX_K;
1260 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1261 (ins KRC:$mask, x86memop:$src2),
1263 " \t{$src2, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src2}"),
1264 [], d>, EVEX, EVEX_KZ;
1267 multiclass avx512_store<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1268 X86MemOperand x86memop, PatFrag store_frag,
1269 string asm, Domain d, ValueType vt> {
1270 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1271 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
1272 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), [], d>,
1274 let Constraints = "$src1 = $dst" in
1275 def alt_rrk : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1276 (ins RC:$src1, KRC:$mask, RC:$src2),
1278 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1280 def alt_rrkz : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1281 (ins KRC:$mask, RC:$src),
1283 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1284 [], d>, EVEX, EVEX_KZ;
1286 let mayStore = 1 in {
1287 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1288 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1289 [(store_frag (vt RC:$src), addr:$dst)], d>, EVEX;
1290 def mrk : AVX512PI<opc, MRMDestMem, (outs),
1291 (ins x86memop:$dst, KRC:$mask, RC:$src),
1293 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
1294 [], d>, EVEX, EVEX_K;
1295 def mrkz : AVX512PI<opc, MRMDestMem, (outs),
1296 (ins x86memop:$dst, KRC:$mask, RC:$src),
1298 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1299 [], d>, EVEX, EVEX_KZ;
1303 defm VMOVAPSZ : avx512_load<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1304 "vmovaps", SSEPackedSingle, v16f32>,
1305 avx512_store<0x29, VR512, VK16WM, f512mem, alignedstore512,
1306 "vmovaps", SSEPackedSingle, v16f32>,
1307 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1308 defm VMOVAPDZ : avx512_load<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1309 "vmovapd", SSEPackedDouble, v8f64>,
1310 avx512_store<0x29, VR512, VK8WM, f512mem, alignedstore512,
1311 "vmovapd", SSEPackedDouble, v8f64>,
1312 PD, EVEX_V512, VEX_W,
1313 EVEX_CD8<64, CD8VF>;
1314 defm VMOVUPSZ : avx512_load<0x10, VR512, VK16WM, f512mem, loadv16f32,
1315 "vmovups", SSEPackedSingle, v16f32>,
1316 avx512_store<0x11, VR512, VK16WM, f512mem, store,
1317 "vmovups", SSEPackedSingle, v16f32>,
1318 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1319 defm VMOVUPDZ : avx512_load<0x10, VR512, VK8WM, f512mem, loadv8f64,
1320 "vmovupd", SSEPackedDouble, v8f64, 0>,
1321 avx512_store<0x11, VR512, VK8WM, f512mem, store,
1322 "vmovupd", SSEPackedDouble, v8f64>,
1323 PD, EVEX_V512, VEX_W,
1324 EVEX_CD8<64, CD8VF>;
1325 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
1326 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
1327 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
1329 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
1330 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
1331 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
1333 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
1335 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
1337 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
1339 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
1342 defm VMOVDQA32: avx512_load<0x6F, VR512, VK16WM, i512mem, alignedloadv16i32,
1343 "vmovdqa32", SSEPackedInt, v16i32>,
1344 avx512_store<0x7F, VR512, VK16WM, i512mem, alignedstore512,
1345 "vmovdqa32", SSEPackedInt, v16i32>,
1346 PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1347 defm VMOVDQA64: avx512_load<0x6F, VR512, VK8WM, i512mem, alignedloadv8i64,
1348 "vmovdqa64", SSEPackedInt, v8i64>,
1349 avx512_store<0x7F, VR512, VK8WM, i512mem, alignedstore512,
1350 "vmovdqa64", SSEPackedInt, v8i64>,
1351 PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
1352 defm VMOVDQU32: avx512_load<0x6F, VR512, VK16WM, i512mem, load,
1353 "vmovdqu32", SSEPackedInt, v16i32>,
1354 avx512_store<0x7F, VR512, VK16WM, i512mem, store,
1355 "vmovdqu32", SSEPackedInt, v16i32>,
1356 XS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1357 defm VMOVDQU64: avx512_load<0x6F, VR512, VK8WM, i512mem, load,
1358 "vmovdqu64", SSEPackedInt, v8i64>,
1359 avx512_store<0x7F, VR512, VK8WM, i512mem, store,
1360 "vmovdqu64", SSEPackedInt, v8i64>,
1361 XS, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
1363 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
1364 (v16i32 immAllZerosV), GR16:$mask)),
1365 (VMOVDQU32rmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
1367 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
1368 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
1369 (VMOVDQU64rmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
1371 let AddedComplexity = 20 in {
1372 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
1373 (bc_v8i64 (v16i32 immAllZerosV)))),
1374 (VMOVDQU64rrkz VK8WM:$mask, VR512:$src)>;
1376 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
1377 (v8i64 VR512:$src))),
1378 (VMOVDQU64rrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
1381 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
1382 (v16i32 immAllZerosV))),
1383 (VMOVDQU32rrkz VK16WM:$mask, VR512:$src)>;
1385 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
1386 (v16i32 VR512:$src))),
1387 (VMOVDQU32rrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
1389 def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1390 (v16f32 VR512:$src2))),
1391 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1392 def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1393 (v8f64 VR512:$src2))),
1394 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1395 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1396 (v16i32 VR512:$src2))),
1397 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1398 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1399 (v8i64 VR512:$src2))),
1400 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1402 // Move Int Doubleword to Packed Double Int
1404 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1405 "vmovd\t{$src, $dst|$dst, $src}",
1407 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1409 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1410 "vmovd\t{$src, $dst|$dst, $src}",
1412 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1413 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1414 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1415 "vmovq\t{$src, $dst|$dst, $src}",
1417 (v2i64 (scalar_to_vector GR64:$src)))],
1418 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
1419 let isCodeGenOnly = 1 in {
1420 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1421 "vmovq\t{$src, $dst|$dst, $src}",
1422 [(set FR64:$dst, (bitconvert GR64:$src))],
1423 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1424 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1425 "vmovq\t{$src, $dst|$dst, $src}",
1426 [(set GR64:$dst, (bitconvert FR64:$src))],
1427 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1429 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1430 "vmovq\t{$src, $dst|$dst, $src}",
1431 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1432 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1433 EVEX_CD8<64, CD8VT1>;
1435 // Move Int Doubleword to Single Scalar
1437 let isCodeGenOnly = 1 in {
1438 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1439 "vmovd\t{$src, $dst|$dst, $src}",
1440 [(set FR32X:$dst, (bitconvert GR32:$src))],
1441 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1443 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1444 "vmovd\t{$src, $dst|$dst, $src}",
1445 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1446 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1449 // Move doubleword from xmm register to r/m32
1451 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1452 "vmovd\t{$src, $dst|$dst, $src}",
1453 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1454 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1456 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1457 (ins i32mem:$dst, VR128X:$src),
1458 "vmovd\t{$src, $dst|$dst, $src}",
1459 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1460 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1461 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1463 // Move quadword from xmm1 register to r/m64
1465 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1466 "vmovq\t{$src, $dst|$dst, $src}",
1467 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1469 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
1470 Requires<[HasAVX512, In64BitMode]>;
1472 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
1473 (ins i64mem:$dst, VR128X:$src),
1474 "vmovq\t{$src, $dst|$dst, $src}",
1475 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1476 addr:$dst)], IIC_SSE_MOVDQ>,
1477 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
1478 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1480 // Move Scalar Single to Double Int
1482 let isCodeGenOnly = 1 in {
1483 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
1485 "vmovd\t{$src, $dst|$dst, $src}",
1486 [(set GR32:$dst, (bitconvert FR32X:$src))],
1487 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1488 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1489 (ins i32mem:$dst, FR32X:$src),
1490 "vmovd\t{$src, $dst|$dst, $src}",
1491 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1492 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1495 // Move Quadword Int to Packed Quadword Int
1497 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
1499 "vmovq\t{$src, $dst|$dst, $src}",
1501 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1502 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1504 //===----------------------------------------------------------------------===//
1505 // AVX-512 MOVSS, MOVSD
1506 //===----------------------------------------------------------------------===//
1508 multiclass avx512_move_scalar <string asm, RegisterClass RC,
1509 SDNode OpNode, ValueType vt,
1510 X86MemOperand x86memop, PatFrag mem_pat> {
1511 let hasSideEffects = 0 in {
1512 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1513 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1514 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1515 (scalar_to_vector RC:$src2))))],
1516 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1517 let Constraints = "$src1 = $dst" in
1518 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
1519 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
1521 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
1522 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
1523 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1524 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1525 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1527 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1528 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1529 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1531 } //hasSideEffects = 0
1534 let ExeDomain = SSEPackedSingle in
1535 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
1536 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1538 let ExeDomain = SSEPackedDouble in
1539 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
1540 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1542 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
1543 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
1544 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
1546 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
1547 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
1548 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
1550 // For the disassembler
1551 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
1552 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1553 (ins VR128X:$src1, FR32X:$src2),
1554 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1556 XS, EVEX_4V, VEX_LIG;
1557 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1558 (ins VR128X:$src1, FR64X:$src2),
1559 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1561 XD, EVEX_4V, VEX_LIG, VEX_W;
1564 let Predicates = [HasAVX512] in {
1565 let AddedComplexity = 15 in {
1566 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1567 // MOVS{S,D} to the lower bits.
1568 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1569 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1570 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1571 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1572 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1573 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1574 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1575 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1577 // Move low f32 and clear high bits.
1578 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1579 (SUBREG_TO_REG (i32 0),
1580 (VMOVSSZrr (v4f32 (V_SET0)),
1581 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1582 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1583 (SUBREG_TO_REG (i32 0),
1584 (VMOVSSZrr (v4i32 (V_SET0)),
1585 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1588 let AddedComplexity = 20 in {
1589 // MOVSSrm zeros the high parts of the register; represent this
1590 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1591 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1592 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1593 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1594 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1595 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1596 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1598 // MOVSDrm zeros the high parts of the register; represent this
1599 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1600 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1601 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1602 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1603 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1604 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1605 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1606 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1607 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1608 def : Pat<(v2f64 (X86vzload addr:$src)),
1609 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1611 // Represent the same patterns above but in the form they appear for
1613 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1614 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
1615 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
1616 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1617 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1618 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1619 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1620 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1621 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1623 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1624 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1625 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1626 FR32X:$src)), sub_xmm)>;
1627 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1628 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1629 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1630 FR64X:$src)), sub_xmm)>;
1631 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1632 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
1633 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
1635 // Move low f64 and clear high bits.
1636 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1637 (SUBREG_TO_REG (i32 0),
1638 (VMOVSDZrr (v2f64 (V_SET0)),
1639 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1641 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1642 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1643 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1645 // Extract and store.
1646 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1648 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1649 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1651 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1653 // Shuffle with VMOVSS
1654 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1655 (VMOVSSZrr (v4i32 VR128X:$src1),
1656 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1657 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1658 (VMOVSSZrr (v4f32 VR128X:$src1),
1659 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1662 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1663 (SUBREG_TO_REG (i32 0),
1664 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1665 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1667 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1668 (SUBREG_TO_REG (i32 0),
1669 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1670 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1673 // Shuffle with VMOVSD
1674 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1675 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1676 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1677 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1678 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1679 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1680 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1681 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1684 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1685 (SUBREG_TO_REG (i32 0),
1686 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1687 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1689 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1690 (SUBREG_TO_REG (i32 0),
1691 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1692 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1695 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1696 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1697 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1698 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1699 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1700 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1701 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1702 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1705 let AddedComplexity = 15 in
1706 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1708 "vmovq\t{$src, $dst|$dst, $src}",
1709 [(set VR128X:$dst, (v2i64 (X86vzmovl
1710 (v2i64 VR128X:$src))))],
1711 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1713 let AddedComplexity = 20 in
1714 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1716 "vmovq\t{$src, $dst|$dst, $src}",
1717 [(set VR128X:$dst, (v2i64 (X86vzmovl
1718 (loadv2i64 addr:$src))))],
1719 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1720 EVEX_CD8<8, CD8VT8>;
1722 let Predicates = [HasAVX512] in {
1723 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1724 let AddedComplexity = 20 in {
1725 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1726 (VMOVDI2PDIZrm addr:$src)>;
1727 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
1728 (VMOV64toPQIZrr GR64:$src)>;
1729 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
1730 (VMOVDI2PDIZrr GR32:$src)>;
1732 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1733 (VMOVDI2PDIZrm addr:$src)>;
1734 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1735 (VMOVDI2PDIZrm addr:$src)>;
1736 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1737 (VMOVZPQILo2PQIZrm addr:$src)>;
1738 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1739 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1740 def : Pat<(v2i64 (X86vzload addr:$src)),
1741 (VMOVZPQILo2PQIZrm addr:$src)>;
1744 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1745 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1746 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1747 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1748 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1749 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1750 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1753 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
1754 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1756 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
1757 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1759 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
1760 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1762 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
1763 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1765 //===----------------------------------------------------------------------===//
1766 // AVX-512 - Integer arithmetic
1768 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1769 ValueType OpVT, RegisterClass KRC,
1770 RegisterClass RC, PatFrag memop_frag,
1771 X86MemOperand x86memop, PatFrag scalar_mfrag,
1772 X86MemOperand x86scalar_mop, string BrdcstStr,
1773 OpndItins itins, bit IsCommutable = 0> {
1774 let isCommutable = IsCommutable in
1775 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1776 (ins RC:$src1, RC:$src2),
1777 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1778 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1780 let AddedComplexity = 30 in {
1781 let Constraints = "$src0 = $dst" in
1782 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1783 (ins RC:$src0, KRC:$mask, RC:$src1, RC:$src2),
1784 !strconcat(OpcodeStr,
1785 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1786 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1787 (OpNode (OpVT RC:$src1), (OpVT RC:$src2)),
1789 itins.rr>, EVEX_4V, EVEX_K;
1790 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1791 (ins KRC:$mask, RC:$src1, RC:$src2),
1792 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
1793 "|$dst {${mask}} {z}, $src1, $src2}"),
1794 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1795 (OpNode (OpVT RC:$src1), (OpVT RC:$src2)),
1796 (OpVT immAllZerosV))))],
1797 itins.rr>, EVEX_4V, EVEX_KZ;
1800 let mayLoad = 1 in {
1801 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1802 (ins RC:$src1, x86memop:$src2),
1803 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1804 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
1806 let AddedComplexity = 30 in {
1807 let Constraints = "$src0 = $dst" in
1808 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1809 (ins RC:$src0, KRC:$mask, RC:$src1, x86memop:$src2),
1810 !strconcat(OpcodeStr,
1811 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1812 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1813 (OpNode (OpVT RC:$src1), (memop_frag addr:$src2)),
1815 itins.rm>, EVEX_4V, EVEX_K;
1816 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1817 (ins KRC:$mask, RC:$src1, x86memop:$src2),
1818 !strconcat(OpcodeStr,
1819 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
1820 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1821 (OpNode (OpVT RC:$src1), (memop_frag addr:$src2)),
1822 (OpVT immAllZerosV))))],
1823 itins.rm>, EVEX_4V, EVEX_KZ;
1825 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1826 (ins RC:$src1, x86scalar_mop:$src2),
1827 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1828 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1829 [(set RC:$dst, (OpNode RC:$src1,
1830 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1831 itins.rm>, EVEX_4V, EVEX_B;
1832 let AddedComplexity = 30 in {
1833 let Constraints = "$src0 = $dst" in
1834 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1835 (ins RC:$src0, KRC:$mask, RC:$src1, x86scalar_mop:$src2),
1836 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1837 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
1839 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1840 (OpNode (OpVT RC:$src1),
1841 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))),
1843 itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
1844 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1845 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
1846 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1847 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
1849 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1850 (OpNode (OpVT RC:$src1),
1851 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))),
1852 (OpVT immAllZerosV))))],
1853 itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
1858 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
1859 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
1860 PatFrag memop_frag, X86MemOperand x86memop,
1861 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
1862 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
1863 let isCommutable = IsCommutable in
1865 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1866 (ins RC:$src1, RC:$src2),
1867 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1869 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1870 (ins KRC:$mask, RC:$src1, RC:$src2),
1871 !strconcat(OpcodeStr,
1872 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1873 [], itins.rr>, EVEX_4V, EVEX_K;
1874 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1875 (ins KRC:$mask, RC:$src1, RC:$src2),
1876 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
1877 "|$dst {${mask}} {z}, $src1, $src2}"),
1878 [], itins.rr>, EVEX_4V, EVEX_KZ;
1880 let mayLoad = 1 in {
1881 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1882 (ins RC:$src1, x86memop:$src2),
1883 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1885 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1886 (ins KRC:$mask, RC:$src1, x86memop:$src2),
1887 !strconcat(OpcodeStr,
1888 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1889 [], itins.rm>, EVEX_4V, EVEX_K;
1890 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1891 (ins KRC:$mask, RC:$src1, x86memop:$src2),
1892 !strconcat(OpcodeStr,
1893 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
1894 [], itins.rm>, EVEX_4V, EVEX_KZ;
1895 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1896 (ins RC:$src1, x86scalar_mop:$src2),
1897 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1898 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1899 [], itins.rm>, EVEX_4V, EVEX_B;
1900 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1901 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
1902 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1903 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
1905 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
1906 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1907 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
1908 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1909 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
1911 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
1915 defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VK16WM, VR512,
1916 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1917 SSE_INTALU_ITINS_P, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1919 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VK16WM, VR512,
1920 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1921 SSE_INTALU_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1923 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VK16WM, VR512,
1924 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1925 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1927 defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VK8WM, VR512,
1928 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
1929 SSE_INTALU_ITINS_P, 1>, EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
1931 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VK8WM, VR512,
1932 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
1933 SSE_INTALU_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1935 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
1936 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
1937 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
1938 EVEX_CD8<64, CD8VF>, VEX_W;
1940 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
1941 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
1942 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
1944 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
1945 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1947 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
1948 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1949 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1950 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
1951 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1952 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
1954 defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VK16WM, VR512,
1955 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1956 SSE_INTALU_ITINS_P, 1>,
1957 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1958 defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VK8WM, VR512,
1959 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
1960 SSE_INTALU_ITINS_P, 0>,
1961 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1963 defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VK16WM, VR512,
1964 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1965 SSE_INTALU_ITINS_P, 1>,
1966 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1967 defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VK8WM, VR512,
1968 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
1969 SSE_INTALU_ITINS_P, 0>,
1970 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1972 defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VK16WM, VR512,
1973 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1974 SSE_INTALU_ITINS_P, 1>,
1975 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1976 defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VK8WM, VR512,
1977 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
1978 SSE_INTALU_ITINS_P, 0>,
1979 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1981 defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VK16WM, VR512,
1982 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1983 SSE_INTALU_ITINS_P, 1>,
1984 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1985 defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VK8WM, VR512,
1986 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
1987 SSE_INTALU_ITINS_P, 0>,
1988 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1990 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
1991 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1992 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
1993 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
1994 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1995 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
1996 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
1997 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1998 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
1999 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
2000 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2001 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
2002 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
2003 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2004 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
2005 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
2006 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2007 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
2008 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
2009 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2010 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
2011 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
2012 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2013 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
2014 //===----------------------------------------------------------------------===//
2015 // AVX-512 - Unpack Instructions
2016 //===----------------------------------------------------------------------===//
2018 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
2019 PatFrag mem_frag, RegisterClass RC,
2020 X86MemOperand x86memop, string asm,
2022 def rr : AVX512PI<opc, MRMSrcReg,
2023 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2025 (vt (OpNode RC:$src1, RC:$src2)))],
2027 def rm : AVX512PI<opc, MRMSrcMem,
2028 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2030 (vt (OpNode RC:$src1,
2031 (bitconvert (mem_frag addr:$src2)))))],
2035 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
2036 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2037 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2038 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
2039 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2040 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2041 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
2042 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2043 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2044 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
2045 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2046 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2048 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
2049 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2050 X86MemOperand x86memop> {
2051 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2052 (ins RC:$src1, RC:$src2),
2053 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2054 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2055 IIC_SSE_UNPCK>, EVEX_4V;
2056 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2057 (ins RC:$src1, x86memop:$src2),
2058 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2059 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
2060 (bitconvert (memop_frag addr:$src2)))))],
2061 IIC_SSE_UNPCK>, EVEX_4V;
2063 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
2064 VR512, memopv16i32, i512mem>, EVEX_V512,
2065 EVEX_CD8<32, CD8VF>;
2066 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
2067 VR512, memopv8i64, i512mem>, EVEX_V512,
2068 VEX_W, EVEX_CD8<64, CD8VF>;
2069 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
2070 VR512, memopv16i32, i512mem>, EVEX_V512,
2071 EVEX_CD8<32, CD8VF>;
2072 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
2073 VR512, memopv8i64, i512mem>, EVEX_V512,
2074 VEX_W, EVEX_CD8<64, CD8VF>;
2075 //===----------------------------------------------------------------------===//
2079 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
2080 SDNode OpNode, PatFrag mem_frag,
2081 X86MemOperand x86memop, ValueType OpVT> {
2082 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
2083 (ins RC:$src1, i8imm:$src2),
2084 !strconcat(OpcodeStr,
2085 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2087 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
2089 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
2090 (ins x86memop:$src1, i8imm:$src2),
2091 !strconcat(OpcodeStr,
2092 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2094 (OpVT (OpNode (mem_frag addr:$src1),
2095 (i8 imm:$src2))))]>, EVEX;
2098 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
2099 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2101 let ExeDomain = SSEPackedSingle in
2102 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
2103 memopv16f32, i512mem, v16f32>, TAPD, EVEX_V512,
2104 EVEX_CD8<32, CD8VF>;
2105 let ExeDomain = SSEPackedDouble in
2106 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
2107 memopv8f64, i512mem, v8f64>, TAPD, EVEX_V512,
2108 VEX_W, EVEX_CD8<32, CD8VF>;
2110 def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
2111 (VPERMILPSZri VR512:$src1, imm:$imm)>;
2112 def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
2113 (VPERMILPDZri VR512:$src1, imm:$imm)>;
2115 //===----------------------------------------------------------------------===//
2116 // AVX-512 Logical Instructions
2117 //===----------------------------------------------------------------------===//
2119 defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VK16WM, VR512, memopv16i32,
2120 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2121 EVEX_V512, EVEX_CD8<32, CD8VF>;
2122 defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VK8WM, VR512, memopv8i64,
2123 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2124 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2125 defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VK16WM, VR512, memopv16i32,
2126 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2127 EVEX_V512, EVEX_CD8<32, CD8VF>;
2128 defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VK8WM, VR512, memopv8i64,
2129 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2130 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2131 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VK16WM, VR512, memopv16i32,
2132 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2133 EVEX_V512, EVEX_CD8<32, CD8VF>;
2134 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VK8WM, VR512, memopv8i64,
2135 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2136 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2137 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VK16WM, VR512,
2138 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2139 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2140 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VK8WM, VR512,
2141 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2142 SSE_BIT_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2144 //===----------------------------------------------------------------------===//
2145 // AVX-512 FP arithmetic
2146 //===----------------------------------------------------------------------===//
2148 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2150 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
2151 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
2152 EVEX_CD8<32, CD8VT1>;
2153 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
2154 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
2155 EVEX_CD8<64, CD8VT1>;
2158 let isCommutable = 1 in {
2159 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
2160 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
2161 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
2162 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
2164 let isCommutable = 0 in {
2165 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
2166 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
2169 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2171 RegisterClass RC, ValueType vt,
2172 X86MemOperand x86memop, PatFrag mem_frag,
2173 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2175 Domain d, OpndItins itins, bit commutable> {
2176 let isCommutable = commutable in {
2177 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2178 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2179 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
2182 def rrk: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2183 !strconcat(OpcodeStr,
2184 " \t{$src2, $src1, $dst {${mask}} |$dst {${mask}}, $src1, $src2}"),
2185 [], itins.rr, d>, EVEX_4V, EVEX_K;
2187 def rrkz: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2188 !strconcat(OpcodeStr,
2189 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2190 [], itins.rr, d>, EVEX_4V, EVEX_KZ;
2193 let mayLoad = 1 in {
2194 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2195 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2196 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
2197 itins.rm, d>, EVEX_4V;
2199 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
2200 (ins RC:$src1, x86scalar_mop:$src2),
2201 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2202 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2203 [(set RC:$dst, (OpNode RC:$src1,
2204 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
2205 itins.rm, d>, EVEX_4V, EVEX_B;
2207 def rmk : PI<opc, MRMSrcMem, (outs RC:$dst),
2208 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2209 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2210 [], itins.rm, d>, EVEX_4V, EVEX_K;
2212 def rmkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2213 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2214 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2215 [], itins.rm, d>, EVEX_4V, EVEX_KZ;
2217 def rmbk : PI<opc, MRMSrcMem, (outs RC:$dst),
2218 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2219 " \t{${src2}", BrdcstStr,
2220 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}", BrdcstStr, "}"),
2221 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_K;
2223 def rmbkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2224 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2225 " \t{${src2}", BrdcstStr,
2226 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2228 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_KZ;
2232 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VK16WM, VR512, v16f32, f512mem,
2233 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2234 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2236 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VK8WM, VR512, v8f64, f512mem,
2237 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2238 SSE_ALU_ITINS_P.d, 1>,
2239 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2241 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VK16WM, VR512, v16f32, f512mem,
2242 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2243 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2244 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VK8WM, VR512, v8f64, f512mem,
2245 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2246 SSE_ALU_ITINS_P.d, 1>,
2247 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2249 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VK16WM, VR512, v16f32, f512mem,
2250 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2251 SSE_ALU_ITINS_P.s, 1>,
2252 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2253 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VK16WM, VR512, v16f32, f512mem,
2254 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2255 SSE_ALU_ITINS_P.s, 1>,
2256 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2258 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VK8WM, VR512, v8f64, f512mem,
2259 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2260 SSE_ALU_ITINS_P.d, 1>,
2261 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2262 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VK8WM, VR512, v8f64, f512mem,
2263 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2264 SSE_ALU_ITINS_P.d, 1>,
2265 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2267 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VK16WM, VR512, v16f32, f512mem,
2268 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2269 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2270 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VK16WM, VR512, v16f32, f512mem,
2271 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2272 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2274 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VK8WM, VR512, v8f64, f512mem,
2275 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2276 SSE_ALU_ITINS_P.d, 0>,
2277 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2278 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VK8WM, VR512, v8f64, f512mem,
2279 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2280 SSE_ALU_ITINS_P.d, 0>,
2281 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2283 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
2284 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2285 (i16 -1), FROUND_CURRENT)),
2286 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
2288 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
2289 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2290 (i8 -1), FROUND_CURRENT)),
2291 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
2293 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
2294 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2295 (i16 -1), FROUND_CURRENT)),
2296 (VMINPSZrr VR512:$src1, VR512:$src2)>;
2298 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
2299 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2300 (i8 -1), FROUND_CURRENT)),
2301 (VMINPDZrr VR512:$src1, VR512:$src2)>;
2302 //===----------------------------------------------------------------------===//
2303 // AVX-512 VPTESTM instructions
2304 //===----------------------------------------------------------------------===//
2306 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2307 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
2308 SDNode OpNode, ValueType vt> {
2309 def rr : AVX512PI<opc, MRMSrcReg,
2310 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
2311 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2312 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
2313 SSEPackedInt>, EVEX_4V;
2314 def rm : AVX512PI<opc, MRMSrcMem,
2315 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
2316 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2317 [(set KRC:$dst, (OpNode (vt RC:$src1),
2318 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
2321 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
2322 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
2323 EVEX_CD8<32, CD8VF>;
2324 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
2325 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
2326 EVEX_CD8<64, CD8VF>;
2328 let Predicates = [HasCDI] in {
2329 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
2330 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
2331 EVEX_CD8<32, CD8VF>;
2332 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
2333 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
2334 EVEX_CD8<64, CD8VF>;
2337 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
2338 (v16i32 VR512:$src2), (i16 -1))),
2339 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
2341 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
2342 (v8i64 VR512:$src2), (i8 -1))),
2343 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
2344 //===----------------------------------------------------------------------===//
2345 // AVX-512 Shift instructions
2346 //===----------------------------------------------------------------------===//
2347 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
2348 string OpcodeStr, SDNode OpNode, RegisterClass RC,
2349 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
2350 RegisterClass KRC> {
2351 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2352 (ins RC:$src1, i8imm:$src2),
2353 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2354 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
2355 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2356 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2357 (ins KRC:$mask, RC:$src1, i8imm:$src2),
2358 !strconcat(OpcodeStr,
2359 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2360 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2361 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2362 (ins x86memop:$src1, i8imm:$src2),
2363 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2364 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
2365 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2366 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2367 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
2368 !strconcat(OpcodeStr,
2369 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2370 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2373 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2374 RegisterClass RC, ValueType vt, ValueType SrcVT,
2375 PatFrag bc_frag, RegisterClass KRC> {
2376 // src2 is always 128-bit
2377 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2378 (ins RC:$src1, VR128X:$src2),
2379 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2380 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
2381 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2382 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2383 (ins KRC:$mask, RC:$src1, VR128X:$src2),
2384 !strconcat(OpcodeStr,
2385 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2386 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2387 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2388 (ins RC:$src1, i128mem:$src2),
2389 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2390 [(set RC:$dst, (vt (OpNode RC:$src1,
2391 (bc_frag (memopv2i64 addr:$src2)))))],
2392 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2393 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2394 (ins KRC:$mask, RC:$src1, i128mem:$src2),
2395 !strconcat(OpcodeStr,
2396 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2397 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2400 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
2401 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2402 EVEX_V512, EVEX_CD8<32, CD8VF>;
2403 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
2404 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2405 EVEX_CD8<32, CD8VQ>;
2407 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
2408 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2409 EVEX_CD8<64, CD8VF>, VEX_W;
2410 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
2411 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2412 EVEX_CD8<64, CD8VQ>, VEX_W;
2414 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
2415 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
2416 EVEX_CD8<32, CD8VF>;
2417 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
2418 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2419 EVEX_CD8<32, CD8VQ>;
2421 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
2422 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2423 EVEX_CD8<64, CD8VF>, VEX_W;
2424 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
2425 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2426 EVEX_CD8<64, CD8VQ>, VEX_W;
2428 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
2429 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2430 EVEX_V512, EVEX_CD8<32, CD8VF>;
2431 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
2432 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2433 EVEX_CD8<32, CD8VQ>;
2435 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
2436 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2437 EVEX_CD8<64, CD8VF>, VEX_W;
2438 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
2439 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2440 EVEX_CD8<64, CD8VQ>, VEX_W;
2442 //===-------------------------------------------------------------------===//
2443 // Variable Bit Shifts
2444 //===-------------------------------------------------------------------===//
2445 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
2446 RegisterClass RC, ValueType vt,
2447 X86MemOperand x86memop, PatFrag mem_frag> {
2448 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
2449 (ins RC:$src1, RC:$src2),
2450 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2452 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
2454 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
2455 (ins RC:$src1, x86memop:$src2),
2456 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2458 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
2462 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
2463 i512mem, memopv16i32>, EVEX_V512,
2464 EVEX_CD8<32, CD8VF>;
2465 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
2466 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2467 EVEX_CD8<64, CD8VF>;
2468 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
2469 i512mem, memopv16i32>, EVEX_V512,
2470 EVEX_CD8<32, CD8VF>;
2471 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
2472 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2473 EVEX_CD8<64, CD8VF>;
2474 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
2475 i512mem, memopv16i32>, EVEX_V512,
2476 EVEX_CD8<32, CD8VF>;
2477 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
2478 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2479 EVEX_CD8<64, CD8VF>;
2481 //===----------------------------------------------------------------------===//
2482 // AVX-512 - MOVDDUP
2483 //===----------------------------------------------------------------------===//
2485 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
2486 X86MemOperand x86memop, PatFrag memop_frag> {
2487 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2488 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2489 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
2490 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2491 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2493 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
2496 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
2497 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
2498 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
2499 (VMOVDDUPZrm addr:$src)>;
2501 //===---------------------------------------------------------------------===//
2502 // Replicate Single FP - MOVSHDUP and MOVSLDUP
2503 //===---------------------------------------------------------------------===//
2504 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
2505 ValueType vt, RegisterClass RC, PatFrag mem_frag,
2506 X86MemOperand x86memop> {
2507 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2508 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2509 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
2511 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2512 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2513 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
2516 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
2517 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2518 EVEX_CD8<32, CD8VF>;
2519 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
2520 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2521 EVEX_CD8<32, CD8VF>;
2523 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
2524 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
2525 (VMOVSHDUPZrm addr:$src)>;
2526 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
2527 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
2528 (VMOVSLDUPZrm addr:$src)>;
2530 //===----------------------------------------------------------------------===//
2531 // Move Low to High and High to Low packed FP Instructions
2532 //===----------------------------------------------------------------------===//
2533 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
2534 (ins VR128X:$src1, VR128X:$src2),
2535 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2536 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2537 IIC_SSE_MOV_LH>, EVEX_4V;
2538 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2539 (ins VR128X:$src1, VR128X:$src2),
2540 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2541 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2542 IIC_SSE_MOV_LH>, EVEX_4V;
2544 let Predicates = [HasAVX512] in {
2546 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2547 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2548 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2549 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
2552 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2553 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2556 //===----------------------------------------------------------------------===//
2557 // FMA - Fused Multiply Operations
2559 let Constraints = "$src1 = $dst" in {
2560 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2561 RegisterClass RC, X86MemOperand x86memop,
2562 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2563 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2564 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2565 (ins RC:$src1, RC:$src2, RC:$src3),
2566 !strconcat(OpcodeStr," \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2567 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2570 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2571 (ins RC:$src1, RC:$src2, x86memop:$src3),
2572 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2573 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2574 (mem_frag addr:$src3))))]>;
2575 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2576 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2577 !strconcat(OpcodeStr, " \t{${src3}", BrdcstStr,
2578 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2579 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2580 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2582 } // Constraints = "$src1 = $dst"
2584 let ExeDomain = SSEPackedSingle in {
2585 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2586 memopv16f32, f32mem, loadf32, "{1to16}",
2587 X86Fmadd, v16f32>, EVEX_V512,
2588 EVEX_CD8<32, CD8VF>;
2589 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2590 memopv16f32, f32mem, loadf32, "{1to16}",
2591 X86Fmsub, v16f32>, EVEX_V512,
2592 EVEX_CD8<32, CD8VF>;
2593 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2594 memopv16f32, f32mem, loadf32, "{1to16}",
2595 X86Fmaddsub, v16f32>,
2596 EVEX_V512, EVEX_CD8<32, CD8VF>;
2597 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2598 memopv16f32, f32mem, loadf32, "{1to16}",
2599 X86Fmsubadd, v16f32>,
2600 EVEX_V512, EVEX_CD8<32, CD8VF>;
2601 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2602 memopv16f32, f32mem, loadf32, "{1to16}",
2603 X86Fnmadd, v16f32>, EVEX_V512,
2604 EVEX_CD8<32, CD8VF>;
2605 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2606 memopv16f32, f32mem, loadf32, "{1to16}",
2607 X86Fnmsub, v16f32>, EVEX_V512,
2608 EVEX_CD8<32, CD8VF>;
2610 let ExeDomain = SSEPackedDouble in {
2611 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2612 memopv8f64, f64mem, loadf64, "{1to8}",
2613 X86Fmadd, v8f64>, EVEX_V512,
2614 VEX_W, EVEX_CD8<64, CD8VF>;
2615 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2616 memopv8f64, f64mem, loadf64, "{1to8}",
2617 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2618 EVEX_CD8<64, CD8VF>;
2619 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2620 memopv8f64, f64mem, loadf64, "{1to8}",
2621 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2622 EVEX_CD8<64, CD8VF>;
2623 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2624 memopv8f64, f64mem, loadf64, "{1to8}",
2625 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2626 EVEX_CD8<64, CD8VF>;
2627 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2628 memopv8f64, f64mem, loadf64, "{1to8}",
2629 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2630 EVEX_CD8<64, CD8VF>;
2631 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2632 memopv8f64, f64mem, loadf64, "{1to8}",
2633 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2634 EVEX_CD8<64, CD8VF>;
2637 let Constraints = "$src1 = $dst" in {
2638 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2639 RegisterClass RC, X86MemOperand x86memop,
2640 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2641 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2643 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2644 (ins RC:$src1, RC:$src3, x86memop:$src2),
2645 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2646 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2647 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2648 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2649 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2650 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2651 [(set RC:$dst, (OpNode RC:$src1,
2652 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2654 } // Constraints = "$src1 = $dst"
2657 let ExeDomain = SSEPackedSingle in {
2658 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2659 memopv16f32, f32mem, loadf32, "{1to16}",
2660 X86Fmadd, v16f32>, EVEX_V512,
2661 EVEX_CD8<32, CD8VF>;
2662 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2663 memopv16f32, f32mem, loadf32, "{1to16}",
2664 X86Fmsub, v16f32>, EVEX_V512,
2665 EVEX_CD8<32, CD8VF>;
2666 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
2667 memopv16f32, f32mem, loadf32, "{1to16}",
2668 X86Fmaddsub, v16f32>,
2669 EVEX_V512, EVEX_CD8<32, CD8VF>;
2670 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
2671 memopv16f32, f32mem, loadf32, "{1to16}",
2672 X86Fmsubadd, v16f32>,
2673 EVEX_V512, EVEX_CD8<32, CD8VF>;
2674 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
2675 memopv16f32, f32mem, loadf32, "{1to16}",
2676 X86Fnmadd, v16f32>, EVEX_V512,
2677 EVEX_CD8<32, CD8VF>;
2678 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
2679 memopv16f32, f32mem, loadf32, "{1to16}",
2680 X86Fnmsub, v16f32>, EVEX_V512,
2681 EVEX_CD8<32, CD8VF>;
2683 let ExeDomain = SSEPackedDouble in {
2684 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
2685 memopv8f64, f64mem, loadf64, "{1to8}",
2686 X86Fmadd, v8f64>, EVEX_V512,
2687 VEX_W, EVEX_CD8<64, CD8VF>;
2688 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
2689 memopv8f64, f64mem, loadf64, "{1to8}",
2690 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2691 EVEX_CD8<64, CD8VF>;
2692 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
2693 memopv8f64, f64mem, loadf64, "{1to8}",
2694 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2695 EVEX_CD8<64, CD8VF>;
2696 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
2697 memopv8f64, f64mem, loadf64, "{1to8}",
2698 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2699 EVEX_CD8<64, CD8VF>;
2700 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
2701 memopv8f64, f64mem, loadf64, "{1to8}",
2702 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2703 EVEX_CD8<64, CD8VF>;
2704 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
2705 memopv8f64, f64mem, loadf64, "{1to8}",
2706 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2707 EVEX_CD8<64, CD8VF>;
2711 let Constraints = "$src1 = $dst" in {
2712 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2713 RegisterClass RC, ValueType OpVT,
2714 X86MemOperand x86memop, Operand memop,
2716 let isCommutable = 1 in
2717 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2718 (ins RC:$src1, RC:$src2, RC:$src3),
2719 !strconcat(OpcodeStr,
2720 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2722 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
2724 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2725 (ins RC:$src1, RC:$src2, f128mem:$src3),
2726 !strconcat(OpcodeStr,
2727 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2729 (OpVT (OpNode RC:$src2, RC:$src1,
2730 (mem_frag addr:$src3))))]>;
2733 } // Constraints = "$src1 = $dst"
2735 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
2736 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2737 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
2738 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2739 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
2740 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2741 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
2742 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2743 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
2744 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2745 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
2746 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2747 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
2748 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2749 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
2750 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2752 //===----------------------------------------------------------------------===//
2753 // AVX-512 Scalar convert from sign integer to float/double
2754 //===----------------------------------------------------------------------===//
2756 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2757 X86MemOperand x86memop, string asm> {
2758 let hasSideEffects = 0 in {
2759 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
2760 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2763 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
2764 (ins DstRC:$src1, x86memop:$src),
2765 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2767 } // hasSideEffects = 0
2769 let Predicates = [HasAVX512] in {
2770 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
2771 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2772 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
2773 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2774 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
2775 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2776 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
2777 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2779 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
2780 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2781 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
2782 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2783 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
2784 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2785 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
2786 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2788 def : Pat<(f32 (sint_to_fp GR32:$src)),
2789 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2790 def : Pat<(f32 (sint_to_fp GR64:$src)),
2791 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2792 def : Pat<(f64 (sint_to_fp GR32:$src)),
2793 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2794 def : Pat<(f64 (sint_to_fp GR64:$src)),
2795 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2797 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
2798 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2799 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
2800 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2801 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
2802 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2803 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
2804 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2806 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
2807 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2808 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
2809 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2810 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
2811 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2812 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
2813 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2815 def : Pat<(f32 (uint_to_fp GR32:$src)),
2816 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2817 def : Pat<(f32 (uint_to_fp GR64:$src)),
2818 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2819 def : Pat<(f64 (uint_to_fp GR32:$src)),
2820 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2821 def : Pat<(f64 (uint_to_fp GR64:$src)),
2822 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2825 //===----------------------------------------------------------------------===//
2826 // AVX-512 Scalar convert from float/double to integer
2827 //===----------------------------------------------------------------------===//
2828 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2829 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
2831 let hasSideEffects = 0 in {
2832 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2833 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2834 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
2835 Requires<[HasAVX512]>;
2837 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
2838 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
2839 Requires<[HasAVX512]>;
2840 } // hasSideEffects = 0
2842 let Predicates = [HasAVX512] in {
2843 // Convert float/double to signed/unsigned int 32/64
2844 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
2845 ssmem, sse_load_f32, "cvtss2si">,
2846 XS, EVEX_CD8<32, CD8VT1>;
2847 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
2848 ssmem, sse_load_f32, "cvtss2si">,
2849 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
2850 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
2851 ssmem, sse_load_f32, "cvtss2usi">,
2852 XS, EVEX_CD8<32, CD8VT1>;
2853 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2854 int_x86_avx512_cvtss2usi64, ssmem,
2855 sse_load_f32, "cvtss2usi">, XS, VEX_W,
2856 EVEX_CD8<32, CD8VT1>;
2857 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
2858 sdmem, sse_load_f64, "cvtsd2si">,
2859 XD, EVEX_CD8<64, CD8VT1>;
2860 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
2861 sdmem, sse_load_f64, "cvtsd2si">,
2862 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2863 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
2864 sdmem, sse_load_f64, "cvtsd2usi">,
2865 XD, EVEX_CD8<64, CD8VT1>;
2866 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2867 int_x86_avx512_cvtsd2usi64, sdmem,
2868 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
2869 EVEX_CD8<64, CD8VT1>;
2871 let isCodeGenOnly = 1 in {
2872 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2873 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
2874 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2875 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2876 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
2877 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2878 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2879 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
2880 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2881 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2882 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
2883 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2885 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2886 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
2887 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2888 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2889 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
2890 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2891 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2892 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
2893 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2894 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2895 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
2896 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2897 } // isCodeGenOnly = 1
2899 // Convert float/double to signed/unsigned int 32/64 with truncation
2900 let isCodeGenOnly = 1 in {
2901 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
2902 ssmem, sse_load_f32, "cvttss2si">,
2903 XS, EVEX_CD8<32, CD8VT1>;
2904 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2905 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
2906 "cvttss2si">, XS, VEX_W,
2907 EVEX_CD8<32, CD8VT1>;
2908 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
2909 sdmem, sse_load_f64, "cvttsd2si">, XD,
2910 EVEX_CD8<64, CD8VT1>;
2911 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2912 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
2913 "cvttsd2si">, XD, VEX_W,
2914 EVEX_CD8<64, CD8VT1>;
2915 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2916 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
2917 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
2918 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2919 int_x86_avx512_cvttss2usi64, ssmem,
2920 sse_load_f32, "cvttss2usi">, XS, VEX_W,
2921 EVEX_CD8<32, CD8VT1>;
2922 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2923 int_x86_avx512_cvttsd2usi,
2924 sdmem, sse_load_f64, "cvttsd2usi">, XD,
2925 EVEX_CD8<64, CD8VT1>;
2926 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2927 int_x86_avx512_cvttsd2usi64, sdmem,
2928 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
2929 EVEX_CD8<64, CD8VT1>;
2930 } // isCodeGenOnly = 1
2932 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2933 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
2935 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2936 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2937 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
2938 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2939 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2940 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
2943 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
2944 loadf32, "cvttss2si">, XS,
2945 EVEX_CD8<32, CD8VT1>;
2946 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
2947 loadf32, "cvttss2usi">, XS,
2948 EVEX_CD8<32, CD8VT1>;
2949 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
2950 loadf32, "cvttss2si">, XS, VEX_W,
2951 EVEX_CD8<32, CD8VT1>;
2952 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
2953 loadf32, "cvttss2usi">, XS, VEX_W,
2954 EVEX_CD8<32, CD8VT1>;
2955 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
2956 loadf64, "cvttsd2si">, XD,
2957 EVEX_CD8<64, CD8VT1>;
2958 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
2959 loadf64, "cvttsd2usi">, XD,
2960 EVEX_CD8<64, CD8VT1>;
2961 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
2962 loadf64, "cvttsd2si">, XD, VEX_W,
2963 EVEX_CD8<64, CD8VT1>;
2964 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
2965 loadf64, "cvttsd2usi">, XD, VEX_W,
2966 EVEX_CD8<64, CD8VT1>;
2968 //===----------------------------------------------------------------------===//
2969 // AVX-512 Convert form float to double and back
2970 //===----------------------------------------------------------------------===//
2971 let hasSideEffects = 0 in {
2972 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
2973 (ins FR32X:$src1, FR32X:$src2),
2974 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2975 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
2977 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
2978 (ins FR32X:$src1, f32mem:$src2),
2979 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2980 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
2981 EVEX_CD8<32, CD8VT1>;
2983 // Convert scalar double to scalar single
2984 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
2985 (ins FR64X:$src1, FR64X:$src2),
2986 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2987 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
2989 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
2990 (ins FR64X:$src1, f64mem:$src2),
2991 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2992 []>, EVEX_4V, VEX_LIG, VEX_W,
2993 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
2996 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
2997 Requires<[HasAVX512]>;
2998 def : Pat<(fextend (loadf32 addr:$src)),
2999 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3001 def : Pat<(extloadf32 addr:$src),
3002 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3003 Requires<[HasAVX512, OptForSize]>;
3005 def : Pat<(extloadf32 addr:$src),
3006 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3007 Requires<[HasAVX512, OptForSpeed]>;
3009 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3010 Requires<[HasAVX512]>;
3012 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
3013 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3014 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3016 let hasSideEffects = 0 in {
3017 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3018 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3020 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3021 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3022 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3023 [], d>, EVEX, EVEX_B, EVEX_RC;
3025 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3026 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3028 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3029 } // hasSideEffects = 0
3032 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
3033 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3034 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3036 let hasSideEffects = 0 in {
3037 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3038 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3040 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3042 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3043 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3045 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3046 } // hasSideEffects = 0
3049 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
3050 memopv8f64, f512mem, v8f32, v8f64,
3051 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
3052 EVEX_CD8<64, CD8VF>;
3054 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3055 memopv4f64, f256mem, v8f64, v8f32,
3056 SSEPackedDouble>, EVEX_V512, PS,
3057 EVEX_CD8<32, CD8VH>;
3058 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3059 (VCVTPS2PDZrm addr:$src)>;
3061 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3062 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3063 (VCVTPD2PSZrr VR512:$src)>;
3065 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3066 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3067 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
3069 //===----------------------------------------------------------------------===//
3070 // AVX-512 Vector convert from sign integer to float/double
3071 //===----------------------------------------------------------------------===//
3073 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
3074 memopv8i64, i512mem, v16f32, v16i32,
3075 SSEPackedSingle>, EVEX_V512, PS,
3076 EVEX_CD8<32, CD8VF>;
3078 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
3079 memopv4i64, i256mem, v8f64, v8i32,
3080 SSEPackedDouble>, EVEX_V512, XS,
3081 EVEX_CD8<32, CD8VH>;
3083 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
3084 memopv16f32, f512mem, v16i32, v16f32,
3085 SSEPackedSingle>, EVEX_V512, XS,
3086 EVEX_CD8<32, CD8VF>;
3088 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
3089 memopv8f64, f512mem, v8i32, v8f64,
3090 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
3091 EVEX_CD8<64, CD8VF>;
3093 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
3094 memopv16f32, f512mem, v16i32, v16f32,
3095 SSEPackedSingle>, EVEX_V512, PS,
3096 EVEX_CD8<32, CD8VF>;
3098 // cvttps2udq (src, 0, mask-all-ones, sae-current)
3099 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
3100 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
3101 (VCVTTPS2UDQZrr VR512:$src)>;
3103 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
3104 memopv8f64, f512mem, v8i32, v8f64,
3105 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
3106 EVEX_CD8<64, CD8VF>;
3108 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
3109 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
3110 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
3111 (VCVTTPD2UDQZrr VR512:$src)>;
3113 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
3114 memopv4i64, f256mem, v8f64, v8i32,
3115 SSEPackedDouble>, EVEX_V512, XS,
3116 EVEX_CD8<32, CD8VH>;
3118 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
3119 memopv16i32, f512mem, v16f32, v16i32,
3120 SSEPackedSingle>, EVEX_V512, XD,
3121 EVEX_CD8<32, CD8VF>;
3123 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
3124 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3125 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3127 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
3128 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3129 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3131 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
3132 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3133 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3135 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
3136 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3137 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3139 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
3140 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3141 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
3142 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
3143 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3144 (VCVTDQ2PDZrr VR256X:$src)>;
3145 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
3146 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3147 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
3148 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
3149 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3150 (VCVTUDQ2PDZrr VR256X:$src)>;
3152 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
3153 RegisterClass DstRC, PatFrag mem_frag,
3154 X86MemOperand x86memop, Domain d> {
3155 let hasSideEffects = 0 in {
3156 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3157 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3159 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3160 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3161 [], d>, EVEX, EVEX_B, EVEX_RC;
3163 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3164 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3166 } // hasSideEffects = 0
3169 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
3170 memopv16f32, f512mem, SSEPackedSingle>, PD,
3171 EVEX_V512, EVEX_CD8<32, CD8VF>;
3172 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
3173 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
3174 EVEX_V512, EVEX_CD8<64, CD8VF>;
3176 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
3177 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3178 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
3180 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
3181 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3182 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
3184 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
3185 memopv16f32, f512mem, SSEPackedSingle>,
3186 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3187 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
3188 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
3189 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
3191 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
3192 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3193 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
3195 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
3196 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3197 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
3199 let Predicates = [HasAVX512] in {
3200 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
3201 (VCVTPD2PSZrm addr:$src)>;
3202 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3203 (VCVTPS2PDZrm addr:$src)>;
3206 //===----------------------------------------------------------------------===//
3207 // Half precision conversion instructions
3208 //===----------------------------------------------------------------------===//
3209 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
3210 X86MemOperand x86memop> {
3211 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
3212 "vcvtph2ps\t{$src, $dst|$dst, $src}",
3214 let hasSideEffects = 0, mayLoad = 1 in
3215 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
3216 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
3219 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
3220 X86MemOperand x86memop> {
3221 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
3222 (ins srcRC:$src1, i32i8imm:$src2),
3223 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}",
3225 let hasSideEffects = 0, mayStore = 1 in
3226 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
3227 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
3228 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
3231 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
3232 EVEX_CD8<32, CD8VH>;
3233 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
3234 EVEX_CD8<32, CD8VH>;
3236 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
3237 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
3238 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
3240 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
3241 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
3242 (VCVTPH2PSZrr VR256X:$src)>;
3244 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
3245 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
3246 "ucomiss">, PS, EVEX, VEX_LIG,
3247 EVEX_CD8<32, CD8VT1>;
3248 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
3249 "ucomisd">, PD, EVEX,
3250 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3251 let Pattern = []<dag> in {
3252 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
3253 "comiss">, PS, EVEX, VEX_LIG,
3254 EVEX_CD8<32, CD8VT1>;
3255 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
3256 "comisd">, PD, EVEX,
3257 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3259 let isCodeGenOnly = 1 in {
3260 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
3261 load, "ucomiss">, PS, EVEX, VEX_LIG,
3262 EVEX_CD8<32, CD8VT1>;
3263 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
3264 load, "ucomisd">, PD, EVEX,
3265 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3267 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
3268 load, "comiss">, PS, EVEX, VEX_LIG,
3269 EVEX_CD8<32, CD8VT1>;
3270 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
3271 load, "comisd">, PD, EVEX,
3272 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3276 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
3277 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3278 X86MemOperand x86memop> {
3279 let hasSideEffects = 0 in {
3280 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3281 (ins RC:$src1, RC:$src2),
3282 !strconcat(OpcodeStr,
3283 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3284 let mayLoad = 1 in {
3285 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3286 (ins RC:$src1, x86memop:$src2),
3287 !strconcat(OpcodeStr,
3288 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3293 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
3294 EVEX_CD8<32, CD8VT1>;
3295 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
3296 VEX_W, EVEX_CD8<64, CD8VT1>;
3297 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
3298 EVEX_CD8<32, CD8VT1>;
3299 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
3300 VEX_W, EVEX_CD8<64, CD8VT1>;
3302 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
3303 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3304 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3305 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3307 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
3308 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3309 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3310 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3312 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
3313 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3314 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3315 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3317 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
3318 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3319 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3320 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3322 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
3323 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3324 RegisterClass RC, X86MemOperand x86memop,
3325 PatFrag mem_frag, ValueType OpVt> {
3326 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3327 !strconcat(OpcodeStr,
3328 " \t{$src, $dst|$dst, $src}"),
3329 [(set RC:$dst, (OpVt (OpNode RC:$src)))]>,
3331 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3332 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3333 [(set RC:$dst, (OpVt (OpNode (mem_frag addr:$src))))]>,
3336 defm VRSQRT14PSZ : avx512_fp14_p<0x4E, "vrsqrt14ps", X86frsqrt, VR512, f512mem,
3337 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3338 defm VRSQRT14PDZ : avx512_fp14_p<0x4E, "vrsqrt14pd", X86frsqrt, VR512, f512mem,
3339 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3340 defm VRCP14PSZ : avx512_fp14_p<0x4C, "vrcp14ps", X86frcp, VR512, f512mem,
3341 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3342 defm VRCP14PDZ : avx512_fp14_p<0x4C, "vrcp14pd", X86frcp, VR512, f512mem,
3343 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3345 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
3346 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3347 (VRSQRT14PSZr VR512:$src)>;
3348 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
3349 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3350 (VRSQRT14PDZr VR512:$src)>;
3352 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
3353 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3354 (VRCP14PSZr VR512:$src)>;
3355 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
3356 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3357 (VRCP14PDZr VR512:$src)>;
3359 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
3360 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3361 X86MemOperand x86memop> {
3362 let hasSideEffects = 0, Predicates = [HasERI] in {
3363 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3364 (ins RC:$src1, RC:$src2),
3365 !strconcat(OpcodeStr,
3366 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3367 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3368 (ins RC:$src1, RC:$src2),
3369 !strconcat(OpcodeStr,
3370 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
3371 []>, EVEX_4V, EVEX_B;
3372 let mayLoad = 1 in {
3373 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3374 (ins RC:$src1, x86memop:$src2),
3375 !strconcat(OpcodeStr,
3376 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3381 defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
3382 EVEX_CD8<32, CD8VT1>;
3383 defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
3384 VEX_W, EVEX_CD8<64, CD8VT1>;
3385 defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
3386 EVEX_CD8<32, CD8VT1>;
3387 defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
3388 VEX_W, EVEX_CD8<64, CD8VT1>;
3390 def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
3391 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3393 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3394 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3396 def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
3397 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3399 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3400 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3402 def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
3403 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3405 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3406 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3408 def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
3409 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3411 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3412 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3414 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
3415 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr,
3416 RegisterClass RC, X86MemOperand x86memop> {
3417 let hasSideEffects = 0, Predicates = [HasERI] in {
3418 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3419 !strconcat(OpcodeStr,
3420 " \t{$src, $dst|$dst, $src}"),
3422 def rb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3423 !strconcat(OpcodeStr,
3424 " \t{{sae}, $src, $dst|$dst, $src, {sae}}"),
3426 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3427 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3431 defm VRSQRT28PSZ : avx512_fp28_p<0xCC, "vrsqrt28ps", VR512, f512mem>,
3432 EVEX_V512, EVEX_CD8<32, CD8VF>;
3433 defm VRSQRT28PDZ : avx512_fp28_p<0xCC, "vrsqrt28pd", VR512, f512mem>,
3434 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3435 defm VRCP28PSZ : avx512_fp28_p<0xCA, "vrcp28ps", VR512, f512mem>,
3436 EVEX_V512, EVEX_CD8<32, CD8VF>;
3437 defm VRCP28PDZ : avx512_fp28_p<0xCA, "vrcp28pd", VR512, f512mem>,
3438 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3440 def : Pat <(v16f32 (int_x86_avx512_rsqrt28_ps (v16f32 VR512:$src),
3441 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3442 (VRSQRT28PSZrb VR512:$src)>;
3443 def : Pat <(v8f64 (int_x86_avx512_rsqrt28_pd (v8f64 VR512:$src),
3444 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3445 (VRSQRT28PDZrb VR512:$src)>;
3447 def : Pat <(v16f32 (int_x86_avx512_rcp28_ps (v16f32 VR512:$src),
3448 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3449 (VRCP28PSZrb VR512:$src)>;
3450 def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src),
3451 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3452 (VRCP28PDZrb VR512:$src)>;
3454 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3455 Intrinsic V16F32Int, Intrinsic V8F64Int,
3456 OpndItins itins_s, OpndItins itins_d> {
3457 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3458 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3459 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
3463 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3464 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3466 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
3467 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
3469 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3470 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3471 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
3475 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3476 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3477 [(set VR512:$dst, (OpNode
3478 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
3479 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
3481 let isCodeGenOnly = 1 in {
3482 def PSZr_Int : AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3483 !strconcat(OpcodeStr,
3484 "ps\t{$src, $dst|$dst, $src}"),
3485 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
3487 def PSZm_Int : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3488 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3490 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
3491 EVEX_V512, EVEX_CD8<32, CD8VF>;
3492 def PDZr_Int : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3493 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3494 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
3495 EVEX, EVEX_V512, VEX_W;
3496 def PDZm_Int : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3497 !strconcat(OpcodeStr,
3498 "pd\t{$src, $dst|$dst, $src}"),
3499 [(set VR512:$dst, (V8F64Int (memopv8f64 addr:$src)))]>,
3500 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3501 } // isCodeGenOnly = 1
3504 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
3505 Intrinsic F32Int, Intrinsic F64Int,
3506 OpndItins itins_s, OpndItins itins_d> {
3507 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
3508 (ins FR32X:$src1, FR32X:$src2),
3509 !strconcat(OpcodeStr,
3510 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3511 [], itins_s.rr>, XS, EVEX_4V;
3512 let isCodeGenOnly = 1 in
3513 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3514 (ins VR128X:$src1, VR128X:$src2),
3515 !strconcat(OpcodeStr,
3516 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3518 (F32Int VR128X:$src1, VR128X:$src2))],
3519 itins_s.rr>, XS, EVEX_4V;
3520 let mayLoad = 1 in {
3521 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
3522 (ins FR32X:$src1, f32mem:$src2),
3523 !strconcat(OpcodeStr,
3524 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3525 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3526 let isCodeGenOnly = 1 in
3527 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3528 (ins VR128X:$src1, ssmem:$src2),
3529 !strconcat(OpcodeStr,
3530 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3532 (F32Int VR128X:$src1, sse_load_f32:$src2))],
3533 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3535 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
3536 (ins FR64X:$src1, FR64X:$src2),
3537 !strconcat(OpcodeStr,
3538 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3540 let isCodeGenOnly = 1 in
3541 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3542 (ins VR128X:$src1, VR128X:$src2),
3543 !strconcat(OpcodeStr,
3544 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3546 (F64Int VR128X:$src1, VR128X:$src2))],
3547 itins_s.rr>, XD, EVEX_4V, VEX_W;
3548 let mayLoad = 1 in {
3549 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
3550 (ins FR64X:$src1, f64mem:$src2),
3551 !strconcat(OpcodeStr,
3552 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3553 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3554 let isCodeGenOnly = 1 in
3555 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3556 (ins VR128X:$src1, sdmem:$src2),
3557 !strconcat(OpcodeStr,
3558 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3560 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
3561 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3566 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
3567 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
3568 SSE_SQRTSS, SSE_SQRTSD>,
3569 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
3570 int_x86_avx512_sqrt_ps_512, int_x86_avx512_sqrt_pd_512,
3571 SSE_SQRTPS, SSE_SQRTPD>;
3573 let Predicates = [HasAVX512] in {
3574 def : Pat<(f32 (fsqrt FR32X:$src)),
3575 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3576 def : Pat<(f32 (fsqrt (load addr:$src))),
3577 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3578 Requires<[OptForSize]>;
3579 def : Pat<(f64 (fsqrt FR64X:$src)),
3580 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
3581 def : Pat<(f64 (fsqrt (load addr:$src))),
3582 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
3583 Requires<[OptForSize]>;
3585 def : Pat<(f32 (X86frsqrt FR32X:$src)),
3586 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3587 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3588 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3589 Requires<[OptForSize]>;
3591 def : Pat<(f32 (X86frcp FR32X:$src)),
3592 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3593 def : Pat<(f32 (X86frcp (load addr:$src))),
3594 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3595 Requires<[OptForSize]>;
3597 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
3598 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
3599 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3601 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3602 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3604 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
3605 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
3606 (COPY_TO_REGCLASS VR128X:$src, FR64)),
3608 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3609 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3613 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
3614 X86MemOperand x86memop, RegisterClass RC,
3615 PatFrag mem_frag32, PatFrag mem_frag64,
3616 Intrinsic V4F32Int, Intrinsic V2F64Int,
3618 let ExeDomain = SSEPackedSingle in {
3619 // Intrinsic operation, reg.
3620 // Vector intrinsic operation, reg
3621 def PSr : AVX512AIi8<opcps, MRMSrcReg,
3622 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3623 !strconcat(OpcodeStr,
3624 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3625 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
3627 // Vector intrinsic operation, mem
3628 def PSm : AVX512AIi8<opcps, MRMSrcMem,
3629 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3630 !strconcat(OpcodeStr,
3631 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3633 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
3634 EVEX_CD8<32, VForm>;
3635 } // ExeDomain = SSEPackedSingle
3637 let ExeDomain = SSEPackedDouble in {
3638 // Vector intrinsic operation, reg
3639 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
3640 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3641 !strconcat(OpcodeStr,
3642 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3643 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
3645 // Vector intrinsic operation, mem
3646 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
3647 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3648 !strconcat(OpcodeStr,
3649 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3651 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
3652 EVEX_CD8<64, VForm>;
3653 } // ExeDomain = SSEPackedDouble
3656 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3660 let ExeDomain = GenericDomain in {
3662 let hasSideEffects = 0 in
3663 def SSr : AVX512AIi8<opcss, MRMSrcReg,
3664 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
3665 !strconcat(OpcodeStr,
3666 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3669 // Intrinsic operation, reg.
3670 let isCodeGenOnly = 1 in
3671 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
3672 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3673 !strconcat(OpcodeStr,
3674 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3675 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
3677 // Intrinsic operation, mem.
3678 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
3679 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
3680 !strconcat(OpcodeStr,
3681 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3682 [(set VR128X:$dst, (F32Int VR128X:$src1,
3683 sse_load_f32:$src2, imm:$src3))]>,
3684 EVEX_CD8<32, CD8VT1>;
3687 let hasSideEffects = 0 in
3688 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
3689 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
3690 !strconcat(OpcodeStr,
3691 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3694 // Intrinsic operation, reg.
3695 let isCodeGenOnly = 1 in
3696 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
3697 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3698 !strconcat(OpcodeStr,
3699 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3700 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
3703 // Intrinsic operation, mem.
3704 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
3705 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
3706 !strconcat(OpcodeStr,
3707 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3709 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
3710 VEX_W, EVEX_CD8<64, CD8VT1>;
3711 } // ExeDomain = GenericDomain
3714 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
3715 X86MemOperand x86memop, RegisterClass RC,
3716 PatFrag mem_frag, Domain d> {
3717 let ExeDomain = d in {
3718 // Intrinsic operation, reg.
3719 // Vector intrinsic operation, reg
3720 def r : AVX512AIi8<opc, MRMSrcReg,
3721 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3722 !strconcat(OpcodeStr,
3723 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3726 // Vector intrinsic operation, mem
3727 def m : AVX512AIi8<opc, MRMSrcMem,
3728 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3729 !strconcat(OpcodeStr,
3730 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3736 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
3737 memopv16f32, SSEPackedSingle>, EVEX_V512,
3738 EVEX_CD8<32, CD8VF>;
3740 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
3741 imm:$src2, (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1),
3743 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
3746 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
3747 memopv8f64, SSEPackedDouble>, EVEX_V512,
3748 VEX_W, EVEX_CD8<64, CD8VF>;
3750 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
3751 imm:$src2, (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1),
3753 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
3755 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
3756 Operand x86memop, RegisterClass RC, Domain d> {
3757 let ExeDomain = d in {
3758 def r : AVX512AIi8<opc, MRMSrcReg,
3759 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
3760 !strconcat(OpcodeStr,
3761 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3764 def m : AVX512AIi8<opc, MRMSrcMem,
3765 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
3766 !strconcat(OpcodeStr,
3767 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3772 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
3773 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
3775 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
3776 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
3778 def : Pat<(ffloor FR32X:$src),
3779 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
3780 def : Pat<(f64 (ffloor FR64X:$src)),
3781 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
3782 def : Pat<(f32 (fnearbyint FR32X:$src)),
3783 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
3784 def : Pat<(f64 (fnearbyint FR64X:$src)),
3785 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
3786 def : Pat<(f32 (fceil FR32X:$src)),
3787 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
3788 def : Pat<(f64 (fceil FR64X:$src)),
3789 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
3790 def : Pat<(f32 (frint FR32X:$src)),
3791 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
3792 def : Pat<(f64 (frint FR64X:$src)),
3793 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
3794 def : Pat<(f32 (ftrunc FR32X:$src)),
3795 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
3796 def : Pat<(f64 (ftrunc FR64X:$src)),
3797 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
3799 def : Pat<(v16f32 (ffloor VR512:$src)),
3800 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
3801 def : Pat<(v16f32 (fnearbyint VR512:$src)),
3802 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
3803 def : Pat<(v16f32 (fceil VR512:$src)),
3804 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
3805 def : Pat<(v16f32 (frint VR512:$src)),
3806 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
3807 def : Pat<(v16f32 (ftrunc VR512:$src)),
3808 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
3810 def : Pat<(v8f64 (ffloor VR512:$src)),
3811 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
3812 def : Pat<(v8f64 (fnearbyint VR512:$src)),
3813 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
3814 def : Pat<(v8f64 (fceil VR512:$src)),
3815 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
3816 def : Pat<(v8f64 (frint VR512:$src)),
3817 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
3818 def : Pat<(v8f64 (ftrunc VR512:$src)),
3819 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
3821 //-------------------------------------------------
3822 // Integer truncate and extend operations
3823 //-------------------------------------------------
3825 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
3826 RegisterClass dstRC, RegisterClass srcRC,
3827 RegisterClass KRC, X86MemOperand x86memop> {
3828 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3830 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
3833 def krr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3834 (ins KRC:$mask, srcRC:$src),
3835 !strconcat(OpcodeStr,
3836 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3839 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
3840 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3843 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
3844 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3845 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
3846 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3847 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
3848 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3849 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
3850 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3851 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
3852 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3853 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
3854 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3855 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
3856 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3857 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
3858 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3859 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
3860 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3861 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
3862 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3863 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
3864 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3865 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
3866 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3867 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
3868 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3869 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
3870 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3871 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
3872 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3874 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
3875 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
3876 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
3877 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
3878 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
3880 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3881 (VPMOVDBkrr VK16WM:$mask, VR512:$src)>;
3882 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3883 (VPMOVDWkrr VK16WM:$mask, VR512:$src)>;
3884 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3885 (VPMOVQWkrr VK8WM:$mask, VR512:$src)>;
3886 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3887 (VPMOVQDkrr VK8WM:$mask, VR512:$src)>;
3890 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass DstRC,
3891 RegisterClass SrcRC, SDNode OpNode, PatFrag mem_frag,
3892 X86MemOperand x86memop, ValueType OpVT, ValueType InVT> {
3894 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
3896 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3897 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
3898 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
3899 (ins x86memop:$src),
3900 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
3902 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
3906 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VR512, VR128X, X86vzext,
3907 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3909 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VR512, VR128X, X86vzext,
3910 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3912 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VR512, VR256X, X86vzext,
3913 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3914 EVEX_CD8<16, CD8VH>;
3915 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VR512, VR128X, X86vzext,
3916 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3917 EVEX_CD8<16, CD8VQ>;
3918 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VR512, VR256X, X86vzext,
3919 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3920 EVEX_CD8<32, CD8VH>;
3922 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VR512, VR128X, X86vsext,
3923 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3925 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VR512, VR128X, X86vsext,
3926 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3928 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VR512, VR256X, X86vsext,
3929 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3930 EVEX_CD8<16, CD8VH>;
3931 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VR512, VR128X, X86vsext,
3932 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3933 EVEX_CD8<16, CD8VQ>;
3934 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VR512, VR256X, X86vsext,
3935 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3936 EVEX_CD8<32, CD8VH>;
3938 //===----------------------------------------------------------------------===//
3939 // GATHER - SCATTER Operations
3941 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3942 RegisterClass RC, X86MemOperand memop> {
3944 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
3945 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
3946 (ins RC:$src1, KRC:$mask, memop:$src2),
3947 !strconcat(OpcodeStr,
3948 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3952 let ExeDomain = SSEPackedDouble in {
3953 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
3954 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3955 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
3956 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3959 let ExeDomain = SSEPackedSingle in {
3960 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
3961 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3962 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
3963 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3966 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
3967 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3968 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
3969 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3971 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
3972 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3973 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
3974 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3976 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3977 RegisterClass RC, X86MemOperand memop> {
3978 let mayStore = 1, Constraints = "$mask = $mask_wb" in
3979 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
3980 (ins memop:$dst, KRC:$mask, RC:$src2),
3981 !strconcat(OpcodeStr,
3982 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3986 let ExeDomain = SSEPackedDouble in {
3987 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
3988 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3989 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
3990 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3993 let ExeDomain = SSEPackedSingle in {
3994 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
3995 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3996 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
3997 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4000 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4001 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4002 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4003 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4005 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4006 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4007 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4008 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4010 //===----------------------------------------------------------------------===//
4011 // VSHUFPS - VSHUFPD Operations
4013 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
4014 ValueType vt, string OpcodeStr, PatFrag mem_frag,
4016 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
4017 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4018 !strconcat(OpcodeStr,
4019 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4020 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
4021 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4022 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
4023 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
4024 (ins RC:$src1, RC:$src2, i8imm:$src3),
4025 !strconcat(OpcodeStr,
4026 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4027 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
4028 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4029 EVEX_4V, Sched<[WriteShuffle]>;
4032 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
4033 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4034 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
4035 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4037 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4038 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4039 def : Pat<(v16i32 (X86Shufp VR512:$src1,
4040 (memopv16i32 addr:$src2), (i8 imm:$imm))),
4041 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4043 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4044 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4045 def : Pat<(v8i64 (X86Shufp VR512:$src1,
4046 (memopv8i64 addr:$src2), (i8 imm:$imm))),
4047 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4049 multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
4050 X86MemOperand x86memop> {
4051 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
4052 (ins RC:$src1, RC:$src2, i8imm:$src3),
4053 !strconcat(OpcodeStr,
4054 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4057 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
4058 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4059 !strconcat(OpcodeStr,
4060 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4063 defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
4064 EVEX_V512, EVEX_CD8<32, CD8VF>;
4065 defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
4066 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4068 def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4069 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
4070 def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4071 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
4072 def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4073 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
4074 def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4075 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
4077 // Helper fragments to match sext vXi1 to vXiY.
4078 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
4079 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
4081 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
4082 RegisterClass KRC, RegisterClass RC,
4083 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
4085 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4086 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4088 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4089 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4091 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4092 !strconcat(OpcodeStr,
4093 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4095 let mayLoad = 1 in {
4096 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4097 (ins x86memop:$src),
4098 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4100 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4101 (ins KRC:$mask, x86memop:$src),
4102 !strconcat(OpcodeStr,
4103 " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4105 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4106 (ins KRC:$mask, x86memop:$src),
4107 !strconcat(OpcodeStr,
4108 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4110 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4111 (ins x86scalar_mop:$src),
4112 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4113 ", $dst|$dst, ${src}", BrdcstStr, "}"),
4115 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4116 (ins KRC:$mask, x86scalar_mop:$src),
4117 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4118 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
4119 []>, EVEX, EVEX_B, EVEX_K;
4120 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4121 (ins KRC:$mask, x86scalar_mop:$src),
4122 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4123 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
4125 []>, EVEX, EVEX_B, EVEX_KZ;
4129 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
4130 i512mem, i32mem, "{1to16}">, EVEX_V512,
4131 EVEX_CD8<32, CD8VF>;
4132 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
4133 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
4134 EVEX_CD8<64, CD8VF>;
4137 (bc_v16i32 (v16i1sextv16i32)),
4138 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
4139 (VPABSDZrr VR512:$src)>;
4141 (bc_v8i64 (v8i1sextv8i64)),
4142 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
4143 (VPABSQZrr VR512:$src)>;
4145 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
4146 (v16i32 immAllZerosV), (i16 -1))),
4147 (VPABSDZrr VR512:$src)>;
4148 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
4149 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
4150 (VPABSQZrr VR512:$src)>;
4152 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
4153 RegisterClass RC, RegisterClass KRC,
4154 X86MemOperand x86memop,
4155 X86MemOperand x86scalar_mop, string BrdcstStr> {
4156 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4158 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"),
4160 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4161 (ins x86memop:$src),
4162 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"),
4164 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4165 (ins x86scalar_mop:$src),
4166 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4167 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
4169 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4170 (ins KRC:$mask, RC:$src),
4171 !strconcat(OpcodeStr,
4172 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4174 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4175 (ins KRC:$mask, x86memop:$src),
4176 !strconcat(OpcodeStr,
4177 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4179 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4180 (ins KRC:$mask, x86scalar_mop:$src),
4181 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4182 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
4184 []>, EVEX, EVEX_KZ, EVEX_B;
4186 let Constraints = "$src1 = $dst" in {
4187 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4188 (ins RC:$src1, KRC:$mask, RC:$src2),
4189 !strconcat(OpcodeStr,
4190 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4192 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4193 (ins RC:$src1, KRC:$mask, x86memop:$src2),
4194 !strconcat(OpcodeStr,
4195 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4197 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4198 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
4199 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
4200 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
4201 []>, EVEX, EVEX_K, EVEX_B;
4205 let Predicates = [HasCDI] in {
4206 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
4207 i512mem, i32mem, "{1to16}">,
4208 EVEX_V512, EVEX_CD8<32, CD8VF>;
4211 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
4212 i512mem, i64mem, "{1to8}">,
4213 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4217 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
4219 (VPCONFLICTDrrk VR512:$src1,
4220 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4222 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
4224 (VPCONFLICTQrrk VR512:$src1,
4225 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
4227 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4228 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4229 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;