1 // Bitcasts between 512-bit vector types. Return the original type since
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2 // no instruction is needed for the conversion
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3 let Predicates = [HasAVX512] in {
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4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
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5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
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6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
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7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
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8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
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9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
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10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
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11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
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12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
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13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
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14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
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15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
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16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
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18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
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19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
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20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
\r
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
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22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
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23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
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24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
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25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
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26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
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27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
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28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
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29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
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30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
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31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
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32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
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33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
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34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
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35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
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36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
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37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
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38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
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39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
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40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
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41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
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42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
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43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
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44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
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45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
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46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
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47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
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49 // Bitcasts between 256-bit vector types. Return the original type since
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50 // no instruction is needed for the conversion
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51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
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52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
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53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
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54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
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55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
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56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
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57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
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58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
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59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
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60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
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61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
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62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
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63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
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64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
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65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
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66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
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67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
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68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
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69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
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70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
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71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
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72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
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73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
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74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
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75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
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76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
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77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
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78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
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79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
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80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
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84 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
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87 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
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88 isPseudo = 1, Predicates = [HasAVX512] in {
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89 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
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90 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
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93 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
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94 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
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95 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
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96 def : Pat<(v16f32 immAllZerosV), (AVX512_512_SET0)>;
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98 //===----------------------------------------------------------------------===//
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99 // AVX-512 - VECTOR INSERT
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102 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
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103 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
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104 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
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105 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
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106 []>, EVEX_4V, EVEX_V512;
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108 def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
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109 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
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110 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
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111 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
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114 // -- 64x4 fp form --
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115 let neverHasSideEffects = 1, ExeDomain = SSEPackedDouble in {
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116 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
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117 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
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118 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
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119 []>, EVEX_4V, EVEX_V512, VEX_W;
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121 def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
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122 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
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123 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
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124 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
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126 // -- 32x4 integer form --
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127 let neverHasSideEffects = 1 in {
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128 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
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129 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
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130 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
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131 []>, EVEX_4V, EVEX_V512;
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133 def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
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134 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
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135 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
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136 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
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140 let neverHasSideEffects = 1 in {
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142 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
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143 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
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144 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
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145 []>, EVEX_4V, EVEX_V512, VEX_W;
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147 def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
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148 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
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149 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
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150 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
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153 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
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154 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
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155 (INSERT_get_vinsert128_imm VR512:$ins))>;
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156 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
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157 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
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158 (INSERT_get_vinsert128_imm VR512:$ins))>;
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159 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
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160 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
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161 (INSERT_get_vinsert128_imm VR512:$ins))>;
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162 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
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163 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
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164 (INSERT_get_vinsert128_imm VR512:$ins))>;
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166 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
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167 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
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168 (INSERT_get_vinsert128_imm VR512:$ins))>;
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169 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
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170 (bc_v4i32 (loadv2i64 addr:$src2)),
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171 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
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172 (INSERT_get_vinsert128_imm VR512:$ins))>;
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173 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
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174 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
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175 (INSERT_get_vinsert128_imm VR512:$ins))>;
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176 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
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177 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
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178 (INSERT_get_vinsert128_imm VR512:$ins))>;
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180 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
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181 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
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182 (INSERT_get_vinsert256_imm VR512:$ins))>;
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183 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
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184 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
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185 (INSERT_get_vinsert256_imm VR512:$ins))>;
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186 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
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187 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
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188 (INSERT_get_vinsert256_imm VR512:$ins))>;
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189 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
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190 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
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191 (INSERT_get_vinsert256_imm VR512:$ins))>;
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193 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
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194 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
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195 (INSERT_get_vinsert256_imm VR512:$ins))>;
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196 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
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197 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
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198 (INSERT_get_vinsert256_imm VR512:$ins))>;
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199 def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
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200 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
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201 (INSERT_get_vinsert256_imm VR512:$ins))>;
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202 def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
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203 (bc_v8i32 (loadv4i64 addr:$src2)),
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204 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
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205 (INSERT_get_vinsert256_imm VR512:$ins))>;
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207 // vinsertps - insert f32 to XMM
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208 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
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209 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
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210 "vinsertps{z}\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
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211 [(set VR128X:$dst, (X86insrtps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
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213 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
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214 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
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215 "vinsertps{z}\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
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216 [(set VR128X:$dst, (X86insrtps VR128X:$src1,
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217 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
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218 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
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220 //===----------------------------------------------------------------------===//
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221 // AVX-512 VECTOR EXTRACT
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223 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
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225 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
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226 (ins VR512:$src1, i8imm:$src2),
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227 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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228 []>, EVEX, EVEX_V512;
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229 def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
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230 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
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231 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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232 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
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235 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
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236 (ins VR512:$src1, i8imm:$src2),
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237 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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238 []>, EVEX, EVEX_V512, VEX_W;
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239 let mayStore = 1 in
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240 def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
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241 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
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242 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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243 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
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246 let neverHasSideEffects = 1 in {
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248 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
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249 (ins VR512:$src1, i8imm:$src2),
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250 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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251 []>, EVEX, EVEX_V512;
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252 def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
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253 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
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254 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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255 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
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258 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
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259 (ins VR512:$src1, i8imm:$src2),
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260 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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261 []>, EVEX, EVEX_V512, VEX_W;
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262 let mayStore = 1 in
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263 def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
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264 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
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265 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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266 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
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269 def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
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270 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
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271 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
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273 def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
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274 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
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275 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
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277 def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
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278 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
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279 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
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281 def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
\r
282 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
\r
283 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
\r
286 def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
\r
287 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
\r
288 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
\r
290 def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
\r
291 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
\r
292 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
\r
294 def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
\r
295 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
\r
296 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
\r
298 def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
\r
299 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
\r
300 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
\r
302 // A 256-bit subvector extract from the first 512-bit vector position
\r
303 // is a subregister copy that needs no instruction.
\r
304 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
\r
305 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
\r
306 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
\r
307 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
\r
308 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
\r
309 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
\r
310 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
\r
311 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
\r
314 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
\r
315 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
\r
316 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
\r
317 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
\r
318 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
\r
319 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
\r
320 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
\r
321 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
\r
324 // A 128-bit subvector insert to the first 512-bit vector position
\r
325 // is a subregister copy that needs no instruction.
\r
326 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
\r
327 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
\r
328 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
\r
330 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
\r
331 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
\r
332 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
\r
334 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
\r
335 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
\r
336 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
\r
338 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
\r
339 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
\r
340 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
\r
343 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
\r
344 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
\r
345 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
\r
346 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
\r
347 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
\r
348 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
\r
349 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
\r
350 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
\r
352 // vextractps - extract 32 bits from XMM
\r
353 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
\r
354 (ins VR128X:$src1, u32u8imm:$src2),
\r
355 "vextractps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
\r
356 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
\r
359 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
\r
360 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
\r
361 "vextractps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
\r
362 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
\r
363 addr:$dst)]>, EVEX;
\r
365 //===---------------------------------------------------------------------===//
\r
366 // AVX-512 BROADCAST
\r
368 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
\r
369 RegisterClass DestRC,
\r
370 RegisterClass SrcRC, X86MemOperand x86memop> {
\r
371 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
\r
372 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
\r
374 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
\r
375 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),[]>, EVEX;
\r
377 let ExeDomain = SSEPackedSingle in {
\r
378 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss{z}", VR512,
\r
380 EVEX_V512, EVEX_CD8<32, CD8VT1>;
\r
383 let ExeDomain = SSEPackedDouble in {
\r
384 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd{z}", VR512,
\r
386 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
\r
389 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
\r
390 (VBROADCASTSSZrm addr:$src)>;
\r
391 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
\r
392 (VBROADCASTSDZrm addr:$src)>;
\r
394 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
\r
395 RegisterClass SrcRC, RegisterClass KRC> {
\r
396 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
\r
397 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
\r
398 []>, EVEX, EVEX_V512;
\r
399 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
\r
400 (ins KRC:$mask, SrcRC:$src),
\r
401 !strconcat(OpcodeStr,
\r
402 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
\r
403 []>, EVEX, EVEX_V512, EVEX_KZ;
\r
406 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
\r
407 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
\r
410 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
\r
411 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
\r
413 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
\r
414 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
\r
416 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
\r
417 (VPBROADCASTDrZrr GR32:$src)>;
\r
418 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
\r
419 (VPBROADCASTQrZrr GR64:$src)>;
\r
421 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
\r
422 X86MemOperand x86memop, PatFrag ld_frag,
\r
423 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
\r
424 RegisterClass KRC> {
\r
425 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
\r
426 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
\r
428 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
\r
429 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
\r
431 !strconcat(OpcodeStr,
\r
432 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
\r
434 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
\r
436 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
\r
437 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
\r
439 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
\r
440 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
\r
442 !strconcat(OpcodeStr,
\r
443 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
\r
444 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
\r
445 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
\r
448 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
\r
449 loadi32, VR512, v16i32, v4i32, VK16WM>,
\r
450 EVEX_V512, EVEX_CD8<32, CD8VT1>;
\r
451 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
\r
452 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
\r
453 EVEX_CD8<64, CD8VT1>;
\r
455 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
\r
456 (VBROADCASTSSZrr VR128X:$src)>;
\r
457 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
\r
458 (VBROADCASTSDZrr VR128X:$src)>;
\r
460 // Provide fallback in case the load node that is used in the patterns above
\r
461 // is used by additional users, which prevents the pattern selection.
\r
462 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
\r
463 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
\r
464 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
\r
465 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
\r
468 let Predicates = [HasAVX512] in {
\r
469 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
\r
471 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
\r
472 addr:$src)), sub_ymm)>;
\r
474 //===----------------------------------------------------------------------===//
\r
475 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
\r
478 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
\r
479 RegisterClass DstRC, RegisterClass KRC,
\r
480 ValueType OpVT, ValueType SrcVT> {
\r
481 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
\r
482 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
\r
486 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
\r
487 VK16, v16i32, v16i1>, EVEX_V512;
\r
488 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
\r
489 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
\r
491 //===----------------------------------------------------------------------===//
\r
494 // -- immediate form --
\r
495 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
\r
496 SDNode OpNode, PatFrag mem_frag,
\r
497 X86MemOperand x86memop, ValueType OpVT> {
\r
498 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
\r
499 (ins RC:$src1, i8imm:$src2),
\r
500 !strconcat(OpcodeStr,
\r
501 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
\r
503 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
\r
505 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
\r
506 (ins x86memop:$src1, i8imm:$src2),
\r
507 !strconcat(OpcodeStr,
\r
508 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
\r
510 (OpVT (OpNode (mem_frag addr:$src1),
\r
511 (i8 imm:$src2))))]>, EVEX;
\r
514 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
\r
515 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
\r
516 let ExeDomain = SSEPackedDouble in
\r
517 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
\r
518 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
\r
520 // -- VPERM - register form --
\r
521 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
\r
522 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
\r
524 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
\r
525 (ins RC:$src1, RC:$src2),
\r
526 !strconcat(OpcodeStr,
\r
527 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
\r
529 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
\r
531 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
\r
532 (ins RC:$src1, x86memop:$src2),
\r
533 !strconcat(OpcodeStr,
\r
534 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
\r
536 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
\r
540 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
\r
541 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
\r
542 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
\r
543 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
\r
544 let ExeDomain = SSEPackedSingle in
\r
545 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
\r
546 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
\r
547 let ExeDomain = SSEPackedDouble in
\r
548 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
\r
549 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
\r
551 // -- VPERM2I - 3 source operands form --
\r
552 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
\r
553 PatFrag mem_frag, X86MemOperand x86memop,
\r
555 let Constraints = "$src1 = $dst" in {
\r
556 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
\r
557 (ins RC:$src1, RC:$src2, RC:$src3),
\r
558 !strconcat(OpcodeStr,
\r
559 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
\r
561 (OpVT (X86VPermv3 RC:$src1, RC:$src2, RC:$src3)))]>,
\r
564 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
\r
565 (ins RC:$src1, RC:$src2, x86memop:$src3),
\r
566 !strconcat(OpcodeStr,
\r
567 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
\r
569 (OpVT (X86VPermv3 RC:$src1, RC:$src2,
\r
570 (mem_frag addr:$src3))))]>, EVEX_4V;
\r
573 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem,
\r
574 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
\r
575 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem,
\r
576 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
\r
577 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem,
\r
578 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
\r
579 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
\r
580 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
\r
582 //===----------------------------------------------------------------------===//
\r
583 // AVX-512 - BLEND using mask
\r
585 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
\r
586 RegisterClass KRC, RegisterClass RC,
\r
587 X86MemOperand x86memop, PatFrag mem_frag,
\r
588 SDNode OpNode, ValueType vt> {
\r
589 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
\r
590 (ins KRC:$mask, RC:$src1, RC:$src2),
\r
591 !strconcat(OpcodeStr,
\r
592 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
\r
593 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
\r
594 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
\r
596 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
\r
597 (ins KRC:$mask, RC:$src1, x86memop:$src2),
\r
598 !strconcat(OpcodeStr,
\r
599 "\t{$src2, $src1, $mask, $dst|$dst, $mask, $src1, $src2}"),
\r
604 let ExeDomain = SSEPackedSingle in
\r
605 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps", VK16WM, VR512, f512mem,
\r
606 memopv16f32, vselect, v16f32>,
\r
607 EVEX_CD8<32, CD8VF>, EVEX_V512;
\r
608 let ExeDomain = SSEPackedDouble in
\r
609 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd", VK8WM, VR512, f512mem,
\r
610 memopv8f64, vselect, v8f64>,
\r
611 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
\r
613 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd", VK16WM, VR512, f512mem,
\r
614 memopv8i64, vselect, v16i32>,
\r
615 EVEX_CD8<32, CD8VF>, EVEX_V512;
\r
617 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq", VK8WM, VR512, f512mem,
\r
618 memopv8i64, vselect, v8i64>, VEX_W,
\r
619 EVEX_CD8<64, CD8VF>, EVEX_V512;
\r
622 let Predicates = [HasAVX512] in {
\r
623 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
\r
624 (v8f32 VR256X:$src2))),
\r
626 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
\r
627 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
\r
628 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
\r
630 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
\r
631 (v8i32 VR256X:$src2))),
\r
633 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
\r
634 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
\r
635 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
\r
638 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
\r
639 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
\r
640 SDNode OpNode, ValueType vt> {
\r
641 def rr : AVX512BI<opc, MRMSrcReg,
\r
642 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
\r
643 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
\r
644 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
\r
645 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
\r
646 def rm : AVX512BI<opc, MRMSrcMem,
\r
647 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
\r
648 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
\r
649 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
\r
650 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
\r
653 defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
\r
654 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512;
\r
655 defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
\r
656 memopv8i64, X86pcmpeqm, v8i64>, T8, EVEX_V512, VEX_W;
\r
658 defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
\r
659 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512;
\r
660 defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
\r
661 memopv8i64, X86pcmpgtm, v8i64>, T8, EVEX_V512, VEX_W;
\r
663 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
\r
664 (COPY_TO_REGCLASS (VPCMPGTDZrr
\r
665 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
\r
666 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
\r
668 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
\r
669 (COPY_TO_REGCLASS (VPCMPEQDZrr
\r
670 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
\r
671 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
\r
673 multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
\r
674 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
\r
675 SDNode OpNode, ValueType vt, Operand CC, string asm,
\r
677 def rri : AVX512AIi8<opc, MRMSrcReg,
\r
678 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
\r
679 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
\r
680 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
\r
681 def rmi : AVX512AIi8<opc, MRMSrcMem,
\r
682 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
\r
683 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
\r
684 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
\r
685 // Accept explicit immediate argument form instead of comparison code.
\r
686 let neverHasSideEffects = 1 in {
\r
687 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
\r
688 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
\r
689 asm_alt, [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
\r
690 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
\r
691 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
\r
692 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
\r
696 defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv16i32,
\r
697 X86cmpm, v16i32, AVXCC,
\r
698 "vpcmp${cc}d\t{$src2, $src1, $dst|$dst, $src1, $src2}",
\r
699 "vpcmpd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
\r
700 EVEX_V512, EVEX_CD8<32, CD8VF>;
\r
701 defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv16i32,
\r
702 X86cmpmu, v16i32, AVXCC,
\r
703 "vpcmp${cc}ud\t{$src2, $src1, $dst|$dst, $src1, $src2}",
\r
704 "vpcmpud\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
\r
705 EVEX_V512, EVEX_CD8<32, CD8VF>;
\r
707 defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64,
\r
708 X86cmpm, v8i64, AVXCC,
\r
709 "vpcmp${cc}q\t{$src2, $src1, $dst|$dst, $src1, $src2}",
\r
710 "vpcmpq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
\r
711 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
\r
712 defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64,
\r
713 X86cmpmu, v8i64, AVXCC,
\r
714 "vpcmp${cc}uq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
\r
715 "vpcmpuq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
\r
716 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
\r
718 // avx512_cmp_packed - sse 1 & 2 compare packed instructions
\r
719 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
\r
720 X86MemOperand x86memop, Operand CC,
\r
721 SDNode OpNode, ValueType vt, string asm,
\r
722 string asm_alt, Domain d> {
\r
723 def rri : AVX512PIi8<0xC2, MRMSrcReg,
\r
724 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
\r
725 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
\r
726 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
\r
727 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
\r
729 (OpNode (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
\r
731 // Accept explicit immediate argument form instead of comparison code.
\r
732 let neverHasSideEffects = 1 in {
\r
733 def rri_alt : PIi8<0xC2, MRMSrcReg,
\r
734 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
\r
735 asm_alt, [], IIC_SSE_ALU_F32P_RR, d>;
\r
736 def rmi_alt : PIi8<0xC2, MRMSrcMem,
\r
737 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
\r
738 asm_alt, [], IIC_SSE_ALU_F32P_RM, d>;
\r
742 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, AVXCC, X86cmpm, v16f32,
\r
743 "vcmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
\r
744 "vcmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
\r
745 SSEPackedSingle>, TB, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VF>;
\r
746 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, AVXCC, X86cmpm, v8f64,
\r
747 "vcmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
\r
748 "vcmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
\r
749 SSEPackedDouble>, TB, OpSize, EVEX_4V, VEX_W, EVEX_V512,
\r
750 EVEX_CD8<64, CD8VF>;
\r
752 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
\r
753 (COPY_TO_REGCLASS (VCMPPSZrri
\r
754 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
\r
755 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
\r
757 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
\r
758 (COPY_TO_REGCLASS (VPCMPDZrri
\r
759 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
\r
760 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
\r
762 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
\r
763 (COPY_TO_REGCLASS (VPCMPUDZrri
\r
764 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
\r
765 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
\r
768 // Mask register copy, including
\r
769 // - copy between mask registers
\r
770 // - load/store mask registers
\r
771 // - copy from GPR to mask register and vice versa
\r
773 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
\r
774 string OpcodeStr, RegisterClass KRC,
\r
775 ValueType vt, X86MemOperand x86memop> {
\r
776 let neverHasSideEffects = 1 in {
\r
777 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
\r
778 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
\r
780 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
\r
781 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
\r
782 [(set KRC:$dst, (vt (load addr:$src)))]>;
\r
783 let mayStore = 1 in
\r
784 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
\r
785 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
\r
789 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
\r
791 RegisterClass KRC, RegisterClass GRC> {
\r
792 let neverHasSideEffects = 1 in {
\r
793 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
\r
794 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
\r
795 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
\r
796 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
\r
800 let Predicates = [HasAVX512] in {
\r
801 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
\r
803 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
\r
807 let Predicates = [HasAVX512] in {
\r
808 // GR16 from/to 16-bit mask
\r
809 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
\r
810 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
\r
811 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
\r
812 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
\r
814 // Store kreg in memory
\r
815 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
\r
816 (KMOVWmk addr:$dst, VK16:$src)>;
\r
818 def : Pat<(store (v8i1 VK8:$src), addr:$dst),
\r
819 (KMOVWmk addr:$dst, (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16)))>;
\r
821 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
\r
822 let Predicates = [HasAVX512] in {
\r
823 // GR from/to 8-bit mask without native support
\r
824 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
\r
826 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
\r
828 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
\r
830 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
\r
834 // Mask unary operation
\r
836 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
\r
837 RegisterClass KRC, SDPatternOperator OpNode> {
\r
838 let Predicates = [HasAVX512] in
\r
839 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
\r
840 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
\r
841 [(set KRC:$dst, (OpNode KRC:$src))]>;
\r
844 multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
\r
845 SDPatternOperator OpNode> {
\r
846 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
\r
850 defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
\r
852 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
\r
853 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
\r
854 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
\r
856 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
\r
857 def : Pat<(not VK8:$src),
\r
859 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
\r
861 // Mask binary operation
\r
862 // - KADD, KAND, KANDN, KOR, KXNOR, KXOR
\r
863 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
\r
864 RegisterClass KRC, SDPatternOperator OpNode> {
\r
865 let Predicates = [HasAVX512] in
\r
866 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
\r
867 !strconcat(OpcodeStr,
\r
868 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
\r
869 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
\r
872 multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
\r
873 SDPatternOperator OpNode> {
\r
874 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
\r
878 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
\r
879 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
\r
881 let isCommutable = 1 in {
\r
882 defm KADD : avx512_mask_binop_w<0x4a, "kadd", add>;
\r
883 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
\r
884 let isCommutable = 0 in
\r
885 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
\r
886 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
\r
887 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
\r
888 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
\r
891 multiclass avx512_mask_binop_int<string IntName, string InstName> {
\r
892 let Predicates = [HasAVX512] in
\r
893 def : Pat<(!cast<Intrinsic>("int_x86_"##IntName##"_v16i1")
\r
894 VK16:$src1, VK16:$src2),
\r
895 (!cast<Instruction>(InstName##"Wrr") VK16:$src1, VK16:$src2)>;
\r
898 defm : avx512_mask_binop_int<"kadd", "KADD">;
\r
899 defm : avx512_mask_binop_int<"kand", "KAND">;
\r
900 defm : avx512_mask_binop_int<"kandn", "KANDN">;
\r
901 defm : avx512_mask_binop_int<"kor", "KOR">;
\r
902 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
\r
903 defm : avx512_mask_binop_int<"kxor", "KXOR">;
\r
904 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
\r
905 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
\r
906 let Predicates = [HasAVX512] in
\r
907 def : Pat<(OpNode VK8:$src1, VK8:$src2),
\r
909 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
\r
910 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
\r
913 defm : avx512_binop_pat<and, KANDWrr>;
\r
914 defm : avx512_binop_pat<andn, KANDNWrr>;
\r
915 defm : avx512_binop_pat<or, KORWrr>;
\r
916 defm : avx512_binop_pat<xnor, KXNORWrr>;
\r
917 defm : avx512_binop_pat<xor, KXORWrr>;
\r
920 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
\r
921 RegisterClass KRC1, RegisterClass KRC2> {
\r
922 let Predicates = [HasAVX512] in
\r
923 def rr : I<opc, MRMSrcReg, (outs KRC1:$dst), (ins KRC2:$src1, KRC2:$src2),
\r
924 !strconcat(OpcodeStr,
\r
925 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
\r
928 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
\r
929 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16, VK8>,
\r
930 VEX_4V, VEX_L, OpSize, TB;
\r
933 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
\r
935 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
\r
936 let Predicates = [HasAVX512] in
\r
937 def : Pat<(!cast<Intrinsic>("int_x86_"##IntName##"_v16i1")
\r
938 VK8:$src1, VK8:$src2),
\r
939 (!cast<Instruction>(InstName##"BWrr") VK8:$src1, VK8:$src2)>;
\r
942 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
\r
943 // Mask bit testing
\r
944 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
\r
946 let Predicates = [HasAVX512], Defs = [EFLAGS] in
\r
947 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
\r
948 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
\r
949 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
\r
952 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
\r
953 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
\r
957 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
\r
958 defm KTEST : avx512_mask_testop_w<0x99, "ktest", X86ktest>;
\r
961 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
\r
963 let Predicates = [HasAVX512] in
\r
964 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
\r
965 !strconcat(OpcodeStr,
\r
966 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
\r
967 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
\r
970 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
\r
972 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
\r
973 VEX, OpSize, TA, VEX_W;
\r
976 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", shl>;
\r
977 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", srl>;
\r
979 // Mask setting all 0s or 1s
\r
980 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
\r
981 let Predicates = [HasAVX512] in
\r
982 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
\r
983 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
\r
984 [(set KRC:$dst, (VT Val))]>;
\r
987 multiclass avx512_mask_setop_w<PatFrag Val> {
\r
988 defm B : avx512_mask_setop<VK8, v8i1, Val>;
\r
989 defm W : avx512_mask_setop<VK16, v16i1, Val>;
\r
992 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
\r
993 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
\r
995 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
\r
996 let Predicates = [HasAVX512] in {
\r
997 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
\r
998 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
\r
1000 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
\r
1001 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
\r
1003 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
\r
1004 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
\r
1006 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
\r
1007 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
\r
1009 //===----------------------------------------------------------------------===//
\r
1010 // AVX-512 - Aligned and unaligned load and store
\r
1013 multiclass avx512_mov_packed<bits<8> opc, RegisterClass RC, RegisterClass KRC,
\r
1014 X86MemOperand x86memop, PatFrag ld_frag,
\r
1015 string asm, Domain d> {
\r
1016 let neverHasSideEffects = 1 in
\r
1017 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
\r
1018 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>,
\r
1020 let canFoldAsLoad = 1 in
\r
1021 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
\r
1022 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
\r
1023 [(set RC:$dst, (ld_frag addr:$src))], d>, EVEX;
\r
1024 let Constraints = "$src1 = $dst" in {
\r
1025 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
\r
1026 (ins RC:$src1, KRC:$mask, RC:$src2),
\r
1028 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
\r
1030 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
\r
1031 (ins RC:$src1, KRC:$mask, x86memop:$src2),
\r
1033 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
\r
1034 [], d>, EVEX, EVEX_K;
\r
1038 defm VMOVAPSZ : avx512_mov_packed<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
\r
1039 "vmovaps", SSEPackedSingle>,
\r
1040 EVEX_V512, EVEX_CD8<32, CD8VF>;
\r
1041 defm VMOVAPDZ : avx512_mov_packed<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
\r
1042 "vmovapd", SSEPackedDouble>,
\r
1043 OpSize, EVEX_V512, VEX_W,
\r
1044 EVEX_CD8<64, CD8VF>;
\r
1045 defm VMOVUPSZ : avx512_mov_packed<0x10, VR512, VK16WM, f512mem, loadv16f32,
\r
1046 "vmovups", SSEPackedSingle>,
\r
1047 TB, EVEX_V512, EVEX_CD8<32, CD8VF>;
\r
1048 defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64,
\r
1049 "vmovupd", SSEPackedDouble>,
\r
1050 OpSize, EVEX_V512, VEX_W,
\r
1051 EVEX_CD8<64, CD8VF>;
\r
1052 def VMOVAPSZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
\r
1053 "vmovaps\t{$src, $dst|$dst, $src}",
\r
1054 [(alignedstore512 (v16f32 VR512:$src), addr:$dst)],
\r
1055 SSEPackedSingle>, EVEX, EVEX_V512, TB,
\r
1056 EVEX_CD8<32, CD8VF>;
\r
1057 def VMOVAPDZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
\r
1058 "vmovapd\t{$src, $dst|$dst, $src}",
\r
1059 [(alignedstore512 (v8f64 VR512:$src), addr:$dst)],
\r
1060 SSEPackedDouble>, EVEX, EVEX_V512,
\r
1061 OpSize, TB, VEX_W, EVEX_CD8<64, CD8VF>;
\r
1062 def VMOVUPSZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
\r
1063 "vmovups\t{$src, $dst|$dst, $src}",
\r
1064 [(store (v16f32 VR512:$src), addr:$dst)],
\r
1065 SSEPackedSingle>, EVEX, EVEX_V512, TB,
\r
1066 EVEX_CD8<32, CD8VF>;
\r
1067 def VMOVUPDZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
\r
1068 "vmovupd\t{$src, $dst|$dst, $src}",
\r
1069 [(store (v8f64 VR512:$src), addr:$dst)],
\r
1070 SSEPackedDouble>, EVEX, EVEX_V512,
\r
1071 OpSize, TB, VEX_W, EVEX_CD8<64, CD8VF>;
\r
1073 // Use vmovaps/vmovups for AVX-512 integer load/store.
\r
1074 // 512-bit load/store
\r
1075 def : Pat<(alignedloadv8i64 addr:$src),
\r
1076 (VMOVAPSZrm addr:$src)>;
\r
1077 def : Pat<(loadv8i64 addr:$src),
\r
1078 (VMOVUPSZrm addr:$src)>;
\r
1080 def : Pat<(alignedstore512 (v8i64 VR512:$src), addr:$dst),
\r
1081 (VMOVAPSZmr addr:$dst, VR512:$src)>;
\r
1082 def : Pat<(alignedstore512 (v16i32 VR512:$src), addr:$dst),
\r
1083 (VMOVAPSZmr addr:$dst, VR512:$src)>;
\r
1085 def : Pat<(store (v8i64 VR512:$src), addr:$dst),
\r
1086 (VMOVUPDZmr addr:$dst, VR512:$src)>;
\r
1087 def : Pat<(store (v16i32 VR512:$src), addr:$dst),
\r
1088 (VMOVUPSZmr addr:$dst, VR512:$src)>;
\r
1090 let neverHasSideEffects = 1 in {
\r
1091 def VMOVDQA32rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
\r
1093 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
\r
1095 def VMOVDQA64rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
\r
1097 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
\r
1098 EVEX, EVEX_V512, VEX_W;
\r
1099 let mayStore = 1 in {
\r
1100 def VMOVDQA32mr : AVX512BI<0x7F, MRMDestMem, (outs),
\r
1101 (ins i512mem:$dst, VR512:$src),
\r
1102 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
\r
1103 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
\r
1104 def VMOVDQA64mr : AVX512BI<0x7F, MRMDestMem, (outs),
\r
1105 (ins i512mem:$dst, VR512:$src),
\r
1106 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
\r
1107 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
\r
1109 let mayLoad = 1 in {
\r
1110 def VMOVDQA32rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
\r
1111 (ins i512mem:$src),
\r
1112 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
\r
1113 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
\r
1114 def VMOVDQA64rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
\r
1115 (ins i512mem:$src),
\r
1116 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
\r
1117 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
\r
1121 multiclass avx512_mov_int<bits<8> opc, string asm, RegisterClass RC,
\r
1122 RegisterClass KRC,
\r
1123 PatFrag ld_frag, X86MemOperand x86memop> {
\r
1124 let neverHasSideEffects = 1 in
\r
1125 def rr : AVX512XSI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
\r
1126 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>,
\r
1128 let canFoldAsLoad = 1 in
\r
1129 def rm : AVX512XSI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
\r
1130 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
\r
1131 [(set RC:$dst, (ld_frag addr:$src))]>,
\r
1133 let Constraints = "$src1 = $dst" in {
\r
1134 def rrk : AVX512XSI<opc, MRMSrcReg, (outs RC:$dst),
\r
1135 (ins RC:$src1, KRC:$mask, RC:$src2),
\r
1137 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), []>,
\r
1139 def rmk : AVX512XSI<opc, MRMSrcMem, (outs RC:$dst),
\r
1140 (ins RC:$src1, KRC:$mask, x86memop:$src2),
\r
1142 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
\r
1143 []>, EVEX, EVEX_K;
\r
1147 defm VMOVDQU32 : avx512_mov_int<0x6F, "vmovdqu32", VR512, VK16WM, memopv16i32, i512mem>,
\r
1148 EVEX_V512, EVEX_CD8<32, CD8VF>;
\r
1149 defm VMOVDQU64 : avx512_mov_int<0x6F, "vmovdqu64", VR512, VK8WM, memopv8i64, i512mem>,
\r
1150 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
\r
1152 let AddedComplexity = 20 in {
\r
1153 def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
\r
1154 (v16f32 VR512:$src2))),
\r
1155 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
\r
1156 def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
\r
1157 (v8f64 VR512:$src2))),
\r
1158 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
\r
1159 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
\r
1160 (v16i32 VR512:$src2))),
\r
1161 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
\r
1162 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
\r
1163 (v8i64 VR512:$src2))),
\r
1164 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
\r
1166 // Move Int Doubleword to Packed Double Int
\r
1168 def VMOVDI2PDIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
\r
1169 "vmovd{z}\t{$src, $dst|$dst, $src}",
\r
1170 [(set VR128X:$dst,
\r
1171 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
\r
1173 def VMOVDI2PDIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
\r
1174 "vmovd{z}\t{$src, $dst|$dst, $src}",
\r
1175 [(set VR128X:$dst,
\r
1176 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
\r
1177 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
\r
1178 def VMOV64toPQIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
\r
1179 "vmovq{z}\t{$src, $dst|$dst, $src}",
\r
1180 [(set VR128X:$dst,
\r
1181 (v2i64 (scalar_to_vector GR64:$src)))],
\r
1182 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
\r
1183 def VMOV64toSDZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
\r
1184 "vmovq{z}\t{$src, $dst|$dst, $src}",
\r
1185 [(set FR64:$dst, (bitconvert GR64:$src))],
\r
1186 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
\r
1187 def VMOVSDto64Zrr : AVX512SI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
\r
1188 "vmovq{z}\t{$src, $dst|$dst, $src}",
\r
1189 [(set GR64:$dst, (bitconvert FR64:$src))],
\r
1190 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
\r
1191 def VMOVSDto64Zmr : AVX512SI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
\r
1192 "vmovq{z}\t{$src, $dst|$dst, $src}",
\r
1193 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
\r
1194 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
\r
1195 EVEX_CD8<64, CD8VT1>;
\r
1197 // Move Int Doubleword to Single Scalar
\r
1199 def VMOVDI2SSZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
\r
1200 "vmovd{z}\t{$src, $dst|$dst, $src}",
\r
1201 [(set FR32X:$dst, (bitconvert GR32:$src))],
\r
1202 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
\r
1204 def VMOVDI2SSZrm : AVX512SI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
\r
1205 "vmovd{z}\t{$src, $dst|$dst, $src}",
\r
1206 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
\r
1207 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
\r
1209 // Move Packed Doubleword Int to Packed Double Int
\r
1211 def VMOVPDI2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
\r
1212 "vmovd{z}\t{$src, $dst|$dst, $src}",
\r
1213 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
\r
1214 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
\r
1216 def VMOVPDI2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
\r
1217 (ins i32mem:$dst, VR128X:$src),
\r
1218 "vmovd{z}\t{$src, $dst|$dst, $src}",
\r
1219 [(store (i32 (vector_extract (v4i32 VR128X:$src),
\r
1220 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
\r
1221 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
\r
1223 // Move Packed Doubleword Int first element to Doubleword Int
\r
1225 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
\r
1226 "vmovq{z}\t{$src, $dst|$dst, $src}",
\r
1227 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
\r
1229 IIC_SSE_MOVD_ToGP>, TB, OpSize, EVEX, VEX_LIG, VEX_W,
\r
1230 Requires<[HasAVX512, In64BitMode]>;
\r
1232 def VMOVPQIto64Zmr : I<0x7E, MRMDestMem, (outs),
\r
1233 (ins i64mem:$dst, VR128X:$src),
\r
1234 "vmovq{z}\t{$src, $dst|$dst, $src}",
\r
1235 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
\r
1236 addr:$dst)], IIC_SSE_MOVDQ>,
\r
1237 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
\r
1238 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
\r
1240 // Move Scalar Single to Double Int
\r
1242 def VMOVSS2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst),
\r
1244 "vmovd{z}\t{$src, $dst|$dst, $src}",
\r
1245 [(set GR32:$dst, (bitconvert FR32X:$src))],
\r
1246 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
\r
1247 def VMOVSS2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
\r
1248 (ins i32mem:$dst, FR32X:$src),
\r
1249 "vmovd{z}\t{$src, $dst|$dst, $src}",
\r
1250 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
\r
1251 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
\r
1253 // Move Quadword Int to Packed Quadword Int
\r
1255 def VMOVQI2PQIZrm : AVX512SI<0x7E, MRMSrcMem, (outs VR128X:$dst),
\r
1256 (ins i64mem:$src),
\r
1257 "vmovq{z}\t{$src, $dst|$dst, $src}",
\r
1258 [(set VR128X:$dst,
\r
1259 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
\r
1260 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
\r
1262 //===----------------------------------------------------------------------===//
\r
1263 // AVX-512 MOVSS, MOVSD
\r
1264 //===----------------------------------------------------------------------===//
\r
1266 multiclass avx512_move_scalar <string asm, RegisterClass RC,
\r
1267 SDNode OpNode, ValueType vt,
\r
1268 X86MemOperand x86memop, PatFrag mem_pat> {
\r
1269 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
\r
1270 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
\r
1271 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
\r
1272 (scalar_to_vector RC:$src2))))],
\r
1273 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
\r
1274 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
\r
1275 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
\r
1276 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
\r
1278 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
\r
1279 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
\r
1280 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
\r
1284 let ExeDomain = SSEPackedSingle in
\r
1285 defm VMOVSSZ : avx512_move_scalar<"movss{z}", FR32X, X86Movss, v4f32, f32mem,
\r
1286 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
\r
1288 let ExeDomain = SSEPackedDouble in
\r
1289 defm VMOVSDZ : avx512_move_scalar<"movsd{z}", FR64X, X86Movsd, v2f64, f64mem,
\r
1290 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
\r
1293 // For the disassembler
\r
1294 let isCodeGenOnly = 1 in {
\r
1295 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
\r
1296 (ins VR128X:$src1, FR32X:$src2),
\r
1297 "movss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
\r
1298 IIC_SSE_MOV_S_RR>,
\r
1299 XS, EVEX_4V, VEX_LIG;
\r
1300 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
\r
1301 (ins VR128X:$src1, FR64X:$src2),
\r
1302 "movsd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
\r
1303 IIC_SSE_MOV_S_RR>,
\r
1304 XD, EVEX_4V, VEX_LIG, VEX_W;
\r
1307 let Predicates = [HasAVX512] in {
\r
1308 let AddedComplexity = 15 in {
\r
1309 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
\r
1310 // MOVS{S,D} to the lower bits.
\r
1311 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
\r
1312 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
\r
1313 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
\r
1314 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
\r
1315 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
\r
1316 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
\r
1317 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
\r
1318 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
\r
1320 // Move low f32 and clear high bits.
\r
1321 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
\r
1322 (SUBREG_TO_REG (i32 0),
\r
1323 (VMOVSSZrr (v4f32 (V_SET0)),
\r
1324 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
\r
1325 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
\r
1326 (SUBREG_TO_REG (i32 0),
\r
1327 (VMOVSSZrr (v4i32 (V_SET0)),
\r
1328 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
\r
1331 let AddedComplexity = 20 in {
\r
1332 // MOVSSrm zeros the high parts of the register; represent this
\r
1333 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
\r
1334 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
\r
1335 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
\r
1336 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
\r
1337 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
\r
1338 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
\r
1339 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
\r
1341 // MOVSDrm zeros the high parts of the register; represent this
\r
1342 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
\r
1343 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
\r
1344 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
\r
1345 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
\r
1346 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
\r
1347 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
\r
1348 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
\r
1349 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
\r
1350 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
\r
1351 def : Pat<(v2f64 (X86vzload addr:$src)),
\r
1352 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
\r
1354 // Represent the same patterns above but in the form they appear for
\r
1356 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
\r
1357 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
\r
1358 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
\r
1359 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
\r
1360 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
\r
1361 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
\r
1362 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
\r
1363 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
\r
1364 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
\r
1366 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
\r
1367 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
\r
1368 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
\r
1369 FR32X:$src)), sub_xmm)>;
\r
1370 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
\r
1371 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
\r
1372 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
\r
1373 FR64X:$src)), sub_xmm)>;
\r
1374 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
\r
1375 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
\r
1376 (SUBREG_TO_REG (i64 0), (VMOVSDZrm addr:$src), sub_xmm)>;
\r
1378 // Move low f64 and clear high bits.
\r
1379 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
\r
1380 (SUBREG_TO_REG (i32 0),
\r
1381 (VMOVSDZrr (v2f64 (V_SET0)),
\r
1382 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
\r
1384 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
\r
1385 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
\r
1386 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
\r
1388 // Extract and store.
\r
1389 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
\r
1391 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
\r
1392 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
\r
1394 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
\r
1396 // Shuffle with VMOVSS
\r
1397 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
\r
1398 (VMOVSSZrr (v4i32 VR128X:$src1),
\r
1399 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
\r
1400 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
\r
1401 (VMOVSSZrr (v4f32 VR128X:$src1),
\r
1402 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
\r
1404 // 256-bit variants
\r
1405 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
\r
1406 (SUBREG_TO_REG (i32 0),
\r
1407 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
\r
1408 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
\r
1410 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
\r
1411 (SUBREG_TO_REG (i32 0),
\r
1412 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
\r
1413 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
\r
1416 // Shuffle with VMOVSD
\r
1417 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
\r
1418 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
\r
1419 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
\r
1420 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
\r
1421 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
\r
1422 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
\r
1423 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
\r
1424 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
\r
1426 // 256-bit variants
\r
1427 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
\r
1428 (SUBREG_TO_REG (i32 0),
\r
1429 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
\r
1430 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
\r
1432 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
\r
1433 (SUBREG_TO_REG (i32 0),
\r
1434 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
\r
1435 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
\r
1438 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
\r
1439 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
\r
1440 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
\r
1441 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
\r
1442 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
\r
1443 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
\r
1444 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
\r
1445 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
\r
1448 let AddedComplexity = 15 in
\r
1449 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
\r
1450 (ins VR128X:$src),
\r
1451 "vmovq{z}\t{$src, $dst|$dst, $src}",
\r
1452 [(set VR128X:$dst, (v2i64 (X86vzmovl
\r
1453 (v2i64 VR128X:$src))))],
\r
1454 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
\r
1456 let AddedComplexity = 20 in
\r
1457 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
\r
1458 (ins i128mem:$src),
\r
1459 "vmovq{z}\t{$src, $dst|$dst, $src}",
\r
1460 [(set VR128X:$dst, (v2i64 (X86vzmovl
\r
1461 (loadv2i64 addr:$src))))],
\r
1462 IIC_SSE_MOVDQ>, EVEX, VEX_W,
\r
1463 EVEX_CD8<8, CD8VT8>;
\r
1465 let Predicates = [HasAVX512] in {
\r
1466 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
\r
1467 let AddedComplexity = 20 in {
\r
1468 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
\r
1469 (VMOVDI2PDIZrm addr:$src)>;
\r
1471 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
\r
1472 (VMOVDI2PDIZrm addr:$src)>;
\r
1473 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
\r
1474 (VMOVDI2PDIZrm addr:$src)>;
\r
1475 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
\r
1476 (VMOVZPQILo2PQIZrm addr:$src)>;
\r
1477 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
\r
1478 (VMOVZPQILo2PQIZrr VR128X:$src)>;
\r
1480 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
\r
1481 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
\r
1482 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
\r
1483 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
\r
1484 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
\r
1485 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
\r
1486 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
\r
1489 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
\r
1490 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
\r
1492 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
\r
1493 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
\r
1495 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
\r
1496 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
\r
1498 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
\r
1499 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
\r
1501 //===----------------------------------------------------------------------===//
\r
1502 // AVX-512 - Integer arithmetic
\r
1504 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
\r
1505 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
\r
1506 X86MemOperand x86memop, PatFrag scalar_mfrag,
\r
1507 X86MemOperand x86scalar_mop, string BrdcstStr,
\r
1508 OpndItins itins, bit IsCommutable = 0> {
\r
1509 let isCommutable = IsCommutable in
\r
1510 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
\r
1511 (ins RC:$src1, RC:$src2),
\r
1512 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
\r
1513 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
\r
1514 itins.rr>, EVEX_4V;
\r
1515 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
\r
1516 (ins RC:$src1, x86memop:$src2),
\r
1517 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
\r
1518 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
\r
1519 itins.rm>, EVEX_4V;
\r
1520 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
\r
1521 (ins RC:$src1, x86scalar_mop:$src2),
\r
1522 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
\r
1523 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
\r
1524 [(set RC:$dst, (OpNode RC:$src1,
\r
1525 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
\r
1526 itins.rm>, EVEX_4V, EVEX_B;
\r
1528 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr,
\r
1529 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
\r
1530 PatFrag memop_frag, X86MemOperand x86memop,
\r
1532 bit IsCommutable = 0> {
\r
1533 let isCommutable = IsCommutable in
\r
1534 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
\r
1535 (ins RC:$src1, RC:$src2),
\r
1536 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
\r
1537 []>, EVEX_4V, VEX_W;
\r
1538 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
\r
1539 (ins RC:$src1, x86memop:$src2),
\r
1540 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
\r
1541 []>, EVEX_4V, VEX_W;
\r
1544 defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VR512, memopv16i32,
\r
1545 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
\r
1546 EVEX_V512, EVEX_CD8<32, CD8VF>;
\r
1548 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VR512, memopv16i32,
\r
1549 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 0>,
\r
1550 EVEX_V512, EVEX_CD8<32, CD8VF>;
\r
1552 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VR512, memopv16i32,
\r
1553 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
\r
1554 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
\r
1556 defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VR512, memopv8i64,
\r
1557 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 1>,
\r
1558 EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
\r
1560 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VR512, memopv8i64,
\r
1561 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
\r
1562 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
\r
1564 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32,
\r
1565 VR512, memopv8i64, i512mem, SSE_INTALU_ITINS_P, 1>, T8,
\r
1566 EVEX_V512, EVEX_CD8<64, CD8VF>;
\r
1568 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32,
\r
1569 VR512, memopv8i64, i512mem, SSE_INTMUL_ITINS_P, 1>, EVEX_V512,
\r
1570 EVEX_CD8<64, CD8VF>;
\r
1572 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
\r
1573 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
\r
1575 //===----------------------------------------------------------------------===//
\r
1576 // AVX-512 - Unpack Instructions
\r
1577 //===----------------------------------------------------------------------===//
\r
1579 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
\r
1580 PatFrag mem_frag, RegisterClass RC,
\r
1581 X86MemOperand x86memop, string asm,
\r
1583 def rr : AVX512PI<opc, MRMSrcReg,
\r
1584 (outs RC:$dst), (ins RC:$src1, RC:$src2),
\r
1585 asm, [(set RC:$dst,
\r
1586 (vt (OpNode RC:$src1, RC:$src2)))],
\r
1588 def rm : AVX512PI<opc, MRMSrcMem,
\r
1589 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
\r
1590 asm, [(set RC:$dst,
\r
1591 (vt (OpNode RC:$src1,
\r
1592 (bitconvert (mem_frag addr:$src2)))))],
\r
1596 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
\r
1597 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
\r
1598 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
\r
1599 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
\r
1600 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
\r
1601 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
\r
1602 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
\r
1603 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
\r
1604 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
\r
1605 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
\r
1606 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
\r
1607 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
\r
1609 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
\r
1610 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
\r
1611 X86MemOperand x86memop> {
\r
1612 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
\r
1613 (ins RC:$src1, RC:$src2),
\r
1614 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
\r
1615 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
\r
1616 IIC_SSE_UNPCK>, EVEX_4V;
\r
1617 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
\r
1618 (ins RC:$src1, x86memop:$src2),
\r
1619 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
\r
1620 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
\r
1621 (bitconvert (memop_frag addr:$src2)))))],
\r
1622 IIC_SSE_UNPCK>, EVEX_4V;
\r
1624 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
\r
1625 VR512, memopv16i32, i512mem>, EVEX_V512,
\r
1626 EVEX_CD8<32, CD8VF>;
\r
1627 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
\r
1628 VR512, memopv8i64, i512mem>, EVEX_V512,
\r
1629 VEX_W, EVEX_CD8<64, CD8VF>;
\r
1630 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
\r
1631 VR512, memopv16i32, i512mem>, EVEX_V512,
\r
1632 EVEX_CD8<32, CD8VF>;
\r
1633 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
\r
1634 VR512, memopv8i64, i512mem>, EVEX_V512,
\r
1635 VEX_W, EVEX_CD8<64, CD8VF>;
\r
1636 //===----------------------------------------------------------------------===//
\r
1637 // AVX-512 - PSHUFD
\r
1640 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
\r
1641 SDNode OpNode, PatFrag mem_frag,
\r
1642 X86MemOperand x86memop, ValueType OpVT> {
\r
1643 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
\r
1644 (ins RC:$src1, i8imm:$src2),
\r
1645 !strconcat(OpcodeStr,
\r
1646 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
\r
1648 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
\r
1650 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
\r
1651 (ins x86memop:$src1, i8imm:$src2),
\r
1652 !strconcat(OpcodeStr,
\r
1653 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
\r
1655 (OpVT (OpNode (mem_frag addr:$src1),
\r
1656 (i8 imm:$src2))))]>, EVEX;
\r
1659 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
\r
1660 i512mem, v16i32>, OpSize, EVEX_V512, EVEX_CD8<32, CD8VF>;
\r
1662 let ExeDomain = SSEPackedSingle in
\r
1663 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
\r
1664 memopv16f32, i512mem, v16f32>, OpSize, TA, EVEX_V512,
\r
1665 EVEX_CD8<32, CD8VF>;
\r
1666 let ExeDomain = SSEPackedDouble in
\r
1667 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
\r
1668 memopv8f64, i512mem, v8f64>, OpSize, TA, EVEX_V512,
\r
1669 VEX_W, EVEX_CD8<32, CD8VF>;
\r
1671 def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
\r
1672 (VPERMILPSZri VR512:$src1, imm:$imm)>;
\r
1673 def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
\r
1674 (VPERMILPDZri VR512:$src1, imm:$imm)>;
\r
1676 //===----------------------------------------------------------------------===//
\r
1677 // AVX-512 Logical Instructions
\r
1678 //===----------------------------------------------------------------------===//
\r
1680 defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VR512, memopv16i32,
\r
1681 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
\r
1682 EVEX_V512, EVEX_CD8<32, CD8VF>;
\r
1683 defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VR512, memopv8i64,
\r
1684 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
\r
1685 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
\r
1686 defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VR512, memopv16i32,
\r
1687 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
\r
1688 EVEX_V512, EVEX_CD8<32, CD8VF>;
\r
1689 defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VR512, memopv8i64,
\r
1690 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
\r
1691 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
\r
1692 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VR512, memopv16i32,
\r
1693 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
\r
1694 EVEX_V512, EVEX_CD8<32, CD8VF>;
\r
1695 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VR512, memopv8i64,
\r
1696 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
\r
1697 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
\r
1698 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VR512,
\r
1699 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
\r
1700 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
\r
1701 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VR512, memopv8i64,
\r
1702 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 0>,
\r
1703 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
\r
1705 //===----------------------------------------------------------------------===//
\r
1706 // AVX-512 FP arithmetic
\r
1707 //===----------------------------------------------------------------------===//
\r
1709 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
\r
1710 SizeItins itins> {
\r
1711 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss{z}"), OpNode, FR32X,
\r
1712 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
\r
1713 EVEX_CD8<32, CD8VT1>;
\r
1714 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd{z}"), OpNode, FR64X,
\r
1715 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
\r
1716 EVEX_CD8<64, CD8VT1>;
\r
1719 let isCommutable = 1 in {
\r
1720 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
\r
1721 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
\r
1722 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
\r
1723 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
\r
1725 let isCommutable = 0 in {
\r
1726 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
\r
1727 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
\r
1730 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
\r
1731 RegisterClass RC, ValueType vt,
\r
1732 X86MemOperand x86memop, PatFrag mem_frag,
\r
1733 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
\r
1735 Domain d, OpndItins itins, bit commutable> {
\r
1736 let isCommutable = commutable in
\r
1737 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
\r
1738 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
\r
1739 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
\r
1741 let mayLoad = 1 in {
\r
1742 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
\r
1743 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
\r
1744 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
\r
1745 itins.rm, d>, EVEX_4V;
\r
1746 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
\r
1747 (ins RC:$src1, x86scalar_mop:$src2),
\r
1748 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
\r
1749 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
\r
1750 [(set RC:$dst, (OpNode RC:$src1,
\r
1751 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
\r
1752 itins.rm, d>, EVEX_4V, EVEX_B;
\r
1756 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VR512, v16f32, f512mem,
\r
1757 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
\r
1758 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
\r
1760 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VR512, v8f64, f512mem,
\r
1761 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
\r
1762 SSE_ALU_ITINS_P.d, 1>,
\r
1763 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
\r
1765 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VR512, v16f32, f512mem,
\r
1766 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
\r
1767 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
\r
1768 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VR512, v8f64, f512mem,
\r
1769 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
\r
1770 SSE_ALU_ITINS_P.d, 1>,
\r
1771 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
\r
1773 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VR512, v16f32, f512mem,
\r
1774 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
\r
1775 SSE_ALU_ITINS_P.s, 1>,
\r
1776 EVEX_V512, EVEX_CD8<32, CD8VF>;
\r
1777 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VR512, v16f32, f512mem,
\r
1778 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
\r
1779 SSE_ALU_ITINS_P.s, 1>,
\r
1780 EVEX_V512, EVEX_CD8<32, CD8VF>;
\r
1782 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VR512, v8f64, f512mem,
\r
1783 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
\r
1784 SSE_ALU_ITINS_P.d, 1>,
\r
1785 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
\r
1786 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VR512, v8f64, f512mem,
\r
1787 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
\r
1788 SSE_ALU_ITINS_P.d, 1>,
\r
1789 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
\r
1791 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VR512, v16f32, f512mem,
\r
1792 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
\r
1793 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
\r
1794 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VR512, v16f32, f512mem,
\r
1795 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
\r
1796 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
\r
1798 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VR512, v8f64, f512mem,
\r
1799 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
\r
1800 SSE_ALU_ITINS_P.d, 0>,
\r
1801 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
\r
1802 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VR512, v8f64, f512mem,
\r
1803 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
\r
1804 SSE_ALU_ITINS_P.d, 0>,
\r
1805 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
\r
1807 //===----------------------------------------------------------------------===//
\r
1808 // AVX-512 VPTESTM instructions
\r
1809 //===----------------------------------------------------------------------===//
\r
1811 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
\r
1812 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
\r
1813 SDNode OpNode, ValueType vt> {
\r
1814 def rr : AVX5128I<opc, MRMSrcReg,
\r
1815 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
\r
1816 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
\r
1817 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))]>, EVEX_4V;
\r
1818 def rm : AVX5128I<opc, MRMSrcMem,
\r
1819 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
\r
1820 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
\r
1821 [(set KRC:$dst, (OpNode (vt RC:$src1),
\r
1822 (bitconvert (memop_frag addr:$src2))))]>, EVEX_4V;
\r
1825 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
\r
1826 memopv16i32, X86testm, v16i32>, EVEX_V512,
\r
1827 EVEX_CD8<32, CD8VF>;
\r
1828 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
\r
1829 memopv8i64, X86testm, v8i64>, EVEX_V512, VEX_W,
\r
1830 EVEX_CD8<64, CD8VF>;
\r
1832 //===----------------------------------------------------------------------===//
\r
1833 // AVX-512 Shift instructions
\r
1834 //===----------------------------------------------------------------------===//
\r
1835 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
\r
1836 string OpcodeStr, SDNode OpNode, RegisterClass RC,
\r
1837 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
\r
1838 RegisterClass KRC> {
\r
1839 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
\r
1840 (ins RC:$src1, i32i8imm:$src2),
\r
1841 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
\r
1842 [(set RC:$dst, (vt (OpNode RC:$src1, (i32 imm:$src2))))],
\r
1843 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
\r
1844 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
\r
1845 (ins KRC:$mask, RC:$src1, i32i8imm:$src2),
\r
1846 !strconcat(OpcodeStr,
\r
1847 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
\r
1848 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
\r
1849 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
\r
1850 (ins x86memop:$src1, i32i8imm:$src2),
\r
1851 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
\r
1852 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
\r
1853 (i32 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
\r
1854 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
\r
1855 (ins KRC:$mask, x86memop:$src1, i32i8imm:$src2),
\r
1856 !strconcat(OpcodeStr,
\r
1857 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
\r
1858 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
\r
1861 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
\r
1862 RegisterClass RC, ValueType vt, ValueType SrcVT,
\r
1863 PatFrag bc_frag, RegisterClass KRC> {
\r
1864 // src2 is always 128-bit
\r
1865 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
\r
1866 (ins RC:$src1, VR128X:$src2),
\r
1867 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
\r
1868 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
\r
1869 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
\r
1870 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
\r
1871 (ins KRC:$mask, RC:$src1, VR128X:$src2),
\r
1872 !strconcat(OpcodeStr,
\r
1873 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
\r
1874 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
\r
1875 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
\r
1876 (ins RC:$src1, i128mem:$src2),
\r
1877 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
\r
1878 [(set RC:$dst, (vt (OpNode RC:$src1,
\r
1879 (bc_frag (memopv2i64 addr:$src2)))))],
\r
1880 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
\r
1881 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
\r
1882 (ins KRC:$mask, RC:$src1, i128mem:$src2),
\r
1883 !strconcat(OpcodeStr,
\r
1884 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
\r
1885 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
\r
1888 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
\r
1889 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
\r
1890 EVEX_V512, EVEX_CD8<32, CD8VF>;
\r
1891 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
\r
1892 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
\r
1893 EVEX_CD8<32, CD8VQ>;
\r
1895 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
\r
1896 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
\r
1897 EVEX_CD8<64, CD8VF>, VEX_W;
\r
1898 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
\r
1899 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
\r
1900 EVEX_CD8<64, CD8VQ>, VEX_W;
\r
1902 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
\r
1903 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
\r
1904 EVEX_CD8<32, CD8VF>;
\r
1905 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
\r
1906 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
\r
1907 EVEX_CD8<32, CD8VQ>;
\r
1909 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
\r
1910 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
\r
1911 EVEX_CD8<64, CD8VF>, VEX_W;
\r
1912 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
\r
1913 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
\r
1914 EVEX_CD8<64, CD8VQ>, VEX_W;
\r
1916 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
\r
1917 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
\r
1918 EVEX_V512, EVEX_CD8<32, CD8VF>;
\r
1919 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
\r
1920 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
\r
1921 EVEX_CD8<32, CD8VQ>;
\r
1923 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
\r
1924 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
\r
1925 EVEX_CD8<64, CD8VF>, VEX_W;
\r
1926 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
\r
1927 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
\r
1928 EVEX_CD8<64, CD8VQ>, VEX_W;
\r
1930 //===-------------------------------------------------------------------===//
\r
1931 // Variable Bit Shifts
\r
1932 //===-------------------------------------------------------------------===//
\r
1933 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
\r
1934 RegisterClass RC, ValueType vt,
\r
1935 X86MemOperand x86memop, PatFrag mem_frag> {
\r
1936 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
\r
1937 (ins RC:$src1, RC:$src2),
\r
1938 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
\r
1940 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
\r
1942 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
\r
1943 (ins RC:$src1, x86memop:$src2),
\r
1944 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
\r
1946 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
\r
1950 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
\r
1951 i512mem, memopv16i32>, EVEX_V512,
\r
1952 EVEX_CD8<32, CD8VF>;
\r
1953 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
\r
1954 i512mem, memopv8i64>, EVEX_V512, VEX_W,
\r
1955 EVEX_CD8<64, CD8VF>;
\r
1956 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
\r
1957 i512mem, memopv16i32>, EVEX_V512,
\r
1958 EVEX_CD8<32, CD8VF>;
\r
1959 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
\r
1960 i512mem, memopv8i64>, EVEX_V512, VEX_W,
\r
1961 EVEX_CD8<64, CD8VF>;
\r
1962 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
\r
1963 i512mem, memopv16i32>, EVEX_V512,
\r
1964 EVEX_CD8<32, CD8VF>;
\r
1965 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
\r
1966 i512mem, memopv8i64>, EVEX_V512, VEX_W,
\r
1967 EVEX_CD8<64, CD8VF>;
\r
1969 //===----------------------------------------------------------------------===//
\r
1970 // AVX-512 - MOVDDUP
\r
1971 //===----------------------------------------------------------------------===//
\r
1973 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
\r
1974 X86MemOperand x86memop, PatFrag memop_frag> {
\r
1975 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
\r
1976 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
\r
1977 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
\r
1978 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
\r
1979 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
\r
1981 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
\r
1984 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
\r
1985 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
\r
1986 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
\r
1987 (VMOVDDUPZrm addr:$src)>;
\r
1989 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
\r
1990 (ins VR128X:$src1, VR128X:$src2),
\r
1991 "vmovlhps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
\r
1992 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
\r
1993 IIC_SSE_MOV_LH>, EVEX_4V;
\r
1994 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
\r
1995 (ins VR128X:$src1, VR128X:$src2),
\r
1996 "vmovhlps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
\r
1997 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
\r
1998 IIC_SSE_MOV_LH>, EVEX_4V;
\r
2000 // MOVLHPS patterns
\r
2001 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
\r
2002 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
\r
2003 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
\r
2004 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
\r
2006 // MOVHLPS patterns
\r
2007 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
\r
2008 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
\r
2010 //===----------------------------------------------------------------------===//
\r
2011 // FMA - Fused Multiply Operations
\r
2013 let Constraints = "$src1 = $dst" in {
\r
2014 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
\r
2015 RegisterClass RC, X86MemOperand x86memop,
\r
2016 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
\r
2017 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
\r
2018 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
\r
2019 (ins RC:$src1, RC:$src2, RC:$src3),
\r
2020 !strconcat(OpcodeStr,"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
\r
2021 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
\r
2023 let mayLoad = 1 in
\r
2024 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
\r
2025 (ins RC:$src1, RC:$src2, x86memop:$src3),
\r
2026 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
\r
2027 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
\r
2028 (mem_frag addr:$src3))))]>;
\r
2029 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
\r
2030 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
\r
2031 !strconcat(OpcodeStr, "\t{${src3}", BrdcstStr,
\r
2032 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
\r
2033 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
\r
2034 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
\r
2036 } // Constraints = "$src1 = $dst"
\r
2038 let ExeDomain = SSEPackedSingle in {
\r
2039 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
\r
2040 memopv16f32, f32mem, loadf32, "{1to16}",
\r
2041 X86Fmadd, v16f32>, EVEX_V512,
\r
2042 EVEX_CD8<32, CD8VF>;
\r
2043 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
\r
2044 memopv16f32, f32mem, loadf32, "{1to16}",
\r
2045 X86Fmsub, v16f32>, EVEX_V512,
\r
2046 EVEX_CD8<32, CD8VF>;
\r
2047 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
\r
2048 memopv16f32, f32mem, loadf32, "{1to16}",
\r
2049 X86Fmaddsub, v16f32>,
\r
2050 EVEX_V512, EVEX_CD8<32, CD8VF>;
\r
2051 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
\r
2052 memopv16f32, f32mem, loadf32, "{1to16}",
\r
2053 X86Fmsubadd, v16f32>,
\r
2054 EVEX_V512, EVEX_CD8<32, CD8VF>;
\r
2055 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
\r
2056 memopv16f32, f32mem, loadf32, "{1to16}",
\r
2057 X86Fnmadd, v16f32>, EVEX_V512,
\r
2058 EVEX_CD8<32, CD8VF>;
\r
2059 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
\r
2060 memopv16f32, f32mem, loadf32, "{1to16}",
\r
2061 X86Fnmsub, v16f32>, EVEX_V512,
\r
2062 EVEX_CD8<32, CD8VF>;
\r
2064 let ExeDomain = SSEPackedDouble in {
\r
2065 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
\r
2066 memopv8f64, f64mem, loadf64, "{1to8}",
\r
2067 X86Fmadd, v8f64>, EVEX_V512,
\r
2068 VEX_W, EVEX_CD8<64, CD8VF>;
\r
2069 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
\r
2070 memopv8f64, f64mem, loadf64, "{1to8}",
\r
2071 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
\r
2072 EVEX_CD8<64, CD8VF>;
\r
2073 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
\r
2074 memopv8f64, f64mem, loadf64, "{1to8}",
\r
2075 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
\r
2076 EVEX_CD8<64, CD8VF>;
\r
2077 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
\r
2078 memopv8f64, f64mem, loadf64, "{1to8}",
\r
2079 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
\r
2080 EVEX_CD8<64, CD8VF>;
\r
2081 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
\r
2082 memopv8f64, f64mem, loadf64, "{1to8}",
\r
2083 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
\r
2084 EVEX_CD8<64, CD8VF>;
\r
2085 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
\r
2086 memopv8f64, f64mem, loadf64, "{1to8}",
\r
2087 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
\r
2088 EVEX_CD8<64, CD8VF>;
\r
2091 let Constraints = "$src1 = $dst" in {
\r
2092 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
\r
2093 RegisterClass RC, X86MemOperand x86memop,
\r
2094 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
\r
2095 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
\r
2096 let mayLoad = 1 in
\r
2097 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
\r
2098 (ins RC:$src1, RC:$src3, x86memop:$src2),
\r
2099 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
\r
2100 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
\r
2101 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
\r
2102 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
\r
2103 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
\r
2104 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
\r
2105 [(set RC:$dst, (OpNode RC:$src1,
\r
2106 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
\r
2108 } // Constraints = "$src1 = $dst"
\r
2111 let ExeDomain = SSEPackedSingle in {
\r
2112 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
\r
2113 memopv16f32, f32mem, loadf32, "{1to16}",
\r
2114 X86Fmadd, v16f32>, EVEX_V512,
\r
2115 EVEX_CD8<32, CD8VF>;
\r
2116 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
\r
2117 memopv16f32, f32mem, loadf32, "{1to16}",
\r
2118 X86Fmsub, v16f32>, EVEX_V512,
\r
2119 EVEX_CD8<32, CD8VF>;
\r
2120 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
\r
2121 memopv16f32, f32mem, loadf32, "{1to16}",
\r
2122 X86Fmaddsub, v16f32>,
\r
2123 EVEX_V512, EVEX_CD8<32, CD8VF>;
\r
2124 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
\r
2125 memopv16f32, f32mem, loadf32, "{1to16}",
\r
2126 X86Fmsubadd, v16f32>,
\r
2127 EVEX_V512, EVEX_CD8<32, CD8VF>;
\r
2128 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
\r
2129 memopv16f32, f32mem, loadf32, "{1to16}",
\r
2130 X86Fnmadd, v16f32>, EVEX_V512,
\r
2131 EVEX_CD8<32, CD8VF>;
\r
2132 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
\r
2133 memopv16f32, f32mem, loadf32, "{1to16}",
\r
2134 X86Fnmsub, v16f32>, EVEX_V512,
\r
2135 EVEX_CD8<32, CD8VF>;
\r
2137 let ExeDomain = SSEPackedDouble in {
\r
2138 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
\r
2139 memopv8f64, f64mem, loadf64, "{1to8}",
\r
2140 X86Fmadd, v8f64>, EVEX_V512,
\r
2141 VEX_W, EVEX_CD8<64, CD8VF>;
\r
2142 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
\r
2143 memopv8f64, f64mem, loadf64, "{1to8}",
\r
2144 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
\r
2145 EVEX_CD8<64, CD8VF>;
\r
2146 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
\r
2147 memopv8f64, f64mem, loadf64, "{1to8}",
\r
2148 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
\r
2149 EVEX_CD8<64, CD8VF>;
\r
2150 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
\r
2151 memopv8f64, f64mem, loadf64, "{1to8}",
\r
2152 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
\r
2153 EVEX_CD8<64, CD8VF>;
\r
2154 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
\r
2155 memopv8f64, f64mem, loadf64, "{1to8}",
\r
2156 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
\r
2157 EVEX_CD8<64, CD8VF>;
\r
2158 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
\r
2159 memopv8f64, f64mem, loadf64, "{1to8}",
\r
2160 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
\r
2161 EVEX_CD8<64, CD8VF>;
\r
2165 let Constraints = "$src1 = $dst" in {
\r
2166 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
\r
2167 RegisterClass RC, ValueType OpVT,
\r
2168 X86MemOperand x86memop, Operand memop,
\r
2169 PatFrag mem_frag> {
\r
2170 let isCommutable = 1 in
\r
2171 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
\r
2172 (ins RC:$src1, RC:$src2, RC:$src3),
\r
2173 !strconcat(OpcodeStr,
\r
2174 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
\r
2176 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
\r
2177 let mayLoad = 1 in
\r
2178 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
\r
2179 (ins RC:$src1, RC:$src2, f128mem:$src3),
\r
2180 !strconcat(OpcodeStr,
\r
2181 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
\r
2183 (OpVT (OpNode RC:$src2, RC:$src1,
\r
2184 (mem_frag addr:$src3))))]>;
\r
2187 } // Constraints = "$src1 = $dst"
\r
2189 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss{z}", X86Fmadd, FR32X,
\r
2190 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
\r
2191 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd{z}", X86Fmadd, FR64X,
\r
2192 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
\r
2193 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss{z}", X86Fmsub, FR32X,
\r
2194 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
\r
2195 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd{z}", X86Fmsub, FR64X,
\r
2196 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
\r
2197 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss{z}", X86Fnmadd, FR32X,
\r
2198 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
\r
2199 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd{z}", X86Fnmadd, FR64X,
\r
2200 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
\r
2201 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss{z}", X86Fnmsub, FR32X,
\r
2202 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
\r
2203 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd{z}", X86Fnmsub, FR64X,
\r
2204 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
\r
2206 //===----------------------------------------------------------------------===//
\r
2207 // AVX-512 Scalar convert from sign integer to float/double
\r
2208 //===----------------------------------------------------------------------===//
\r
2210 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
\r
2211 X86MemOperand x86memop, string asm> {
\r
2212 let neverHasSideEffects = 1 in {
\r
2213 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
\r
2214 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>, EVEX_4V;
\r
2215 let mayLoad = 1 in
\r
2216 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
\r
2217 (ins DstRC:$src1, x86memop:$src),
\r
2218 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>, EVEX_4V;
\r
2219 } // neverHasSideEffects = 1
\r
2222 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}{z}">,
\r
2223 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
\r
2224 defm VCVTSI2SS64Z : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}{z}">,
\r
2225 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
\r
2226 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}{z}">,
\r
2227 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
\r
2228 defm VCVTSI2SD64Z : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}{z}">,
\r
2229 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
\r
2231 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
\r
2232 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
\r
2233 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
\r
2234 (VCVTSI2SS64Zrm (f32 (IMPLICIT_DEF)), addr:$src)>;
\r
2235 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
\r
2236 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
\r
2237 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
\r
2238 (VCVTSI2SD64Zrm (f64 (IMPLICIT_DEF)), addr:$src)>;
\r
2240 def : Pat<(f32 (sint_to_fp GR32:$src)),
\r
2241 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
\r
2242 def : Pat<(f32 (sint_to_fp GR64:$src)),
\r
2243 (VCVTSI2SS64Zrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
\r
2244 def : Pat<(f64 (sint_to_fp GR32:$src)),
\r
2245 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
\r
2246 def : Pat<(f64 (sint_to_fp GR64:$src)),
\r
2247 (VCVTSI2SD64Zrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
\r
2250 //===----------------------------------------------------------------------===//
\r
2251 // AVX-512 Convert form float to double and back
\r
2252 //===----------------------------------------------------------------------===//
\r
2253 let neverHasSideEffects = 1 in {
\r
2254 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
\r
2255 (ins FR32X:$src1, FR32X:$src2),
\r
2256 "vcvtss2sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
\r
2257 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
\r
2258 let mayLoad = 1 in
\r
2259 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
\r
2260 (ins FR32X:$src1, f32mem:$src2),
\r
2261 "vcvtss2sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
\r
2262 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
\r
2263 EVEX_CD8<32, CD8VT1>;
\r
2265 // Convert scalar double to scalar single
\r
2266 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
\r
2267 (ins FR64X:$src1, FR64X:$src2),
\r
2268 "vcvtsd2ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
\r
2269 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
\r
2270 let mayLoad = 1 in
\r
2271 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
\r
2272 (ins FR64X:$src1, f64mem:$src2),
\r
2273 "vcvtsd2ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
\r
2274 []>, EVEX_4V, VEX_LIG, VEX_W,
\r
2275 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
\r
2278 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
\r
2279 Requires<[HasAVX512]>;
\r
2280 def : Pat<(fextend (loadf32 addr:$src)),
\r
2281 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
\r
2283 def : Pat<(extloadf32 addr:$src),
\r
2284 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
\r
2285 Requires<[HasAVX512, OptForSize]>;
\r
2287 def : Pat<(extloadf32 addr:$src),
\r
2288 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
\r
2289 Requires<[HasAVX512, OptForSpeed]>;
\r
2291 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
\r
2292 Requires<[HasAVX512]>;
\r
2294 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
\r
2295 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
\r
2296 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
\r
2298 let neverHasSideEffects = 1 in {
\r
2299 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
\r
2300 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
\r
2302 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
\r
2303 let mayLoad = 1 in
\r
2304 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
\r
2305 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
\r
2307 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
\r
2308 } // neverHasSideEffects = 1
\r
2311 defm VCVTPD2PSZ : avx512_vcvt_fp<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
\r
2312 memopv8f64, f512mem, v8f32, v8f64,
\r
2313 SSEPackedSingle>, EVEX_V512, VEX_W, OpSize,
\r
2314 EVEX_CD8<64, CD8VF>;
\r
2316 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
\r
2317 memopv4f64, f256mem, v8f64, v8f32,
\r
2318 SSEPackedDouble>, EVEX_V512, EVEX_CD8<32, CD8VH>;
\r
2319 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
\r
2320 (VCVTPS2PDZrm addr:$src)>;
\r
2322 //===----------------------------------------------------------------------===//
\r
2323 // AVX-512 Vector convert from sign integer to float/double
\r
2324 //===----------------------------------------------------------------------===//
\r
2326 defm VCVTDQ2PSZ : avx512_vcvt_fp<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
\r
2327 memopv8i64, i512mem, v16f32, v16i32,
\r
2328 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
\r
2330 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
\r
2331 memopv4i64, i256mem, v8f64, v8i32,
\r
2332 SSEPackedDouble>, EVEX_V512, XS,
\r
2333 EVEX_CD8<32, CD8VH>;
\r
2335 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
\r
2336 memopv16f32, f512mem, v16i32, v16f32,
\r
2337 SSEPackedSingle>, EVEX_V512, XS,
\r
2338 EVEX_CD8<32, CD8VF>;
\r
2340 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
\r
2341 memopv8f64, f512mem, v8i32, v8f64,
\r
2342 SSEPackedDouble>, EVEX_V512, OpSize, VEX_W,
\r
2343 EVEX_CD8<64, CD8VF>;
\r
2345 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
\r
2346 memopv16f32, f512mem, v16i32, v16f32,
\r
2347 SSEPackedSingle>, EVEX_V512,
\r
2348 EVEX_CD8<32, CD8VF>;
\r
2350 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
\r
2351 memopv8f64, f512mem, v8i32, v8f64,
\r
2352 SSEPackedDouble>, EVEX_V512, VEX_W,
\r
2353 EVEX_CD8<64, CD8VF>;
\r
2355 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
\r
2356 memopv4i64, f256mem, v8f64, v8i32,
\r
2357 SSEPackedDouble>, EVEX_V512, XS,
\r
2358 EVEX_CD8<32, CD8VH>;
\r
2360 defm VCVTUDQ2PSZ : avx512_vcvt_fp<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
\r
2361 memopv16i32, f512mem, v16f32, v16i32,
\r
2362 SSEPackedSingle>, EVEX_V512, XD,
\r
2363 EVEX_CD8<32, CD8VF>;
\r
2365 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
\r
2366 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
\r
2367 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
\r
2370 def : Pat<(int_x86_avx512_cvtdq2_ps_512 VR512:$src),
\r
2371 (VCVTDQ2PSZrr VR512:$src)>;
\r
2372 def : Pat<(int_x86_avx512_cvtdq2_ps_512 (bitconvert (memopv8i64 addr:$src))),
\r
2373 (VCVTDQ2PSZrm addr:$src)>;
\r
2375 def VCVTPS2DQZrr : AVX512BI<0x5B, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
\r
2376 "vcvtps2dq\t{$src, $dst|$dst, $src}",
\r
2378 (int_x86_avx512_cvt_ps2dq_512 VR512:$src))],
\r
2379 IIC_SSE_CVT_PS_RR>, EVEX, EVEX_V512;
\r
2380 def VCVTPS2DQZrm : AVX512BI<0x5B, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
\r
2381 "vcvtps2dq\t{$src, $dst|$dst, $src}",
\r
2383 (int_x86_avx512_cvt_ps2dq_512 (memopv16f32 addr:$src)))],
\r
2384 IIC_SSE_CVT_PS_RM>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
\r
2387 let Predicates = [HasAVX512] in {
\r
2388 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
\r
2389 (VCVTPD2PSZrm addr:$src)>;
\r
2390 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
\r
2391 (VCVTPS2PDZrm addr:$src)>;
\r
2394 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
\r
2395 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
\r
2396 "ucomiss{z}">, TB, EVEX, VEX_LIG,
\r
2397 EVEX_CD8<32, CD8VT1>;
\r
2398 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
\r
2399 "ucomisd{z}">, TB, OpSize, EVEX,
\r
2400 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
\r
2401 let Pattern = []<dag> in {
\r
2402 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
\r
2403 "comiss{z}">, TB, EVEX, VEX_LIG,
\r
2404 EVEX_CD8<32, CD8VT1>;
\r
2405 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
\r
2406 "comisd{z}">, TB, OpSize, EVEX,
\r
2407 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
\r
2409 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
\r
2410 load, "ucomiss">, TB, EVEX, VEX_LIG,
\r
2411 EVEX_CD8<32, CD8VT1>;
\r
2412 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
\r
2413 load, "ucomisd">, TB, OpSize, EVEX,
\r
2414 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
\r
2416 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
\r
2417 load, "comiss">, TB, EVEX, VEX_LIG,
\r
2418 EVEX_CD8<32, CD8VT1>;
\r
2419 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
\r
2420 load, "comisd">, TB, OpSize, EVEX,
\r
2421 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
\r
2424 /// avx512_unop_p - AVX-512 unops in packed form.
\r
2425 multiclass avx512_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
\r
2426 def PSZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
\r
2427 !strconcat(OpcodeStr,
\r
2428 "ps\t{$src, $dst|$dst, $src}"),
\r
2429 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))]>,
\r
2431 def PSZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f256mem:$src),
\r
2432 !strconcat(OpcodeStr,
\r
2433 "ps\t{$src, $dst|$dst, $src}"),
\r
2434 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
\r
2435 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
\r
2436 def PDZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
\r
2437 !strconcat(OpcodeStr,
\r
2438 "pd\t{$src, $dst|$dst, $src}"),
\r
2439 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))]>,
\r
2440 EVEX, EVEX_V512, VEX_W;
\r
2441 def PDZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
\r
2442 !strconcat(OpcodeStr,
\r
2443 "pd\t{$src, $dst|$dst, $src}"),
\r
2444 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
\r
2445 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
\r
2448 /// avx512_fp_unop_p_int - AVX-512 intrinsics unops in packed forms.
\r
2449 multiclass avx512_fp_unop_p_int<bits<8> opc, string OpcodeStr,
\r
2450 Intrinsic V16F32Int, Intrinsic V8F64Int> {
\r
2451 def PSZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
\r
2452 !strconcat(OpcodeStr,
\r
2453 "ps\t{$src, $dst|$dst, $src}"),
\r
2454 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
\r
2456 def PSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
\r
2457 !strconcat(OpcodeStr,
\r
2458 "ps\t{$src, $dst|$dst, $src}"),
\r
2459 [(set VR512:$dst,
\r
2460 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
\r
2461 EVEX_V512, EVEX_CD8<32, CD8VF>;
\r
2462 def PDZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
\r
2463 !strconcat(OpcodeStr,
\r
2464 "pd\t{$src, $dst|$dst, $src}"),
\r
2465 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
\r
2466 EVEX, EVEX_V512, VEX_W;
\r
2467 def PDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
\r
2468 !strconcat(OpcodeStr,
\r
2469 "pd\t{$src, $dst|$dst, $src}"),
\r
2470 [(set VR512:$dst,
\r
2471 (V8F64Int (memopv8f64 addr:$src)))]>,
\r
2472 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
\r
2475 /// avx512_fp_unop_s - AVX-512 unops in scalar form.
\r
2476 multiclass avx512_fp_unop_s<bits<8> opc, string OpcodeStr,
\r
2477 Intrinsic F32Int, Intrinsic F64Int> {
\r
2478 let hasSideEffects = 0 in {
\r
2479 def SSZr : AVX5128I<opc, MRMSrcReg, (outs FR32X:$dst),
\r
2480 (ins FR32X:$src1, FR32X:$src2),
\r
2481 !strconcat(OpcodeStr,
\r
2482 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
\r
2484 let mayLoad = 1 in {
\r
2485 def SSZm : AVX5128I<opc, MRMSrcMem, (outs FR32X:$dst),
\r
2486 (ins FR32X:$src1, f32mem:$src2),
\r
2487 !strconcat(OpcodeStr,
\r
2488 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
\r
2489 []>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
\r
2490 def SSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
\r
2491 (ins VR128X:$src1, ssmem:$src2),
\r
2492 !strconcat(OpcodeStr,
\r
2493 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
\r
2494 [(set VR128X:$dst, (F32Int VR128X:$src1, sse_load_f32:$src2))]>,
\r
2495 EVEX_4V, EVEX_CD8<32, CD8VT1>;
\r
2497 def SDZr : AVX5128I<opc, MRMSrcReg, (outs FR64X:$dst),
\r
2498 (ins FR64X:$src1, FR64X:$src2),
\r
2499 !strconcat(OpcodeStr,
\r
2500 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
\r
2502 let mayLoad = 1 in {
\r
2503 def SDZm : AVX5128I<opc, MRMSrcMem, (outs FR64X:$dst),
\r
2504 (ins FR64X:$src1, f64mem:$src2),
\r
2505 !strconcat(OpcodeStr,
\r
2506 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
\r
2507 EVEX_4V, VEX_W, EVEX_CD8<32, CD8VT1>;
\r
2508 def SDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
\r
2509 (ins VR128X:$src1, sdmem:$src2),
\r
2510 !strconcat(OpcodeStr,
\r
2511 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
\r
2512 [(set VR128X:$dst, (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
\r
2513 EVEX_4V, VEX_W, EVEX_CD8<32, CD8VT1>;
\r
2518 defm VRCP14 : avx512_fp_unop_s<0x4D, "vrcp14", int_x86_avx512_rcp14_ss,
\r
2519 int_x86_avx512_rcp14_sd>,
\r
2520 avx512_fp_unop_p<0x4C, "vrcp14", X86frcp>,
\r
2521 avx512_fp_unop_p_int<0x4C, "vrcp14",
\r
2522 int_x86_avx512_rcp14_ps_512, int_x86_avx512_rcp14_pd_512>;
\r
2524 defm VRSQRT14 : avx512_fp_unop_s<0x4F, "vrsqrt14", int_x86_avx512_rsqrt14_ss,
\r
2525 int_x86_avx512_rsqrt14_sd>,
\r
2526 avx512_fp_unop_p<0x4E, "vrsqrt14", X86frsqrt>,
\r
2527 avx512_fp_unop_p_int<0x4E, "vrsqrt14",
\r
2528 int_x86_avx512_rsqrt14_ps_512, int_x86_avx512_rsqrt14_pd_512>;
\r
2530 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
\r
2531 Intrinsic V16F32Int, Intrinsic V8F64Int,
\r
2532 OpndItins itins_s, OpndItins itins_d> {
\r
2533 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
\r
2534 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
\r
2535 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
\r
2538 let mayLoad = 1 in
\r
2539 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
\r
2540 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
\r
2541 [(set VR512:$dst,
\r
2542 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
\r
2543 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
\r
2545 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
\r
2546 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
\r
2547 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
\r
2550 let mayLoad = 1 in
\r
2551 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
\r
2552 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
\r
2553 [(set VR512:$dst, (OpNode
\r
2554 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
\r
2555 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
\r
2557 def PSZr_Int : AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
\r
2558 !strconcat(OpcodeStr,
\r
2559 "ps\t{$src, $dst|$dst, $src}"),
\r
2560 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
\r
2562 def PSZm_Int : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
\r
2563 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
\r
2564 [(set VR512:$dst,
\r
2565 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
\r
2566 EVEX_V512, EVEX_CD8<32, CD8VF>;
\r
2567 def PDZr_Int : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
\r
2568 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
\r
2569 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
\r
2570 EVEX, EVEX_V512, VEX_W;
\r
2571 def PDZm_Int : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
\r
2572 !strconcat(OpcodeStr,
\r
2573 "pd\t{$src, $dst|$dst, $src}"),
\r
2574 [(set VR512:$dst, (V8F64Int (memopv8f64 addr:$src)))]>,
\r
2575 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
\r
2578 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
\r
2579 Intrinsic F32Int, Intrinsic F64Int,
\r
2580 OpndItins itins_s, OpndItins itins_d> {
\r
2581 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
\r
2582 (ins FR32X:$src1, FR32X:$src2),
\r
2583 !strconcat(OpcodeStr,
\r
2584 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
\r
2585 [], itins_s.rr>, XS, EVEX_4V;
\r
2586 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
\r
2587 (ins VR128X:$src1, VR128X:$src2),
\r
2588 !strconcat(OpcodeStr,
\r
2589 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
\r
2590 [(set VR128X:$dst,
\r
2591 (F32Int VR128X:$src1, VR128X:$src2))],
\r
2592 itins_s.rr>, XS, EVEX_4V;
\r
2593 let mayLoad = 1 in {
\r
2594 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
\r
2595 (ins FR32X:$src1, f32mem:$src2),
\r
2596 !strconcat(OpcodeStr,
\r
2597 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
\r
2598 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
\r
2599 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
\r
2600 (ins VR128X:$src1, ssmem:$src2),
\r
2601 !strconcat(OpcodeStr,
\r
2602 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
\r
2603 [(set VR128X:$dst,
\r
2604 (F32Int VR128X:$src1, sse_load_f32:$src2))],
\r
2605 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
\r
2607 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
\r
2608 (ins FR64X:$src1, FR64X:$src2),
\r
2609 !strconcat(OpcodeStr,
\r
2610 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
\r
2611 XD, EVEX_4V, VEX_W;
\r
2612 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
\r
2613 (ins VR128X:$src1, VR128X:$src2),
\r
2614 !strconcat(OpcodeStr,
\r
2615 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
\r
2616 [(set VR128X:$dst,
\r
2617 (F64Int VR128X:$src1, VR128X:$src2))],
\r
2618 itins_s.rr>, XD, EVEX_4V, VEX_W;
\r
2619 let mayLoad = 1 in {
\r
2620 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
\r
2621 (ins FR64X:$src1, f64mem:$src2),
\r
2622 !strconcat(OpcodeStr,
\r
2623 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
\r
2624 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
\r
2625 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
\r
2626 (ins VR128X:$src1, sdmem:$src2),
\r
2627 !strconcat(OpcodeStr,
\r
2628 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
\r
2629 [(set VR128X:$dst,
\r
2630 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
\r
2631 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
\r
2636 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
\r
2637 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
\r
2638 SSE_SQRTSS, SSE_SQRTSD>,
\r
2639 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
\r
2640 int_x86_avx512_sqrt_ps_512, int_x86_avx512_sqrt_pd_512,
\r
2641 SSE_SQRTPS, SSE_SQRTPD>;
\r
2643 def : Pat<(f32 (fsqrt FR32X:$src)),
\r
2644 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
\r
2645 def : Pat<(f32 (fsqrt (load addr:$src))),
\r
2646 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
\r
2647 Requires<[OptForSize]>;
\r
2648 def : Pat<(f64 (fsqrt FR64X:$src)),
\r
2649 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
\r
2650 def : Pat<(f64 (fsqrt (load addr:$src))),
\r
2651 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
\r
2652 Requires<[OptForSize]>;
\r
2654 def : Pat<(f32 (X86frsqrt FR32X:$src)),
\r
2655 (VRSQRT14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
\r
2656 def : Pat<(f32 (X86frsqrt (load addr:$src))),
\r
2657 (VRSQRT14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
\r
2658 Requires<[OptForSize]>;
\r
2660 def : Pat<(f32 (X86frcp FR32X:$src)),
\r
2661 (VRCP14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
\r
2662 def : Pat<(f32 (X86frcp (load addr:$src))),
\r
2663 (VRCP14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
\r
2664 Requires<[OptForSize]>;
\r
2666 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
\r
2667 X86MemOperand x86memop, RegisterClass RC,
\r
2668 PatFrag mem_frag32, PatFrag mem_frag64,
\r
2669 Intrinsic V4F32Int, Intrinsic V2F64Int,
\r
2671 let ExeDomain = SSEPackedSingle in {
\r
2672 // Intrinsic operation, reg.
\r
2673 // Vector intrinsic operation, reg
\r
2674 def PSr : AVX512AIi8<opcps, MRMSrcReg,
\r
2675 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
\r
2676 !strconcat(OpcodeStr,
\r
2677 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
\r
2678 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
\r
2680 // Vector intrinsic operation, mem
\r
2681 def PSm : AVX512AIi8<opcps, MRMSrcMem,
\r
2682 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
\r
2683 !strconcat(OpcodeStr,
\r
2684 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
\r
2686 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
\r
2687 EVEX_CD8<32, VForm>;
\r
2688 } // ExeDomain = SSEPackedSingle
\r
2690 let ExeDomain = SSEPackedDouble in {
\r
2691 // Vector intrinsic operation, reg
\r
2692 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
\r
2693 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
\r
2694 !strconcat(OpcodeStr,
\r
2695 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
\r
2696 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
\r
2698 // Vector intrinsic operation, mem
\r
2699 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
\r
2700 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
\r
2701 !strconcat(OpcodeStr,
\r
2702 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
\r
2704 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
\r
2705 EVEX_CD8<64, VForm>;
\r
2706 } // ExeDomain = SSEPackedDouble
\r
2709 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
\r
2712 Intrinsic F64Int> {
\r
2713 let ExeDomain = GenericDomain in {
\r
2714 // Operation, reg.
\r
2715 let hasSideEffects = 0 in
\r
2716 def SSr : AVX512AIi8<opcss, MRMSrcReg,
\r
2717 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
\r
2718 !strconcat(OpcodeStr,
\r
2719 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
\r
2722 // Intrinsic operation, reg.
\r
2723 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
\r
2724 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
\r
2725 !strconcat(OpcodeStr,
\r
2726 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
\r
2727 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
\r
2729 // Intrinsic operation, mem.
\r
2730 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
\r
2731 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
\r
2732 !strconcat(OpcodeStr,
\r
2733 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
\r
2734 [(set VR128X:$dst, (F32Int VR128X:$src1,
\r
2735 sse_load_f32:$src2, imm:$src3))]>,
\r
2736 EVEX_CD8<32, CD8VT1>;
\r
2738 // Operation, reg.
\r
2739 let hasSideEffects = 0 in
\r
2740 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
\r
2741 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
\r
2742 !strconcat(OpcodeStr,
\r
2743 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
\r
2746 // Intrinsic operation, reg.
\r
2747 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
\r
2748 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
\r
2749 !strconcat(OpcodeStr,
\r
2750 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
\r
2751 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
\r
2754 // Intrinsic operation, mem.
\r
2755 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
\r
2756 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
\r
2757 !strconcat(OpcodeStr,
\r
2758 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
\r
2759 [(set VR128X:$dst,
\r
2760 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
\r
2761 VEX_W, EVEX_CD8<64, CD8VT1>;
\r
2762 } // ExeDomain = GenericDomain
\r
2765 let Predicates = [HasAVX512] in {
\r
2766 defm VRNDSCALE : avx512_fp_binop_rm<0x0A, 0x0B, "vrndscale",
\r
2767 int_x86_avx512_rndscale_ss,
\r
2768 int_x86_avx512_rndscale_sd>, EVEX_4V;
\r
2770 defm VRNDSCALEZ : avx512_fp_unop_rm<0x08, 0x09, "vrndscale", f256mem, VR512,
\r
2771 memopv16f32, memopv8f64,
\r
2772 int_x86_avx512_rndscale_ps_512,
\r
2773 int_x86_avx512_rndscale_pd_512, CD8VF>,
\r
2777 def : Pat<(ffloor FR32X:$src),
\r
2778 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
\r
2779 def : Pat<(f64 (ffloor FR64X:$src)),
\r
2780 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
\r
2781 def : Pat<(f32 (fnearbyint FR32X:$src)),
\r
2782 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
\r
2783 def : Pat<(f64 (fnearbyint FR64X:$src)),
\r
2784 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
\r
2785 def : Pat<(f32 (fceil FR32X:$src)),
\r
2786 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
\r
2787 def : Pat<(f64 (fceil FR64X:$src)),
\r
2788 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
\r
2789 def : Pat<(f32 (frint FR32X:$src)),
\r
2790 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
\r
2791 def : Pat<(f64 (frint FR64X:$src)),
\r
2792 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
\r
2793 def : Pat<(f32 (ftrunc FR32X:$src)),
\r
2794 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
\r
2795 def : Pat<(f64 (ftrunc FR64X:$src)),
\r
2796 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
\r
2798 def : Pat<(v16f32 (ffloor VR512:$src)),
\r
2799 (VRNDSCALEZPSr VR512:$src, (i32 0x1))>;
\r
2800 def : Pat<(v16f32 (fnearbyint VR512:$src)),
\r
2801 (VRNDSCALEZPSr VR512:$src, (i32 0xC))>;
\r
2802 def : Pat<(v16f32 (fceil VR512:$src)),
\r
2803 (VRNDSCALEZPSr VR512:$src, (i32 0x2))>;
\r
2804 def : Pat<(v16f32 (frint VR512:$src)),
\r
2805 (VRNDSCALEZPSr VR512:$src, (i32 0x4))>;
\r
2806 def : Pat<(v16f32 (ftrunc VR512:$src)),
\r
2807 (VRNDSCALEZPSr VR512:$src, (i32 0x3))>;
\r
2809 def : Pat<(v8f64 (ffloor VR512:$src)),
\r
2810 (VRNDSCALEZPDr VR512:$src, (i32 0x1))>;
\r
2811 def : Pat<(v8f64 (fnearbyint VR512:$src)),
\r
2812 (VRNDSCALEZPDr VR512:$src, (i32 0xC))>;
\r
2813 def : Pat<(v8f64 (fceil VR512:$src)),
\r
2814 (VRNDSCALEZPDr VR512:$src, (i32 0x2))>;
\r
2815 def : Pat<(v8f64 (frint VR512:$src)),
\r
2816 (VRNDSCALEZPDr VR512:$src, (i32 0x4))>;
\r
2817 def : Pat<(v8f64 (ftrunc VR512:$src)),
\r
2818 (VRNDSCALEZPDr VR512:$src, (i32 0x3))>;
\r
2820 //-------------------------------------------------
\r
2821 // Integer truncate and extend operations
\r
2822 //-------------------------------------------------
\r
2824 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
\r
2825 RegisterClass dstRC, RegisterClass srcRC,
\r
2826 RegisterClass KRC, X86MemOperand x86memop> {
\r
2827 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
\r
2829 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
\r
2832 def krr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
\r
2833 (ins KRC:$mask, srcRC:$src),
\r
2834 !strconcat(OpcodeStr,
\r
2835 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
\r
2836 []>, EVEX, EVEX_KZ;
\r
2838 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
\r
2839 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
\r
2842 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
\r
2843 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
\r
2844 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
\r
2845 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
\r
2846 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
\r
2847 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
\r
2848 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
\r
2849 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
\r
2850 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
\r
2851 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
\r
2852 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
\r
2853 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
\r
2854 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
\r
2855 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
\r
2856 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
\r
2857 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
\r
2858 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
\r
2859 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
\r
2860 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
\r
2861 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
\r
2862 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
\r
2863 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
\r
2864 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
\r
2865 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
\r
2866 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
\r
2867 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
\r
2868 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
\r
2869 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
\r
2870 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
\r
2871 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
\r
2873 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
\r
2874 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
\r
2875 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
\r
2876 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
\r
2877 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
\r
2879 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
\r
2880 (VPMOVDBkrr VK16WM:$mask, VR512:$src)>;
\r
2881 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
\r
2882 (VPMOVDWkrr VK16WM:$mask, VR512:$src)>;
\r
2883 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
\r
2884 (VPMOVQWkrr VK8WM:$mask, VR512:$src)>;
\r
2885 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
\r
2886 (VPMOVQDkrr VK8WM:$mask, VR512:$src)>;
\r
2889 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass DstRC,
\r
2890 RegisterClass SrcRC, SDNode OpNode, PatFrag mem_frag,
\r
2891 X86MemOperand x86memop, ValueType OpVT, ValueType InVT> {
\r
2893 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
\r
2895 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
\r
2896 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
\r
2897 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
\r
2898 (ins x86memop:$src),
\r
2899 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
\r
2901 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
\r
2905 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VR512, VR128X, X86vzext,
\r
2906 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
\r
2907 EVEX_CD8<8, CD8VQ>;
\r
2908 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VR512, VR128X, X86vzext,
\r
2909 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
\r
2910 EVEX_CD8<8, CD8VO>;
\r
2911 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VR512, VR256X, X86vzext,
\r
2912 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
\r
2913 EVEX_CD8<16, CD8VH>;
\r
2914 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VR512, VR128X, X86vzext,
\r
2915 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
\r
2916 EVEX_CD8<16, CD8VQ>;
\r
2917 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VR512, VR256X, X86vzext,
\r
2918 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
\r
2919 EVEX_CD8<32, CD8VH>;
\r
2921 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VR512, VR128X, X86vsext,
\r
2922 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
\r
2923 EVEX_CD8<8, CD8VQ>;
\r
2924 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VR512, VR128X, X86vsext,
\r
2925 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
\r
2926 EVEX_CD8<8, CD8VO>;
\r
2927 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VR512, VR256X, X86vsext,
\r
2928 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
\r
2929 EVEX_CD8<16, CD8VH>;
\r
2930 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VR512, VR128X, X86vsext,
\r
2931 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
\r
2932 EVEX_CD8<16, CD8VQ>;
\r
2933 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VR512, VR256X, X86vsext,
\r
2934 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
\r
2935 EVEX_CD8<32, CD8VH>;
\r
2937 //===----------------------------------------------------------------------===//
\r
2938 // GATHER - SCATTER Operations
\r
2940 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
\r
2941 RegisterClass RC, X86MemOperand memop> {
\r
2943 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
\r
2944 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
\r
2945 (ins RC:$src1, KRC:$mask, memop:$src2),
\r
2946 !strconcat(OpcodeStr,
\r
2947 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
\r
2948 []>, EVEX, EVEX_K;
\r
2950 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
\r
2951 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
\r
2952 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
\r
2953 EVEX_V512, EVEX_CD8<32, CD8VT1>;
\r
2955 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
\r
2956 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
\r
2957 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
\r
2958 EVEX_V512, EVEX_CD8<32, CD8VT1>;
\r
2960 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
\r
2961 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
\r
2962 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
\r
2963 EVEX_V512, EVEX_CD8<32, CD8VT1>;
\r
2965 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
\r
2966 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
\r
2967 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
\r
2968 EVEX_V512, EVEX_CD8<32, CD8VT1>;
\r
2970 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
\r
2971 RegisterClass RC, X86MemOperand memop> {
\r
2972 let mayStore = 1, Constraints = "$mask = $mask_wb" in
\r
2973 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
\r
2974 (ins memop:$dst, KRC:$mask, RC:$src2),
\r
2975 !strconcat(OpcodeStr,
\r
2976 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
\r
2977 []>, EVEX, EVEX_K;
\r
2980 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
\r
2981 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
\r
2982 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
\r
2983 EVEX_V512, EVEX_CD8<32, CD8VT1>;
\r
2985 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
\r
2986 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
\r
2987 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
\r
2988 EVEX_V512, EVEX_CD8<32, CD8VT1>;
\r
2990 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
\r
2991 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
\r
2992 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
\r
2993 EVEX_V512, EVEX_CD8<32, CD8VT1>;
\r
2995 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
\r
2996 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
\r
2997 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
\r
2998 EVEX_V512, EVEX_CD8<32, CD8VT1>;
\r
3000 //===----------------------------------------------------------------------===//
\r
3001 // VSHUFPS - VSHUFPD Operations
\r
3003 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
\r
3004 ValueType vt, string OpcodeStr, PatFrag mem_frag,
\r
3006 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
\r
3007 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
\r
3008 !strconcat(OpcodeStr,
\r
3009 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
\r
3010 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
\r
3011 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
\r
3012 EVEX_4V, TB, Sched<[WriteShuffleLd, ReadAfterLd]>;
\r
3013 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
\r
3014 (ins RC:$src1, RC:$src2, i8imm:$src3),
\r
3015 !strconcat(OpcodeStr,
\r
3016 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
\r
3017 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
\r
3018 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
\r
3019 EVEX_4V, TB, Sched<[WriteShuffle]>;
\r
3022 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
\r
3023 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
\r
3024 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
\r
3025 SSEPackedDouble>, OpSize, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
\r
3028 multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
\r
3029 X86MemOperand x86memop> {
\r
3030 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
\r
3031 (ins RC:$src1, RC:$src2, i8imm:$src3),
\r
3032 !strconcat(OpcodeStr,
\r
3033 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
\r
3035 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
\r
3036 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
\r
3037 !strconcat(OpcodeStr,
\r
3038 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
\r
3041 defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
\r
3042 EVEX_V512, EVEX_CD8<32, CD8VF>;
\r
3043 defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
\r
3044 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
\r
3046 def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
\r
3047 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
\r
3048 def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
\r
3049 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
\r
3050 def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
\r
3051 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
\r
3052 def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
\r
3053 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
\r
3055 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, RegisterClass RC,
\r
3056 X86MemOperand x86memop> {
\r
3057 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
\r
3058 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
\r
3060 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
\r
3061 (ins x86memop:$src),
\r
3062 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
\r
3066 defm VPABSD : avx512_vpabs<0x1E, "vpabsd", VR512, i512mem>, EVEX_V512,
\r
3067 EVEX_CD8<32, CD8VF>;
\r
3068 defm VPABSQ : avx512_vpabs<0x1F, "vpabsq", VR512, i512mem>, EVEX_V512, VEX_W,
\r
3069 EVEX_CD8<64, CD8VF>;
\r