1 //===-- X86InstrAVX512.td - AVX512 Instruction Set ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 AVX512 instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // Group template arguments that can be derived from the vector type (EltNum x
17 // EltVT). These are things like the register class for the writemask, etc.
18 // The idea is to pass one of these as the template argument rather than the
19 // individual arguments.
20 // The template is also used for scalar types, in this case numelts is 1.
21 class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,
23 RegisterClass RC = rc;
24 ValueType EltVT = eltvt;
25 int NumElts = numelts;
27 // Corresponding mask register class.
28 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
30 // Corresponding write-mask register class.
31 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
33 // The GPR register class that can hold the write mask. Use GR8 for fewer
34 // than 8 elements. Use shift-right and equal to work around the lack of
37 !cast<RegisterClass>("GR" #
38 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
40 // Suffix used in the instruction mnemonic.
41 string Suffix = suffix;
43 // VTName is a string name for vector VT. For vector types it will be
44 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
45 // It is a little bit complex for scalar types, where NumElts = 1.
46 // In this case we build v4f32 or v2f64
47 string VTName = "v" # !if (!eq (NumElts, 1),
48 !if (!eq (EltVT.Size, 32), 4,
49 !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT;
52 ValueType VT = !cast<ValueType>(VTName);
54 string EltTypeName = !cast<string>(EltVT);
55 // Size of the element type in bits, e.g. 32 for v16i32.
56 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
57 int EltSize = EltVT.Size;
59 // "i" for integer types and "f" for floating-point types
60 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
62 // Size of RC in bits, e.g. 512 for VR512.
65 // The corresponding memory operand, e.g. i512mem for VR512.
66 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
67 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
70 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
71 // due to load promotion during legalization
72 PatFrag LdFrag = !cast<PatFrag>("load" #
73 !if (!eq (TypeVariantName, "i"),
74 !if (!eq (Size, 128), "v2i64",
75 !if (!eq (Size, 256), "v4i64",
77 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
79 // The corresponding float type, e.g. v16f32 for v16i32
80 // Note: For EltSize < 32, FloatVT is illegal and TableGen
81 // fails to compile, so we choose FloatVT = VT
82 ValueType FloatVT = !cast<ValueType>(
83 !if (!eq (!srl(EltSize,5),0),
85 !if (!eq(TypeVariantName, "i"),
86 "v" # NumElts # "f" # EltSize,
89 // The string to specify embedded broadcast in assembly.
90 string BroadcastStr = "{1to" # NumElts # "}";
92 // 8-bit compressed displacement tuple/subvector format. This is only
93 // defined for NumElts <= 8.
94 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
95 !cast<CD8VForm>("CD8VT" # NumElts), ?);
97 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
98 !if (!eq (Size, 256), sub_ymm, ?));
100 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
101 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
104 // A vector type of the same width with element type i32. This is used to
105 // create the canonical constant zero node ImmAllZerosV.
106 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
107 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
110 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
111 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
112 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
113 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
114 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
115 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
117 // "x" in v32i8x_info means RC = VR256X
118 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
119 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
120 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
121 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
122 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
123 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
125 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
126 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
127 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
128 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
129 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
130 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
132 // We map scalar types to the smallest (128-bit) vector type
133 // with the appropriate element type. This allows to use the same masking logic.
134 def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;
135 def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;
137 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
138 X86VectorVTInfo i128> {
139 X86VectorVTInfo info512 = i512;
140 X86VectorVTInfo info256 = i256;
141 X86VectorVTInfo info128 = i128;
144 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
146 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
148 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
150 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
152 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
154 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
157 // This multiclass generates the masking variants from the non-masking
158 // variant. It only provides the assembly pieces for the masking variants.
159 // It assumes custom ISel patterns for masking which can be provided as
160 // template arguments.
161 multiclass AVX512_maskable_custom<bits<8> O, Format F,
163 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
165 string AttSrcAsm, string IntelSrcAsm,
167 list<dag> MaskingPattern,
168 list<dag> ZeroMaskingPattern,
170 string MaskingConstraint = "",
171 InstrItinClass itin = NoItinerary,
172 bit IsCommutable = 0> {
173 let isCommutable = IsCommutable in
174 def NAME: AVX512<O, F, Outs, Ins,
175 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
176 "$dst "#Round#", "#IntelSrcAsm#"}",
179 // Prefer over VMOV*rrk Pat<>
180 let AddedComplexity = 20 in
181 def NAME#k: AVX512<O, F, Outs, MaskingIns,
182 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}"#Round#"|"#
183 "$dst {${mask}}"#Round#", "#IntelSrcAsm#"}",
184 MaskingPattern, itin>,
186 // In case of the 3src subclass this is overridden with a let.
187 string Constraints = MaskingConstraint;
189 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
190 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
191 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}"#Round#"|"#
192 "$dst {${mask}} {z}"#Round#", "#IntelSrcAsm#"}",
199 // Common base class of AVX512_maskable and AVX512_maskable_3src.
200 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
202 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
204 string AttSrcAsm, string IntelSrcAsm,
205 dag RHS, dag MaskingRHS,
206 SDNode Select = vselect, string Round = "",
207 string MaskingConstraint = "",
208 InstrItinClass itin = NoItinerary,
209 bit IsCommutable = 0> :
210 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
211 AttSrcAsm, IntelSrcAsm,
212 [(set _.RC:$dst, RHS)],
213 [(set _.RC:$dst, MaskingRHS)],
215 (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
216 Round, MaskingConstraint, NoItinerary, IsCommutable>;
218 // This multiclass generates the unconditional/non-masking, the masking and
219 // the zero-masking variant of the vector instruction. In the masking case, the
220 // perserved vector elements come from a new dummy input operand tied to $dst.
221 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
222 dag Outs, dag Ins, string OpcodeStr,
223 string AttSrcAsm, string IntelSrcAsm,
224 dag RHS, string Round = "",
225 InstrItinClass itin = NoItinerary,
226 bit IsCommutable = 0> :
227 AVX512_maskable_common<O, F, _, Outs, Ins,
228 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
229 !con((ins _.KRCWM:$mask), Ins),
230 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
231 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect,
232 Round, "$src0 = $dst", itin, IsCommutable>;
234 // This multiclass generates the unconditional/non-masking, the masking and
235 // the zero-masking variant of the scalar instruction.
236 multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
237 dag Outs, dag Ins, string OpcodeStr,
238 string AttSrcAsm, string IntelSrcAsm,
239 dag RHS, string Round = "",
240 InstrItinClass itin = NoItinerary,
241 bit IsCommutable = 0> :
242 AVX512_maskable_common<O, F, _, Outs, Ins,
243 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
244 !con((ins _.KRCWM:$mask), Ins),
245 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
246 (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select,
247 Round, "$src0 = $dst", itin, IsCommutable>;
249 // Similar to AVX512_maskable but in this case one of the source operands
250 // ($src1) is already tied to $dst so we just use that for the preserved
251 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
253 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
254 dag Outs, dag NonTiedIns, string OpcodeStr,
255 string AttSrcAsm, string IntelSrcAsm,
257 AVX512_maskable_common<O, F, _, Outs,
258 !con((ins _.RC:$src1), NonTiedIns),
259 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
260 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
261 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
262 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
265 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
268 string AttSrcAsm, string IntelSrcAsm,
270 AVX512_maskable_custom<O, F, Outs, Ins,
271 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
272 !con((ins _.KRCWM:$mask), Ins),
273 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [], "",
276 // Bitcasts between 512-bit vector types. Return the original type since
277 // no instruction is needed for the conversion
278 let Predicates = [HasAVX512] in {
279 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
280 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
281 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
282 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
283 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
284 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
285 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
286 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
287 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
288 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
289 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
290 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
291 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
292 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
293 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
294 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
295 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
296 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
297 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
298 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
299 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
300 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
301 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
302 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
303 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
304 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
305 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
306 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
307 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
308 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
309 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
311 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
312 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
313 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
314 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
315 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
316 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
317 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
318 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
319 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
320 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
321 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
322 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
323 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
324 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
325 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
326 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
327 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
328 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
329 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
330 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
331 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
332 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
333 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
334 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
335 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
336 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
337 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
338 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
339 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
340 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
342 // Bitcasts between 256-bit vector types. Return the original type since
343 // no instruction is needed for the conversion
344 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
345 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
346 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
347 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
348 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
349 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
350 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
351 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
352 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
353 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
354 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
355 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
356 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
357 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
358 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
359 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
360 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
361 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
362 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
363 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
364 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
365 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
366 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
367 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
368 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
369 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
370 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
371 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
372 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
373 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
377 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
380 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
381 isPseudo = 1, Predicates = [HasAVX512] in {
382 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
383 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
386 let Predicates = [HasAVX512] in {
387 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
388 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
389 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
392 //===----------------------------------------------------------------------===//
393 // AVX-512 - VECTOR INSERT
396 multiclass vinsert_for_size_no_alt<int Opcode,
397 X86VectorVTInfo From, X86VectorVTInfo To,
398 PatFrag vinsert_insert,
399 SDNodeXForm INSERT_get_vinsert_imm> {
400 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
401 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
402 (ins VR512:$src1, From.RC:$src2, u8imm:$src3),
403 "vinsert" # From.EltTypeName # "x" # From.NumElts #
404 "\t{$src3, $src2, $src1, $dst|"
405 "$dst, $src1, $src2, $src3}",
406 [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
407 (From.VT From.RC:$src2),
412 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
413 (ins VR512:$src1, From.MemOp:$src2, u8imm:$src3),
414 "vinsert" # From.EltTypeName # "x" # From.NumElts #
415 "\t{$src3, $src2, $src1, $dst|"
416 "$dst, $src1, $src2, $src3}",
418 EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, From.CD8TupleForm>;
422 multiclass vinsert_for_size<int Opcode,
423 X86VectorVTInfo From, X86VectorVTInfo To,
424 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
425 PatFrag vinsert_insert,
426 SDNodeXForm INSERT_get_vinsert_imm> :
427 vinsert_for_size_no_alt<Opcode, From, To,
428 vinsert_insert, INSERT_get_vinsert_imm> {
429 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
430 // vinserti32x4. Only add this if 64x2 and friends are not supported
431 // natively via AVX512DQ.
432 let Predicates = [NoDQI] in
433 def : Pat<(vinsert_insert:$ins
434 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
435 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
436 VR512:$src1, From.RC:$src2,
437 (INSERT_get_vinsert_imm VR512:$ins)))>;
440 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
441 ValueType EltVT64, int Opcode256> {
442 defm NAME # "32x4" : vinsert_for_size<Opcode128,
443 X86VectorVTInfo< 4, EltVT32, VR128X>,
444 X86VectorVTInfo<16, EltVT32, VR512>,
445 X86VectorVTInfo< 2, EltVT64, VR128X>,
446 X86VectorVTInfo< 8, EltVT64, VR512>,
448 INSERT_get_vinsert128_imm>;
449 let Predicates = [HasDQI] in
450 defm NAME # "64x2" : vinsert_for_size_no_alt<Opcode128,
451 X86VectorVTInfo< 2, EltVT64, VR128X>,
452 X86VectorVTInfo< 8, EltVT64, VR512>,
454 INSERT_get_vinsert128_imm>, VEX_W;
455 defm NAME # "64x4" : vinsert_for_size<Opcode256,
456 X86VectorVTInfo< 4, EltVT64, VR256X>,
457 X86VectorVTInfo< 8, EltVT64, VR512>,
458 X86VectorVTInfo< 8, EltVT32, VR256>,
459 X86VectorVTInfo<16, EltVT32, VR512>,
461 INSERT_get_vinsert256_imm>, VEX_W;
462 let Predicates = [HasDQI] in
463 defm NAME # "32x8" : vinsert_for_size_no_alt<Opcode256,
464 X86VectorVTInfo< 8, EltVT32, VR256X>,
465 X86VectorVTInfo<16, EltVT32, VR512>,
467 INSERT_get_vinsert256_imm>;
470 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
471 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
473 // vinsertps - insert f32 to XMM
474 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
475 (ins VR128X:$src1, VR128X:$src2, u8imm:$src3),
476 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
477 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
479 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
480 (ins VR128X:$src1, f32mem:$src2, u8imm:$src3),
481 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
482 [(set VR128X:$dst, (X86insertps VR128X:$src1,
483 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
484 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
486 //===----------------------------------------------------------------------===//
487 // AVX-512 VECTOR EXTRACT
490 multiclass vextract_for_size<int Opcode,
491 X86VectorVTInfo From, X86VectorVTInfo To,
492 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
493 PatFrag vextract_extract,
494 SDNodeXForm EXTRACT_get_vextract_imm> {
495 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
496 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
497 (ins VR512:$src1, u8imm:$idx),
498 "vextract" # To.EltTypeName # "x4",
499 "$idx, $src1", "$src1, $idx",
500 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
502 AVX512AIi8Base, EVEX, EVEX_V512;
504 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
505 (ins To.MemOp:$dst, VR512:$src1, u8imm:$src2),
506 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
507 "$dst, $src1, $src2}",
508 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
511 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
513 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
514 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
516 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
518 // A 128/256-bit subvector extract from the first 512-bit vector position is
519 // a subregister copy that needs no instruction.
520 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
522 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
524 // And for the alternative types.
525 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
527 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
529 // Intrinsic call with masking.
530 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
532 VR512:$src1, (iPTR imm:$idx), To.RC:$src0, GR8:$mask),
533 (!cast<Instruction>(NAME # To.EltSize # "x4rrk") To.RC:$src0,
534 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
535 VR512:$src1, imm:$idx)>;
537 // Intrinsic call with zero-masking.
538 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
540 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, GR8:$mask),
541 (!cast<Instruction>(NAME # To.EltSize # "x4rrkz")
542 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
543 VR512:$src1, imm:$idx)>;
545 // Intrinsic call without masking.
546 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
548 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
549 (!cast<Instruction>(NAME # To.EltSize # "x4rr")
550 VR512:$src1, imm:$idx)>;
553 multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
554 ValueType EltVT64, int Opcode64> {
555 defm NAME # "32x4" : vextract_for_size<Opcode32,
556 X86VectorVTInfo<16, EltVT32, VR512>,
557 X86VectorVTInfo< 4, EltVT32, VR128X>,
558 X86VectorVTInfo< 8, EltVT64, VR512>,
559 X86VectorVTInfo< 2, EltVT64, VR128X>,
561 EXTRACT_get_vextract128_imm>;
562 defm NAME # "64x4" : vextract_for_size<Opcode64,
563 X86VectorVTInfo< 8, EltVT64, VR512>,
564 X86VectorVTInfo< 4, EltVT64, VR256X>,
565 X86VectorVTInfo<16, EltVT32, VR512>,
566 X86VectorVTInfo< 8, EltVT32, VR256>,
568 EXTRACT_get_vextract256_imm>, VEX_W;
571 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
572 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
574 // A 128-bit subvector insert to the first 512-bit vector position
575 // is a subregister copy that needs no instruction.
576 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
577 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
578 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
580 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
581 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
582 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
584 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
585 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
586 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
588 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
589 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
590 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
593 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
594 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
595 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
596 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
597 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
598 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
599 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
600 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
602 // vextractps - extract 32 bits from XMM
603 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
604 (ins VR128X:$src1, u8imm:$src2),
605 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
606 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
609 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
610 (ins f32mem:$dst, VR128X:$src1, u8imm:$src2),
611 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
612 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
613 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
615 //===---------------------------------------------------------------------===//
618 multiclass avx512_fp_broadcast<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
619 ValueType svt, X86VectorVTInfo _> {
620 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
621 (ins SrcRC:$src), "vbroadcast"## !subst("p", "s", _.Suffix),
622 "$src", "$src", (_.VT (OpNode (svt SrcRC:$src)))>,
626 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
627 (ins _.ScalarMemOp:$src),
628 "vbroadcast"##!subst("p", "s", _.Suffix), "$src", "$src",
629 (_.VT (OpNode (_.ScalarLdFrag addr:$src)))>,
634 multiclass avx512_fp_broadcast_vl<bits<8> opc, SDNode OpNode,
635 AVX512VLVectorVTInfo _> {
636 defm Z : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info512>,
639 let Predicates = [HasVLX] in {
640 defm Z256 : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info256>,
645 let ExeDomain = SSEPackedSingle in {
646 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, X86VBroadcast,
647 avx512vl_f32_info>, EVEX_CD8<32, CD8VT1>;
648 let Predicates = [HasVLX] in {
649 defm VBROADCASTSSZ128 : avx512_fp_broadcast<0x18, X86VBroadcast, VR128X,
650 v4f32, v4f32x_info>, EVEX_V128,
651 EVEX_CD8<32, CD8VT1>;
655 let ExeDomain = SSEPackedDouble in {
656 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, X86VBroadcast,
657 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VT1>;
660 // avx512_broadcast_pat introduces patterns for broadcast with a scalar argument.
661 // Later, we can canonize broadcast instructions before ISel phase and
662 // eliminate additional patterns on ISel.
663 // SrcRC_v and SrcRC_s are RegisterClasses for vector and scalar
664 // representations of source
665 multiclass avx512_broadcast_pat<string InstName, SDNode OpNode,
666 X86VectorVTInfo _, RegisterClass SrcRC_v,
667 RegisterClass SrcRC_s> {
668 def : Pat<(_.VT (OpNode (_.EltVT SrcRC_s:$src))),
669 (!cast<Instruction>(InstName##"r")
670 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
672 let AddedComplexity = 30 in {
673 def : Pat<(_.VT (vselect _.KRCWM:$mask,
674 (OpNode (_.EltVT SrcRC_s:$src)), _.RC:$src0)),
675 (!cast<Instruction>(InstName##"rk") _.RC:$src0, _.KRCWM:$mask,
676 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
678 def : Pat<(_.VT(vselect _.KRCWM:$mask,
679 (OpNode (_.EltVT SrcRC_s:$src)), _.ImmAllZerosV)),
680 (!cast<Instruction>(InstName##"rkz") _.KRCWM:$mask,
681 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
685 defm : avx512_broadcast_pat<"VBROADCASTSSZ", X86VBroadcast, v16f32_info,
687 defm : avx512_broadcast_pat<"VBROADCASTSDZ", X86VBroadcast, v8f64_info,
690 let Predicates = [HasVLX] in {
691 defm : avx512_broadcast_pat<"VBROADCASTSSZ256", X86VBroadcast,
692 v8f32x_info, VR128X, FR32X>;
693 defm : avx512_broadcast_pat<"VBROADCASTSSZ128", X86VBroadcast,
694 v4f32x_info, VR128X, FR32X>;
695 defm : avx512_broadcast_pat<"VBROADCASTSDZ256", X86VBroadcast,
696 v4f64x_info, VR128X, FR64X>;
699 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
700 (VBROADCASTSSZm addr:$src)>;
701 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
702 (VBROADCASTSDZm addr:$src)>;
704 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
705 (VBROADCASTSSZm addr:$src)>;
706 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
707 (VBROADCASTSDZm addr:$src)>;
709 multiclass avx512_int_broadcast_reg<bits<8> opc, X86VectorVTInfo _,
710 RegisterClass SrcRC> {
711 defm r : AVX512_maskable_in_asm<opc, MRMSrcReg, _, (outs _.RC:$dst),
712 (ins SrcRC:$src), "vpbroadcast"##_.Suffix,
713 "$src", "$src", []>, T8PD, EVEX;
716 multiclass avx512_int_broadcast_reg_vl<bits<8> opc, AVX512VLVectorVTInfo _,
717 RegisterClass SrcRC, Predicate prd> {
718 let Predicates = [prd] in
719 defm Z : avx512_int_broadcast_reg<opc, _.info512, SrcRC>, EVEX_V512;
720 let Predicates = [prd, HasVLX] in {
721 defm Z256 : avx512_int_broadcast_reg<opc, _.info256, SrcRC>, EVEX_V256;
722 defm Z128 : avx512_int_broadcast_reg<opc, _.info128, SrcRC>, EVEX_V128;
726 defm VPBROADCASTBr : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info, GR32,
728 defm VPBROADCASTWr : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info, GR32,
730 defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, GR32,
732 defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, GR64,
735 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
736 (VPBROADCASTDrZrkz VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
738 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
739 (VPBROADCASTQrZrkz VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
741 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
742 (VPBROADCASTDrZr GR32:$src)>;
743 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
744 (VPBROADCASTDrZrkz VK16WM:$mask, GR32:$src)>;
745 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
746 (VPBROADCASTQrZr GR64:$src)>;
747 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
748 (VPBROADCASTQrZrkz VK8WM:$mask, GR64:$src)>;
750 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
751 (VPBROADCASTDrZr GR32:$src)>;
752 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
753 (VPBROADCASTQrZr GR64:$src)>;
755 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
756 (v16i32 immAllZerosV), (i16 GR16:$mask))),
757 (VPBROADCASTDrZrkz (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
758 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
759 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
760 (VPBROADCASTQrZrkz (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
762 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
763 X86MemOperand x86memop, PatFrag ld_frag,
764 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
766 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
767 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
769 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
770 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
772 !strconcat(OpcodeStr,
773 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
775 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
778 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
779 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
781 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
782 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
784 !strconcat(OpcodeStr,
785 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
786 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
787 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
791 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
792 loadi32, VR512, v16i32, v4i32, VK16WM>,
793 EVEX_V512, EVEX_CD8<32, CD8VT1>;
794 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
795 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
796 EVEX_CD8<64, CD8VT1>;
798 multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
799 X86MemOperand x86memop, PatFrag ld_frag,
802 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
803 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
805 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
807 !strconcat(OpcodeStr,
808 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
813 defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
814 i128mem, loadv2i64, VK16WM>,
815 EVEX_V512, EVEX_CD8<32, CD8VT4>;
816 defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
817 i256mem, loadv4i64, VK16WM>, VEX_W,
818 EVEX_V512, EVEX_CD8<64, CD8VT4>;
820 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
821 (VPBROADCASTDZrr VR128X:$src)>;
822 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
823 (VPBROADCASTQZrr VR128X:$src)>;
825 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
826 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
827 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
828 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
830 def : Pat<(v16i32 (X86VBroadcast (v16i32 VR512:$src))),
831 (VPBROADCASTDZrr (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
832 def : Pat<(v8i64 (X86VBroadcast (v8i64 VR512:$src))),
833 (VPBROADCASTQZrr (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
835 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
836 (VBROADCASTSSZr VR128X:$src)>;
837 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
838 (VBROADCASTSDZr VR128X:$src)>;
840 // Provide fallback in case the load node that is used in the patterns above
841 // is used by additional users, which prevents the pattern selection.
842 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
843 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
844 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
845 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
848 let Predicates = [HasAVX512] in {
849 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
851 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
852 addr:$src)), sub_ymm)>;
854 //===----------------------------------------------------------------------===//
855 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
858 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
860 let Predicates = [HasCDI] in
861 def Zrr : AVX512XS8I<opc, MRMSrcReg, (outs VR512:$dst), (ins KRC:$src),
862 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
863 []>, EVEX, EVEX_V512;
865 let Predicates = [HasCDI, HasVLX] in {
866 def Z128rr : AVX512XS8I<opc, MRMSrcReg, (outs VR128:$dst), (ins KRC:$src),
867 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
868 []>, EVEX, EVEX_V128;
869 def Z256rr : AVX512XS8I<opc, MRMSrcReg, (outs VR256:$dst), (ins KRC:$src),
870 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
871 []>, EVEX, EVEX_V256;
875 let Predicates = [HasCDI] in {
876 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
878 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
882 //===----------------------------------------------------------------------===//
885 // -- immediate form --
886 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
888 let ExeDomain = _.ExeDomain in {
889 def ri : AVX512AIi8<opc, MRMSrcReg, (outs _.RC:$dst),
890 (ins _.RC:$src1, u8imm:$src2),
891 !strconcat(OpcodeStr,
892 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
894 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>,
896 def mi : AVX512AIi8<opc, MRMSrcMem, (outs _.RC:$dst),
897 (ins _.MemOp:$src1, u8imm:$src2),
898 !strconcat(OpcodeStr,
899 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
901 (_.VT (OpNode (_.LdFrag addr:$src1),
903 EVEX, EVEX_CD8<_.EltSize, CD8VF>;
907 multiclass avx512_permil<bits<8> OpcImm, bits<8> OpcVar, X86VectorVTInfo _,
908 X86VectorVTInfo Ctrl> :
909 avx512_perm_imm<OpcImm, "vpermil" # _.Suffix, X86VPermilpi, _> {
910 let ExeDomain = _.ExeDomain in {
911 def rr : AVX5128I<OpcVar, MRMSrcReg, (outs _.RC:$dst),
912 (ins _.RC:$src1, _.RC:$src2),
913 !strconcat("vpermil" # _.Suffix,
914 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
916 (_.VT (X86VPermilpv _.RC:$src1,
917 (Ctrl.VT Ctrl.RC:$src2))))]>,
919 def rm : AVX5128I<OpcVar, MRMSrcMem, (outs _.RC:$dst),
920 (ins _.RC:$src1, Ctrl.MemOp:$src2),
921 !strconcat("vpermil" # _.Suffix,
922 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
924 (_.VT (X86VPermilpv _.RC:$src1,
925 (Ctrl.VT (Ctrl.LdFrag addr:$src2)))))]>,
930 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", X86VPermi, v8i64_info>,
932 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", X86VPermi, v8f64_info>,
935 defm VPERMILPSZ : avx512_permil<0x04, 0x0C, v16f32_info, v16i32_info>,
937 defm VPERMILPDZ : avx512_permil<0x05, 0x0D, v8f64_info, v8i64_info>,
940 def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
941 (VPERMILPSZri VR512:$src1, imm:$imm)>;
942 def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
943 (VPERMILPDZri VR512:$src1, imm:$imm)>;
945 // -- VPERM - register form --
946 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
947 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
949 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
950 (ins RC:$src1, RC:$src2),
951 !strconcat(OpcodeStr,
952 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
954 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
956 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
957 (ins RC:$src1, x86memop:$src2),
958 !strconcat(OpcodeStr,
959 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
961 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
965 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, loadv16i32, i512mem,
966 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
967 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, loadv8i64, i512mem,
968 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
969 let ExeDomain = SSEPackedSingle in
970 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, loadv16f32, f512mem,
971 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
972 let ExeDomain = SSEPackedDouble in
973 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, loadv8f64, f512mem,
974 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
976 // -- VPERM2I - 3 source operands form --
977 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
978 PatFrag mem_frag, X86MemOperand x86memop,
979 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
980 let Constraints = "$src1 = $dst" in {
981 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
982 (ins RC:$src1, RC:$src2, RC:$src3),
983 !strconcat(OpcodeStr,
984 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
986 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
989 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
990 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
991 !strconcat(OpcodeStr,
992 "\t{$src3, $src2, $dst {${mask}}|"
993 "$dst {${mask}}, $src2, $src3}"),
994 [(set RC:$dst, (OpVT (vselect KRC:$mask,
995 (OpNode RC:$src1, RC:$src2,
1000 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
1001 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
1002 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
1003 !strconcat(OpcodeStr,
1004 "\t{$src3, $src2, $dst {${mask}} {z} |",
1005 "$dst {${mask}} {z}, $src2, $src3}"),
1006 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1007 (OpNode RC:$src1, RC:$src2,
1010 (v16i32 immAllZerosV))))))]>,
1013 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1014 (ins RC:$src1, RC:$src2, x86memop:$src3),
1015 !strconcat(OpcodeStr,
1016 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
1018 (OpVT (OpNode RC:$src1, RC:$src2,
1019 (mem_frag addr:$src3))))]>, EVEX_4V;
1021 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1022 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
1023 !strconcat(OpcodeStr,
1024 "\t{$src3, $src2, $dst {${mask}}|"
1025 "$dst {${mask}}, $src2, $src3}"),
1027 (OpVT (vselect KRC:$mask,
1028 (OpNode RC:$src1, RC:$src2,
1029 (mem_frag addr:$src3)),
1033 let AddedComplexity = 10 in // Prefer over the rrkz variant
1034 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1035 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
1036 !strconcat(OpcodeStr,
1037 "\t{$src3, $src2, $dst {${mask}} {z}|"
1038 "$dst {${mask}} {z}, $src2, $src3}"),
1040 (OpVT (vselect KRC:$mask,
1041 (OpNode RC:$src1, RC:$src2,
1042 (mem_frag addr:$src3)),
1044 (v16i32 immAllZerosV))))))]>,
1048 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, loadv16i32,
1049 i512mem, X86VPermiv3, v16i32, VK16WM>,
1050 EVEX_V512, EVEX_CD8<32, CD8VF>;
1051 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, loadv8i64,
1052 i512mem, X86VPermiv3, v8i64, VK8WM>,
1053 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1054 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, loadv16f32,
1055 i512mem, X86VPermiv3, v16f32, VK16WM>,
1056 EVEX_V512, EVEX_CD8<32, CD8VF>;
1057 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, loadv8f64,
1058 i512mem, X86VPermiv3, v8f64, VK8WM>,
1059 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1061 multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
1062 PatFrag mem_frag, X86MemOperand x86memop,
1063 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
1064 ValueType MaskVT, RegisterClass MRC> :
1065 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
1067 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
1068 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
1069 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
1071 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
1072 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
1073 (!cast<Instruction>(NAME#rrk) VR512:$src1,
1074 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
1077 defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, loadv16i32, i512mem,
1078 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
1079 EVEX_V512, EVEX_CD8<32, CD8VF>;
1080 defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, loadv8i64, i512mem,
1081 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
1082 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1083 defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, loadv16f32, i512mem,
1084 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
1085 EVEX_V512, EVEX_CD8<32, CD8VF>;
1086 defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, loadv8f64, i512mem,
1087 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
1088 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1090 //===----------------------------------------------------------------------===//
1091 // AVX-512 - BLEND using mask
1093 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1094 let ExeDomain = _.ExeDomain in {
1095 def rr : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1096 (ins _.RC:$src1, _.RC:$src2),
1097 !strconcat(OpcodeStr,
1098 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1100 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1101 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1102 !strconcat(OpcodeStr,
1103 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1104 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1105 (_.VT _.RC:$src2)))]>, EVEX_4V, EVEX_K;
1106 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1107 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1108 !strconcat(OpcodeStr,
1109 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1110 []>, EVEX_4V, EVEX_KZ;
1111 let mayLoad = 1 in {
1112 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1113 (ins _.RC:$src1, _.MemOp:$src2),
1114 !strconcat(OpcodeStr,
1115 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1116 []>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
1117 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1118 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1119 !strconcat(OpcodeStr,
1120 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1121 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1122 (_.VT (bitconvert (_.LdFrag addr:$src2)))))]>,
1123 EVEX_4V, EVEX_K, EVEX_CD8<_.EltSize, CD8VF>;
1124 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1125 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1126 !strconcat(OpcodeStr,
1127 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1128 []>, EVEX_4V, EVEX_KZ, EVEX_CD8<_.EltSize, CD8VF>;
1132 multiclass avx512_blendmask_rmb<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1134 def rmbk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1135 (ins _.KRCWM:$mask, _.RC:$src1, _.ScalarMemOp:$src2),
1136 !strconcat(OpcodeStr,
1137 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1138 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1139 [(set _.RC:$dst,(X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1140 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))]>,
1141 EVEX_4V, EVEX_K, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1143 def rmb : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1144 (ins _.RC:$src1, _.ScalarMemOp:$src2),
1145 !strconcat(OpcodeStr,
1146 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1147 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1148 []>, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1152 multiclass blendmask_dq <bits<8> opc, string OpcodeStr,
1153 AVX512VLVectorVTInfo VTInfo> {
1154 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>,
1155 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1157 let Predicates = [HasVLX] in {
1158 defm Z256 : avx512_blendmask<opc, OpcodeStr, VTInfo.info256>,
1159 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1160 defm Z128 : avx512_blendmask<opc, OpcodeStr, VTInfo.info128>,
1161 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1165 multiclass blendmask_bw <bits<8> opc, string OpcodeStr,
1166 AVX512VLVectorVTInfo VTInfo> {
1167 let Predicates = [HasBWI] in
1168 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1170 let Predicates = [HasBWI, HasVLX] in {
1171 defm Z256 : avx512_blendmask <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1172 defm Z128 : avx512_blendmask <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1177 defm VBLENDMPS : blendmask_dq <0x65, "vblendmps", avx512vl_f32_info>;
1178 defm VBLENDMPD : blendmask_dq <0x65, "vblendmpd", avx512vl_f64_info>, VEX_W;
1179 defm VPBLENDMD : blendmask_dq <0x64, "vpblendmd", avx512vl_i32_info>;
1180 defm VPBLENDMQ : blendmask_dq <0x64, "vpblendmq", avx512vl_i64_info>, VEX_W;
1181 defm VPBLENDMB : blendmask_bw <0x66, "vpblendmb", avx512vl_i8_info>;
1182 defm VPBLENDMW : blendmask_bw <0x66, "vpblendmw", avx512vl_i16_info>, VEX_W;
1185 let Predicates = [HasAVX512] in {
1186 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1187 (v8f32 VR256X:$src2))),
1189 (v16f32 (VBLENDMPSZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1190 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1191 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1193 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1194 (v8i32 VR256X:$src2))),
1196 (v16i32 (VPBLENDMDZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1197 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1198 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1200 //===----------------------------------------------------------------------===//
1201 // Compare Instructions
1202 //===----------------------------------------------------------------------===//
1204 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1205 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1206 SDNode OpNode, ValueType VT,
1207 PatFrag ld_frag, string Suffix> {
1208 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1209 (outs VK1:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1210 !strconcat("vcmp${cc}", Suffix,
1211 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1212 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
1213 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1214 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1215 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1216 !strconcat("vcmp${cc}", Suffix,
1217 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1218 [(set VK1:$dst, (OpNode (VT RC:$src1),
1219 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1220 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1221 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
1222 (outs VK1:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc),
1223 !strconcat("vcmp", Suffix,
1224 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1225 [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1227 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
1228 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, u8imm:$cc),
1229 !strconcat("vcmp", Suffix,
1230 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1231 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1235 let Predicates = [HasAVX512] in {
1236 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, X86cmpms, f32, loadf32, "ss">,
1238 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, X86cmpms, f64, loadf64, "sd">,
1242 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1243 X86VectorVTInfo _> {
1244 def rr : AVX512BI<opc, MRMSrcReg,
1245 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1246 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1247 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1248 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1250 def rm : AVX512BI<opc, MRMSrcMem,
1251 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1252 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1253 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1254 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1255 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1256 def rrk : AVX512BI<opc, MRMSrcReg,
1257 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1258 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1259 "$dst {${mask}}, $src1, $src2}"),
1260 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1261 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1262 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1264 def rmk : AVX512BI<opc, MRMSrcMem,
1265 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1266 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1267 "$dst {${mask}}, $src1, $src2}"),
1268 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1269 (OpNode (_.VT _.RC:$src1),
1271 (_.LdFrag addr:$src2))))))],
1272 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1275 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1276 X86VectorVTInfo _> :
1277 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1278 let mayLoad = 1 in {
1279 def rmb : AVX512BI<opc, MRMSrcMem,
1280 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1281 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1282 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1283 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1284 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1285 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1286 def rmbk : AVX512BI<opc, MRMSrcMem,
1287 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1288 _.ScalarMemOp:$src2),
1289 !strconcat(OpcodeStr,
1290 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1291 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1292 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1293 (OpNode (_.VT _.RC:$src1),
1295 (_.ScalarLdFrag addr:$src2)))))],
1296 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1300 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1301 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1302 let Predicates = [prd] in
1303 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1306 let Predicates = [prd, HasVLX] in {
1307 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1309 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1314 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1315 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1317 let Predicates = [prd] in
1318 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1321 let Predicates = [prd, HasVLX] in {
1322 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1324 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1329 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1330 avx512vl_i8_info, HasBWI>,
1333 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1334 avx512vl_i16_info, HasBWI>,
1335 EVEX_CD8<16, CD8VF>;
1337 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1338 avx512vl_i32_info, HasAVX512>,
1339 EVEX_CD8<32, CD8VF>;
1341 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1342 avx512vl_i64_info, HasAVX512>,
1343 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1345 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1346 avx512vl_i8_info, HasBWI>,
1349 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1350 avx512vl_i16_info, HasBWI>,
1351 EVEX_CD8<16, CD8VF>;
1353 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1354 avx512vl_i32_info, HasAVX512>,
1355 EVEX_CD8<32, CD8VF>;
1357 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1358 avx512vl_i64_info, HasAVX512>,
1359 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1361 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1362 (COPY_TO_REGCLASS (VPCMPGTDZrr
1363 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1364 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1366 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1367 (COPY_TO_REGCLASS (VPCMPEQDZrr
1368 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1369 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1371 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1372 X86VectorVTInfo _> {
1373 def rri : AVX512AIi8<opc, MRMSrcReg,
1374 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVX512ICC:$cc),
1375 !strconcat("vpcmp${cc}", Suffix,
1376 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1377 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1379 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1381 def rmi : AVX512AIi8<opc, MRMSrcMem,
1382 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVX512ICC:$cc),
1383 !strconcat("vpcmp${cc}", Suffix,
1384 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1385 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1386 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1388 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1389 def rrik : AVX512AIi8<opc, MRMSrcReg,
1390 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1392 !strconcat("vpcmp${cc}", Suffix,
1393 "\t{$src2, $src1, $dst {${mask}}|",
1394 "$dst {${mask}}, $src1, $src2}"),
1395 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1396 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1398 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1400 def rmik : AVX512AIi8<opc, MRMSrcMem,
1401 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1403 !strconcat("vpcmp${cc}", Suffix,
1404 "\t{$src2, $src1, $dst {${mask}}|",
1405 "$dst {${mask}}, $src1, $src2}"),
1406 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1407 (OpNode (_.VT _.RC:$src1),
1408 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1410 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1412 // Accept explicit immediate argument form instead of comparison code.
1413 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1414 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1415 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1416 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1417 "$dst, $src1, $src2, $cc}"),
1418 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1420 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1421 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1422 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1423 "$dst, $src1, $src2, $cc}"),
1424 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1425 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1426 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1428 !strconcat("vpcmp", Suffix,
1429 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1430 "$dst {${mask}}, $src1, $src2, $cc}"),
1431 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1433 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1434 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1436 !strconcat("vpcmp", Suffix,
1437 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1438 "$dst {${mask}}, $src1, $src2, $cc}"),
1439 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1443 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1444 X86VectorVTInfo _> :
1445 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1446 def rmib : AVX512AIi8<opc, MRMSrcMem,
1447 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1449 !strconcat("vpcmp${cc}", Suffix,
1450 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1451 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1452 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1453 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1455 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1456 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1457 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1458 _.ScalarMemOp:$src2, AVX512ICC:$cc),
1459 !strconcat("vpcmp${cc}", Suffix,
1460 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1461 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1462 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1463 (OpNode (_.VT _.RC:$src1),
1464 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1466 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1468 // Accept explicit immediate argument form instead of comparison code.
1469 let isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 1 in {
1470 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1471 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1473 !strconcat("vpcmp", Suffix,
1474 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1475 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1476 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1477 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1478 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1479 _.ScalarMemOp:$src2, u8imm:$cc),
1480 !strconcat("vpcmp", Suffix,
1481 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1482 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1483 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1487 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1488 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1489 let Predicates = [prd] in
1490 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1492 let Predicates = [prd, HasVLX] in {
1493 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1494 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1498 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1499 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1500 let Predicates = [prd] in
1501 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1504 let Predicates = [prd, HasVLX] in {
1505 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1507 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1512 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1513 HasBWI>, EVEX_CD8<8, CD8VF>;
1514 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1515 HasBWI>, EVEX_CD8<8, CD8VF>;
1517 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1518 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1519 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1520 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1522 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1523 HasAVX512>, EVEX_CD8<32, CD8VF>;
1524 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1525 HasAVX512>, EVEX_CD8<32, CD8VF>;
1527 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1528 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1529 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1530 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1532 // avx512_cmp_packed - compare packed instructions
1533 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
1534 X86MemOperand x86memop, ValueType vt,
1535 string suffix, Domain d> {
1536 def rri : AVX512PIi8<0xC2, MRMSrcReg,
1537 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1538 !strconcat("vcmp${cc}", suffix,
1539 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1540 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
1541 let hasSideEffects = 0 in
1542 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
1543 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1544 !strconcat("vcmp${cc}", suffix,
1545 "\t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
1547 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
1548 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1549 !strconcat("vcmp${cc}", suffix,
1550 "\t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1552 (X86cmpm (vt RC:$src1), (load addr:$src2), imm:$cc))], d>;
1554 // Accept explicit immediate argument form instead of comparison code.
1555 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1556 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
1557 (outs KRC:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc),
1558 !strconcat("vcmp", suffix,
1559 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1561 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
1562 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, u8imm:$cc),
1563 !strconcat("vcmp", suffix,
1564 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1568 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
1569 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
1570 EVEX_CD8<32, CD8VF>;
1571 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
1572 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
1573 EVEX_CD8<64, CD8VF>;
1575 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1576 (COPY_TO_REGCLASS (VCMPPSZrri
1577 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1578 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1580 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1581 (COPY_TO_REGCLASS (VPCMPDZrri
1582 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1583 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1585 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1586 (COPY_TO_REGCLASS (VPCMPUDZrri
1587 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1588 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1591 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1592 (v16f32 VR512:$src2), i8immZExt5:$cc, (i16 -1),
1594 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
1595 (I8Imm imm:$cc)), GR16)>;
1597 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1598 (v8f64 VR512:$src2), i8immZExt5:$cc, (i8 -1),
1600 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
1601 (I8Imm imm:$cc)), GR8)>;
1603 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1604 (v16f32 VR512:$src2), i8immZExt5:$cc, (i16 -1),
1606 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1607 (I8Imm imm:$cc)), GR16)>;
1609 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1610 (v8f64 VR512:$src2), i8immZExt5:$cc, (i8 -1),
1612 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1613 (I8Imm imm:$cc)), GR8)>;
1615 // Mask register copy, including
1616 // - copy between mask registers
1617 // - load/store mask registers
1618 // - copy from GPR to mask register and vice versa
1620 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1621 string OpcodeStr, RegisterClass KRC,
1622 ValueType vvt, X86MemOperand x86memop> {
1623 let hasSideEffects = 0 in {
1624 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1625 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1627 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1628 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1629 [(set KRC:$dst, (vvt (load addr:$src)))]>;
1631 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1632 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1633 [(store KRC:$src, addr:$dst)]>;
1637 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1639 RegisterClass KRC, RegisterClass GRC> {
1640 let hasSideEffects = 0 in {
1641 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1642 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1643 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1644 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1648 let Predicates = [HasDQI] in
1649 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8mem>,
1650 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1653 let Predicates = [HasAVX512] in
1654 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
1655 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1658 let Predicates = [HasBWI] in {
1659 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1,i32mem>,
1661 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1665 let Predicates = [HasBWI] in {
1666 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64mem>,
1668 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1672 // GR from/to mask register
1673 let Predicates = [HasDQI] in {
1674 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1675 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1676 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1677 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1679 let Predicates = [HasAVX512] in {
1680 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1681 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1682 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1683 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1685 let Predicates = [HasBWI] in {
1686 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1687 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1689 let Predicates = [HasBWI] in {
1690 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1691 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1695 let Predicates = [HasDQI] in {
1696 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1697 (KMOVBmk addr:$dst, VK8:$src)>;
1698 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1699 (KMOVBkm addr:$src)>;
1701 let Predicates = [HasAVX512, NoDQI] in {
1702 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1703 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1704 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1705 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1707 let Predicates = [HasAVX512] in {
1708 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1709 (KMOVWmk addr:$dst, VK16:$src)>;
1710 def : Pat<(i1 (load addr:$src)),
1711 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
1712 def : Pat<(v16i1 (bitconvert (i16 (load addr:$src)))),
1713 (KMOVWkm addr:$src)>;
1715 let Predicates = [HasBWI] in {
1716 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1717 (KMOVDmk addr:$dst, VK32:$src)>;
1718 def : Pat<(v32i1 (bitconvert (i32 (load addr:$src)))),
1719 (KMOVDkm addr:$src)>;
1721 let Predicates = [HasBWI] in {
1722 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1723 (KMOVQmk addr:$dst, VK64:$src)>;
1724 def : Pat<(v64i1 (bitconvert (i64 (load addr:$src)))),
1725 (KMOVQkm addr:$src)>;
1728 let Predicates = [HasAVX512] in {
1729 def : Pat<(i1 (trunc (i64 GR64:$src))),
1730 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1733 def : Pat<(i1 (trunc (i32 GR32:$src))),
1734 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1736 def : Pat<(i1 (trunc (i8 GR8:$src))),
1738 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1740 def : Pat<(i1 (trunc (i16 GR16:$src))),
1742 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1745 def : Pat<(i32 (zext VK1:$src)),
1746 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1747 def : Pat<(i8 (zext VK1:$src)),
1750 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1751 def : Pat<(i64 (zext VK1:$src)),
1752 (AND64ri8 (SUBREG_TO_REG (i64 0),
1753 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1754 def : Pat<(i16 (zext VK1:$src)),
1756 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1758 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1759 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1760 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1761 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1763 let Predicates = [HasBWI] in {
1764 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1765 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1766 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1767 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1771 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1772 let Predicates = [HasAVX512] in {
1773 // GR from/to 8-bit mask without native support
1774 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1776 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1778 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1780 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1783 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1784 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1785 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1786 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1788 let Predicates = [HasBWI] in {
1789 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1790 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1791 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1792 (COPY_TO_REGCLASS VK64:$src, VK1)>;
1795 // Mask unary operation
1797 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1798 RegisterClass KRC, SDPatternOperator OpNode,
1800 let Predicates = [prd] in
1801 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1802 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1803 [(set KRC:$dst, (OpNode KRC:$src))]>;
1806 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1807 SDPatternOperator OpNode> {
1808 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1810 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1811 HasAVX512>, VEX, PS;
1812 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1813 HasBWI>, VEX, PD, VEX_W;
1814 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1815 HasBWI>, VEX, PS, VEX_W;
1818 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
1820 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1821 let Predicates = [HasAVX512] in
1822 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1824 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1825 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1827 defm : avx512_mask_unop_int<"knot", "KNOT">;
1829 let Predicates = [HasDQI] in
1830 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1831 let Predicates = [HasAVX512] in
1832 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1833 let Predicates = [HasBWI] in
1834 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1835 let Predicates = [HasBWI] in
1836 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1838 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1839 let Predicates = [HasAVX512, NoDQI] in {
1840 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1841 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1843 def : Pat<(not VK8:$src),
1845 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1848 // Mask binary operation
1849 // - KAND, KANDN, KOR, KXNOR, KXOR
1850 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1851 RegisterClass KRC, SDPatternOperator OpNode,
1853 let Predicates = [prd] in
1854 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1855 !strconcat(OpcodeStr,
1856 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1857 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1860 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1861 SDPatternOperator OpNode> {
1862 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1863 HasDQI>, VEX_4V, VEX_L, PD;
1864 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1865 HasAVX512>, VEX_4V, VEX_L, PS;
1866 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1867 HasBWI>, VEX_4V, VEX_L, VEX_W, PD;
1868 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1869 HasBWI>, VEX_4V, VEX_L, VEX_W, PS;
1872 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1873 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1875 let isCommutable = 1 in {
1876 defm KAND : avx512_mask_binop_all<0x41, "kand", and>;
1877 defm KOR : avx512_mask_binop_all<0x45, "kor", or>;
1878 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>;
1879 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>;
1881 let isCommutable = 0 in
1882 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
1884 def : Pat<(xor VK1:$src1, VK1:$src2),
1885 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1886 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1888 def : Pat<(or VK1:$src1, VK1:$src2),
1889 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1890 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1892 def : Pat<(and VK1:$src1, VK1:$src2),
1893 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1894 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1896 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1897 let Predicates = [HasAVX512] in
1898 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1899 (i16 GR16:$src1), (i16 GR16:$src2)),
1900 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1901 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1902 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1905 defm : avx512_mask_binop_int<"kand", "KAND">;
1906 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1907 defm : avx512_mask_binop_int<"kor", "KOR">;
1908 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1909 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1911 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1912 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1913 let Predicates = [HasAVX512] in
1914 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1916 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1917 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1920 defm : avx512_binop_pat<and, KANDWrr>;
1921 defm : avx512_binop_pat<andn, KANDNWrr>;
1922 defm : avx512_binop_pat<or, KORWrr>;
1923 defm : avx512_binop_pat<xnor, KXNORWrr>;
1924 defm : avx512_binop_pat<xor, KXORWrr>;
1927 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1928 RegisterClass KRC> {
1929 let Predicates = [HasAVX512] in
1930 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1931 !strconcat(OpcodeStr,
1932 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1935 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1936 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1940 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1941 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1942 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1943 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1946 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1947 let Predicates = [HasAVX512] in
1948 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1949 (i16 GR16:$src1), (i16 GR16:$src2)),
1950 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1951 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1952 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1954 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1957 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1959 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1960 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1961 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1962 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1965 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1966 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1968 let Predicates = [HasDQI] in
1969 defm B : avx512_mask_testop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
1971 let Predicates = [HasBWI] in {
1972 defm Q : avx512_mask_testop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
1974 defm D : avx512_mask_testop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
1979 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1982 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1984 let Predicates = [HasAVX512] in
1985 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, u8imm:$imm),
1986 !strconcat(OpcodeStr,
1987 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
1988 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1991 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1993 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1995 let Predicates = [HasDQI] in
1996 defm B : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
1998 let Predicates = [HasBWI] in {
1999 defm Q : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
2001 let Predicates = [HasDQI] in
2002 defm D : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
2007 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
2008 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
2010 // Mask setting all 0s or 1s
2011 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
2012 let Predicates = [HasAVX512] in
2013 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
2014 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
2015 [(set KRC:$dst, (VT Val))]>;
2018 multiclass avx512_mask_setop_w<PatFrag Val> {
2019 defm B : avx512_mask_setop<VK8, v8i1, Val>;
2020 defm W : avx512_mask_setop<VK16, v16i1, Val>;
2023 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
2024 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
2026 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2027 let Predicates = [HasAVX512] in {
2028 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
2029 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
2030 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
2031 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
2032 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
2034 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
2035 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
2037 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
2038 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
2040 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
2041 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
2043 let Predicates = [HasVLX] in {
2044 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
2045 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
2046 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2047 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
2048 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2049 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
2050 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2051 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
2054 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
2055 (v8i1 (COPY_TO_REGCLASS
2056 (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16),
2057 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2059 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
2060 (v8i1 (COPY_TO_REGCLASS
2061 (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16),
2062 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2063 //===----------------------------------------------------------------------===//
2064 // AVX-512 - Aligned and unaligned load and store
2067 multiclass avx512_load<bits<8> opc, string OpcodeStr, PatFrag ld_frag,
2068 RegisterClass KRC, RegisterClass RC,
2069 ValueType vt, ValueType zvt, X86MemOperand memop,
2070 Domain d, bit IsReMaterializable = 1> {
2071 let hasSideEffects = 0 in {
2072 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2073 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
2075 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
2076 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2077 "${dst} {${mask}} {z}, $src}"), [], d>, EVEX, EVEX_KZ;
2079 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
2080 SchedRW = [WriteLoad] in
2081 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins memop:$src),
2082 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2083 [(set RC:$dst, (vt (bitconvert (ld_frag addr:$src))))],
2086 let AddedComplexity = 20 in {
2087 let Constraints = "$src0 = $dst", hasSideEffects = 0 in {
2088 let hasSideEffects = 0 in
2089 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
2090 (ins RC:$src0, KRC:$mask, RC:$src1),
2091 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2092 "${dst} {${mask}}, $src1}"),
2093 [(set RC:$dst, (vt (vselect KRC:$mask,
2097 let mayLoad = 1, SchedRW = [WriteLoad] in
2098 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
2099 (ins RC:$src0, KRC:$mask, memop:$src1),
2100 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2101 "${dst} {${mask}}, $src1}"),
2104 (vt (bitconvert (ld_frag addr:$src1))),
2108 let mayLoad = 1, SchedRW = [WriteLoad] in
2109 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
2110 (ins KRC:$mask, memop:$src),
2111 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2112 "${dst} {${mask}} {z}, $src}"),
2115 (vt (bitconvert (ld_frag addr:$src))),
2116 (vt (bitconvert (zvt immAllZerosV))))))],
2121 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat,
2122 string elty, string elsz, string vsz512,
2123 string vsz256, string vsz128, Domain d,
2124 Predicate prd, bit IsReMaterializable = 1> {
2125 let Predicates = [prd] in
2126 defm Z : avx512_load<opc, OpcodeStr,
2127 !cast<PatFrag>(ld_pat##"v"##vsz512##elty##elsz),
2128 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
2129 !cast<ValueType>("v"##vsz512##elty##elsz), v16i32,
2130 !cast<X86MemOperand>(elty##"512mem"), d,
2131 IsReMaterializable>, EVEX_V512;
2133 let Predicates = [prd, HasVLX] in {
2134 defm Z256 : avx512_load<opc, OpcodeStr,
2135 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
2136 "v"##vsz256##elty##elsz, "v4i64")),
2137 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
2138 !cast<ValueType>("v"##vsz256##elty##elsz), v8i32,
2139 !cast<X86MemOperand>(elty##"256mem"), d,
2140 IsReMaterializable>, EVEX_V256;
2142 defm Z128 : avx512_load<opc, OpcodeStr,
2143 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
2144 "v"##vsz128##elty##elsz, "v2i64")),
2145 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
2146 !cast<ValueType>("v"##vsz128##elty##elsz), v4i32,
2147 !cast<X86MemOperand>(elty##"128mem"), d,
2148 IsReMaterializable>, EVEX_V128;
2153 multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2154 ValueType OpVT, RegisterClass KRC, RegisterClass RC,
2155 X86MemOperand memop, Domain d> {
2156 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2157 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
2158 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>,
2160 let Constraints = "$src1 = $dst" in
2161 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
2162 (ins RC:$src1, KRC:$mask, RC:$src2),
2163 !strconcat(OpcodeStr,
2164 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
2166 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
2167 (ins KRC:$mask, RC:$src),
2168 !strconcat(OpcodeStr,
2169 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
2170 [], d>, EVEX, EVEX_KZ;
2172 let mayStore = 1 in {
2173 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2174 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2175 [(st_frag (OpVT RC:$src), addr:$dst)], d>, EVEX;
2176 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2177 (ins memop:$dst, KRC:$mask, RC:$src),
2178 !strconcat(OpcodeStr,
2179 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
2180 [], d>, EVEX, EVEX_K;
2185 multiclass avx512_store_vl<bits<8> opc, string OpcodeStr, string st_pat,
2186 string st_suff_512, string st_suff_256,
2187 string st_suff_128, string elty, string elsz,
2188 string vsz512, string vsz256, string vsz128,
2189 Domain d, Predicate prd> {
2190 let Predicates = [prd] in
2191 defm Z : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_512),
2192 !cast<ValueType>("v"##vsz512##elty##elsz),
2193 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
2194 !cast<X86MemOperand>(elty##"512mem"), d>, EVEX_V512;
2196 let Predicates = [prd, HasVLX] in {
2197 defm Z256 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_256),
2198 !cast<ValueType>("v"##vsz256##elty##elsz),
2199 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
2200 !cast<X86MemOperand>(elty##"256mem"), d>, EVEX_V256;
2202 defm Z128 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_128),
2203 !cast<ValueType>("v"##vsz128##elty##elsz),
2204 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
2205 !cast<X86MemOperand>(elty##"128mem"), d>, EVEX_V128;
2209 defm VMOVAPS : avx512_load_vl<0x28, "vmovaps", "alignedload", "f", "32",
2210 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2211 avx512_store_vl<0x29, "vmovaps", "alignedstore",
2212 "512", "256", "", "f", "32", "16", "8", "4",
2213 SSEPackedSingle, HasAVX512>,
2214 PS, EVEX_CD8<32, CD8VF>;
2216 defm VMOVAPD : avx512_load_vl<0x28, "vmovapd", "alignedload", "f", "64",
2217 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2218 avx512_store_vl<0x29, "vmovapd", "alignedstore",
2219 "512", "256", "", "f", "64", "8", "4", "2",
2220 SSEPackedDouble, HasAVX512>,
2221 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2223 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", "load", "f", "32",
2224 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2225 avx512_store_vl<0x11, "vmovups", "store", "", "", "", "f", "32",
2226 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2227 PS, EVEX_CD8<32, CD8VF>;
2229 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", "load", "f", "64",
2230 "8", "4", "2", SSEPackedDouble, HasAVX512, 0>,
2231 avx512_store_vl<0x11, "vmovupd", "store", "", "", "", "f", "64",
2232 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2233 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2235 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2236 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2237 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2239 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2240 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2241 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2243 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2244 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2245 (VMOVAPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2247 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2248 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2249 (VMOVAPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2251 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2252 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2253 (VMOVAPDZrm addr:$ptr)>;
2255 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2256 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
2257 (VMOVAPSZrm addr:$ptr)>;
2259 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2261 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2263 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2265 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2268 def: Pat<(int_x86_avx512_mask_store_ps_512 addr:$ptr, (v16f32 VR512:$src),
2270 (VMOVAPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2272 def: Pat<(int_x86_avx512_mask_store_pd_512 addr:$ptr, (v8f64 VR512:$src),
2274 (VMOVAPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2277 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src)),
2278 (VMOVUPSZmrk addr:$ptr,
2279 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2280 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2282 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2283 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmkz
2284 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2286 def: Pat<(masked_store addr:$ptr, VK16WM:$mask, (v16f32 VR512:$src)),
2287 (VMOVUPSZmrk addr:$ptr, VK16WM:$mask, VR512:$src)>;
2289 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8f64 VR512:$src)),
2290 (VMOVUPDZmrk addr:$ptr, VK8WM:$mask, VR512:$src)>;
2292 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask, undef)),
2293 (VMOVUPSZrmkz VK16WM:$mask, addr:$ptr)>;
2295 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask,
2296 (bc_v16f32 (v16i32 immAllZerosV)))),
2297 (VMOVUPSZrmkz VK16WM:$mask, addr:$ptr)>;
2299 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask, (v16f32 VR512:$src0))),
2300 (VMOVUPSZrmk VR512:$src0, VK16WM:$mask, addr:$ptr)>;
2302 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2303 (VMOVUPDZrmkz VK8WM:$mask, addr:$ptr)>;
2305 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask,
2306 (bc_v8f64 (v16i32 immAllZerosV)))),
2307 (VMOVUPDZrmkz VK8WM:$mask, addr:$ptr)>;
2309 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask, (v8f64 VR512:$src0))),
2310 (VMOVUPDZrmk VR512:$src0, VK8WM:$mask, addr:$ptr)>;
2312 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src0))),
2313 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmk
2314 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src0, sub_ymm),
2315 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2317 defm VMOVDQA32 : avx512_load_vl<0x6F, "vmovdqa32", "alignedload", "i", "32",
2318 "16", "8", "4", SSEPackedInt, HasAVX512>,
2319 avx512_store_vl<0x7F, "vmovdqa32", "alignedstore",
2320 "512", "256", "", "i", "32", "16", "8", "4",
2321 SSEPackedInt, HasAVX512>,
2322 PD, EVEX_CD8<32, CD8VF>;
2324 defm VMOVDQA64 : avx512_load_vl<0x6F, "vmovdqa64", "alignedload", "i", "64",
2325 "8", "4", "2", SSEPackedInt, HasAVX512>,
2326 avx512_store_vl<0x7F, "vmovdqa64", "alignedstore",
2327 "512", "256", "", "i", "64", "8", "4", "2",
2328 SSEPackedInt, HasAVX512>,
2329 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2331 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", "load", "i", "8",
2332 "64", "32", "16", SSEPackedInt, HasBWI>,
2333 avx512_store_vl<0x7F, "vmovdqu8", "store", "", "", "",
2334 "i", "8", "64", "32", "16", SSEPackedInt,
2335 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2337 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", "load", "i", "16",
2338 "32", "16", "8", SSEPackedInt, HasBWI>,
2339 avx512_store_vl<0x7F, "vmovdqu16", "store", "", "", "",
2340 "i", "16", "32", "16", "8", SSEPackedInt,
2341 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2343 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", "load", "i", "32",
2344 "16", "8", "4", SSEPackedInt, HasAVX512>,
2345 avx512_store_vl<0x7F, "vmovdqu32", "store", "", "", "",
2346 "i", "32", "16", "8", "4", SSEPackedInt,
2347 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2349 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", "load", "i", "64",
2350 "8", "4", "2", SSEPackedInt, HasAVX512>,
2351 avx512_store_vl<0x7F, "vmovdqu64", "store", "", "", "",
2352 "i", "64", "8", "4", "2", SSEPackedInt,
2353 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2355 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2356 (v16i32 immAllZerosV), GR16:$mask)),
2357 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2359 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2360 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2361 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2363 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2365 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2367 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2369 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2372 let AddedComplexity = 20 in {
2373 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2374 (bc_v8i64 (v16i32 immAllZerosV)))),
2375 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2377 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2378 (v8i64 VR512:$src))),
2379 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2382 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2383 (v16i32 immAllZerosV))),
2384 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2386 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2387 (v16i32 VR512:$src))),
2388 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2391 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, (v16i32 immAllZerosV))),
2392 (VMOVDQU32Zrmkz VK16WM:$mask, addr:$ptr)>;
2394 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, undef)),
2395 (VMOVDQU32Zrmkz VK16WM:$mask, addr:$ptr)>;
2397 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, (v16i32 VR512:$src0))),
2398 (VMOVDQU32Zrmk VR512:$src0, VK16WM:$mask, addr:$ptr)>;
2400 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask,
2401 (bc_v8i64 (v16i32 immAllZerosV)))),
2402 (VMOVDQU64Zrmkz VK8WM:$mask, addr:$ptr)>;
2404 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2405 (VMOVDQU64Zrmkz VK8WM:$mask, addr:$ptr)>;
2407 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask, (v8i64 VR512:$src0))),
2408 (VMOVDQU64Zrmk VR512:$src0, VK8WM:$mask, addr:$ptr)>;
2410 def: Pat<(masked_store addr:$ptr, VK16WM:$mask, (v16i32 VR512:$src)),
2411 (VMOVDQU32Zmrk addr:$ptr, VK16WM:$mask, VR512:$src)>;
2413 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i64 VR512:$src)),
2414 (VMOVDQU64Zmrk addr:$ptr, VK8WM:$mask, VR512:$src)>;
2417 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2418 (VMOVDQU32Z256mrk addr:$ptr, VK8WM:$mask, VR256:$src)>;
2421 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2422 (VMOVDQU32Zmrk addr:$ptr,
2423 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2424 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2426 def: Pat<(v8i32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2427 (v8i32 (EXTRACT_SUBREG (v16i32 (VMOVDQU32Zrmkz
2428 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2431 // Move Int Doubleword to Packed Double Int
2433 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2434 "vmovd\t{$src, $dst|$dst, $src}",
2436 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2438 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2439 "vmovd\t{$src, $dst|$dst, $src}",
2441 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2442 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2443 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2444 "vmovq\t{$src, $dst|$dst, $src}",
2446 (v2i64 (scalar_to_vector GR64:$src)))],
2447 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2448 let isCodeGenOnly = 1 in {
2449 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2450 "vmovq\t{$src, $dst|$dst, $src}",
2451 [(set FR64:$dst, (bitconvert GR64:$src))],
2452 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2453 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2454 "vmovq\t{$src, $dst|$dst, $src}",
2455 [(set GR64:$dst, (bitconvert FR64:$src))],
2456 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2458 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2459 "vmovq\t{$src, $dst|$dst, $src}",
2460 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2461 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2462 EVEX_CD8<64, CD8VT1>;
2464 // Move Int Doubleword to Single Scalar
2466 let isCodeGenOnly = 1 in {
2467 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2468 "vmovd\t{$src, $dst|$dst, $src}",
2469 [(set FR32X:$dst, (bitconvert GR32:$src))],
2470 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2472 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2473 "vmovd\t{$src, $dst|$dst, $src}",
2474 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2475 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2478 // Move doubleword from xmm register to r/m32
2480 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2481 "vmovd\t{$src, $dst|$dst, $src}",
2482 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2483 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2485 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2486 (ins i32mem:$dst, VR128X:$src),
2487 "vmovd\t{$src, $dst|$dst, $src}",
2488 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2489 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2490 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2492 // Move quadword from xmm1 register to r/m64
2494 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2495 "vmovq\t{$src, $dst|$dst, $src}",
2496 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2498 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2499 Requires<[HasAVX512, In64BitMode]>;
2501 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2502 (ins i64mem:$dst, VR128X:$src),
2503 "vmovq\t{$src, $dst|$dst, $src}",
2504 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2505 addr:$dst)], IIC_SSE_MOVDQ>,
2506 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2507 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2509 // Move Scalar Single to Double Int
2511 let isCodeGenOnly = 1 in {
2512 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2514 "vmovd\t{$src, $dst|$dst, $src}",
2515 [(set GR32:$dst, (bitconvert FR32X:$src))],
2516 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2517 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2518 (ins i32mem:$dst, FR32X:$src),
2519 "vmovd\t{$src, $dst|$dst, $src}",
2520 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2521 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2524 // Move Quadword Int to Packed Quadword Int
2526 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2528 "vmovq\t{$src, $dst|$dst, $src}",
2530 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2531 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2533 //===----------------------------------------------------------------------===//
2534 // AVX-512 MOVSS, MOVSD
2535 //===----------------------------------------------------------------------===//
2537 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2538 SDNode OpNode, ValueType vt,
2539 X86MemOperand x86memop, PatFrag mem_pat> {
2540 let hasSideEffects = 0 in {
2541 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2542 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2543 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2544 (scalar_to_vector RC:$src2))))],
2545 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2546 let Constraints = "$src1 = $dst" in
2547 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2548 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2550 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2551 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2552 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2553 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2554 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2556 let mayStore = 1 in {
2557 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2558 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2559 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2561 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2562 !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2563 [], IIC_SSE_MOV_S_MR>,
2564 EVEX, VEX_LIG, EVEX_K;
2566 } //hasSideEffects = 0
2569 let ExeDomain = SSEPackedSingle in
2570 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2571 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2573 let ExeDomain = SSEPackedDouble in
2574 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2575 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2577 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2578 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2579 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2581 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2582 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2583 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2585 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2586 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2587 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2589 // For the disassembler
2590 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2591 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2592 (ins VR128X:$src1, FR32X:$src2),
2593 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2595 XS, EVEX_4V, VEX_LIG;
2596 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2597 (ins VR128X:$src1, FR64X:$src2),
2598 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2600 XD, EVEX_4V, VEX_LIG, VEX_W;
2603 let Predicates = [HasAVX512] in {
2604 let AddedComplexity = 15 in {
2605 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2606 // MOVS{S,D} to the lower bits.
2607 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2608 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2609 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2610 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2611 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2612 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2613 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2614 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2616 // Move low f32 and clear high bits.
2617 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2618 (SUBREG_TO_REG (i32 0),
2619 (VMOVSSZrr (v4f32 (V_SET0)),
2620 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2621 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2622 (SUBREG_TO_REG (i32 0),
2623 (VMOVSSZrr (v4i32 (V_SET0)),
2624 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2627 let AddedComplexity = 20 in {
2628 // MOVSSrm zeros the high parts of the register; represent this
2629 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2630 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2631 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2632 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2633 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2634 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2635 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2637 // MOVSDrm zeros the high parts of the register; represent this
2638 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2639 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2640 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2641 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2642 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2643 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2644 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2645 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2646 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2647 def : Pat<(v2f64 (X86vzload addr:$src)),
2648 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2650 // Represent the same patterns above but in the form they appear for
2652 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2653 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
2654 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
2655 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2656 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2657 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2658 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2659 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2660 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2662 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2663 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2664 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2665 FR32X:$src)), sub_xmm)>;
2666 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2667 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2668 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2669 FR64X:$src)), sub_xmm)>;
2670 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2671 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
2672 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
2674 // Move low f64 and clear high bits.
2675 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2676 (SUBREG_TO_REG (i32 0),
2677 (VMOVSDZrr (v2f64 (V_SET0)),
2678 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2680 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2681 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2682 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2684 // Extract and store.
2685 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2687 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2688 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2690 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2692 // Shuffle with VMOVSS
2693 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2694 (VMOVSSZrr (v4i32 VR128X:$src1),
2695 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2696 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2697 (VMOVSSZrr (v4f32 VR128X:$src1),
2698 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2701 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2702 (SUBREG_TO_REG (i32 0),
2703 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2704 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2706 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2707 (SUBREG_TO_REG (i32 0),
2708 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2709 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2712 // Shuffle with VMOVSD
2713 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2714 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2715 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2716 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2717 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2718 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2719 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2720 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2723 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2724 (SUBREG_TO_REG (i32 0),
2725 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2726 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2728 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2729 (SUBREG_TO_REG (i32 0),
2730 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2731 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2734 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2735 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2736 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2737 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2738 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2739 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2740 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2741 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2744 let AddedComplexity = 15 in
2745 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2747 "vmovq\t{$src, $dst|$dst, $src}",
2748 [(set VR128X:$dst, (v2i64 (X86vzmovl
2749 (v2i64 VR128X:$src))))],
2750 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2752 let AddedComplexity = 20 in
2753 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2755 "vmovq\t{$src, $dst|$dst, $src}",
2756 [(set VR128X:$dst, (v2i64 (X86vzmovl
2757 (loadv2i64 addr:$src))))],
2758 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2759 EVEX_CD8<8, CD8VT8>;
2761 let Predicates = [HasAVX512] in {
2762 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2763 let AddedComplexity = 20 in {
2764 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2765 (VMOVDI2PDIZrm addr:$src)>;
2766 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2767 (VMOV64toPQIZrr GR64:$src)>;
2768 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2769 (VMOVDI2PDIZrr GR32:$src)>;
2771 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2772 (VMOVDI2PDIZrm addr:$src)>;
2773 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2774 (VMOVDI2PDIZrm addr:$src)>;
2775 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2776 (VMOVZPQILo2PQIZrm addr:$src)>;
2777 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2778 (VMOVZPQILo2PQIZrr VR128X:$src)>;
2779 def : Pat<(v2i64 (X86vzload addr:$src)),
2780 (VMOVZPQILo2PQIZrm addr:$src)>;
2783 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2784 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2785 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2786 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2787 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2788 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2789 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2792 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2793 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2795 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2796 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2798 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2799 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2801 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2802 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2804 //===----------------------------------------------------------------------===//
2805 // AVX-512 - Non-temporals
2806 //===----------------------------------------------------------------------===//
2807 let SchedRW = [WriteLoad] in {
2808 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2809 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2810 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2811 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2812 EVEX_CD8<64, CD8VF>;
2814 let Predicates = [HasAVX512, HasVLX] in {
2815 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2817 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2818 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2819 EVEX_CD8<64, CD8VF>;
2821 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2823 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2824 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2825 EVEX_CD8<64, CD8VF>;
2829 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2830 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2831 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2832 let SchedRW = [WriteStore], mayStore = 1,
2833 AddedComplexity = 400 in
2834 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2835 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2836 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2839 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2840 string elty, string elsz, string vsz512,
2841 string vsz256, string vsz128, Domain d,
2842 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2843 let Predicates = [prd] in
2844 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2845 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2846 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2849 let Predicates = [prd, HasVLX] in {
2850 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2851 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2852 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2855 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2856 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2857 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2862 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2863 "i", "64", "8", "4", "2", SSEPackedInt,
2864 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2866 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2867 "f", "64", "8", "4", "2", SSEPackedDouble,
2868 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2870 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2871 "f", "32", "16", "8", "4", SSEPackedSingle,
2872 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2874 //===----------------------------------------------------------------------===//
2875 // AVX-512 - Integer arithmetic
2877 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2878 X86VectorVTInfo _, OpndItins itins,
2879 bit IsCommutable = 0> {
2880 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
2881 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
2882 "$src2, $src1", "$src1, $src2",
2883 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
2884 "", itins.rr, IsCommutable>,
2885 AVX512BIBase, EVEX_4V;
2888 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2889 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
2890 "$src2, $src1", "$src1, $src2",
2891 (_.VT (OpNode _.RC:$src1,
2892 (bitconvert (_.LdFrag addr:$src2)))),
2894 AVX512BIBase, EVEX_4V;
2897 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
2898 X86VectorVTInfo _, OpndItins itins,
2899 bit IsCommutable = 0> :
2900 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
2902 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2903 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
2904 "${src2}"##_.BroadcastStr##", $src1",
2905 "$src1, ${src2}"##_.BroadcastStr,
2906 (_.VT (OpNode _.RC:$src1,
2908 (_.ScalarLdFrag addr:$src2)))),
2910 AVX512BIBase, EVEX_4V, EVEX_B;
2913 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2914 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2915 Predicate prd, bit IsCommutable = 0> {
2916 let Predicates = [prd] in
2917 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2918 IsCommutable>, EVEX_V512;
2920 let Predicates = [prd, HasVLX] in {
2921 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2922 IsCommutable>, EVEX_V256;
2923 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2924 IsCommutable>, EVEX_V128;
2928 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2929 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2930 Predicate prd, bit IsCommutable = 0> {
2931 let Predicates = [prd] in
2932 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2933 IsCommutable>, EVEX_V512;
2935 let Predicates = [prd, HasVLX] in {
2936 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2937 IsCommutable>, EVEX_V256;
2938 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2939 IsCommutable>, EVEX_V128;
2943 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
2944 OpndItins itins, Predicate prd,
2945 bit IsCommutable = 0> {
2946 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
2947 itins, prd, IsCommutable>,
2948 VEX_W, EVEX_CD8<64, CD8VF>;
2951 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
2952 OpndItins itins, Predicate prd,
2953 bit IsCommutable = 0> {
2954 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
2955 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
2958 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
2959 OpndItins itins, Predicate prd,
2960 bit IsCommutable = 0> {
2961 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
2962 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
2965 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
2966 OpndItins itins, Predicate prd,
2967 bit IsCommutable = 0> {
2968 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
2969 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
2972 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
2973 SDNode OpNode, OpndItins itins, Predicate prd,
2974 bit IsCommutable = 0> {
2975 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr, OpNode, itins, prd,
2978 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr, OpNode, itins, prd,
2982 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
2983 SDNode OpNode, OpndItins itins, Predicate prd,
2984 bit IsCommutable = 0> {
2985 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr, OpNode, itins, prd,
2988 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr, OpNode, itins, prd,
2992 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
2993 bits<8> opc_d, bits<8> opc_q,
2994 string OpcodeStr, SDNode OpNode,
2995 OpndItins itins, bit IsCommutable = 0> {
2996 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
2997 itins, HasAVX512, IsCommutable>,
2998 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
2999 itins, HasBWI, IsCommutable>;
3002 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
3003 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
3004 PatFrag memop_frag, X86MemOperand x86memop,
3005 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
3006 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
3007 let isCommutable = IsCommutable in
3009 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3010 (ins RC:$src1, RC:$src2),
3011 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3013 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3014 (ins KRC:$mask, RC:$src1, RC:$src2),
3015 !strconcat(OpcodeStr,
3016 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
3017 [], itins.rr>, EVEX_4V, EVEX_K;
3018 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3019 (ins KRC:$mask, RC:$src1, RC:$src2),
3020 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}} {z}" ,
3021 "|$dst {${mask}} {z}, $src1, $src2}"),
3022 [], itins.rr>, EVEX_4V, EVEX_KZ;
3024 let mayLoad = 1 in {
3025 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3026 (ins RC:$src1, x86memop:$src2),
3027 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3029 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3030 (ins KRC:$mask, RC:$src1, x86memop:$src2),
3031 !strconcat(OpcodeStr,
3032 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
3033 [], itins.rm>, EVEX_4V, EVEX_K;
3034 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3035 (ins KRC:$mask, RC:$src1, x86memop:$src2),
3036 !strconcat(OpcodeStr,
3037 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
3038 [], itins.rm>, EVEX_4V, EVEX_KZ;
3039 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3040 (ins RC:$src1, x86scalar_mop:$src2),
3041 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
3042 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
3043 [], itins.rm>, EVEX_4V, EVEX_B;
3044 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3045 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
3046 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
3047 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
3049 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
3050 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3051 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
3052 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
3053 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
3055 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
3059 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
3060 SSE_INTALU_ITINS_P, 1>;
3061 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
3062 SSE_INTALU_ITINS_P, 0>;
3063 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmull", mul,
3064 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3065 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmull", mul,
3066 SSE_INTALU_ITINS_P, HasBWI, 1>;
3067 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmull", mul,
3068 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
3070 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
3071 loadv8i64, i512mem, loadi64, i64mem, "{1to8}",
3072 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
3073 EVEX_CD8<64, CD8VF>, VEX_W;
3075 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
3076 loadv8i64, i512mem, loadi64, i64mem, "{1to8}",
3077 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
3079 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
3080 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
3082 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
3083 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3084 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
3085 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
3086 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3087 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
3089 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxs", X86smax,
3090 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3091 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxs", X86smax,
3092 SSE_INTALU_ITINS_P, HasBWI, 1>;
3093 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", X86smax,
3094 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3096 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxu", X86umax,
3097 SSE_INTALU_ITINS_P, HasBWI, 1>;
3098 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxu", X86umax,
3099 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3100 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", X86umax,
3101 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3103 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpmins", X86smin,
3104 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3105 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpmins", X86smin,
3106 SSE_INTALU_ITINS_P, HasBWI, 1>;
3107 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", X86smin,
3108 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3110 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminu", X86umin,
3111 SSE_INTALU_ITINS_P, HasBWI, 1>;
3112 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminu", X86umin,
3113 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3114 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", X86umin,
3115 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3117 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
3118 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3119 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
3120 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
3121 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3122 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
3123 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
3124 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3125 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
3126 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
3127 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3128 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
3129 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
3130 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3131 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
3132 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
3133 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3134 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
3135 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
3136 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3137 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
3138 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
3139 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3140 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
3141 //===----------------------------------------------------------------------===//
3142 // AVX-512 - Unpack Instructions
3143 //===----------------------------------------------------------------------===//
3145 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
3146 PatFrag mem_frag, RegisterClass RC,
3147 X86MemOperand x86memop, string asm,
3149 def rr : AVX512PI<opc, MRMSrcReg,
3150 (outs RC:$dst), (ins RC:$src1, RC:$src2),
3152 (vt (OpNode RC:$src1, RC:$src2)))],
3154 def rm : AVX512PI<opc, MRMSrcMem,
3155 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3157 (vt (OpNode RC:$src1,
3158 (bitconvert (mem_frag addr:$src2)))))],
3162 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, loadv8f64,
3163 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3164 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3165 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, loadv8f64,
3166 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3167 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3168 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, loadv8f64,
3169 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3170 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3171 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, loadv8f64,
3172 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3173 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3175 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
3176 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
3177 X86MemOperand x86memop> {
3178 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3179 (ins RC:$src1, RC:$src2),
3180 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3181 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
3182 IIC_SSE_UNPCK>, EVEX_4V;
3183 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3184 (ins RC:$src1, x86memop:$src2),
3185 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3186 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
3187 (bitconvert (memop_frag addr:$src2)))))],
3188 IIC_SSE_UNPCK>, EVEX_4V;
3190 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
3191 VR512, loadv16i32, i512mem>, EVEX_V512,
3192 EVEX_CD8<32, CD8VF>;
3193 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
3194 VR512, loadv8i64, i512mem>, EVEX_V512,
3195 VEX_W, EVEX_CD8<64, CD8VF>;
3196 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
3197 VR512, loadv16i32, i512mem>, EVEX_V512,
3198 EVEX_CD8<32, CD8VF>;
3199 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
3200 VR512, loadv8i64, i512mem>, EVEX_V512,
3201 VEX_W, EVEX_CD8<64, CD8VF>;
3202 //===----------------------------------------------------------------------===//
3206 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
3207 SDNode OpNode, PatFrag mem_frag,
3208 X86MemOperand x86memop, ValueType OpVT> {
3209 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
3210 (ins RC:$src1, u8imm:$src2),
3211 !strconcat(OpcodeStr,
3212 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3214 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
3216 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
3217 (ins x86memop:$src1, u8imm:$src2),
3218 !strconcat(OpcodeStr,
3219 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3221 (OpVT (OpNode (mem_frag addr:$src1),
3222 (i8 imm:$src2))))]>, EVEX;
3225 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, loadv16i32,
3226 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
3228 //===----------------------------------------------------------------------===//
3229 // AVX-512 Logical Instructions
3230 //===----------------------------------------------------------------------===//
3232 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
3233 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3234 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
3235 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3236 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
3237 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3238 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
3239 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3241 //===----------------------------------------------------------------------===//
3242 // AVX-512 FP arithmetic
3243 //===----------------------------------------------------------------------===//
3245 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3247 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
3248 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
3249 EVEX_CD8<32, CD8VT1>;
3250 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
3251 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
3252 EVEX_CD8<64, CD8VT1>;
3255 let isCommutable = 1 in {
3256 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
3257 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
3258 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
3259 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
3261 let isCommutable = 0 in {
3262 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
3263 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
3266 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3267 X86VectorVTInfo _, bit IsCommutable> {
3268 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3269 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3270 "$src2, $src1", "$src1, $src2",
3271 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
3272 let mayLoad = 1 in {
3273 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3274 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3275 "$src2, $src1", "$src1, $src2",
3276 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3277 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3278 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3279 "${src2}"##_.BroadcastStr##", $src1",
3280 "$src1, ${src2}"##_.BroadcastStr,
3281 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3282 (_.ScalarLdFrag addr:$src2))))>,
3287 multiclass avx512_fp_round_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3288 X86VectorVTInfo _, bit IsCommutable> {
3289 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3290 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr##_.Suffix,
3291 "$rc, $src2, $src1", "$src1, $src2, $rc",
3292 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 imm:$rc)))>,
3293 EVEX_4V, EVEX_B, EVEX_RC;
3296 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3297 bit IsCommutable = 0> {
3298 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3299 IsCommutable>, EVEX_V512, PS,
3300 EVEX_CD8<32, CD8VF>;
3301 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3302 IsCommutable>, EVEX_V512, PD, VEX_W,
3303 EVEX_CD8<64, CD8VF>;
3305 // Define only if AVX512VL feature is present.
3306 let Predicates = [HasVLX] in {
3307 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3308 IsCommutable>, EVEX_V128, PS,
3309 EVEX_CD8<32, CD8VF>;
3310 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3311 IsCommutable>, EVEX_V256, PS,
3312 EVEX_CD8<32, CD8VF>;
3313 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3314 IsCommutable>, EVEX_V128, PD, VEX_W,
3315 EVEX_CD8<64, CD8VF>;
3316 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3317 IsCommutable>, EVEX_V256, PD, VEX_W,
3318 EVEX_CD8<64, CD8VF>;
3322 multiclass avx512_fp_binop_p_round<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3323 defm PSZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info, 0>,
3324 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3325 defm PDZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info, 0>,
3326 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3329 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>,
3330 avx512_fp_binop_p_round<0x58, "vadd", X86faddRnd>;
3331 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>,
3332 avx512_fp_binop_p_round<0x59, "vmul", X86fmulRnd>;
3333 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>,
3334 avx512_fp_binop_p_round<0x5C, "vsub", X86fsubRnd>;
3335 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>,
3336 avx512_fp_binop_p_round<0x5E, "vdiv", X86fdivRnd>;
3337 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>;
3338 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>;
3340 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
3341 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3342 (i16 -1), FROUND_CURRENT)),
3343 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
3345 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
3346 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3347 (i8 -1), FROUND_CURRENT)),
3348 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
3350 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
3351 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3352 (i16 -1), FROUND_CURRENT)),
3353 (VMINPSZrr VR512:$src1, VR512:$src2)>;
3355 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
3356 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3357 (i8 -1), FROUND_CURRENT)),
3358 (VMINPDZrr VR512:$src1, VR512:$src2)>;
3359 //===----------------------------------------------------------------------===//
3360 // AVX-512 VPTESTM instructions
3361 //===----------------------------------------------------------------------===//
3363 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3364 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
3365 SDNode OpNode, ValueType vt> {
3366 def rr : AVX512PI<opc, MRMSrcReg,
3367 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
3368 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3369 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
3370 SSEPackedInt>, EVEX_4V;
3371 def rm : AVX512PI<opc, MRMSrcMem,
3372 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
3373 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3374 [(set KRC:$dst, (OpNode (vt RC:$src1),
3375 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
3378 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
3379 loadv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
3380 EVEX_CD8<32, CD8VF>;
3381 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
3382 loadv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
3383 EVEX_CD8<64, CD8VF>;
3385 let Predicates = [HasCDI] in {
3386 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
3387 loadv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
3388 EVEX_CD8<32, CD8VF>;
3389 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
3390 loadv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
3391 EVEX_CD8<64, CD8VF>;
3394 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3395 (v16i32 VR512:$src2), (i16 -1))),
3396 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3398 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3399 (v8i64 VR512:$src2), (i8 -1))),
3400 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3402 //===----------------------------------------------------------------------===//
3403 // AVX-512 Shift instructions
3404 //===----------------------------------------------------------------------===//
3405 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3406 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3407 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
3408 (ins _.RC:$src1, u8imm:$src2), OpcodeStr,
3409 "$src2, $src1", "$src1, $src2",
3410 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
3411 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIi8Base, EVEX_4V;
3412 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3413 (ins _.MemOp:$src1, u8imm:$src2), OpcodeStr,
3414 "$src2, $src1", "$src1, $src2",
3415 (_.VT (OpNode (_.LdFrag addr:$src1), (i8 imm:$src2))),
3416 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIi8Base, EVEX_4V;
3419 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3420 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3421 // src2 is always 128-bit
3422 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3423 (ins _.RC:$src1, VR128X:$src2), OpcodeStr,
3424 "$src2, $src1", "$src1, $src2",
3425 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))),
3426 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V;
3427 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3428 (ins _.RC:$src1, i128mem:$src2), OpcodeStr,
3429 "$src2, $src1", "$src1, $src2",
3430 (_.VT (OpNode _.RC:$src1, (bc_frag (loadv2i64 addr:$src2)))),
3431 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase, EVEX_4V;
3434 multiclass avx512_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3435 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3436 defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag, _>, EVEX_V512;
3439 multiclass avx512_shift_types<bits<8> opcd, bits<8> opcq, string OpcodeStr,
3441 defm D : avx512_shift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,
3442 v16i32_info>, EVEX_CD8<32, CD8VQ>;
3443 defm Q : avx512_shift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,
3444 v8i64_info>, EVEX_CD8<64, CD8VQ>, VEX_W;
3447 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
3449 EVEX_V512, EVEX_CD8<32, CD8VF>;
3450 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
3451 v8i64_info>, EVEX_V512,
3452 EVEX_CD8<64, CD8VF>, VEX_W;
3454 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
3455 v16i32_info>, EVEX_V512,
3456 EVEX_CD8<32, CD8VF>;
3457 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
3458 v8i64_info>, EVEX_V512,
3459 EVEX_CD8<64, CD8VF>, VEX_W;
3461 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
3463 EVEX_V512, EVEX_CD8<32, CD8VF>;
3464 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
3465 v8i64_info>, EVEX_V512,
3466 EVEX_CD8<64, CD8VF>, VEX_W;
3468 defm VPSLL : avx512_shift_types<0xF2, 0xF3, "vpsll", X86vshl>;
3469 defm VPSRA : avx512_shift_types<0xE2, 0xE2, "vpsra", X86vsra>;
3470 defm VPSRL : avx512_shift_types<0xD2, 0xD3, "vpsrl", X86vsrl>;
3472 //===-------------------------------------------------------------------===//
3473 // Variable Bit Shifts
3474 //===-------------------------------------------------------------------===//
3475 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3476 X86VectorVTInfo _> {
3477 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3478 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3479 "$src2, $src1", "$src1, $src2",
3480 (_.VT (OpNode _.RC:$src1, (_.VT _.RC:$src2))),
3481 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX5128IBase, EVEX_4V;
3482 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3483 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3484 "$src2, $src1", "$src1, $src2",
3485 (_.VT (OpNode _.RC:$src1, (_.LdFrag addr:$src2))),
3486 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_4V;
3489 multiclass avx512_var_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3490 AVX512VLVectorVTInfo _> {
3491 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3494 multiclass avx512_var_shift_types<bits<8> opc, string OpcodeStr,
3496 defm D : avx512_var_shift_sizes<opc, OpcodeStr#"d", OpNode,
3497 avx512vl_i32_info>, EVEX_CD8<32, CD8VQ>;
3498 defm Q : avx512_var_shift_sizes<opc, OpcodeStr#"q", OpNode,
3499 avx512vl_i64_info>, EVEX_CD8<64, CD8VQ>, VEX_W;
3502 defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl>;
3503 defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra>;
3504 defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl>;
3506 //===----------------------------------------------------------------------===//
3507 // AVX-512 - MOVDDUP
3508 //===----------------------------------------------------------------------===//
3510 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3511 X86MemOperand x86memop, PatFrag memop_frag> {
3512 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3513 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3514 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3515 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3516 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3518 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3521 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, loadv8f64>,
3522 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3523 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3524 (VMOVDDUPZrm addr:$src)>;
3526 //===---------------------------------------------------------------------===//
3527 // Replicate Single FP - MOVSHDUP and MOVSLDUP
3528 //===---------------------------------------------------------------------===//
3529 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3530 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3531 X86MemOperand x86memop> {
3532 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3533 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3534 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3536 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3537 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3538 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3541 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3542 v16f32, VR512, loadv16f32, f512mem>, EVEX_V512,
3543 EVEX_CD8<32, CD8VF>;
3544 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3545 v16f32, VR512, loadv16f32, f512mem>, EVEX_V512,
3546 EVEX_CD8<32, CD8VF>;
3548 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3549 def : Pat<(v16i32 (X86Movshdup (loadv16i32 addr:$src))),
3550 (VMOVSHDUPZrm addr:$src)>;
3551 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3552 def : Pat<(v16i32 (X86Movsldup (loadv16i32 addr:$src))),
3553 (VMOVSLDUPZrm addr:$src)>;
3555 //===----------------------------------------------------------------------===//
3556 // Move Low to High and High to Low packed FP Instructions
3557 //===----------------------------------------------------------------------===//
3558 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3559 (ins VR128X:$src1, VR128X:$src2),
3560 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3561 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3562 IIC_SSE_MOV_LH>, EVEX_4V;
3563 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3564 (ins VR128X:$src1, VR128X:$src2),
3565 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3566 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3567 IIC_SSE_MOV_LH>, EVEX_4V;
3569 let Predicates = [HasAVX512] in {
3571 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3572 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3573 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3574 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
3577 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3578 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3581 //===----------------------------------------------------------------------===//
3582 // FMA - Fused Multiply Operations
3585 let Constraints = "$src1 = $dst" in {
3586 // Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
3587 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
3588 SDPatternOperator OpNode = null_frag> {
3589 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3590 (ins _.RC:$src2, _.RC:$src3),
3591 OpcodeStr, "$src3, $src2", "$src2, $src3",
3592 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
3596 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
3597 (ins _.RC:$src2, _.MemOp:$src3),
3598 OpcodeStr, "$src3, $src2", "$src2, $src3",
3599 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (_.LdFrag addr:$src3)))>,
3602 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
3603 (ins _.RC:$src2, _.ScalarMemOp:$src3),
3604 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"), !strconcat("$src2, ${src3}", _.BroadcastStr ),
3605 (OpNode _.RC:$src1, _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))>,
3606 AVX512FMA3Base, EVEX_B;
3608 } // Constraints = "$src1 = $dst"
3610 let Constraints = "$src1 = $dst" in {
3611 // Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
3612 multiclass avx512_fma3_round_rrb<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
3613 SDPatternOperator OpNode> {
3614 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3615 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
3616 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
3617 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
3618 AVX512FMA3Base, EVEX_B, EVEX_RC;
3620 } // Constraints = "$src1 = $dst"
3622 multiclass avx512_fma3_round_forms<bits<8> opc213, string OpcodeStr,
3623 X86VectorVTInfo VTI, SDPatternOperator OpNode> {
3624 defm v213r : avx512_fma3_round_rrb<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
3625 VTI, OpNode>, EVEX_CD8<VTI.EltSize, CD8VF>;
3628 multiclass avx512_fma3p_forms<bits<8> opc213, bits<8> opc231,
3629 string OpcodeStr, X86VectorVTInfo VTI,
3630 SDPatternOperator OpNode> {
3631 defm v213r : avx512_fma3p_rm<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
3632 VTI, OpNode>, EVEX_CD8<VTI.EltSize, CD8VF>;
3634 defm v231r : avx512_fma3p_rm<opc231, !strconcat(OpcodeStr, "231", VTI.Suffix),
3635 VTI>, EVEX_CD8<VTI.EltSize, CD8VF>;
3638 multiclass avx512_fma3p<bits<8> opc213, bits<8> opc231,
3640 SDPatternOperator OpNode,
3641 SDPatternOperator OpNodeRnd> {
3642 let ExeDomain = SSEPackedSingle in {
3643 defm NAME##PSZ : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3644 v16f32_info, OpNode>,
3645 avx512_fma3_round_forms<opc213, OpcodeStr,
3646 v16f32_info, OpNodeRnd>, EVEX_V512;
3647 defm NAME##PSZ256 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3648 v8f32x_info, OpNode>, EVEX_V256;
3649 defm NAME##PSZ128 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3650 v4f32x_info, OpNode>, EVEX_V128;
3652 let ExeDomain = SSEPackedDouble in {
3653 defm NAME##PDZ : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3654 v8f64_info, OpNode>,
3655 avx512_fma3_round_forms<opc213, OpcodeStr,
3656 v8f64_info, OpNodeRnd>, EVEX_V512, VEX_W;
3657 defm NAME##PDZ256 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3658 v4f64x_info, OpNode>, EVEX_V256, VEX_W;
3659 defm NAME##PDZ128 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3660 v2f64x_info, OpNode>, EVEX_V128, VEX_W;
3664 defm VFMADD : avx512_fma3p<0xA8, 0xB8, "vfmadd", X86Fmadd, X86FmaddRnd>;
3665 defm VFMSUB : avx512_fma3p<0xAA, 0xBA, "vfmsub", X86Fmsub, X86FmsubRnd>;
3666 defm VFMADDSUB : avx512_fma3p<0xA6, 0xB6, "vfmaddsub", X86Fmaddsub, X86FmaddsubRnd>;
3667 defm VFMSUBADD : avx512_fma3p<0xA7, 0xB7, "vfmsubadd", X86Fmsubadd, X86FmsubaddRnd>;
3668 defm VFNMADD : avx512_fma3p<0xAC, 0xBC, "vfnmadd", X86Fnmadd, X86FnmaddRnd>;
3669 defm VFNMSUB : avx512_fma3p<0xAE, 0xBE, "vfnmsub", X86Fnmsub, X86FnmsubRnd>;
3671 let Constraints = "$src1 = $dst" in {
3672 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
3673 X86VectorVTInfo _> {
3675 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3676 (ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2),
3677 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
3678 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.LdFrag addr:$src2),
3680 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3681 (ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2),
3682 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr,
3683 ", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"),
3685 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3686 (_.ScalarLdFrag addr:$src2))),
3687 _.RC:$src3))]>, EVEX_B;
3689 } // Constraints = "$src1 = $dst"
3692 multiclass avx512_fma3p_m132_f<bits<8> opc,
3696 let ExeDomain = SSEPackedSingle in {
3697 defm NAME##PSZ : avx512_fma3p_m132<opc, OpcodeStr##ps,
3698 OpNode,v16f32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3699 defm NAME##PSZ256 : avx512_fma3p_m132<opc, OpcodeStr##ps,
3700 OpNode, v8f32x_info>, EVEX_V256, EVEX_CD8<32, CD8VF>;
3701 defm NAME##PSZ128 : avx512_fma3p_m132<opc, OpcodeStr##ps,
3702 OpNode, v4f32x_info>, EVEX_V128, EVEX_CD8<32, CD8VF>;
3704 let ExeDomain = SSEPackedDouble in {
3705 defm NAME##PDZ : avx512_fma3p_m132<opc, OpcodeStr##pd,
3706 OpNode, v8f64_info>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VF>;
3707 defm NAME##PDZ256 : avx512_fma3p_m132<opc, OpcodeStr##pd,
3708 OpNode, v4f64x_info>, EVEX_V256, VEX_W, EVEX_CD8<32, CD8VF>;
3709 defm NAME##PDZ128 : avx512_fma3p_m132<opc, OpcodeStr##pd,
3710 OpNode, v2f64x_info>, EVEX_V128, VEX_W, EVEX_CD8<32, CD8VF>;
3714 defm VFMADD132 : avx512_fma3p_m132_f<0x98, "vfmadd132", X86Fmadd>;
3715 defm VFMSUB132 : avx512_fma3p_m132_f<0x9A, "vfmsub132", X86Fmsub>;
3716 defm VFMADDSUB132 : avx512_fma3p_m132_f<0x96, "vfmaddsub132", X86Fmaddsub>;
3717 defm VFMSUBADD132 : avx512_fma3p_m132_f<0x97, "vfmsubadd132", X86Fmsubadd>;
3718 defm VFNMADD132 : avx512_fma3p_m132_f<0x9C, "vfnmadd132", X86Fnmadd>;
3719 defm VFNMSUB132 : avx512_fma3p_m132_f<0x9E, "vfnmsub132", X86Fnmsub>;
3723 let Constraints = "$src1 = $dst" in {
3724 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3725 RegisterClass RC, ValueType OpVT,
3726 X86MemOperand x86memop, Operand memop,
3728 let isCommutable = 1 in
3729 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
3730 (ins RC:$src1, RC:$src2, RC:$src3),
3731 !strconcat(OpcodeStr,
3732 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3734 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
3736 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3737 (ins RC:$src1, RC:$src2, f128mem:$src3),
3738 !strconcat(OpcodeStr,
3739 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3741 (OpVT (OpNode RC:$src2, RC:$src1,
3742 (mem_frag addr:$src3))))]>;
3745 } // Constraints = "$src1 = $dst"
3747 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
3748 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3749 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
3750 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3751 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
3752 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3753 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
3754 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3755 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
3756 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3757 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
3758 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3759 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
3760 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3761 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
3762 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3764 //===----------------------------------------------------------------------===//
3765 // AVX-512 Scalar convert from sign integer to float/double
3766 //===----------------------------------------------------------------------===//
3768 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3769 X86MemOperand x86memop, string asm> {
3770 let hasSideEffects = 0 in {
3771 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
3772 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3775 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
3776 (ins DstRC:$src1, x86memop:$src),
3777 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3779 } // hasSideEffects = 0
3781 let Predicates = [HasAVX512] in {
3782 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
3783 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3784 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
3785 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3786 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
3787 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3788 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
3789 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3791 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
3792 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3793 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
3794 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3795 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
3796 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3797 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
3798 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3800 def : Pat<(f32 (sint_to_fp GR32:$src)),
3801 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3802 def : Pat<(f32 (sint_to_fp GR64:$src)),
3803 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3804 def : Pat<(f64 (sint_to_fp GR32:$src)),
3805 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3806 def : Pat<(f64 (sint_to_fp GR64:$src)),
3807 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3809 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
3810 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3811 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
3812 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3813 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
3814 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3815 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
3816 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3818 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
3819 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3820 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
3821 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3822 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
3823 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3824 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
3825 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3827 def : Pat<(f32 (uint_to_fp GR32:$src)),
3828 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3829 def : Pat<(f32 (uint_to_fp GR64:$src)),
3830 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3831 def : Pat<(f64 (uint_to_fp GR32:$src)),
3832 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3833 def : Pat<(f64 (uint_to_fp GR64:$src)),
3834 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3837 //===----------------------------------------------------------------------===//
3838 // AVX-512 Scalar convert from float/double to integer
3839 //===----------------------------------------------------------------------===//
3840 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3841 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
3843 let hasSideEffects = 0 in {
3844 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3845 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3846 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
3847 Requires<[HasAVX512]>;
3849 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
3850 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
3851 Requires<[HasAVX512]>;
3852 } // hasSideEffects = 0
3854 let Predicates = [HasAVX512] in {
3855 // Convert float/double to signed/unsigned int 32/64
3856 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
3857 ssmem, sse_load_f32, "cvtss2si">,
3858 XS, EVEX_CD8<32, CD8VT1>;
3859 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
3860 ssmem, sse_load_f32, "cvtss2si">,
3861 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3862 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
3863 ssmem, sse_load_f32, "cvtss2usi">,
3864 XS, EVEX_CD8<32, CD8VT1>;
3865 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3866 int_x86_avx512_cvtss2usi64, ssmem,
3867 sse_load_f32, "cvtss2usi">, XS, VEX_W,
3868 EVEX_CD8<32, CD8VT1>;
3869 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
3870 sdmem, sse_load_f64, "cvtsd2si">,
3871 XD, EVEX_CD8<64, CD8VT1>;
3872 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
3873 sdmem, sse_load_f64, "cvtsd2si">,
3874 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3875 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
3876 sdmem, sse_load_f64, "cvtsd2usi">,
3877 XD, EVEX_CD8<64, CD8VT1>;
3878 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3879 int_x86_avx512_cvtsd2usi64, sdmem,
3880 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
3881 EVEX_CD8<64, CD8VT1>;
3883 let isCodeGenOnly = 1 in {
3884 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3885 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3886 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3887 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3888 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3889 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3890 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3891 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3892 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3893 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3894 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3895 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3897 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3898 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3899 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3900 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3901 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3902 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3903 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3904 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3905 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3906 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3907 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3908 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3909 } // isCodeGenOnly = 1
3911 // Convert float/double to signed/unsigned int 32/64 with truncation
3912 let isCodeGenOnly = 1 in {
3913 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3914 ssmem, sse_load_f32, "cvttss2si">,
3915 XS, EVEX_CD8<32, CD8VT1>;
3916 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3917 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3918 "cvttss2si">, XS, VEX_W,
3919 EVEX_CD8<32, CD8VT1>;
3920 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3921 sdmem, sse_load_f64, "cvttsd2si">, XD,
3922 EVEX_CD8<64, CD8VT1>;
3923 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3924 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3925 "cvttsd2si">, XD, VEX_W,
3926 EVEX_CD8<64, CD8VT1>;
3927 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3928 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3929 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3930 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3931 int_x86_avx512_cvttss2usi64, ssmem,
3932 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3933 EVEX_CD8<32, CD8VT1>;
3934 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3935 int_x86_avx512_cvttsd2usi,
3936 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3937 EVEX_CD8<64, CD8VT1>;
3938 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3939 int_x86_avx512_cvttsd2usi64, sdmem,
3940 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3941 EVEX_CD8<64, CD8VT1>;
3942 } // isCodeGenOnly = 1
3944 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3945 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3947 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3948 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3949 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3950 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3951 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3952 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3955 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
3956 loadf32, "cvttss2si">, XS,
3957 EVEX_CD8<32, CD8VT1>;
3958 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
3959 loadf32, "cvttss2usi">, XS,
3960 EVEX_CD8<32, CD8VT1>;
3961 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
3962 loadf32, "cvttss2si">, XS, VEX_W,
3963 EVEX_CD8<32, CD8VT1>;
3964 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
3965 loadf32, "cvttss2usi">, XS, VEX_W,
3966 EVEX_CD8<32, CD8VT1>;
3967 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
3968 loadf64, "cvttsd2si">, XD,
3969 EVEX_CD8<64, CD8VT1>;
3970 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
3971 loadf64, "cvttsd2usi">, XD,
3972 EVEX_CD8<64, CD8VT1>;
3973 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
3974 loadf64, "cvttsd2si">, XD, VEX_W,
3975 EVEX_CD8<64, CD8VT1>;
3976 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
3977 loadf64, "cvttsd2usi">, XD, VEX_W,
3978 EVEX_CD8<64, CD8VT1>;
3980 //===----------------------------------------------------------------------===//
3981 // AVX-512 Convert form float to double and back
3982 //===----------------------------------------------------------------------===//
3983 let hasSideEffects = 0 in {
3984 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3985 (ins FR32X:$src1, FR32X:$src2),
3986 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3987 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3989 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3990 (ins FR32X:$src1, f32mem:$src2),
3991 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3992 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3993 EVEX_CD8<32, CD8VT1>;
3995 // Convert scalar double to scalar single
3996 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3997 (ins FR64X:$src1, FR64X:$src2),
3998 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3999 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
4001 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
4002 (ins FR64X:$src1, f64mem:$src2),
4003 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4004 []>, EVEX_4V, VEX_LIG, VEX_W,
4005 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
4008 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
4009 Requires<[HasAVX512]>;
4010 def : Pat<(fextend (loadf32 addr:$src)),
4011 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
4013 def : Pat<(extloadf32 addr:$src),
4014 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4015 Requires<[HasAVX512, OptForSize]>;
4017 def : Pat<(extloadf32 addr:$src),
4018 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
4019 Requires<[HasAVX512, OptForSpeed]>;
4021 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
4022 Requires<[HasAVX512]>;
4024 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
4025 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
4026 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
4028 let hasSideEffects = 0 in {
4029 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4030 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4032 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
4033 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4034 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
4035 [], d>, EVEX, EVEX_B, EVEX_RC;
4037 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4038 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4040 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
4041 } // hasSideEffects = 0
4044 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
4045 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
4046 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
4048 let hasSideEffects = 0 in {
4049 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4050 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4052 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
4054 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4055 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4057 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
4058 } // hasSideEffects = 0
4061 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
4062 loadv8f64, f512mem, v8f32, v8f64,
4063 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
4064 EVEX_CD8<64, CD8VF>;
4066 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
4067 loadv4f64, f256mem, v8f64, v8f32,
4068 SSEPackedDouble>, EVEX_V512, PS,
4069 EVEX_CD8<32, CD8VH>;
4070 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
4071 (VCVTPS2PDZrm addr:$src)>;
4073 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
4074 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
4075 (VCVTPD2PSZrr VR512:$src)>;
4077 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
4078 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
4079 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
4081 //===----------------------------------------------------------------------===//
4082 // AVX-512 Vector convert from sign integer to float/double
4083 //===----------------------------------------------------------------------===//
4085 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
4086 loadv8i64, i512mem, v16f32, v16i32,
4087 SSEPackedSingle>, EVEX_V512, PS,
4088 EVEX_CD8<32, CD8VF>;
4090 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
4091 loadv4i64, i256mem, v8f64, v8i32,
4092 SSEPackedDouble>, EVEX_V512, XS,
4093 EVEX_CD8<32, CD8VH>;
4095 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
4096 loadv16f32, f512mem, v16i32, v16f32,
4097 SSEPackedSingle>, EVEX_V512, XS,
4098 EVEX_CD8<32, CD8VF>;
4100 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
4101 loadv8f64, f512mem, v8i32, v8f64,
4102 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
4103 EVEX_CD8<64, CD8VF>;
4105 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
4106 loadv16f32, f512mem, v16i32, v16f32,
4107 SSEPackedSingle>, EVEX_V512, PS,
4108 EVEX_CD8<32, CD8VF>;
4110 // cvttps2udq (src, 0, mask-all-ones, sae-current)
4111 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
4112 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
4113 (VCVTTPS2UDQZrr VR512:$src)>;
4115 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
4116 loadv8f64, f512mem, v8i32, v8f64,
4117 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
4118 EVEX_CD8<64, CD8VF>;
4120 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
4121 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
4122 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
4123 (VCVTTPD2UDQZrr VR512:$src)>;
4125 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
4126 loadv4i64, f256mem, v8f64, v8i32,
4127 SSEPackedDouble>, EVEX_V512, XS,
4128 EVEX_CD8<32, CD8VH>;
4130 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
4131 loadv16i32, f512mem, v16f32, v16i32,
4132 SSEPackedSingle>, EVEX_V512, XD,
4133 EVEX_CD8<32, CD8VF>;
4135 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
4136 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
4137 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
4139 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
4140 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
4141 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
4143 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
4144 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
4145 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
4147 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
4148 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
4149 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
4151 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
4152 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
4153 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
4155 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
4156 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
4157 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
4158 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
4159 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4160 (VCVTDQ2PDZrr VR256X:$src)>;
4161 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
4162 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
4163 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
4164 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
4165 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4166 (VCVTUDQ2PDZrr VR256X:$src)>;
4168 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
4169 RegisterClass DstRC, PatFrag mem_frag,
4170 X86MemOperand x86memop, Domain d> {
4171 let hasSideEffects = 0 in {
4172 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4173 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4175 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4176 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
4177 [], d>, EVEX, EVEX_B, EVEX_RC;
4179 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4180 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4182 } // hasSideEffects = 0
4185 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
4186 loadv16f32, f512mem, SSEPackedSingle>, PD,
4187 EVEX_V512, EVEX_CD8<32, CD8VF>;
4188 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
4189 loadv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
4190 EVEX_V512, EVEX_CD8<64, CD8VF>;
4192 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
4193 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4194 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
4196 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
4197 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4198 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
4200 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
4201 loadv16f32, f512mem, SSEPackedSingle>,
4202 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4203 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
4204 loadv8f64, f512mem, SSEPackedDouble>, VEX_W,
4205 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
4207 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
4208 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4209 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
4211 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
4212 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4213 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
4215 let Predicates = [HasAVX512] in {
4216 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
4217 (VCVTPD2PSZrm addr:$src)>;
4218 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
4219 (VCVTPS2PDZrm addr:$src)>;
4222 //===----------------------------------------------------------------------===//
4223 // Half precision conversion instructions
4224 //===----------------------------------------------------------------------===//
4225 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
4226 X86MemOperand x86memop> {
4227 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
4228 "vcvtph2ps\t{$src, $dst|$dst, $src}",
4230 let hasSideEffects = 0, mayLoad = 1 in
4231 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
4232 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
4235 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
4236 X86MemOperand x86memop> {
4237 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
4238 (ins srcRC:$src1, i32u8imm:$src2),
4239 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4241 let hasSideEffects = 0, mayStore = 1 in
4242 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
4243 (ins x86memop:$dst, srcRC:$src1, i32u8imm:$src2),
4244 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
4247 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
4248 EVEX_CD8<32, CD8VH>;
4249 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
4250 EVEX_CD8<32, CD8VH>;
4252 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
4253 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
4254 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
4256 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
4257 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
4258 (VCVTPH2PSZrr VR256X:$src)>;
4260 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
4261 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
4262 "ucomiss">, PS, EVEX, VEX_LIG,
4263 EVEX_CD8<32, CD8VT1>;
4264 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
4265 "ucomisd">, PD, EVEX,
4266 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4267 let Pattern = []<dag> in {
4268 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
4269 "comiss">, PS, EVEX, VEX_LIG,
4270 EVEX_CD8<32, CD8VT1>;
4271 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
4272 "comisd">, PD, EVEX,
4273 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4275 let isCodeGenOnly = 1 in {
4276 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
4277 load, "ucomiss">, PS, EVEX, VEX_LIG,
4278 EVEX_CD8<32, CD8VT1>;
4279 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
4280 load, "ucomisd">, PD, EVEX,
4281 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4283 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
4284 load, "comiss">, PS, EVEX, VEX_LIG,
4285 EVEX_CD8<32, CD8VT1>;
4286 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
4287 load, "comisd">, PD, EVEX,
4288 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4292 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
4293 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4294 X86MemOperand x86memop> {
4295 let hasSideEffects = 0 in {
4296 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4297 (ins RC:$src1, RC:$src2),
4298 !strconcat(OpcodeStr,
4299 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4300 let mayLoad = 1 in {
4301 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4302 (ins RC:$src1, x86memop:$src2),
4303 !strconcat(OpcodeStr,
4304 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4309 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
4310 EVEX_CD8<32, CD8VT1>;
4311 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
4312 VEX_W, EVEX_CD8<64, CD8VT1>;
4313 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
4314 EVEX_CD8<32, CD8VT1>;
4315 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
4316 VEX_W, EVEX_CD8<64, CD8VT1>;
4318 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
4319 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4320 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4321 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4323 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
4324 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4325 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4326 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4328 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
4329 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4330 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4331 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4333 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
4334 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4335 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4336 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4338 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
4339 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
4340 X86VectorVTInfo _> {
4341 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4342 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4343 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
4344 let mayLoad = 1 in {
4345 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4346 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4348 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
4349 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4350 (ins _.ScalarMemOp:$src), OpcodeStr,
4351 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4353 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4358 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4359 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
4360 EVEX_V512, EVEX_CD8<32, CD8VF>;
4361 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
4362 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4364 // Define only if AVX512VL feature is present.
4365 let Predicates = [HasVLX] in {
4366 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4367 OpNode, v4f32x_info>,
4368 EVEX_V128, EVEX_CD8<32, CD8VF>;
4369 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4370 OpNode, v8f32x_info>,
4371 EVEX_V256, EVEX_CD8<32, CD8VF>;
4372 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4373 OpNode, v2f64x_info>,
4374 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
4375 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4376 OpNode, v4f64x_info>,
4377 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
4381 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
4382 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
4384 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
4385 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4386 (VRSQRT14PSZr VR512:$src)>;
4387 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
4388 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4389 (VRSQRT14PDZr VR512:$src)>;
4391 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
4392 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4393 (VRCP14PSZr VR512:$src)>;
4394 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
4395 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4396 (VRCP14PDZr VR512:$src)>;
4398 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
4399 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
4402 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4403 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4404 "$src2, $src1", "$src1, $src2",
4405 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4406 (i32 FROUND_CURRENT))>;
4408 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4409 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4410 "$src2, $src1", "$src1, $src2",
4411 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4412 (i32 FROUND_NO_EXC)), "{sae}">, EVEX_B;
4414 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4415 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
4416 "$src2, $src1", "$src1, $src2",
4417 (OpNode (_.VT _.RC:$src1),
4418 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
4419 (i32 FROUND_CURRENT))>;
4422 multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4423 defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
4424 EVEX_CD8<32, CD8VT1>;
4425 defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>,
4426 EVEX_CD8<64, CD8VT1>, VEX_W;
4429 let hasSideEffects = 0, Predicates = [HasERI] in {
4430 defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V;
4431 defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V;
4433 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
4435 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4438 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4439 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4440 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
4442 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4443 (ins _.RC:$src), OpcodeStr,
4445 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC)),
4448 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4449 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4451 (bitconvert (_.LdFrag addr:$src))),
4452 (i32 FROUND_CURRENT))>;
4454 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4455 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4457 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
4458 (i32 FROUND_CURRENT))>, EVEX_B;
4461 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4462 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
4463 EVEX_CD8<32, CD8VF>;
4464 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
4465 VEX_W, EVEX_CD8<32, CD8VF>;
4468 let Predicates = [HasERI], hasSideEffects = 0 in {
4470 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX, EVEX_V512, T8PD;
4471 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX, EVEX_V512, T8PD;
4472 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX, EVEX_V512, T8PD;
4475 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
4476 SDNode OpNode, X86VectorVTInfo _>{
4477 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4478 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4479 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
4480 let mayLoad = 1 in {
4481 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4482 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4484 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
4486 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4487 (ins _.ScalarMemOp:$src), OpcodeStr,
4488 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4490 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4495 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
4496 Intrinsic F32Int, Intrinsic F64Int,
4497 OpndItins itins_s, OpndItins itins_d> {
4498 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
4499 (ins FR32X:$src1, FR32X:$src2),
4500 !strconcat(OpcodeStr,
4501 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4502 [], itins_s.rr>, XS, EVEX_4V;
4503 let isCodeGenOnly = 1 in
4504 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4505 (ins VR128X:$src1, VR128X:$src2),
4506 !strconcat(OpcodeStr,
4507 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4509 (F32Int VR128X:$src1, VR128X:$src2))],
4510 itins_s.rr>, XS, EVEX_4V;
4511 let mayLoad = 1 in {
4512 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
4513 (ins FR32X:$src1, f32mem:$src2),
4514 !strconcat(OpcodeStr,
4515 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4516 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4517 let isCodeGenOnly = 1 in
4518 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4519 (ins VR128X:$src1, ssmem:$src2),
4520 !strconcat(OpcodeStr,
4521 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4523 (F32Int VR128X:$src1, sse_load_f32:$src2))],
4524 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4526 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
4527 (ins FR64X:$src1, FR64X:$src2),
4528 !strconcat(OpcodeStr,
4529 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4531 let isCodeGenOnly = 1 in
4532 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4533 (ins VR128X:$src1, VR128X:$src2),
4534 !strconcat(OpcodeStr,
4535 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4537 (F64Int VR128X:$src1, VR128X:$src2))],
4538 itins_s.rr>, XD, EVEX_4V, VEX_W;
4539 let mayLoad = 1 in {
4540 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
4541 (ins FR64X:$src1, f64mem:$src2),
4542 !strconcat(OpcodeStr,
4543 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4544 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4545 let isCodeGenOnly = 1 in
4546 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4547 (ins VR128X:$src1, sdmem:$src2),
4548 !strconcat(OpcodeStr,
4549 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4551 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
4552 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4556 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
4558 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
4560 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
4561 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
4563 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4564 // Define only if AVX512VL feature is present.
4565 let Predicates = [HasVLX] in {
4566 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4567 OpNode, v4f32x_info>,
4568 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
4569 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4570 OpNode, v8f32x_info>,
4571 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
4572 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4573 OpNode, v2f64x_info>,
4574 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4575 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4576 OpNode, v4f64x_info>,
4577 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4581 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>;
4583 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
4584 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
4585 SSE_SQRTSS, SSE_SQRTSD>;
4587 let Predicates = [HasAVX512] in {
4588 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
4589 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
4590 (VSQRTPSZr VR512:$src1)>;
4591 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
4592 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
4593 (VSQRTPDZr VR512:$src1)>;
4595 def : Pat<(f32 (fsqrt FR32X:$src)),
4596 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4597 def : Pat<(f32 (fsqrt (load addr:$src))),
4598 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
4599 Requires<[OptForSize]>;
4600 def : Pat<(f64 (fsqrt FR64X:$src)),
4601 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
4602 def : Pat<(f64 (fsqrt (load addr:$src))),
4603 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
4604 Requires<[OptForSize]>;
4606 def : Pat<(f32 (X86frsqrt FR32X:$src)),
4607 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4608 def : Pat<(f32 (X86frsqrt (load addr:$src))),
4609 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4610 Requires<[OptForSize]>;
4612 def : Pat<(f32 (X86frcp FR32X:$src)),
4613 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4614 def : Pat<(f32 (X86frcp (load addr:$src))),
4615 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4616 Requires<[OptForSize]>;
4618 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
4619 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
4620 (COPY_TO_REGCLASS VR128X:$src, FR32)),
4622 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
4623 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
4625 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
4626 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
4627 (COPY_TO_REGCLASS VR128X:$src, FR64)),
4629 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
4630 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
4634 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
4635 X86MemOperand x86memop, RegisterClass RC,
4636 PatFrag mem_frag, Domain d> {
4637 let ExeDomain = d in {
4638 // Intrinsic operation, reg.
4639 // Vector intrinsic operation, reg
4640 def r : AVX512AIi8<opc, MRMSrcReg,
4641 (outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
4642 !strconcat(OpcodeStr,
4643 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4646 // Vector intrinsic operation, mem
4647 def m : AVX512AIi8<opc, MRMSrcMem,
4648 (outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
4649 !strconcat(OpcodeStr,
4650 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4656 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
4657 loadv16f32, SSEPackedSingle>, EVEX_V512,
4658 EVEX_CD8<32, CD8VF>;
4660 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
4661 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
4663 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
4666 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
4667 loadv8f64, SSEPackedDouble>, EVEX_V512,
4668 VEX_W, EVEX_CD8<64, CD8VF>;
4670 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
4671 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
4673 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
4675 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
4676 Operand x86memop, RegisterClass RC, Domain d> {
4677 let ExeDomain = d in {
4678 def r : AVX512AIi8<opc, MRMSrcReg,
4679 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32u8imm:$src3),
4680 !strconcat(OpcodeStr,
4681 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4684 def m : AVX512AIi8<opc, MRMSrcMem,
4685 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32u8imm:$src3),
4686 !strconcat(OpcodeStr,
4687 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4692 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
4693 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
4695 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
4696 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
4698 let Predicates = [HasAVX512] in {
4699 def : Pat<(ffloor FR32X:$src),
4700 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
4701 def : Pat<(f64 (ffloor FR64X:$src)),
4702 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
4703 def : Pat<(f32 (fnearbyint FR32X:$src)),
4704 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
4705 def : Pat<(f64 (fnearbyint FR64X:$src)),
4706 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
4707 def : Pat<(f32 (fceil FR32X:$src)),
4708 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
4709 def : Pat<(f64 (fceil FR64X:$src)),
4710 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
4711 def : Pat<(f32 (frint FR32X:$src)),
4712 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
4713 def : Pat<(f64 (frint FR64X:$src)),
4714 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
4715 def : Pat<(f32 (ftrunc FR32X:$src)),
4716 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
4717 def : Pat<(f64 (ftrunc FR64X:$src)),
4718 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
4721 def : Pat<(v16f32 (ffloor VR512:$src)),
4722 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
4723 def : Pat<(v16f32 (fnearbyint VR512:$src)),
4724 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
4725 def : Pat<(v16f32 (fceil VR512:$src)),
4726 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
4727 def : Pat<(v16f32 (frint VR512:$src)),
4728 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
4729 def : Pat<(v16f32 (ftrunc VR512:$src)),
4730 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
4732 def : Pat<(v8f64 (ffloor VR512:$src)),
4733 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
4734 def : Pat<(v8f64 (fnearbyint VR512:$src)),
4735 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
4736 def : Pat<(v8f64 (fceil VR512:$src)),
4737 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
4738 def : Pat<(v8f64 (frint VR512:$src)),
4739 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
4740 def : Pat<(v8f64 (ftrunc VR512:$src)),
4741 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
4743 //-------------------------------------------------
4744 // Integer truncate and extend operations
4745 //-------------------------------------------------
4747 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
4748 RegisterClass dstRC, RegisterClass srcRC,
4749 RegisterClass KRC, X86MemOperand x86memop> {
4750 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4752 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
4755 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4756 (ins KRC:$mask, srcRC:$src),
4757 !strconcat(OpcodeStr,
4758 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
4761 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4762 (ins KRC:$mask, srcRC:$src),
4763 !strconcat(OpcodeStr,
4764 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4767 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
4768 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4771 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4772 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4773 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4777 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4778 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4779 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4780 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4781 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4782 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4783 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4784 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4785 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4786 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4787 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4788 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4789 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4790 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4791 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4792 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4793 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4794 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4795 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4796 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4797 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4798 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4799 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4800 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4801 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4802 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4803 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4804 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4805 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4806 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4808 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4809 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4810 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4811 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4812 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4814 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4815 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
4816 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4817 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
4818 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4819 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
4820 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4821 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
4824 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4825 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4826 PatFrag mem_frag, X86MemOperand x86memop,
4827 ValueType OpVT, ValueType InVT> {
4829 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4831 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4832 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
4834 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4835 (ins KRC:$mask, SrcRC:$src),
4836 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4839 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4840 (ins KRC:$mask, SrcRC:$src),
4841 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4844 let mayLoad = 1 in {
4845 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4846 (ins x86memop:$src),
4847 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
4849 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4852 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4853 (ins KRC:$mask, x86memop:$src),
4854 !strconcat(OpcodeStr,"\t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4858 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4859 (ins KRC:$mask, x86memop:$src),
4860 !strconcat(OpcodeStr,"\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4866 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
4867 loadv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4869 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
4870 loadv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4872 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
4873 loadv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4874 EVEX_CD8<16, CD8VH>;
4875 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
4876 loadv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4877 EVEX_CD8<16, CD8VQ>;
4878 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
4879 loadv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4880 EVEX_CD8<32, CD8VH>;
4882 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
4883 loadv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4885 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
4886 loadv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4888 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
4889 loadv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4890 EVEX_CD8<16, CD8VH>;
4891 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
4892 loadv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4893 EVEX_CD8<16, CD8VQ>;
4894 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
4895 loadv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4896 EVEX_CD8<32, CD8VH>;
4898 //===----------------------------------------------------------------------===//
4899 // GATHER - SCATTER Operations
4901 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4902 RegisterClass RC, X86MemOperand memop> {
4904 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4905 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4906 (ins RC:$src1, KRC:$mask, memop:$src2),
4907 !strconcat(OpcodeStr,
4908 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4912 let ExeDomain = SSEPackedDouble in {
4913 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4914 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4915 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4916 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4919 let ExeDomain = SSEPackedSingle in {
4920 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4921 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4922 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4923 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4926 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4927 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4928 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4929 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4931 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4932 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4933 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4934 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4936 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4937 RegisterClass RC, X86MemOperand memop> {
4938 let mayStore = 1, Constraints = "$mask = $mask_wb" in
4939 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4940 (ins memop:$dst, KRC:$mask, RC:$src2),
4941 !strconcat(OpcodeStr,
4942 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4946 let ExeDomain = SSEPackedDouble in {
4947 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4948 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4949 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4950 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4953 let ExeDomain = SSEPackedSingle in {
4954 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4955 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4956 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4957 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4960 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4961 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4962 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4963 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4965 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4966 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4967 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4968 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4971 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4972 RegisterClass KRC, X86MemOperand memop> {
4973 let Predicates = [HasPFI], hasSideEffects = 1 in
4974 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4975 !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"),
4979 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4980 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4982 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4983 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4985 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4986 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4988 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4989 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4991 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4992 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4994 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4995 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4997 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4998 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5000 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
5001 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5003 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
5004 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5006 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
5007 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5009 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
5010 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5012 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
5013 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5015 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
5016 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5018 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
5019 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5021 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
5022 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5024 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
5025 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5026 //===----------------------------------------------------------------------===//
5027 // VSHUFPS - VSHUFPD Operations
5029 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
5030 ValueType vt, string OpcodeStr, PatFrag mem_frag,
5032 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
5033 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
5034 !strconcat(OpcodeStr,
5035 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5036 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
5037 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
5038 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
5039 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
5040 (ins RC:$src1, RC:$src2, u8imm:$src3),
5041 !strconcat(OpcodeStr,
5042 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5043 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
5044 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
5045 EVEX_4V, Sched<[WriteShuffle]>;
5048 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", loadv16f32,
5049 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
5050 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", loadv8f64,
5051 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
5053 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
5054 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
5055 def : Pat<(v16i32 (X86Shufp VR512:$src1,
5056 (loadv16i32 addr:$src2), (i8 imm:$imm))),
5057 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
5059 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
5060 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
5061 def : Pat<(v8i64 (X86Shufp VR512:$src1,
5062 (loadv8i64 addr:$src2), (i8 imm:$imm))),
5063 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
5065 multiclass avx512_valign<X86VectorVTInfo _> {
5066 defm rri : AVX512_maskable<0x03, MRMSrcReg, _, (outs _.RC:$dst),
5067 (ins _.RC:$src1, _.RC:$src2, u8imm:$src3),
5069 "$src3, $src2, $src1", "$src1, $src2, $src3",
5070 (_.VT (X86VAlign _.RC:$src2, _.RC:$src1,
5072 AVX512AIi8Base, EVEX_4V;
5074 // Also match valign of packed floats.
5075 def : Pat<(_.FloatVT (X86VAlign _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
5076 (!cast<Instruction>(NAME##rri) _.RC:$src2, _.RC:$src1, imm:$imm)>;
5079 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs _.RC:$dst),
5080 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$src3),
5081 !strconcat("valign"##_.Suffix,
5082 "\t{$src3, $src2, $src1, $dst|"
5083 "$dst, $src1, $src2, $src3}"),
5086 defm VALIGND : avx512_valign<v16i32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
5087 defm VALIGNQ : avx512_valign<v8i64_info>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
5089 // Helper fragments to match sext vXi1 to vXiY.
5090 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
5091 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
5093 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
5094 RegisterClass KRC, RegisterClass RC,
5095 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
5097 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
5098 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5100 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5101 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
5103 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5104 !strconcat(OpcodeStr,
5105 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5107 let mayLoad = 1 in {
5108 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5109 (ins x86memop:$src),
5110 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5112 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5113 (ins KRC:$mask, x86memop:$src),
5114 !strconcat(OpcodeStr,
5115 "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
5117 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5118 (ins KRC:$mask, x86memop:$src),
5119 !strconcat(OpcodeStr,
5120 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5122 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5123 (ins x86scalar_mop:$src),
5124 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5125 ", $dst|$dst, ${src}", BrdcstStr, "}"),
5127 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5128 (ins KRC:$mask, x86scalar_mop:$src),
5129 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5130 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
5131 []>, EVEX, EVEX_B, EVEX_K;
5132 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5133 (ins KRC:$mask, x86scalar_mop:$src),
5134 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5135 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
5137 []>, EVEX, EVEX_B, EVEX_KZ;
5141 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
5142 i512mem, i32mem, "{1to16}">, EVEX_V512,
5143 EVEX_CD8<32, CD8VF>;
5144 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
5145 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
5146 EVEX_CD8<64, CD8VF>;
5149 (bc_v16i32 (v16i1sextv16i32)),
5150 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
5151 (VPABSDZrr VR512:$src)>;
5153 (bc_v8i64 (v8i1sextv8i64)),
5154 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
5155 (VPABSQZrr VR512:$src)>;
5157 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
5158 (v16i32 immAllZerosV), (i16 -1))),
5159 (VPABSDZrr VR512:$src)>;
5160 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
5161 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
5162 (VPABSQZrr VR512:$src)>;
5164 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
5165 RegisterClass RC, RegisterClass KRC,
5166 X86MemOperand x86memop,
5167 X86MemOperand x86scalar_mop, string BrdcstStr> {
5168 let hasSideEffects = 0 in {
5169 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5171 !strconcat(OpcodeStr, "\t{$src, ${dst} |${dst}, $src}"),
5174 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5175 (ins x86memop:$src),
5176 !strconcat(OpcodeStr, "\t{$src, ${dst}|${dst}, $src}"),
5179 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5180 (ins x86scalar_mop:$src),
5181 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5182 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
5184 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5185 (ins KRC:$mask, RC:$src),
5186 !strconcat(OpcodeStr,
5187 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5190 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5191 (ins KRC:$mask, x86memop:$src),
5192 !strconcat(OpcodeStr,
5193 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5196 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5197 (ins KRC:$mask, x86scalar_mop:$src),
5198 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5199 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
5201 []>, EVEX, EVEX_KZ, EVEX_B;
5203 let Constraints = "$src1 = $dst" in {
5204 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5205 (ins RC:$src1, KRC:$mask, RC:$src2),
5206 !strconcat(OpcodeStr,
5207 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5210 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5211 (ins RC:$src1, KRC:$mask, x86memop:$src2),
5212 !strconcat(OpcodeStr,
5213 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5216 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5217 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
5218 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
5219 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
5220 []>, EVEX, EVEX_K, EVEX_B;
5225 let Predicates = [HasCDI] in {
5226 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
5227 i512mem, i32mem, "{1to16}">,
5228 EVEX_V512, EVEX_CD8<32, CD8VF>;
5231 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
5232 i512mem, i64mem, "{1to8}">,
5233 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5237 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
5239 (VPCONFLICTDrrk VR512:$src1,
5240 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5242 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
5244 (VPCONFLICTQrrk VR512:$src1,
5245 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5247 let Predicates = [HasCDI] in {
5248 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
5249 i512mem, i32mem, "{1to16}">,
5250 EVEX_V512, EVEX_CD8<32, CD8VF>;
5253 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
5254 i512mem, i64mem, "{1to8}">,
5255 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5259 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
5261 (VPLZCNTDrrk VR512:$src1,
5262 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5264 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
5266 (VPLZCNTQrrk VR512:$src1,
5267 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5269 def : Pat<(v16i32 (ctlz (loadv16i32 addr:$src))),
5270 (VPLZCNTDrm addr:$src)>;
5271 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
5272 (VPLZCNTDrr VR512:$src)>;
5273 def : Pat<(v8i64 (ctlz (loadv8i64 addr:$src))),
5274 (VPLZCNTQrm addr:$src)>;
5275 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
5276 (VPLZCNTQrr VR512:$src)>;
5278 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5279 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5280 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
5282 def : Pat<(store VK1:$src, addr:$dst),
5284 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)),
5285 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
5287 def : Pat<(store VK8:$src, addr:$dst),
5289 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
5290 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
5292 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
5293 (truncstore node:$val, node:$ptr), [{
5294 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
5297 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
5298 (MOV8mr addr:$dst, GR8:$src)>;
5300 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
5301 def rr : AVX512XS8I<opc, MRMDestReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
5302 !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
5303 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
5306 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
5307 string OpcodeStr, Predicate prd> {
5308 let Predicates = [prd] in
5309 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5311 let Predicates = [prd, HasVLX] in {
5312 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5313 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5317 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
5318 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
5320 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
5322 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
5324 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
5328 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;
5330 //===----------------------------------------------------------------------===//
5331 // AVX-512 - COMPRESS and EXPAND
5333 multiclass compress_by_vec_width<bits<8> opc, X86VectorVTInfo _,
5335 def rrkz : AVX5128I<opc, MRMDestReg, (outs _.RC:$dst),
5336 (ins _.KRCWM:$mask, _.RC:$src),
5337 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5338 [(set _.RC:$dst, (_.VT (X86compress _.KRCWM:$mask, _.RC:$src,
5339 _.ImmAllZerosV)))]>, EVEX_KZ;
5341 let Constraints = "$src0 = $dst" in
5342 def rrk : AVX5128I<opc, MRMDestReg, (outs _.RC:$dst),
5343 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src),
5344 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5345 [(set _.RC:$dst, (_.VT (X86compress _.KRCWM:$mask, _.RC:$src,
5346 _.RC:$src0)))]>, EVEX_K;
5348 let mayStore = 1 in {
5349 def mrk : AVX5128I<opc, MRMDestMem, (outs),
5350 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
5351 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5352 [(store (_.VT (X86compress _.KRCWM:$mask, _.RC:$src, undef)),
5354 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
5358 multiclass compress_by_elt_width<bits<8> opc, string OpcodeStr,
5359 AVX512VLVectorVTInfo VTInfo> {
5360 defm Z : compress_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5362 let Predicates = [HasVLX] in {
5363 defm Z256 : compress_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5364 defm Z128 : compress_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5368 defm VPCOMPRESSD : compress_by_elt_width <0x8B, "vpcompressd", avx512vl_i32_info>,
5370 defm VPCOMPRESSQ : compress_by_elt_width <0x8B, "vpcompressq", avx512vl_i64_info>,
5372 defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", avx512vl_f32_info>,
5374 defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", avx512vl_f64_info>,
5378 multiclass expand_by_vec_width<bits<8> opc, X86VectorVTInfo _,
5380 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
5381 (ins _.KRCWM:$mask, _.RC:$src),
5382 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5383 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask, (_.VT _.RC:$src),
5384 _.ImmAllZerosV)))]>, EVEX_KZ;
5386 let Constraints = "$src0 = $dst" in
5387 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
5388 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src),
5389 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5390 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5391 (_.VT _.RC:$src), _.RC:$src0)))]>, EVEX_K;
5393 let mayLoad = 1, Constraints = "$src0 = $dst" in
5394 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
5395 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src),
5396 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5397 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5399 (_.LdFrag addr:$src))),
5401 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
5404 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
5405 (ins _.KRCWM:$mask, _.MemOp:$src),
5406 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5407 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5408 (_.VT (bitconvert (_.LdFrag addr:$src))),
5409 _.ImmAllZerosV)))]>,
5410 EVEX_KZ, EVEX_CD8<_.EltSize, CD8VT1>;
5414 multiclass expand_by_elt_width<bits<8> opc, string OpcodeStr,
5415 AVX512VLVectorVTInfo VTInfo> {
5416 defm Z : expand_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5418 let Predicates = [HasVLX] in {
5419 defm Z256 : expand_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5420 defm Z128 : expand_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5424 defm VPEXPANDD : expand_by_elt_width <0x89, "vpexpandd", avx512vl_i32_info>,
5426 defm VPEXPANDQ : expand_by_elt_width <0x89, "vpexpandq", avx512vl_i64_info>,
5428 defm VEXPANDPS : expand_by_elt_width <0x88, "vexpandps", avx512vl_f32_info>,
5430 defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", avx512vl_f64_info>,