1 //===-- X86InstrAVX512.td - AVX512 Instruction Set ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 AVX512 instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // Group template arguments that can be derived from the vector type (EltNum x
17 // EltVT). These are things like the register class for the writemask, etc.
18 // The idea is to pass one of these as the template argument rather than the
19 // individual arguments.
20 // The template is also used for scalar types, in this case numelts is 1.
21 class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,
23 RegisterClass RC = rc;
24 ValueType EltVT = eltvt;
25 int NumElts = numelts;
27 // Corresponding mask register class.
28 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
30 // Corresponding write-mask register class.
31 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
33 // The GPR register class that can hold the write mask. Use GR8 for fewer
34 // than 8 elements. Use shift-right and equal to work around the lack of
37 !cast<RegisterClass>("GR" #
38 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
40 // Suffix used in the instruction mnemonic.
41 string Suffix = suffix;
43 // VTName is a string name for vector VT. For vector types it will be
44 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
45 // It is a little bit complex for scalar types, where NumElts = 1.
46 // In this case we build v4f32 or v2f64
47 string VTName = "v" # !if (!eq (NumElts, 1),
48 !if (!eq (EltVT.Size, 32), 4,
49 !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT;
52 ValueType VT = !cast<ValueType>(VTName);
54 string EltTypeName = !cast<string>(EltVT);
55 // Size of the element type in bits, e.g. 32 for v16i32.
56 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
57 int EltSize = EltVT.Size;
59 // "i" for integer types and "f" for floating-point types
60 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
62 // Size of RC in bits, e.g. 512 for VR512.
65 // The corresponding memory operand, e.g. i512mem for VR512.
66 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
67 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
70 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
71 // due to load promotion during legalization
72 PatFrag LdFrag = !cast<PatFrag>("load" #
73 !if (!eq (TypeVariantName, "i"),
74 !if (!eq (Size, 128), "v2i64",
75 !if (!eq (Size, 256), "v4i64",
78 PatFrag AlignedLdFrag = !cast<PatFrag>("alignedload" #
79 !if (!eq (TypeVariantName, "i"),
80 !if (!eq (Size, 128), "v2i64",
81 !if (!eq (Size, 256), "v4i64",
83 !if (!eq (EltSize, 64), "v8i64", "v16i32"),
86 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
88 // The corresponding float type, e.g. v16f32 for v16i32
89 // Note: For EltSize < 32, FloatVT is illegal and TableGen
90 // fails to compile, so we choose FloatVT = VT
91 ValueType FloatVT = !cast<ValueType>(
92 !if (!eq (!srl(EltSize,5),0),
94 !if (!eq(TypeVariantName, "i"),
95 "v" # NumElts # "f" # EltSize,
98 // The string to specify embedded broadcast in assembly.
99 string BroadcastStr = "{1to" # NumElts # "}";
101 // 8-bit compressed displacement tuple/subvector format. This is only
102 // defined for NumElts <= 8.
103 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
104 !cast<CD8VForm>("CD8VT" # NumElts), ?);
106 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
107 !if (!eq (Size, 256), sub_ymm, ?));
109 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
110 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
113 RegisterClass FRC = !if (!eq (EltTypeName, "f32"), FR32X, FR64X);
115 // A vector type of the same width with element type i32. This is used to
116 // create the canonical constant zero node ImmAllZerosV.
117 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
118 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
120 string ZSuffix = !if (!eq (Size, 128), "Z128",
121 !if (!eq (Size, 256), "Z256", "Z"));
124 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
125 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
126 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
127 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
128 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
129 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
131 // "x" in v32i8x_info means RC = VR256X
132 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
133 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
134 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
135 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
136 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
137 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
139 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
140 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
141 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
142 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
143 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
144 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
146 // We map scalar types to the smallest (128-bit) vector type
147 // with the appropriate element type. This allows to use the same masking logic.
148 def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;
149 def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;
151 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
152 X86VectorVTInfo i128> {
153 X86VectorVTInfo info512 = i512;
154 X86VectorVTInfo info256 = i256;
155 X86VectorVTInfo info128 = i128;
158 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
160 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
162 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
164 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
166 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
168 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
171 // This multiclass generates the masking variants from the non-masking
172 // variant. It only provides the assembly pieces for the masking variants.
173 // It assumes custom ISel patterns for masking which can be provided as
174 // template arguments.
175 multiclass AVX512_maskable_custom<bits<8> O, Format F,
177 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
179 string AttSrcAsm, string IntelSrcAsm,
181 list<dag> MaskingPattern,
182 list<dag> ZeroMaskingPattern,
184 string MaskingConstraint = "",
185 InstrItinClass itin = NoItinerary,
186 bit IsCommutable = 0> {
187 let isCommutable = IsCommutable in
188 def NAME: AVX512<O, F, Outs, Ins,
189 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
190 "$dst "#Round#", "#IntelSrcAsm#"}",
193 // Prefer over VMOV*rrk Pat<>
194 let AddedComplexity = 20 in
195 def NAME#k: AVX512<O, F, Outs, MaskingIns,
196 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}"#Round#"|"#
197 "$dst {${mask}}"#Round#", "#IntelSrcAsm#"}",
198 MaskingPattern, itin>,
200 // In case of the 3src subclass this is overridden with a let.
201 string Constraints = MaskingConstraint;
203 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
204 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
205 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}"#Round#"|"#
206 "$dst {${mask}} {z}"#Round#", "#IntelSrcAsm#"}",
213 // Common base class of AVX512_maskable and AVX512_maskable_3src.
214 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
216 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
218 string AttSrcAsm, string IntelSrcAsm,
219 dag RHS, dag MaskingRHS,
220 SDNode Select = vselect, string Round = "",
221 string MaskingConstraint = "",
222 InstrItinClass itin = NoItinerary,
223 bit IsCommutable = 0> :
224 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
225 AttSrcAsm, IntelSrcAsm,
226 [(set _.RC:$dst, RHS)],
227 [(set _.RC:$dst, MaskingRHS)],
229 (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
230 Round, MaskingConstraint, NoItinerary, IsCommutable>;
232 // This multiclass generates the unconditional/non-masking, the masking and
233 // the zero-masking variant of the vector instruction. In the masking case, the
234 // perserved vector elements come from a new dummy input operand tied to $dst.
235 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
236 dag Outs, dag Ins, string OpcodeStr,
237 string AttSrcAsm, string IntelSrcAsm,
238 dag RHS, string Round = "",
239 InstrItinClass itin = NoItinerary,
240 bit IsCommutable = 0> :
241 AVX512_maskable_common<O, F, _, Outs, Ins,
242 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
243 !con((ins _.KRCWM:$mask), Ins),
244 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
245 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect,
246 Round, "$src0 = $dst", itin, IsCommutable>;
248 // This multiclass generates the unconditional/non-masking, the masking and
249 // the zero-masking variant of the scalar instruction.
250 multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
251 dag Outs, dag Ins, string OpcodeStr,
252 string AttSrcAsm, string IntelSrcAsm,
253 dag RHS, string Round = "",
254 InstrItinClass itin = NoItinerary,
255 bit IsCommutable = 0> :
256 AVX512_maskable_common<O, F, _, Outs, Ins,
257 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
258 !con((ins _.KRCWM:$mask), Ins),
259 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
260 (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select,
261 Round, "$src0 = $dst", itin, IsCommutable>;
263 // Similar to AVX512_maskable but in this case one of the source operands
264 // ($src1) is already tied to $dst so we just use that for the preserved
265 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
267 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
268 dag Outs, dag NonTiedIns, string OpcodeStr,
269 string AttSrcAsm, string IntelSrcAsm,
271 AVX512_maskable_common<O, F, _, Outs,
272 !con((ins _.RC:$src1), NonTiedIns),
273 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
274 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
275 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
276 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
279 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
282 string AttSrcAsm, string IntelSrcAsm,
284 AVX512_maskable_custom<O, F, Outs, Ins,
285 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
286 !con((ins _.KRCWM:$mask), Ins),
287 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [], "",
291 // Instruction with mask that puts result in mask register,
292 // like "compare" and "vptest"
293 multiclass AVX512_maskable_custom_cmp<bits<8> O, Format F,
295 dag Ins, dag MaskingIns,
297 string AttSrcAsm, string IntelSrcAsm,
299 list<dag> MaskingPattern,
301 InstrItinClass itin = NoItinerary> {
302 def NAME: AVX512<O, F, Outs, Ins,
303 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
304 "$dst "#Round#", "#IntelSrcAsm#"}",
307 def NAME#k: AVX512<O, F, Outs, MaskingIns,
308 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}"#Round#"|"#
309 "$dst {${mask}}"#Round#", "#IntelSrcAsm#"}",
310 MaskingPattern, itin>, EVEX_K;
313 multiclass AVX512_maskable_common_cmp<bits<8> O, Format F, X86VectorVTInfo _,
315 dag Ins, dag MaskingIns,
317 string AttSrcAsm, string IntelSrcAsm,
318 dag RHS, dag MaskingRHS,
320 InstrItinClass itin = NoItinerary> :
321 AVX512_maskable_custom_cmp<O, F, Outs, Ins, MaskingIns, OpcodeStr,
322 AttSrcAsm, IntelSrcAsm,
323 [(set _.KRC:$dst, RHS)],
324 [(set _.KRC:$dst, MaskingRHS)],
327 multiclass AVX512_maskable_cmp<bits<8> O, Format F, X86VectorVTInfo _,
328 dag Outs, dag Ins, string OpcodeStr,
329 string AttSrcAsm, string IntelSrcAsm,
330 dag RHS, string Round = "",
331 InstrItinClass itin = NoItinerary> :
332 AVX512_maskable_common_cmp<O, F, _, Outs, Ins,
333 !con((ins _.KRCWM:$mask), Ins),
334 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
335 (and _.KRCWM:$mask, RHS),
338 // Bitcasts between 512-bit vector types. Return the original type since
339 // no instruction is needed for the conversion
340 let Predicates = [HasAVX512] in {
341 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
342 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
343 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
344 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
345 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
346 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
347 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
348 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
349 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
350 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
351 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
352 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
353 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
354 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
355 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
356 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
357 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
358 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
359 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
360 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
361 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
362 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
363 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
364 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
365 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
366 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
367 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
368 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
369 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
370 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
371 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
373 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
374 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
375 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
376 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
377 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
378 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
379 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
380 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
381 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
382 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
383 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
384 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
385 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
386 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
387 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
388 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
389 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
390 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
391 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
392 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
393 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
394 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
395 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
396 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
397 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
398 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
399 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
400 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
401 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
402 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
404 // Bitcasts between 256-bit vector types. Return the original type since
405 // no instruction is needed for the conversion
406 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
407 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
408 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
409 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
410 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
411 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
412 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
413 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
414 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
415 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
416 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
417 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
418 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
419 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
420 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
421 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
422 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
423 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
424 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
425 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
426 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
427 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
428 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
429 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
430 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
431 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
432 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
433 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
434 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
435 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
439 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
442 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
443 isPseudo = 1, Predicates = [HasAVX512] in {
444 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
445 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
448 let Predicates = [HasAVX512] in {
449 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
450 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
451 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
454 //===----------------------------------------------------------------------===//
455 // AVX-512 - VECTOR INSERT
458 multiclass vinsert_for_size_no_alt<int Opcode,
459 X86VectorVTInfo From, X86VectorVTInfo To,
460 PatFrag vinsert_insert,
461 SDNodeXForm INSERT_get_vinsert_imm> {
462 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
463 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
464 (ins VR512:$src1, From.RC:$src2, u8imm:$src3),
465 "vinsert" # From.EltTypeName # "x" # From.NumElts #
466 "\t{$src3, $src2, $src1, $dst|"
467 "$dst, $src1, $src2, $src3}",
468 [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
469 (From.VT From.RC:$src2),
474 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
475 (ins VR512:$src1, From.MemOp:$src2, u8imm:$src3),
476 "vinsert" # From.EltTypeName # "x" # From.NumElts #
477 "\t{$src3, $src2, $src1, $dst|"
478 "$dst, $src1, $src2, $src3}",
480 EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, From.CD8TupleForm>;
484 multiclass vinsert_for_size<int Opcode,
485 X86VectorVTInfo From, X86VectorVTInfo To,
486 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
487 PatFrag vinsert_insert,
488 SDNodeXForm INSERT_get_vinsert_imm> :
489 vinsert_for_size_no_alt<Opcode, From, To,
490 vinsert_insert, INSERT_get_vinsert_imm> {
491 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
492 // vinserti32x4. Only add this if 64x2 and friends are not supported
493 // natively via AVX512DQ.
494 let Predicates = [NoDQI] in
495 def : Pat<(vinsert_insert:$ins
496 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
497 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
498 VR512:$src1, From.RC:$src2,
499 (INSERT_get_vinsert_imm VR512:$ins)))>;
502 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
503 ValueType EltVT64, int Opcode256> {
504 defm NAME # "32x4" : vinsert_for_size<Opcode128,
505 X86VectorVTInfo< 4, EltVT32, VR128X>,
506 X86VectorVTInfo<16, EltVT32, VR512>,
507 X86VectorVTInfo< 2, EltVT64, VR128X>,
508 X86VectorVTInfo< 8, EltVT64, VR512>,
510 INSERT_get_vinsert128_imm>;
511 let Predicates = [HasDQI] in
512 defm NAME # "64x2" : vinsert_for_size_no_alt<Opcode128,
513 X86VectorVTInfo< 2, EltVT64, VR128X>,
514 X86VectorVTInfo< 8, EltVT64, VR512>,
516 INSERT_get_vinsert128_imm>, VEX_W;
517 defm NAME # "64x4" : vinsert_for_size<Opcode256,
518 X86VectorVTInfo< 4, EltVT64, VR256X>,
519 X86VectorVTInfo< 8, EltVT64, VR512>,
520 X86VectorVTInfo< 8, EltVT32, VR256>,
521 X86VectorVTInfo<16, EltVT32, VR512>,
523 INSERT_get_vinsert256_imm>, VEX_W;
524 let Predicates = [HasDQI] in
525 defm NAME # "32x8" : vinsert_for_size_no_alt<Opcode256,
526 X86VectorVTInfo< 8, EltVT32, VR256X>,
527 X86VectorVTInfo<16, EltVT32, VR512>,
529 INSERT_get_vinsert256_imm>;
532 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
533 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
535 // vinsertps - insert f32 to XMM
536 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
537 (ins VR128X:$src1, VR128X:$src2, u8imm:$src3),
538 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
539 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
541 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
542 (ins VR128X:$src1, f32mem:$src2, u8imm:$src3),
543 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
544 [(set VR128X:$dst, (X86insertps VR128X:$src1,
545 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
546 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
548 //===----------------------------------------------------------------------===//
549 // AVX-512 VECTOR EXTRACT
552 multiclass vextract_for_size<int Opcode,
553 X86VectorVTInfo From, X86VectorVTInfo To,
554 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
555 PatFrag vextract_extract,
556 SDNodeXForm EXTRACT_get_vextract_imm> {
557 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
558 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
559 (ins VR512:$src1, u8imm:$idx),
560 "vextract" # To.EltTypeName # "x4",
561 "$idx, $src1", "$src1, $idx",
562 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
564 AVX512AIi8Base, EVEX, EVEX_V512;
566 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
567 (ins To.MemOp:$dst, VR512:$src1, u8imm:$src2),
568 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
569 "$dst, $src1, $src2}",
570 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
573 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
575 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
576 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
578 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
580 // A 128/256-bit subvector extract from the first 512-bit vector position is
581 // a subregister copy that needs no instruction.
582 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
584 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
586 // And for the alternative types.
587 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
589 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
591 // Intrinsic call with masking.
592 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
594 VR512:$src1, (iPTR imm:$idx), To.RC:$src0, GR8:$mask),
595 (!cast<Instruction>(NAME # To.EltSize # "x4rrk") To.RC:$src0,
596 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
597 VR512:$src1, imm:$idx)>;
599 // Intrinsic call with zero-masking.
600 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
602 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, GR8:$mask),
603 (!cast<Instruction>(NAME # To.EltSize # "x4rrkz")
604 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
605 VR512:$src1, imm:$idx)>;
607 // Intrinsic call without masking.
608 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
610 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
611 (!cast<Instruction>(NAME # To.EltSize # "x4rr")
612 VR512:$src1, imm:$idx)>;
615 multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
616 ValueType EltVT64, int Opcode64> {
617 defm NAME # "32x4" : vextract_for_size<Opcode32,
618 X86VectorVTInfo<16, EltVT32, VR512>,
619 X86VectorVTInfo< 4, EltVT32, VR128X>,
620 X86VectorVTInfo< 8, EltVT64, VR512>,
621 X86VectorVTInfo< 2, EltVT64, VR128X>,
623 EXTRACT_get_vextract128_imm>;
624 defm NAME # "64x4" : vextract_for_size<Opcode64,
625 X86VectorVTInfo< 8, EltVT64, VR512>,
626 X86VectorVTInfo< 4, EltVT64, VR256X>,
627 X86VectorVTInfo<16, EltVT32, VR512>,
628 X86VectorVTInfo< 8, EltVT32, VR256>,
630 EXTRACT_get_vextract256_imm>, VEX_W;
633 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
634 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
636 // A 128-bit subvector insert to the first 512-bit vector position
637 // is a subregister copy that needs no instruction.
638 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
639 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
640 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
642 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
643 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
644 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
646 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
647 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
648 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
650 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
651 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
652 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
655 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
656 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
657 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
658 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
659 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
660 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
661 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
662 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
664 // vextractps - extract 32 bits from XMM
665 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
666 (ins VR128X:$src1, u8imm:$src2),
667 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
668 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
671 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
672 (ins f32mem:$dst, VR128X:$src1, u8imm:$src2),
673 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
674 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
675 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
677 //===---------------------------------------------------------------------===//
680 multiclass avx512_fp_broadcast<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
681 ValueType svt, X86VectorVTInfo _> {
682 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
683 (ins SrcRC:$src), "vbroadcast"## !subst("p", "s", _.Suffix),
684 "$src", "$src", (_.VT (OpNode (svt SrcRC:$src)))>,
688 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
689 (ins _.ScalarMemOp:$src),
690 "vbroadcast"##!subst("p", "s", _.Suffix), "$src", "$src",
691 (_.VT (OpNode (_.ScalarLdFrag addr:$src)))>,
696 multiclass avx512_fp_broadcast_vl<bits<8> opc, SDNode OpNode,
697 AVX512VLVectorVTInfo _> {
698 defm Z : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info512>,
701 let Predicates = [HasVLX] in {
702 defm Z256 : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info256>,
707 let ExeDomain = SSEPackedSingle in {
708 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, X86VBroadcast,
709 avx512vl_f32_info>, EVEX_CD8<32, CD8VT1>;
710 let Predicates = [HasVLX] in {
711 defm VBROADCASTSSZ128 : avx512_fp_broadcast<0x18, X86VBroadcast, VR128X,
712 v4f32, v4f32x_info>, EVEX_V128,
713 EVEX_CD8<32, CD8VT1>;
717 let ExeDomain = SSEPackedDouble in {
718 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, X86VBroadcast,
719 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VT1>;
722 // avx512_broadcast_pat introduces patterns for broadcast with a scalar argument.
723 // Later, we can canonize broadcast instructions before ISel phase and
724 // eliminate additional patterns on ISel.
725 // SrcRC_v and SrcRC_s are RegisterClasses for vector and scalar
726 // representations of source
727 multiclass avx512_broadcast_pat<string InstName, SDNode OpNode,
728 X86VectorVTInfo _, RegisterClass SrcRC_v,
729 RegisterClass SrcRC_s> {
730 def : Pat<(_.VT (OpNode (_.EltVT SrcRC_s:$src))),
731 (!cast<Instruction>(InstName##"r")
732 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
734 let AddedComplexity = 30 in {
735 def : Pat<(_.VT (vselect _.KRCWM:$mask,
736 (OpNode (_.EltVT SrcRC_s:$src)), _.RC:$src0)),
737 (!cast<Instruction>(InstName##"rk") _.RC:$src0, _.KRCWM:$mask,
738 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
740 def : Pat<(_.VT(vselect _.KRCWM:$mask,
741 (OpNode (_.EltVT SrcRC_s:$src)), _.ImmAllZerosV)),
742 (!cast<Instruction>(InstName##"rkz") _.KRCWM:$mask,
743 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
747 defm : avx512_broadcast_pat<"VBROADCASTSSZ", X86VBroadcast, v16f32_info,
749 defm : avx512_broadcast_pat<"VBROADCASTSDZ", X86VBroadcast, v8f64_info,
752 let Predicates = [HasVLX] in {
753 defm : avx512_broadcast_pat<"VBROADCASTSSZ256", X86VBroadcast,
754 v8f32x_info, VR128X, FR32X>;
755 defm : avx512_broadcast_pat<"VBROADCASTSSZ128", X86VBroadcast,
756 v4f32x_info, VR128X, FR32X>;
757 defm : avx512_broadcast_pat<"VBROADCASTSDZ256", X86VBroadcast,
758 v4f64x_info, VR128X, FR64X>;
761 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
762 (VBROADCASTSSZm addr:$src)>;
763 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
764 (VBROADCASTSDZm addr:$src)>;
766 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
767 (VBROADCASTSSZm addr:$src)>;
768 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
769 (VBROADCASTSDZm addr:$src)>;
771 multiclass avx512_int_broadcast_reg<bits<8> opc, X86VectorVTInfo _,
772 RegisterClass SrcRC> {
773 defm r : AVX512_maskable_in_asm<opc, MRMSrcReg, _, (outs _.RC:$dst),
774 (ins SrcRC:$src), "vpbroadcast"##_.Suffix,
775 "$src", "$src", []>, T8PD, EVEX;
778 multiclass avx512_int_broadcast_reg_vl<bits<8> opc, AVX512VLVectorVTInfo _,
779 RegisterClass SrcRC, Predicate prd> {
780 let Predicates = [prd] in
781 defm Z : avx512_int_broadcast_reg<opc, _.info512, SrcRC>, EVEX_V512;
782 let Predicates = [prd, HasVLX] in {
783 defm Z256 : avx512_int_broadcast_reg<opc, _.info256, SrcRC>, EVEX_V256;
784 defm Z128 : avx512_int_broadcast_reg<opc, _.info128, SrcRC>, EVEX_V128;
788 defm VPBROADCASTBr : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info, GR32,
790 defm VPBROADCASTWr : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info, GR32,
792 defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, GR32,
794 defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, GR64,
797 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
798 (VPBROADCASTDrZrkz VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
800 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
801 (VPBROADCASTQrZrkz VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
803 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
804 (VPBROADCASTDrZr GR32:$src)>;
805 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
806 (VPBROADCASTDrZrkz VK16WM:$mask, GR32:$src)>;
807 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
808 (VPBROADCASTQrZr GR64:$src)>;
809 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
810 (VPBROADCASTQrZrkz VK8WM:$mask, GR64:$src)>;
812 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
813 (VPBROADCASTDrZr GR32:$src)>;
814 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
815 (VPBROADCASTQrZr GR64:$src)>;
817 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
818 (v16i32 immAllZerosV), (i16 GR16:$mask))),
819 (VPBROADCASTDrZrkz (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
820 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
821 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
822 (VPBROADCASTQrZrkz (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
824 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
825 X86MemOperand x86memop, PatFrag ld_frag,
826 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
828 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
829 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
831 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
832 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
834 !strconcat(OpcodeStr,
835 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
837 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
840 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
841 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
843 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
844 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
846 !strconcat(OpcodeStr,
847 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
848 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
849 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
853 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
854 loadi32, VR512, v16i32, v4i32, VK16WM>,
855 EVEX_V512, EVEX_CD8<32, CD8VT1>;
856 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
857 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
858 EVEX_CD8<64, CD8VT1>;
860 multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
861 X86MemOperand x86memop, PatFrag ld_frag,
864 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
865 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
867 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
869 !strconcat(OpcodeStr,
870 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
875 defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
876 i128mem, loadv2i64, VK16WM>,
877 EVEX_V512, EVEX_CD8<32, CD8VT4>;
878 defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
879 i256mem, loadv4i64, VK16WM>, VEX_W,
880 EVEX_V512, EVEX_CD8<64, CD8VT4>;
882 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
883 (VPBROADCASTDZrr VR128X:$src)>;
884 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
885 (VPBROADCASTQZrr VR128X:$src)>;
887 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
888 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
889 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
890 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
892 def : Pat<(v16i32 (X86VBroadcast (v16i32 VR512:$src))),
893 (VPBROADCASTDZrr (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
894 def : Pat<(v8i64 (X86VBroadcast (v8i64 VR512:$src))),
895 (VPBROADCASTQZrr (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
897 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
898 (VBROADCASTSSZr VR128X:$src)>;
899 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
900 (VBROADCASTSDZr VR128X:$src)>;
902 // Provide fallback in case the load node that is used in the patterns above
903 // is used by additional users, which prevents the pattern selection.
904 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
905 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
906 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
907 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
910 let Predicates = [HasAVX512] in {
911 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
913 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
914 addr:$src)), sub_ymm)>;
916 //===----------------------------------------------------------------------===//
917 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
920 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
922 let Predicates = [HasCDI] in
923 def Zrr : AVX512XS8I<opc, MRMSrcReg, (outs VR512:$dst), (ins KRC:$src),
924 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
925 []>, EVEX, EVEX_V512;
927 let Predicates = [HasCDI, HasVLX] in {
928 def Z128rr : AVX512XS8I<opc, MRMSrcReg, (outs VR128:$dst), (ins KRC:$src),
929 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
930 []>, EVEX, EVEX_V128;
931 def Z256rr : AVX512XS8I<opc, MRMSrcReg, (outs VR256:$dst), (ins KRC:$src),
932 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
933 []>, EVEX, EVEX_V256;
937 let Predicates = [HasCDI] in {
938 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
940 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
944 //===----------------------------------------------------------------------===//
947 // -- immediate form --
948 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
950 let ExeDomain = _.ExeDomain in {
951 def ri : AVX512AIi8<opc, MRMSrcReg, (outs _.RC:$dst),
952 (ins _.RC:$src1, u8imm:$src2),
953 !strconcat(OpcodeStr,
954 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
956 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>,
958 def mi : AVX512AIi8<opc, MRMSrcMem, (outs _.RC:$dst),
959 (ins _.MemOp:$src1, u8imm:$src2),
960 !strconcat(OpcodeStr,
961 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
963 (_.VT (OpNode (_.LdFrag addr:$src1),
965 EVEX, EVEX_CD8<_.EltSize, CD8VF>;
969 multiclass avx512_permil<bits<8> OpcImm, bits<8> OpcVar, X86VectorVTInfo _,
970 X86VectorVTInfo Ctrl> :
971 avx512_perm_imm<OpcImm, "vpermil" # _.Suffix, X86VPermilpi, _> {
972 let ExeDomain = _.ExeDomain in {
973 def rr : AVX5128I<OpcVar, MRMSrcReg, (outs _.RC:$dst),
974 (ins _.RC:$src1, _.RC:$src2),
975 !strconcat("vpermil" # _.Suffix,
976 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
978 (_.VT (X86VPermilpv _.RC:$src1,
979 (Ctrl.VT Ctrl.RC:$src2))))]>,
981 def rm : AVX5128I<OpcVar, MRMSrcMem, (outs _.RC:$dst),
982 (ins _.RC:$src1, Ctrl.MemOp:$src2),
983 !strconcat("vpermil" # _.Suffix,
984 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
986 (_.VT (X86VPermilpv _.RC:$src1,
987 (Ctrl.VT (Ctrl.LdFrag addr:$src2)))))]>,
992 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", X86VPermi, v8i64_info>,
994 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", X86VPermi, v8f64_info>,
997 defm VPERMILPSZ : avx512_permil<0x04, 0x0C, v16f32_info, v16i32_info>,
999 defm VPERMILPDZ : avx512_permil<0x05, 0x0D, v8f64_info, v8i64_info>,
1002 def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
1003 (VPERMILPSZri VR512:$src1, imm:$imm)>;
1004 def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
1005 (VPERMILPDZri VR512:$src1, imm:$imm)>;
1007 // -- VPERM - register form --
1008 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
1009 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
1011 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
1012 (ins RC:$src1, RC:$src2),
1013 !strconcat(OpcodeStr,
1014 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1016 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
1018 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1019 (ins RC:$src1, x86memop:$src2),
1020 !strconcat(OpcodeStr,
1021 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1023 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
1027 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, loadv16i32, i512mem,
1028 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1029 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, loadv8i64, i512mem,
1030 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1031 let ExeDomain = SSEPackedSingle in
1032 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, loadv16f32, f512mem,
1033 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1034 let ExeDomain = SSEPackedDouble in
1035 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, loadv8f64, f512mem,
1036 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1038 // -- VPERM2I - 3 source operands form --
1039 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
1040 PatFrag mem_frag, X86MemOperand x86memop,
1041 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
1042 let Constraints = "$src1 = $dst" in {
1043 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
1044 (ins RC:$src1, RC:$src2, RC:$src3),
1045 !strconcat(OpcodeStr,
1046 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
1048 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
1051 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
1052 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
1053 !strconcat(OpcodeStr,
1054 "\t{$src3, $src2, $dst {${mask}}|"
1055 "$dst {${mask}}, $src2, $src3}"),
1056 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1057 (OpNode RC:$src1, RC:$src2,
1062 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
1063 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
1064 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
1065 !strconcat(OpcodeStr,
1066 "\t{$src3, $src2, $dst {${mask}} {z} |",
1067 "$dst {${mask}} {z}, $src2, $src3}"),
1068 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1069 (OpNode RC:$src1, RC:$src2,
1072 (v16i32 immAllZerosV))))))]>,
1075 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1076 (ins RC:$src1, RC:$src2, x86memop:$src3),
1077 !strconcat(OpcodeStr,
1078 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
1080 (OpVT (OpNode RC:$src1, RC:$src2,
1081 (mem_frag addr:$src3))))]>, EVEX_4V;
1083 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1084 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
1085 !strconcat(OpcodeStr,
1086 "\t{$src3, $src2, $dst {${mask}}|"
1087 "$dst {${mask}}, $src2, $src3}"),
1089 (OpVT (vselect KRC:$mask,
1090 (OpNode RC:$src1, RC:$src2,
1091 (mem_frag addr:$src3)),
1095 let AddedComplexity = 10 in // Prefer over the rrkz variant
1096 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1097 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
1098 !strconcat(OpcodeStr,
1099 "\t{$src3, $src2, $dst {${mask}} {z}|"
1100 "$dst {${mask}} {z}, $src2, $src3}"),
1102 (OpVT (vselect KRC:$mask,
1103 (OpNode RC:$src1, RC:$src2,
1104 (mem_frag addr:$src3)),
1106 (v16i32 immAllZerosV))))))]>,
1110 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, loadv16i32,
1111 i512mem, X86VPermiv3, v16i32, VK16WM>,
1112 EVEX_V512, EVEX_CD8<32, CD8VF>;
1113 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, loadv8i64,
1114 i512mem, X86VPermiv3, v8i64, VK8WM>,
1115 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1116 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, loadv16f32,
1117 i512mem, X86VPermiv3, v16f32, VK16WM>,
1118 EVEX_V512, EVEX_CD8<32, CD8VF>;
1119 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, loadv8f64,
1120 i512mem, X86VPermiv3, v8f64, VK8WM>,
1121 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1123 multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
1124 PatFrag mem_frag, X86MemOperand x86memop,
1125 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
1126 ValueType MaskVT, RegisterClass MRC> :
1127 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
1129 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
1130 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
1131 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
1133 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
1134 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
1135 (!cast<Instruction>(NAME#rrk) VR512:$src1,
1136 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
1139 defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, loadv16i32, i512mem,
1140 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
1141 EVEX_V512, EVEX_CD8<32, CD8VF>;
1142 defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, loadv8i64, i512mem,
1143 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
1144 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1145 defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, loadv16f32, i512mem,
1146 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
1147 EVEX_V512, EVEX_CD8<32, CD8VF>;
1148 defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, loadv8f64, i512mem,
1149 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
1150 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1152 //===----------------------------------------------------------------------===//
1153 // AVX-512 - BLEND using mask
1155 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1156 let ExeDomain = _.ExeDomain in {
1157 def rr : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1158 (ins _.RC:$src1, _.RC:$src2),
1159 !strconcat(OpcodeStr,
1160 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1162 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1163 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1164 !strconcat(OpcodeStr,
1165 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1166 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1167 (_.VT _.RC:$src2)))]>, EVEX_4V, EVEX_K;
1168 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1169 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1170 !strconcat(OpcodeStr,
1171 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1172 []>, EVEX_4V, EVEX_KZ;
1173 let mayLoad = 1 in {
1174 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1175 (ins _.RC:$src1, _.MemOp:$src2),
1176 !strconcat(OpcodeStr,
1177 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1178 []>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
1179 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1180 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1181 !strconcat(OpcodeStr,
1182 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1183 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1184 (_.VT (bitconvert (_.LdFrag addr:$src2)))))]>,
1185 EVEX_4V, EVEX_K, EVEX_CD8<_.EltSize, CD8VF>;
1186 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1187 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1188 !strconcat(OpcodeStr,
1189 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1190 []>, EVEX_4V, EVEX_KZ, EVEX_CD8<_.EltSize, CD8VF>;
1194 multiclass avx512_blendmask_rmb<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1196 def rmbk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1197 (ins _.KRCWM:$mask, _.RC:$src1, _.ScalarMemOp:$src2),
1198 !strconcat(OpcodeStr,
1199 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1200 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1201 [(set _.RC:$dst,(X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1202 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))]>,
1203 EVEX_4V, EVEX_K, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1205 def rmb : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1206 (ins _.RC:$src1, _.ScalarMemOp:$src2),
1207 !strconcat(OpcodeStr,
1208 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1209 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1210 []>, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1214 multiclass blendmask_dq <bits<8> opc, string OpcodeStr,
1215 AVX512VLVectorVTInfo VTInfo> {
1216 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>,
1217 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1219 let Predicates = [HasVLX] in {
1220 defm Z256 : avx512_blendmask<opc, OpcodeStr, VTInfo.info256>,
1221 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1222 defm Z128 : avx512_blendmask<opc, OpcodeStr, VTInfo.info128>,
1223 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1227 multiclass blendmask_bw <bits<8> opc, string OpcodeStr,
1228 AVX512VLVectorVTInfo VTInfo> {
1229 let Predicates = [HasBWI] in
1230 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1232 let Predicates = [HasBWI, HasVLX] in {
1233 defm Z256 : avx512_blendmask <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1234 defm Z128 : avx512_blendmask <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1239 defm VBLENDMPS : blendmask_dq <0x65, "vblendmps", avx512vl_f32_info>;
1240 defm VBLENDMPD : blendmask_dq <0x65, "vblendmpd", avx512vl_f64_info>, VEX_W;
1241 defm VPBLENDMD : blendmask_dq <0x64, "vpblendmd", avx512vl_i32_info>;
1242 defm VPBLENDMQ : blendmask_dq <0x64, "vpblendmq", avx512vl_i64_info>, VEX_W;
1243 defm VPBLENDMB : blendmask_bw <0x66, "vpblendmb", avx512vl_i8_info>;
1244 defm VPBLENDMW : blendmask_bw <0x66, "vpblendmw", avx512vl_i16_info>, VEX_W;
1247 let Predicates = [HasAVX512] in {
1248 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1249 (v8f32 VR256X:$src2))),
1251 (v16f32 (VBLENDMPSZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1252 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1253 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1255 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1256 (v8i32 VR256X:$src2))),
1258 (v16i32 (VPBLENDMDZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1259 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1260 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1262 //===----------------------------------------------------------------------===//
1263 // Compare Instructions
1264 //===----------------------------------------------------------------------===//
1266 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1267 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1268 SDNode OpNode, ValueType VT,
1269 PatFrag ld_frag, string Suffix> {
1270 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1271 (outs VK1:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1272 !strconcat("vcmp${cc}", Suffix,
1273 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1274 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
1275 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1276 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1277 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1278 !strconcat("vcmp${cc}", Suffix,
1279 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1280 [(set VK1:$dst, (OpNode (VT RC:$src1),
1281 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1282 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1283 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
1284 (outs VK1:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc),
1285 !strconcat("vcmp", Suffix,
1286 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1287 [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1289 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
1290 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, u8imm:$cc),
1291 !strconcat("vcmp", Suffix,
1292 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1293 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1297 let Predicates = [HasAVX512] in {
1298 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, X86cmpms, f32, loadf32, "ss">,
1300 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, X86cmpms, f64, loadf64, "sd">,
1304 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1305 X86VectorVTInfo _> {
1306 def rr : AVX512BI<opc, MRMSrcReg,
1307 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1308 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1309 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1310 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1312 def rm : AVX512BI<opc, MRMSrcMem,
1313 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1314 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1315 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1316 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1317 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1318 def rrk : AVX512BI<opc, MRMSrcReg,
1319 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1320 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1321 "$dst {${mask}}, $src1, $src2}"),
1322 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1323 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1324 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1326 def rmk : AVX512BI<opc, MRMSrcMem,
1327 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1328 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1329 "$dst {${mask}}, $src1, $src2}"),
1330 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1331 (OpNode (_.VT _.RC:$src1),
1333 (_.LdFrag addr:$src2))))))],
1334 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1337 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1338 X86VectorVTInfo _> :
1339 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1340 let mayLoad = 1 in {
1341 def rmb : AVX512BI<opc, MRMSrcMem,
1342 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1343 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1344 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1345 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1346 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1347 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1348 def rmbk : AVX512BI<opc, MRMSrcMem,
1349 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1350 _.ScalarMemOp:$src2),
1351 !strconcat(OpcodeStr,
1352 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1353 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1354 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1355 (OpNode (_.VT _.RC:$src1),
1357 (_.ScalarLdFrag addr:$src2)))))],
1358 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1362 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1363 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1364 let Predicates = [prd] in
1365 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1368 let Predicates = [prd, HasVLX] in {
1369 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1371 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1376 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1377 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1379 let Predicates = [prd] in
1380 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1383 let Predicates = [prd, HasVLX] in {
1384 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1386 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1391 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1392 avx512vl_i8_info, HasBWI>,
1395 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1396 avx512vl_i16_info, HasBWI>,
1397 EVEX_CD8<16, CD8VF>;
1399 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1400 avx512vl_i32_info, HasAVX512>,
1401 EVEX_CD8<32, CD8VF>;
1403 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1404 avx512vl_i64_info, HasAVX512>,
1405 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1407 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1408 avx512vl_i8_info, HasBWI>,
1411 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1412 avx512vl_i16_info, HasBWI>,
1413 EVEX_CD8<16, CD8VF>;
1415 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1416 avx512vl_i32_info, HasAVX512>,
1417 EVEX_CD8<32, CD8VF>;
1419 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1420 avx512vl_i64_info, HasAVX512>,
1421 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1423 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1424 (COPY_TO_REGCLASS (VPCMPGTDZrr
1425 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1426 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1428 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1429 (COPY_TO_REGCLASS (VPCMPEQDZrr
1430 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1431 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1433 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1434 X86VectorVTInfo _> {
1435 def rri : AVX512AIi8<opc, MRMSrcReg,
1436 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVX512ICC:$cc),
1437 !strconcat("vpcmp${cc}", Suffix,
1438 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1439 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1441 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1443 def rmi : AVX512AIi8<opc, MRMSrcMem,
1444 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVX512ICC:$cc),
1445 !strconcat("vpcmp${cc}", Suffix,
1446 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1447 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1448 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1450 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1451 def rrik : AVX512AIi8<opc, MRMSrcReg,
1452 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1454 !strconcat("vpcmp${cc}", Suffix,
1455 "\t{$src2, $src1, $dst {${mask}}|",
1456 "$dst {${mask}}, $src1, $src2}"),
1457 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1458 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1460 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1462 def rmik : AVX512AIi8<opc, MRMSrcMem,
1463 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1465 !strconcat("vpcmp${cc}", Suffix,
1466 "\t{$src2, $src1, $dst {${mask}}|",
1467 "$dst {${mask}}, $src1, $src2}"),
1468 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1469 (OpNode (_.VT _.RC:$src1),
1470 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1472 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1474 // Accept explicit immediate argument form instead of comparison code.
1475 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1476 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1477 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1478 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1479 "$dst, $src1, $src2, $cc}"),
1480 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1482 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1483 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1484 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1485 "$dst, $src1, $src2, $cc}"),
1486 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1487 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1488 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1490 !strconcat("vpcmp", Suffix,
1491 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1492 "$dst {${mask}}, $src1, $src2, $cc}"),
1493 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1495 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1496 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1498 !strconcat("vpcmp", Suffix,
1499 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1500 "$dst {${mask}}, $src1, $src2, $cc}"),
1501 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1505 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1506 X86VectorVTInfo _> :
1507 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1508 def rmib : AVX512AIi8<opc, MRMSrcMem,
1509 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1511 !strconcat("vpcmp${cc}", Suffix,
1512 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1513 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1514 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1515 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1517 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1518 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1519 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1520 _.ScalarMemOp:$src2, AVX512ICC:$cc),
1521 !strconcat("vpcmp${cc}", Suffix,
1522 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1523 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1524 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1525 (OpNode (_.VT _.RC:$src1),
1526 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1528 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1530 // Accept explicit immediate argument form instead of comparison code.
1531 let isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 1 in {
1532 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1533 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1535 !strconcat("vpcmp", Suffix,
1536 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1537 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1538 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1539 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1540 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1541 _.ScalarMemOp:$src2, u8imm:$cc),
1542 !strconcat("vpcmp", Suffix,
1543 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1544 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1545 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1549 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1550 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1551 let Predicates = [prd] in
1552 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1554 let Predicates = [prd, HasVLX] in {
1555 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1556 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1560 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1561 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1562 let Predicates = [prd] in
1563 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1566 let Predicates = [prd, HasVLX] in {
1567 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1569 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1574 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1575 HasBWI>, EVEX_CD8<8, CD8VF>;
1576 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1577 HasBWI>, EVEX_CD8<8, CD8VF>;
1579 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1580 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1581 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1582 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1584 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1585 HasAVX512>, EVEX_CD8<32, CD8VF>;
1586 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1587 HasAVX512>, EVEX_CD8<32, CD8VF>;
1589 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1590 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1591 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1592 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1594 // avx512_cmp_packed - compare packed instructions
1595 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
1596 X86MemOperand x86memop, ValueType vt,
1597 string suffix, Domain d> {
1598 def rri : AVX512PIi8<0xC2, MRMSrcReg,
1599 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1600 !strconcat("vcmp${cc}", suffix,
1601 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1602 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
1603 let hasSideEffects = 0 in
1604 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
1605 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1606 !strconcat("vcmp${cc}", suffix,
1607 "\t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
1609 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
1610 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1611 !strconcat("vcmp${cc}", suffix,
1612 "\t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1614 (X86cmpm (vt RC:$src1), (load addr:$src2), imm:$cc))], d>;
1616 // Accept explicit immediate argument form instead of comparison code.
1617 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1618 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
1619 (outs KRC:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc),
1620 !strconcat("vcmp", suffix,
1621 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1622 def rrib_alt: AVX512PIi8<0xC2, MRMSrcReg,
1623 (outs KRC:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc),
1624 !strconcat("vcmp", suffix,
1625 "\t{{sae}, $cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc, {sae}}"),
1628 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
1629 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, u8imm:$cc),
1630 !strconcat("vcmp", suffix,
1631 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1635 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
1636 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
1637 EVEX_CD8<32, CD8VF>;
1638 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
1639 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
1640 EVEX_CD8<64, CD8VF>;
1642 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1643 (COPY_TO_REGCLASS (VCMPPSZrri
1644 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1645 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1647 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1648 (COPY_TO_REGCLASS (VPCMPDZrri
1649 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1650 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1652 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1653 (COPY_TO_REGCLASS (VPCMPUDZrri
1654 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1655 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1658 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1659 (v16f32 VR512:$src2), i8immZExt5:$cc, (i16 -1),
1661 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
1662 (I8Imm imm:$cc)), GR16)>;
1664 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1665 (v8f64 VR512:$src2), i8immZExt5:$cc, (i8 -1),
1667 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
1668 (I8Imm imm:$cc)), GR8)>;
1670 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1671 (v16f32 VR512:$src2), i8immZExt5:$cc, (i16 -1),
1673 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1674 (I8Imm imm:$cc)), GR16)>;
1676 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1677 (v8f64 VR512:$src2), i8immZExt5:$cc, (i8 -1),
1679 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1680 (I8Imm imm:$cc)), GR8)>;
1682 // Mask register copy, including
1683 // - copy between mask registers
1684 // - load/store mask registers
1685 // - copy from GPR to mask register and vice versa
1687 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1688 string OpcodeStr, RegisterClass KRC,
1689 ValueType vvt, X86MemOperand x86memop> {
1690 let hasSideEffects = 0 in {
1691 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1692 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1694 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1695 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1696 [(set KRC:$dst, (vvt (load addr:$src)))]>;
1698 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1699 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1700 [(store KRC:$src, addr:$dst)]>;
1704 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1706 RegisterClass KRC, RegisterClass GRC> {
1707 let hasSideEffects = 0 in {
1708 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1709 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1710 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1711 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1715 let Predicates = [HasDQI] in
1716 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8mem>,
1717 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1720 let Predicates = [HasAVX512] in
1721 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
1722 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1725 let Predicates = [HasBWI] in {
1726 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1,i32mem>,
1728 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1732 let Predicates = [HasBWI] in {
1733 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64mem>,
1735 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1739 // GR from/to mask register
1740 let Predicates = [HasDQI] in {
1741 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1742 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1743 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1744 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1746 let Predicates = [HasAVX512] in {
1747 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1748 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1749 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1750 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1752 let Predicates = [HasBWI] in {
1753 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1754 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1756 let Predicates = [HasBWI] in {
1757 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1758 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1762 let Predicates = [HasDQI] in {
1763 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1764 (KMOVBmk addr:$dst, VK8:$src)>;
1765 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1766 (KMOVBkm addr:$src)>;
1768 let Predicates = [HasAVX512, NoDQI] in {
1769 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1770 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1771 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1772 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1774 let Predicates = [HasAVX512] in {
1775 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1776 (KMOVWmk addr:$dst, VK16:$src)>;
1777 def : Pat<(i1 (load addr:$src)),
1778 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
1779 def : Pat<(v16i1 (bitconvert (i16 (load addr:$src)))),
1780 (KMOVWkm addr:$src)>;
1782 let Predicates = [HasBWI] in {
1783 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1784 (KMOVDmk addr:$dst, VK32:$src)>;
1785 def : Pat<(v32i1 (bitconvert (i32 (load addr:$src)))),
1786 (KMOVDkm addr:$src)>;
1788 let Predicates = [HasBWI] in {
1789 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1790 (KMOVQmk addr:$dst, VK64:$src)>;
1791 def : Pat<(v64i1 (bitconvert (i64 (load addr:$src)))),
1792 (KMOVQkm addr:$src)>;
1795 let Predicates = [HasAVX512] in {
1796 def : Pat<(i1 (trunc (i64 GR64:$src))),
1797 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1800 def : Pat<(i1 (trunc (i32 GR32:$src))),
1801 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1803 def : Pat<(i1 (trunc (i8 GR8:$src))),
1805 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1807 def : Pat<(i1 (trunc (i16 GR16:$src))),
1809 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1812 def : Pat<(i32 (zext VK1:$src)),
1813 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1814 def : Pat<(i8 (zext VK1:$src)),
1817 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1818 def : Pat<(i64 (zext VK1:$src)),
1819 (AND64ri8 (SUBREG_TO_REG (i64 0),
1820 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1821 def : Pat<(i16 (zext VK1:$src)),
1823 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1825 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1826 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1827 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1828 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1830 let Predicates = [HasBWI] in {
1831 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1832 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1833 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1834 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1838 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1839 let Predicates = [HasAVX512] in {
1840 // GR from/to 8-bit mask without native support
1841 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1843 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1845 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1847 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1850 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1851 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1852 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1853 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1855 let Predicates = [HasBWI] in {
1856 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1857 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1858 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1859 (COPY_TO_REGCLASS VK64:$src, VK1)>;
1862 // Mask unary operation
1864 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1865 RegisterClass KRC, SDPatternOperator OpNode,
1867 let Predicates = [prd] in
1868 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1869 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1870 [(set KRC:$dst, (OpNode KRC:$src))]>;
1873 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1874 SDPatternOperator OpNode> {
1875 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1877 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1878 HasAVX512>, VEX, PS;
1879 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1880 HasBWI>, VEX, PD, VEX_W;
1881 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1882 HasBWI>, VEX, PS, VEX_W;
1885 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
1887 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1888 let Predicates = [HasAVX512] in
1889 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1891 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1892 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1894 defm : avx512_mask_unop_int<"knot", "KNOT">;
1896 let Predicates = [HasDQI] in
1897 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1898 let Predicates = [HasAVX512] in
1899 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1900 let Predicates = [HasBWI] in
1901 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1902 let Predicates = [HasBWI] in
1903 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1905 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1906 let Predicates = [HasAVX512, NoDQI] in {
1907 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1908 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1909 def : Pat<(not VK8:$src),
1911 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1913 def : Pat<(xor VK4:$src1, (v4i1 immAllOnesV)),
1914 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK4:$src1, VK16)), VK4)>;
1915 def : Pat<(xor VK2:$src1, (v2i1 immAllOnesV)),
1916 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK2:$src1, VK16)), VK2)>;
1918 // Mask binary operation
1919 // - KAND, KANDN, KOR, KXNOR, KXOR
1920 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1921 RegisterClass KRC, SDPatternOperator OpNode,
1922 Predicate prd, bit IsCommutable> {
1923 let Predicates = [prd], isCommutable = IsCommutable in
1924 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1925 !strconcat(OpcodeStr,
1926 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1927 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1930 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1931 SDPatternOperator OpNode, bit IsCommutable> {
1932 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1933 HasDQI, IsCommutable>, VEX_4V, VEX_L, PD;
1934 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1935 HasAVX512, IsCommutable>, VEX_4V, VEX_L, PS;
1936 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1937 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PD;
1938 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1939 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PS;
1942 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1943 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1945 defm KAND : avx512_mask_binop_all<0x41, "kand", and, 1>;
1946 defm KOR : avx512_mask_binop_all<0x45, "kor", or, 1>;
1947 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor, 1>;
1948 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor, 1>;
1949 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn, 0>;
1951 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1952 let Predicates = [HasAVX512] in
1953 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1954 (i16 GR16:$src1), (i16 GR16:$src2)),
1955 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1956 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1957 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1960 defm : avx512_mask_binop_int<"kand", "KAND">;
1961 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1962 defm : avx512_mask_binop_int<"kor", "KOR">;
1963 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1964 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1966 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1967 // With AVX512F, 8-bit mask is promoted to 16-bit mask,
1968 // for the DQI set, this type is legal and KxxxB instruction is used
1969 let Predicates = [NoDQI] in
1970 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1972 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1973 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1975 // All types smaller than 8 bits require conversion anyway
1976 def : Pat<(OpNode VK1:$src1, VK1:$src2),
1977 (COPY_TO_REGCLASS (Inst
1978 (COPY_TO_REGCLASS VK1:$src1, VK16),
1979 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1980 def : Pat<(OpNode VK2:$src1, VK2:$src2),
1981 (COPY_TO_REGCLASS (Inst
1982 (COPY_TO_REGCLASS VK2:$src1, VK16),
1983 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK1)>;
1984 def : Pat<(OpNode VK4:$src1, VK4:$src2),
1985 (COPY_TO_REGCLASS (Inst
1986 (COPY_TO_REGCLASS VK4:$src1, VK16),
1987 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK1)>;
1990 defm : avx512_binop_pat<and, KANDWrr>;
1991 defm : avx512_binop_pat<andn, KANDNWrr>;
1992 defm : avx512_binop_pat<or, KORWrr>;
1993 defm : avx512_binop_pat<xnor, KXNORWrr>;
1994 defm : avx512_binop_pat<xor, KXORWrr>;
1996 def : Pat<(xor (xor VK16:$src1, VK16:$src2), (v16i1 immAllOnesV)),
1997 (KXNORWrr VK16:$src1, VK16:$src2)>;
1998 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
1999 (KXNORBrr VK8:$src1, VK8:$src2)>;
2000 def : Pat<(xor (xor VK32:$src1, VK32:$src2), (v32i1 immAllOnesV)),
2001 (KXNORDrr VK32:$src1, VK32:$src2)>;
2002 def : Pat<(xor (xor VK64:$src1, VK64:$src2), (v64i1 immAllOnesV)),
2003 (KXNORQrr VK64:$src1, VK64:$src2)>;
2005 let Predicates = [NoDQI] in
2006 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2007 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK8:$src1, VK16),
2008 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2010 def : Pat<(xor (xor VK4:$src1, VK4:$src2), (v4i1 immAllOnesV)),
2011 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK4:$src1, VK16),
2012 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK4)>;
2014 def : Pat<(xor (xor VK2:$src1, VK2:$src2), (v2i1 immAllOnesV)),
2015 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK2:$src1, VK16),
2016 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK2)>;
2018 def : Pat<(xor (xor VK1:$src1, VK1:$src2), (i1 1)),
2019 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
2020 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2023 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
2024 RegisterClass KRC> {
2025 let Predicates = [HasAVX512] in
2026 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
2027 !strconcat(OpcodeStr,
2028 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2031 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
2032 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
2036 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
2037 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
2038 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
2039 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
2042 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
2043 let Predicates = [HasAVX512] in
2044 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
2045 (i16 GR16:$src1), (i16 GR16:$src2)),
2046 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
2047 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
2048 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
2050 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
2053 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2055 let Predicates = [HasAVX512], Defs = [EFLAGS] in
2056 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
2057 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2058 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
2061 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2062 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
2064 let Predicates = [HasDQI] in
2065 defm B : avx512_mask_testop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
2067 let Predicates = [HasBWI] in {
2068 defm Q : avx512_mask_testop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
2070 defm D : avx512_mask_testop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
2075 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
2078 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2080 let Predicates = [HasAVX512] in
2081 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, u8imm:$imm),
2082 !strconcat(OpcodeStr,
2083 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
2084 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
2087 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
2089 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
2091 let Predicates = [HasDQI] in
2092 defm B : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
2094 let Predicates = [HasBWI] in {
2095 defm Q : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
2097 let Predicates = [HasDQI] in
2098 defm D : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
2103 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
2104 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
2106 // Mask setting all 0s or 1s
2107 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
2108 let Predicates = [HasAVX512] in
2109 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
2110 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
2111 [(set KRC:$dst, (VT Val))]>;
2114 multiclass avx512_mask_setop_w<PatFrag Val> {
2115 defm B : avx512_mask_setop<VK8, v8i1, Val>;
2116 defm W : avx512_mask_setop<VK16, v16i1, Val>;
2117 defm D : avx512_mask_setop<VK32, v32i1, Val>;
2118 defm Q : avx512_mask_setop<VK64, v64i1, Val>;
2121 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
2122 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
2124 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2125 let Predicates = [HasAVX512] in {
2126 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
2127 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
2128 def : Pat<(v4i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK4)>;
2129 def : Pat<(v2i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK2)>;
2130 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
2131 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
2132 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
2134 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
2135 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
2137 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
2138 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
2140 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
2141 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
2143 let Predicates = [HasVLX] in {
2144 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
2145 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
2146 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2147 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
2148 def : Pat<(v4i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2149 (v4i1 (COPY_TO_REGCLASS VK2:$src, VK4))>;
2150 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2151 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
2152 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2153 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
2156 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
2157 (v8i1 (COPY_TO_REGCLASS
2158 (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16),
2159 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2161 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
2162 (v8i1 (COPY_TO_REGCLASS
2163 (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16),
2164 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2166 def : Pat<(v4i1 (X86vshli VK4:$src, (i8 imm:$imm))),
2167 (v4i1 (COPY_TO_REGCLASS
2168 (KSHIFTLWri (COPY_TO_REGCLASS VK4:$src, VK16),
2169 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2171 def : Pat<(v4i1 (X86vsrli VK4:$src, (i8 imm:$imm))),
2172 (v4i1 (COPY_TO_REGCLASS
2173 (KSHIFTRWri (COPY_TO_REGCLASS VK4:$src, VK16),
2174 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2176 //===----------------------------------------------------------------------===//
2177 // AVX-512 - Aligned and unaligned load and store
2181 multiclass avx512_load<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2182 PatFrag ld_frag, PatFrag mload,
2183 bit IsReMaterializable = 1> {
2184 let hasSideEffects = 0 in {
2185 def rr : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst), (ins _.RC:$src),
2186 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
2188 def rrkz : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2189 (ins _.KRCWM:$mask, _.RC:$src),
2190 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2191 "${dst} {${mask}} {z}, $src}"), [], _.ExeDomain>,
2194 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
2195 SchedRW = [WriteLoad] in
2196 def rm : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst), (ins _.MemOp:$src),
2197 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2198 [(set _.RC:$dst, (_.VT (bitconvert (ld_frag addr:$src))))],
2201 let Constraints = "$src0 = $dst" in {
2202 def rrk : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2203 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src1),
2204 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2205 "${dst} {${mask}}, $src1}"),
2206 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2208 (_.VT _.RC:$src0))))], _.ExeDomain>,
2210 let mayLoad = 1, SchedRW = [WriteLoad] in
2211 def rmk : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2212 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src1),
2213 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2214 "${dst} {${mask}}, $src1}"),
2215 [(set _.RC:$dst, (_.VT
2216 (vselect _.KRCWM:$mask,
2217 (_.VT (bitconvert (ld_frag addr:$src1))),
2218 (_.VT _.RC:$src0))))], _.ExeDomain>, EVEX, EVEX_K;
2220 let mayLoad = 1, SchedRW = [WriteLoad] in
2221 def rmkz : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2222 (ins _.KRCWM:$mask, _.MemOp:$src),
2223 OpcodeStr #"\t{$src, ${dst} {${mask}} {z}|"#
2224 "${dst} {${mask}} {z}, $src}",
2225 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2226 (_.VT (bitconvert (ld_frag addr:$src))), _.ImmAllZerosV)))],
2227 _.ExeDomain>, EVEX, EVEX_KZ;
2229 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, undef)),
2230 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2232 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, _.ImmAllZerosV)),
2233 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2235 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src0))),
2236 (!cast<Instruction>(NAME#_.ZSuffix##rmk) _.RC:$src0,
2237 _.KRCWM:$mask, addr:$ptr)>;
2240 multiclass avx512_alignedload_vl<bits<8> opc, string OpcodeStr,
2241 AVX512VLVectorVTInfo _,
2243 bit IsReMaterializable = 1> {
2244 let Predicates = [prd] in
2245 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.AlignedLdFrag,
2246 masked_load_aligned512, IsReMaterializable>, EVEX_V512;
2248 let Predicates = [prd, HasVLX] in {
2249 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.AlignedLdFrag,
2250 masked_load_aligned256, IsReMaterializable>, EVEX_V256;
2251 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.AlignedLdFrag,
2252 masked_load_aligned128, IsReMaterializable>, EVEX_V128;
2256 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr,
2257 AVX512VLVectorVTInfo _,
2259 bit IsReMaterializable = 1> {
2260 let Predicates = [prd] in
2261 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.LdFrag,
2262 masked_load_unaligned, IsReMaterializable>, EVEX_V512;
2264 let Predicates = [prd, HasVLX] in {
2265 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.LdFrag,
2266 masked_load_unaligned, IsReMaterializable>, EVEX_V256;
2267 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.LdFrag,
2268 masked_load_unaligned, IsReMaterializable>, EVEX_V128;
2272 multiclass avx512_store<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2273 PatFrag st_frag, PatFrag mstore> {
2274 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2275 def rr_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst), (ins _.RC:$src),
2276 OpcodeStr # "\t{$src, $dst|$dst, $src}", [],
2278 let Constraints = "$src1 = $dst" in
2279 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2280 (ins _.RC:$src1, _.KRCWM:$mask, _.RC:$src2),
2282 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}",
2283 [], _.ExeDomain>, EVEX, EVEX_K;
2284 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2285 (ins _.KRCWM:$mask, _.RC:$src),
2287 "\t{$src, ${dst} {${mask}} {z}|" #
2288 "${dst} {${mask}} {z}, $src}",
2289 [], _.ExeDomain>, EVEX, EVEX_KZ;
2291 let mayStore = 1 in {
2292 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins _.MemOp:$dst, _.RC:$src),
2293 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2294 [(st_frag (_.VT _.RC:$src), addr:$dst)], _.ExeDomain>, EVEX;
2295 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2296 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
2297 OpcodeStr # "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}",
2298 [], _.ExeDomain>, EVEX, EVEX_K;
2301 def: Pat<(mstore addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src)),
2302 (!cast<Instruction>(NAME#_.ZSuffix##mrk) addr:$ptr,
2303 _.KRCWM:$mask, _.RC:$src)>;
2307 multiclass avx512_store_vl< bits<8> opc, string OpcodeStr,
2308 AVX512VLVectorVTInfo _, Predicate prd> {
2309 let Predicates = [prd] in
2310 defm Z : avx512_store<opc, OpcodeStr, _.info512, store,
2311 masked_store_unaligned>, EVEX_V512;
2313 let Predicates = [prd, HasVLX] in {
2314 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, store,
2315 masked_store_unaligned>, EVEX_V256;
2316 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, store,
2317 masked_store_unaligned>, EVEX_V128;
2321 multiclass avx512_alignedstore_vl<bits<8> opc, string OpcodeStr,
2322 AVX512VLVectorVTInfo _, Predicate prd> {
2323 let Predicates = [prd] in
2324 defm Z : avx512_store<opc, OpcodeStr, _.info512, alignedstore512,
2325 masked_store_aligned512>, EVEX_V512;
2327 let Predicates = [prd, HasVLX] in {
2328 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, alignedstore256,
2329 masked_store_aligned256>, EVEX_V256;
2330 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, alignedstore,
2331 masked_store_aligned128>, EVEX_V128;
2335 defm VMOVAPS : avx512_alignedload_vl<0x28, "vmovaps", avx512vl_f32_info,
2337 avx512_alignedstore_vl<0x29, "vmovaps", avx512vl_f32_info,
2338 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2340 defm VMOVAPD : avx512_alignedload_vl<0x28, "vmovapd", avx512vl_f64_info,
2342 avx512_alignedstore_vl<0x29, "vmovapd", avx512vl_f64_info,
2343 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2345 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", avx512vl_f32_info, HasAVX512>,
2346 avx512_store_vl<0x11, "vmovups", avx512vl_f32_info, HasAVX512>,
2347 PS, EVEX_CD8<32, CD8VF>;
2349 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", avx512vl_f64_info, HasAVX512, 0>,
2350 avx512_store_vl<0x11, "vmovupd", avx512vl_f64_info, HasAVX512>,
2351 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2353 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2354 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2355 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2357 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2358 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2359 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2361 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2362 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2363 (VMOVAPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2365 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2366 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2367 (VMOVAPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2369 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2370 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2371 (VMOVAPDZrm addr:$ptr)>;
2373 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2374 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
2375 (VMOVAPSZrm addr:$ptr)>;
2377 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2379 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2381 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2383 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2386 def: Pat<(int_x86_avx512_mask_store_ps_512 addr:$ptr, (v16f32 VR512:$src),
2388 (VMOVAPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2390 def: Pat<(int_x86_avx512_mask_store_pd_512 addr:$ptr, (v8f64 VR512:$src),
2392 (VMOVAPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2395 let Predicates = [HasAVX512, NoVLX] in {
2396 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src)),
2397 (VMOVUPSZmrk addr:$ptr,
2398 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2399 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2401 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2402 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmkz
2403 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2405 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src0))),
2406 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmk
2407 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src0, sub_ymm),
2408 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2411 defm VMOVDQA32 : avx512_alignedload_vl<0x6F, "vmovdqa32", avx512vl_i32_info,
2413 avx512_alignedstore_vl<0x7F, "vmovdqa32", avx512vl_i32_info,
2414 HasAVX512>, PD, EVEX_CD8<32, CD8VF>;
2416 defm VMOVDQA64 : avx512_alignedload_vl<0x6F, "vmovdqa64", avx512vl_i64_info,
2418 avx512_alignedstore_vl<0x7F, "vmovdqa64", avx512vl_i64_info,
2419 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2421 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", avx512vl_i8_info, HasBWI>,
2422 avx512_store_vl<0x7F, "vmovdqu8", avx512vl_i8_info,
2423 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2425 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", avx512vl_i16_info, HasBWI>,
2426 avx512_store_vl<0x7F, "vmovdqu16", avx512vl_i16_info,
2427 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2429 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", avx512vl_i32_info, HasAVX512>,
2430 avx512_store_vl<0x7F, "vmovdqu32", avx512vl_i32_info,
2431 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2433 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", avx512vl_i64_info, HasAVX512>,
2434 avx512_store_vl<0x7F, "vmovdqu64", avx512vl_i64_info,
2435 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2437 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2438 (v16i32 immAllZerosV), GR16:$mask)),
2439 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2441 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2442 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2443 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2445 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2447 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2449 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2451 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2454 let AddedComplexity = 20 in {
2455 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2456 (bc_v8i64 (v16i32 immAllZerosV)))),
2457 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2459 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2460 (v8i64 VR512:$src))),
2461 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2464 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2465 (v16i32 immAllZerosV))),
2466 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2468 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2469 (v16i32 VR512:$src))),
2470 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2473 let Predicates = [HasAVX512, NoVLX] in {
2474 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2475 (VMOVDQU32Zmrk addr:$ptr,
2476 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2477 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2479 def: Pat<(v8i32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2480 (v8i32 (EXTRACT_SUBREG (v16i32 (VMOVDQU32Zrmkz
2481 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2484 // Move Int Doubleword to Packed Double Int
2486 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2487 "vmovd\t{$src, $dst|$dst, $src}",
2489 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2491 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2492 "vmovd\t{$src, $dst|$dst, $src}",
2494 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2495 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2496 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2497 "vmovq\t{$src, $dst|$dst, $src}",
2499 (v2i64 (scalar_to_vector GR64:$src)))],
2500 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2501 let isCodeGenOnly = 1 in {
2502 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2503 "vmovq\t{$src, $dst|$dst, $src}",
2504 [(set FR64:$dst, (bitconvert GR64:$src))],
2505 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2506 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2507 "vmovq\t{$src, $dst|$dst, $src}",
2508 [(set GR64:$dst, (bitconvert FR64:$src))],
2509 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2511 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2512 "vmovq\t{$src, $dst|$dst, $src}",
2513 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2514 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2515 EVEX_CD8<64, CD8VT1>;
2517 // Move Int Doubleword to Single Scalar
2519 let isCodeGenOnly = 1 in {
2520 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2521 "vmovd\t{$src, $dst|$dst, $src}",
2522 [(set FR32X:$dst, (bitconvert GR32:$src))],
2523 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2525 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2526 "vmovd\t{$src, $dst|$dst, $src}",
2527 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2528 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2531 // Move doubleword from xmm register to r/m32
2533 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2534 "vmovd\t{$src, $dst|$dst, $src}",
2535 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2536 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2538 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2539 (ins i32mem:$dst, VR128X:$src),
2540 "vmovd\t{$src, $dst|$dst, $src}",
2541 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2542 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2543 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2545 // Move quadword from xmm1 register to r/m64
2547 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2548 "vmovq\t{$src, $dst|$dst, $src}",
2549 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2551 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2552 Requires<[HasAVX512, In64BitMode]>;
2554 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2555 (ins i64mem:$dst, VR128X:$src),
2556 "vmovq\t{$src, $dst|$dst, $src}",
2557 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2558 addr:$dst)], IIC_SSE_MOVDQ>,
2559 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2560 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2562 // Move Scalar Single to Double Int
2564 let isCodeGenOnly = 1 in {
2565 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2567 "vmovd\t{$src, $dst|$dst, $src}",
2568 [(set GR32:$dst, (bitconvert FR32X:$src))],
2569 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2570 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2571 (ins i32mem:$dst, FR32X:$src),
2572 "vmovd\t{$src, $dst|$dst, $src}",
2573 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2574 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2577 // Move Quadword Int to Packed Quadword Int
2579 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2581 "vmovq\t{$src, $dst|$dst, $src}",
2583 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2584 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2586 //===----------------------------------------------------------------------===//
2587 // AVX-512 MOVSS, MOVSD
2588 //===----------------------------------------------------------------------===//
2590 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2591 SDNode OpNode, ValueType vt,
2592 X86MemOperand x86memop, PatFrag mem_pat> {
2593 let hasSideEffects = 0 in {
2594 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2595 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2596 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2597 (scalar_to_vector RC:$src2))))],
2598 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2599 let Constraints = "$src1 = $dst" in
2600 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2601 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2603 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2604 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2605 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2606 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2607 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2609 let mayStore = 1 in {
2610 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2611 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2612 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2614 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2615 !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2616 [], IIC_SSE_MOV_S_MR>,
2617 EVEX, VEX_LIG, EVEX_K;
2619 } //hasSideEffects = 0
2622 let ExeDomain = SSEPackedSingle in
2623 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2624 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2626 let ExeDomain = SSEPackedDouble in
2627 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2628 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2630 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2631 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2632 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2634 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2635 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2636 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2638 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2639 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2640 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2642 // For the disassembler
2643 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2644 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2645 (ins VR128X:$src1, FR32X:$src2),
2646 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2648 XS, EVEX_4V, VEX_LIG;
2649 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2650 (ins VR128X:$src1, FR64X:$src2),
2651 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2653 XD, EVEX_4V, VEX_LIG, VEX_W;
2656 let Predicates = [HasAVX512] in {
2657 let AddedComplexity = 15 in {
2658 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2659 // MOVS{S,D} to the lower bits.
2660 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2661 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2662 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2663 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2664 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2665 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2666 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2667 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2669 // Move low f32 and clear high bits.
2670 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2671 (SUBREG_TO_REG (i32 0),
2672 (VMOVSSZrr (v4f32 (V_SET0)),
2673 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2674 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2675 (SUBREG_TO_REG (i32 0),
2676 (VMOVSSZrr (v4i32 (V_SET0)),
2677 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2680 let AddedComplexity = 20 in {
2681 // MOVSSrm zeros the high parts of the register; represent this
2682 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2683 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2684 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2685 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2686 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2687 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2688 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2690 // MOVSDrm zeros the high parts of the register; represent this
2691 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2692 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2693 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2694 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2695 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2696 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2697 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2698 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2699 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2700 def : Pat<(v2f64 (X86vzload addr:$src)),
2701 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2703 // Represent the same patterns above but in the form they appear for
2705 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2706 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
2707 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
2708 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2709 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2710 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2711 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2712 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2713 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2715 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2716 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2717 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2718 FR32X:$src)), sub_xmm)>;
2719 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2720 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2721 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2722 FR64X:$src)), sub_xmm)>;
2723 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2724 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
2725 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
2727 // Move low f64 and clear high bits.
2728 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2729 (SUBREG_TO_REG (i32 0),
2730 (VMOVSDZrr (v2f64 (V_SET0)),
2731 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2733 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2734 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2735 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2737 // Extract and store.
2738 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2740 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2741 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2743 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2745 // Shuffle with VMOVSS
2746 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2747 (VMOVSSZrr (v4i32 VR128X:$src1),
2748 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2749 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2750 (VMOVSSZrr (v4f32 VR128X:$src1),
2751 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2754 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2755 (SUBREG_TO_REG (i32 0),
2756 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2757 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2759 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2760 (SUBREG_TO_REG (i32 0),
2761 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2762 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2765 // Shuffle with VMOVSD
2766 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2767 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2768 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2769 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2770 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2771 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2772 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2773 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2776 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2777 (SUBREG_TO_REG (i32 0),
2778 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2779 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2781 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2782 (SUBREG_TO_REG (i32 0),
2783 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2784 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2787 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2788 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2789 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2790 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2791 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2792 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2793 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2794 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2797 let AddedComplexity = 15 in
2798 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2800 "vmovq\t{$src, $dst|$dst, $src}",
2801 [(set VR128X:$dst, (v2i64 (X86vzmovl
2802 (v2i64 VR128X:$src))))],
2803 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2805 let AddedComplexity = 20 in
2806 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2808 "vmovq\t{$src, $dst|$dst, $src}",
2809 [(set VR128X:$dst, (v2i64 (X86vzmovl
2810 (loadv2i64 addr:$src))))],
2811 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2812 EVEX_CD8<8, CD8VT8>;
2814 let Predicates = [HasAVX512] in {
2815 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2816 let AddedComplexity = 20 in {
2817 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2818 (VMOVDI2PDIZrm addr:$src)>;
2819 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2820 (VMOV64toPQIZrr GR64:$src)>;
2821 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2822 (VMOVDI2PDIZrr GR32:$src)>;
2824 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2825 (VMOVDI2PDIZrm addr:$src)>;
2826 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2827 (VMOVDI2PDIZrm addr:$src)>;
2828 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2829 (VMOVZPQILo2PQIZrm addr:$src)>;
2830 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2831 (VMOVZPQILo2PQIZrr VR128X:$src)>;
2832 def : Pat<(v2i64 (X86vzload addr:$src)),
2833 (VMOVZPQILo2PQIZrm addr:$src)>;
2836 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2837 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2838 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2839 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2840 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2841 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2842 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2845 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2846 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2848 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2849 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2851 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2852 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2854 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2855 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2857 //===----------------------------------------------------------------------===//
2858 // AVX-512 - Non-temporals
2859 //===----------------------------------------------------------------------===//
2860 let SchedRW = [WriteLoad] in {
2861 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2862 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2863 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2864 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2865 EVEX_CD8<64, CD8VF>;
2867 let Predicates = [HasAVX512, HasVLX] in {
2868 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2870 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2871 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2872 EVEX_CD8<64, CD8VF>;
2874 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2876 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2877 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2878 EVEX_CD8<64, CD8VF>;
2882 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2883 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2884 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2885 let SchedRW = [WriteStore], mayStore = 1,
2886 AddedComplexity = 400 in
2887 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2888 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2889 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2892 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2893 string elty, string elsz, string vsz512,
2894 string vsz256, string vsz128, Domain d,
2895 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2896 let Predicates = [prd] in
2897 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2898 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2899 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2902 let Predicates = [prd, HasVLX] in {
2903 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2904 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2905 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2908 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2909 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2910 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2915 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2916 "i", "64", "8", "4", "2", SSEPackedInt,
2917 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2919 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2920 "f", "64", "8", "4", "2", SSEPackedDouble,
2921 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2923 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2924 "f", "32", "16", "8", "4", SSEPackedSingle,
2925 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2927 //===----------------------------------------------------------------------===//
2928 // AVX-512 - Integer arithmetic
2930 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2931 X86VectorVTInfo _, OpndItins itins,
2932 bit IsCommutable = 0> {
2933 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
2934 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
2935 "$src2, $src1", "$src1, $src2",
2936 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
2937 "", itins.rr, IsCommutable>,
2938 AVX512BIBase, EVEX_4V;
2941 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2942 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
2943 "$src2, $src1", "$src1, $src2",
2944 (_.VT (OpNode _.RC:$src1,
2945 (bitconvert (_.LdFrag addr:$src2)))),
2947 AVX512BIBase, EVEX_4V;
2950 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
2951 X86VectorVTInfo _, OpndItins itins,
2952 bit IsCommutable = 0> :
2953 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
2955 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2956 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
2957 "${src2}"##_.BroadcastStr##", $src1",
2958 "$src1, ${src2}"##_.BroadcastStr,
2959 (_.VT (OpNode _.RC:$src1,
2961 (_.ScalarLdFrag addr:$src2)))),
2963 AVX512BIBase, EVEX_4V, EVEX_B;
2966 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2967 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2968 Predicate prd, bit IsCommutable = 0> {
2969 let Predicates = [prd] in
2970 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2971 IsCommutable>, EVEX_V512;
2973 let Predicates = [prd, HasVLX] in {
2974 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2975 IsCommutable>, EVEX_V256;
2976 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2977 IsCommutable>, EVEX_V128;
2981 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2982 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2983 Predicate prd, bit IsCommutable = 0> {
2984 let Predicates = [prd] in
2985 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2986 IsCommutable>, EVEX_V512;
2988 let Predicates = [prd, HasVLX] in {
2989 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2990 IsCommutable>, EVEX_V256;
2991 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2992 IsCommutable>, EVEX_V128;
2996 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
2997 OpndItins itins, Predicate prd,
2998 bit IsCommutable = 0> {
2999 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
3000 itins, prd, IsCommutable>,
3001 VEX_W, EVEX_CD8<64, CD8VF>;
3004 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
3005 OpndItins itins, Predicate prd,
3006 bit IsCommutable = 0> {
3007 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
3008 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
3011 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
3012 OpndItins itins, Predicate prd,
3013 bit IsCommutable = 0> {
3014 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
3015 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
3018 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
3019 OpndItins itins, Predicate prd,
3020 bit IsCommutable = 0> {
3021 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
3022 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
3025 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
3026 SDNode OpNode, OpndItins itins, Predicate prd,
3027 bit IsCommutable = 0> {
3028 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr, OpNode, itins, prd,
3031 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr, OpNode, itins, prd,
3035 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
3036 SDNode OpNode, OpndItins itins, Predicate prd,
3037 bit IsCommutable = 0> {
3038 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr, OpNode, itins, prd,
3041 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr, OpNode, itins, prd,
3045 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
3046 bits<8> opc_d, bits<8> opc_q,
3047 string OpcodeStr, SDNode OpNode,
3048 OpndItins itins, bit IsCommutable = 0> {
3049 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
3050 itins, HasAVX512, IsCommutable>,
3051 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
3052 itins, HasBWI, IsCommutable>;
3055 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, OpndItins itins,
3056 SDNode OpNode,X86VectorVTInfo _Src,
3057 X86VectorVTInfo _Dst, bit IsCommutable = 0> {
3058 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3059 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3060 "$src2, $src1","$src1, $src2",
3062 (_Src.VT _Src.RC:$src1),
3063 (_Src.VT _Src.RC:$src2))),
3064 "",itins.rr, IsCommutable>,
3065 AVX512BIBase, EVEX_4V;
3066 let mayLoad = 1 in {
3067 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3068 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3069 "$src2, $src1", "$src1, $src2",
3070 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3071 (bitconvert (_Src.LdFrag addr:$src2)))),
3073 AVX512BIBase, EVEX_4V;
3075 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3076 (ins _Src.RC:$src1, _Dst.ScalarMemOp:$src2),
3078 "${src2}"##_Dst.BroadcastStr##", $src1",
3079 "$src1, ${src2}"##_Dst.BroadcastStr,
3080 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3081 (_Dst.VT (X86VBroadcast
3082 (_Dst.ScalarLdFrag addr:$src2)))))),
3084 AVX512BIBase, EVEX_4V, EVEX_B;
3088 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
3089 SSE_INTALU_ITINS_P, 1>;
3090 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
3091 SSE_INTALU_ITINS_P, 0>;
3092 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmull", mul,
3093 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3094 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmull", mul,
3095 SSE_INTALU_ITINS_P, HasBWI, 1>;
3096 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmull", mul,
3097 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
3100 multiclass avx512_binop_all<bits<8> opc, string OpcodeStr, OpndItins itins,
3101 SDNode OpNode, bit IsCommutable = 0> {
3103 defm NAME#Z : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3104 v16i32_info, v8i64_info, IsCommutable>,
3105 EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
3106 let Predicates = [HasVLX] in {
3107 defm NAME#Z256 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3108 v8i32x_info, v4i64x_info, IsCommutable>,
3109 EVEX_V256, EVEX_CD8<64, CD8VF>, VEX_W;
3110 defm NAME#Z128 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3111 v4i32x_info, v2i64x_info, IsCommutable>,
3112 EVEX_V128, EVEX_CD8<64, CD8VF>, VEX_W;
3116 defm VPMULDQ : avx512_binop_all<0x28, "vpmuldq", SSE_INTALU_ITINS_P,
3118 defm VPMULUDQ : avx512_binop_all<0xF4, "vpmuludq", SSE_INTMUL_ITINS_P,
3121 multiclass avx512_packs_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3122 X86VectorVTInfo _Src, X86VectorVTInfo _Dst> {
3123 let mayLoad = 1 in {
3124 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3125 (ins _Src.RC:$src1, _Src.ScalarMemOp:$src2),
3127 "${src2}"##_Src.BroadcastStr##", $src1",
3128 "$src1, ${src2}"##_Src.BroadcastStr,
3129 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3130 (_Src.VT (X86VBroadcast
3131 (_Src.ScalarLdFrag addr:$src2)))))),
3133 EVEX_4V, EVEX_B, EVEX_CD8<_Src.EltSize, CD8VF>;
3137 multiclass avx512_packs_rm<bits<8> opc, string OpcodeStr,
3138 SDNode OpNode,X86VectorVTInfo _Src,
3139 X86VectorVTInfo _Dst> {
3140 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3141 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3142 "$src2, $src1","$src1, $src2",
3144 (_Src.VT _Src.RC:$src1),
3145 (_Src.VT _Src.RC:$src2))),
3146 "">, EVEX_CD8<_Src.EltSize, CD8VF>, EVEX_4V;
3147 let mayLoad = 1 in {
3148 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3149 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3150 "$src2, $src1", "$src1, $src2",
3151 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3152 (bitconvert (_Src.LdFrag addr:$src2)))),
3153 "">, EVEX_4V, EVEX_CD8<_Src.EltSize, CD8VF>;
3157 multiclass avx512_packs_all_i32_i16<bits<8> opc, string OpcodeStr,
3159 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i32_info,
3161 avx512_packs_rmb<opc, OpcodeStr, OpNode, v16i32_info,
3162 v32i16_info>, EVEX_V512;
3163 let Predicates = [HasVLX] in {
3164 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i32x_info,
3166 avx512_packs_rmb<opc, OpcodeStr, OpNode, v8i32x_info,
3167 v16i16x_info>, EVEX_V256;
3168 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v4i32x_info,
3170 avx512_packs_rmb<opc, OpcodeStr, OpNode, v4i32x_info,
3171 v8i16x_info>, EVEX_V128;
3174 multiclass avx512_packs_all_i16_i8<bits<8> opc, string OpcodeStr,
3176 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v32i16_info,
3177 v64i8_info>, EVEX_V512;
3178 let Predicates = [HasVLX] in {
3179 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i16x_info,
3180 v32i8x_info>, EVEX_V256;
3181 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i16x_info,
3182 v16i8x_info>, EVEX_V128;
3185 let Predicates = [HasBWI] in {
3186 defm VPACKSSDW : avx512_packs_all_i32_i16<0x6B, "vpackssdw", X86Packss>, PD;
3187 defm VPACKUSDW : avx512_packs_all_i32_i16<0x2b, "vpackusdw", X86Packus>, T8PD;
3188 defm VPACKSSWB : avx512_packs_all_i16_i8 <0x63, "vpacksswb", X86Packss>, AVX512BIBase, VEX_W;
3189 defm VPACKUSWB : avx512_packs_all_i16_i8 <0x67, "vpackuswb", X86Packus>, AVX512BIBase, VEX_W;
3192 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxs", X86smax,
3193 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3194 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxs", X86smax,
3195 SSE_INTALU_ITINS_P, HasBWI, 1>;
3196 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", X86smax,
3197 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3199 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxu", X86umax,
3200 SSE_INTALU_ITINS_P, HasBWI, 1>;
3201 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxu", X86umax,
3202 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3203 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", X86umax,
3204 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3206 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpmins", X86smin,
3207 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3208 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpmins", X86smin,
3209 SSE_INTALU_ITINS_P, HasBWI, 1>;
3210 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", X86smin,
3211 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3213 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminu", X86umin,
3214 SSE_INTALU_ITINS_P, HasBWI, 1>;
3215 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminu", X86umin,
3216 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3217 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", X86umin,
3218 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3220 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
3221 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3222 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
3223 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
3224 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3225 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
3226 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
3227 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3228 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
3229 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
3230 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3231 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
3232 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
3233 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3234 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
3235 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
3236 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3237 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
3238 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
3239 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3240 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
3241 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
3242 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3243 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
3244 //===----------------------------------------------------------------------===//
3245 // AVX-512 - Unpack Instructions
3246 //===----------------------------------------------------------------------===//
3248 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
3249 PatFrag mem_frag, RegisterClass RC,
3250 X86MemOperand x86memop, string asm,
3252 def rr : AVX512PI<opc, MRMSrcReg,
3253 (outs RC:$dst), (ins RC:$src1, RC:$src2),
3255 (vt (OpNode RC:$src1, RC:$src2)))],
3257 def rm : AVX512PI<opc, MRMSrcMem,
3258 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3260 (vt (OpNode RC:$src1,
3261 (bitconvert (mem_frag addr:$src2)))))],
3265 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, loadv8f64,
3266 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3267 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3268 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, loadv8f64,
3269 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3270 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3271 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, loadv8f64,
3272 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3273 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3274 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, loadv8f64,
3275 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3276 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3278 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
3279 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
3280 X86MemOperand x86memop> {
3281 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3282 (ins RC:$src1, RC:$src2),
3283 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3284 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
3285 IIC_SSE_UNPCK>, EVEX_4V;
3286 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3287 (ins RC:$src1, x86memop:$src2),
3288 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3289 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
3290 (bitconvert (memop_frag addr:$src2)))))],
3291 IIC_SSE_UNPCK>, EVEX_4V;
3293 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
3294 VR512, loadv16i32, i512mem>, EVEX_V512,
3295 EVEX_CD8<32, CD8VF>;
3296 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
3297 VR512, loadv8i64, i512mem>, EVEX_V512,
3298 VEX_W, EVEX_CD8<64, CD8VF>;
3299 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
3300 VR512, loadv16i32, i512mem>, EVEX_V512,
3301 EVEX_CD8<32, CD8VF>;
3302 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
3303 VR512, loadv8i64, i512mem>, EVEX_V512,
3304 VEX_W, EVEX_CD8<64, CD8VF>;
3305 //===----------------------------------------------------------------------===//
3309 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
3310 SDNode OpNode, PatFrag mem_frag,
3311 X86MemOperand x86memop, ValueType OpVT> {
3312 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
3313 (ins RC:$src1, u8imm:$src2),
3314 !strconcat(OpcodeStr,
3315 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3317 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
3319 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
3320 (ins x86memop:$src1, u8imm:$src2),
3321 !strconcat(OpcodeStr,
3322 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3324 (OpVT (OpNode (mem_frag addr:$src1),
3325 (i8 imm:$src2))))]>, EVEX;
3328 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, loadv16i32,
3329 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
3331 //===----------------------------------------------------------------------===//
3332 // AVX-512 Logical Instructions
3333 //===----------------------------------------------------------------------===//
3335 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
3336 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3337 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
3338 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3339 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
3340 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3341 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
3342 SSE_INTALU_ITINS_P, HasAVX512, 0>;
3344 //===----------------------------------------------------------------------===//
3345 // AVX-512 FP arithmetic
3346 //===----------------------------------------------------------------------===//
3347 multiclass avx512_fp_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3348 SDNode OpNode, SDNode VecNode, OpndItins itins,
3351 defm rr_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3352 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3353 "$src2, $src1", "$src1, $src2",
3354 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3355 (i32 FROUND_CURRENT)),
3356 "", itins.rr, IsCommutable>;
3358 defm rm_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
3359 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3360 "$src2, $src1", "$src1, $src2",
3361 (VecNode (_.VT _.RC:$src1),
3362 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
3363 (i32 FROUND_CURRENT)),
3364 "", itins.rm, IsCommutable>;
3365 let isCodeGenOnly = 1, isCommutable = IsCommutable,
3366 Predicates = [HasAVX512] in {
3367 def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst),
3368 (ins _.FRC:$src1, _.FRC:$src2),
3369 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3370 [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))],
3372 def rm : I< opc, MRMSrcMem, (outs _.FRC:$dst),
3373 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
3374 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3375 [(set _.FRC:$dst, (OpNode _.FRC:$src1,
3376 (_.ScalarLdFrag addr:$src2)))], itins.rr>;
3380 multiclass avx512_fp_scalar_round<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3381 SDNode VecNode, OpndItins itins, bit IsCommutable> {
3383 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3384 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
3385 "$rc, $src2, $src1", "$src1, $src2, $rc",
3386 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3387 (i32 imm:$rc)), "", itins.rr, IsCommutable>,
3390 multiclass avx512_fp_scalar_sae<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3391 SDNode VecNode, OpndItins itins, bit IsCommutable> {
3393 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3394 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3395 "$src2, $src1", "$src1, $src2",
3396 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3397 (i32 FROUND_NO_EXC)), "{sae}">, EVEX_B;
3400 multiclass avx512_binop_s_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
3402 SizeItins itins, bit IsCommutable> {
3403 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3404 itins.s, IsCommutable>,
3405 avx512_fp_scalar_round<opc, OpcodeStr#"ss", f32x_info, VecNode,
3406 itins.s, IsCommutable>,
3407 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3408 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3409 itins.d, IsCommutable>,
3410 avx512_fp_scalar_round<opc, OpcodeStr#"sd", f64x_info, VecNode,
3411 itins.d, IsCommutable>,
3412 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3415 multiclass avx512_binop_s_sae<bits<8> opc, string OpcodeStr, SDNode OpNode,
3417 SizeItins itins, bit IsCommutable> {
3418 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3419 itins.s, IsCommutable>,
3420 avx512_fp_scalar_sae<opc, OpcodeStr#"ss", f32x_info, VecNode,
3421 itins.s, IsCommutable>,
3422 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3423 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3424 itins.d, IsCommutable>,
3425 avx512_fp_scalar_sae<opc, OpcodeStr#"sd", f64x_info, VecNode,
3426 itins.d, IsCommutable>,
3427 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3429 defm VADD : avx512_binop_s_round<0x58, "vadd", fadd, X86faddRnd, SSE_ALU_ITINS_S, 1>;
3430 defm VMUL : avx512_binop_s_round<0x59, "vmul", fmul, X86fmulRnd, SSE_ALU_ITINS_S, 1>;
3431 defm VSUB : avx512_binop_s_round<0x5C, "vsub", fsub, X86fsubRnd, SSE_ALU_ITINS_S, 0>;
3432 defm VDIV : avx512_binop_s_round<0x5E, "vdiv", fdiv, X86fdivRnd, SSE_ALU_ITINS_S, 0>;
3433 defm VMIN : avx512_binop_s_sae <0x5D, "vmin", X86fmin, X86fminRnd, SSE_ALU_ITINS_S, 1>;
3434 defm VMAX : avx512_binop_s_sae <0x5F, "vmax", X86fmax, X86fmaxRnd, SSE_ALU_ITINS_S, 1>;
3436 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3437 X86VectorVTInfo _, bit IsCommutable> {
3438 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3439 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3440 "$src2, $src1", "$src1, $src2",
3441 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
3442 let mayLoad = 1 in {
3443 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3444 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3445 "$src2, $src1", "$src1, $src2",
3446 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3447 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3448 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3449 "${src2}"##_.BroadcastStr##", $src1",
3450 "$src1, ${src2}"##_.BroadcastStr,
3451 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3452 (_.ScalarLdFrag addr:$src2))))>,
3457 multiclass avx512_fp_round_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3458 X86VectorVTInfo _, bit IsCommutable> {
3459 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3460 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr##_.Suffix,
3461 "$rc, $src2, $src1", "$src1, $src2, $rc",
3462 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 imm:$rc)))>,
3463 EVEX_4V, EVEX_B, EVEX_RC;
3466 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3467 bit IsCommutable = 0> {
3468 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3469 IsCommutable>, EVEX_V512, PS,
3470 EVEX_CD8<32, CD8VF>;
3471 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3472 IsCommutable>, EVEX_V512, PD, VEX_W,
3473 EVEX_CD8<64, CD8VF>;
3475 // Define only if AVX512VL feature is present.
3476 let Predicates = [HasVLX] in {
3477 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3478 IsCommutable>, EVEX_V128, PS,
3479 EVEX_CD8<32, CD8VF>;
3480 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3481 IsCommutable>, EVEX_V256, PS,
3482 EVEX_CD8<32, CD8VF>;
3483 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3484 IsCommutable>, EVEX_V128, PD, VEX_W,
3485 EVEX_CD8<64, CD8VF>;
3486 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3487 IsCommutable>, EVEX_V256, PD, VEX_W,
3488 EVEX_CD8<64, CD8VF>;
3492 multiclass avx512_fp_binop_p_round<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3493 defm PSZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info, 0>,
3494 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3495 defm PDZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info, 0>,
3496 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3499 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>,
3500 avx512_fp_binop_p_round<0x58, "vadd", X86faddRnd>;
3501 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>,
3502 avx512_fp_binop_p_round<0x59, "vmul", X86fmulRnd>;
3503 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>,
3504 avx512_fp_binop_p_round<0x5C, "vsub", X86fsubRnd>;
3505 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>,
3506 avx512_fp_binop_p_round<0x5E, "vdiv", X86fdivRnd>;
3507 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>;
3508 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>;
3509 let Predicates = [HasDQI] in {
3510 defm VAND : avx512_fp_binop_p<0x54, "vand", X86fand, 1>;
3511 defm VANDN : avx512_fp_binop_p<0x55, "vandn", X86fandn, 0>;
3512 defm VOR : avx512_fp_binop_p<0x56, "vor", X86for, 1>;
3513 defm VXOR : avx512_fp_binop_p<0x57, "vxor", X86fxor, 1>;
3515 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
3516 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3517 (i16 -1), FROUND_CURRENT)),
3518 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
3520 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
3521 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3522 (i8 -1), FROUND_CURRENT)),
3523 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
3525 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
3526 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3527 (i16 -1), FROUND_CURRENT)),
3528 (VMINPSZrr VR512:$src1, VR512:$src2)>;
3530 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
3531 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3532 (i8 -1), FROUND_CURRENT)),
3533 (VMINPDZrr VR512:$src1, VR512:$src2)>;
3534 //===----------------------------------------------------------------------===//
3535 // AVX-512 VPTESTM instructions
3536 //===----------------------------------------------------------------------===//
3538 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, SDNode OpNode,
3539 X86VectorVTInfo _> {
3540 defm rr : AVX512_maskable_cmp<opc, MRMSrcReg, _, (outs _.KRC:$dst),
3541 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3542 "$src2, $src1", "$src1, $src2",
3543 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>,
3546 defm rm : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3547 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3548 "$src2, $src1", "$src1, $src2",
3549 (OpNode (_.VT _.RC:$src1),
3550 (_.VT (bitconvert (_.LdFrag addr:$src2))))>,
3552 EVEX_CD8<_.EltSize, CD8VF>;
3555 multiclass avx512_vptest_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3556 X86VectorVTInfo _> {
3558 defm rmb : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3559 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3560 "${src2}"##_.BroadcastStr##", $src1",
3561 "$src1, ${src2}"##_.BroadcastStr,
3562 (OpNode (_.VT _.RC:$src1), (_.VT (X86VBroadcast
3563 (_.ScalarLdFrag addr:$src2))))>,
3564 EVEX_B, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
3566 multiclass avx512_vptest_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3567 AVX512VLVectorVTInfo _> {
3568 let Predicates = [HasAVX512] in
3569 defm Z : avx512_vptest<opc, OpcodeStr, OpNode, _.info512>,
3570 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3572 let Predicates = [HasAVX512, HasVLX] in {
3573 defm Z256 : avx512_vptest<opc, OpcodeStr, OpNode, _.info256>,
3574 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
3575 defm Z128 : avx512_vptest<opc, OpcodeStr, OpNode, _.info128>,
3576 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
3580 multiclass avx512_vptest_dq<bits<8> opc, string OpcodeStr, SDNode OpNode> {
3581 defm D : avx512_vptest_dq_sizes<opc, OpcodeStr#"d", OpNode,
3583 defm Q : avx512_vptest_dq_sizes<opc, OpcodeStr#"q", OpNode,
3584 avx512vl_i64_info>, VEX_W;
3587 multiclass avx512_vptest_wb<bits<8> opc, string OpcodeStr,
3589 let Predicates = [HasBWI] in {
3590 defm WZ: avx512_vptest<opc, OpcodeStr#"w", OpNode, v32i16_info>,
3592 defm BZ: avx512_vptest<opc, OpcodeStr#"b", OpNode, v64i8_info>,
3595 let Predicates = [HasVLX, HasBWI] in {
3597 defm WZ256: avx512_vptest<opc, OpcodeStr#"w", OpNode, v16i16x_info>,
3599 defm WZ128: avx512_vptest<opc, OpcodeStr#"w", OpNode, v8i16x_info>,
3601 defm BZ256: avx512_vptest<opc, OpcodeStr#"b", OpNode, v32i8x_info>,
3603 defm BZ128: avx512_vptest<opc, OpcodeStr#"b", OpNode, v16i8x_info>,
3608 multiclass avx512_vptest_all_forms<bits<8> opc_wb, bits<8> opc_dq, string OpcodeStr,
3610 avx512_vptest_wb <opc_wb, OpcodeStr, OpNode>,
3611 avx512_vptest_dq<opc_dq, OpcodeStr, OpNode>;
3613 defm VPTESTM : avx512_vptest_all_forms<0x26, 0x27, "vptestm", X86testm>, T8PD;
3614 defm VPTESTNM : avx512_vptest_all_forms<0x26, 0x27, "vptestnm", X86testnm>, T8XS;
3616 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3617 (v16i32 VR512:$src2), (i16 -1))),
3618 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3620 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3621 (v8i64 VR512:$src2), (i8 -1))),
3622 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3624 //===----------------------------------------------------------------------===//
3625 // AVX-512 Shift instructions
3626 //===----------------------------------------------------------------------===//
3627 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3628 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3629 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
3630 (ins _.RC:$src1, u8imm:$src2), OpcodeStr,
3631 "$src2, $src1", "$src1, $src2",
3632 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
3633 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIi8Base, EVEX_4V;
3635 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3636 (ins _.MemOp:$src1, u8imm:$src2), OpcodeStr,
3637 "$src2, $src1", "$src1, $src2",
3638 (_.VT (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
3640 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIi8Base, EVEX_4V;
3643 multiclass avx512_shift_rmbi<bits<8> opc, Format ImmFormM,
3644 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3646 defm mbi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3647 (ins _.ScalarMemOp:$src1, u8imm:$src2), OpcodeStr,
3648 "$src2, ${src1}"##_.BroadcastStr, "${src1}"##_.BroadcastStr##", $src2",
3649 (_.VT (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src1)), (i8 imm:$src2))),
3650 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIi8Base, EVEX_4V, EVEX_B;
3653 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3654 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3655 // src2 is always 128-bit
3656 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3657 (ins _.RC:$src1, VR128X:$src2), OpcodeStr,
3658 "$src2, $src1", "$src1, $src2",
3659 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))),
3660 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V;
3661 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3662 (ins _.RC:$src1, i128mem:$src2), OpcodeStr,
3663 "$src2, $src1", "$src1, $src2",
3664 (_.VT (OpNode _.RC:$src1, (bc_frag (loadv2i64 addr:$src2)))),
3665 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase,
3669 multiclass avx512_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3670 ValueType SrcVT, PatFrag bc_frag,
3671 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
3672 let Predicates = [prd] in
3673 defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3674 VTInfo.info512>, EVEX_V512,
3675 EVEX_CD8<VTInfo.info512.EltSize, CD8VQ> ;
3676 let Predicates = [prd, HasVLX] in {
3677 defm Z256 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3678 VTInfo.info256>, EVEX_V256,
3679 EVEX_CD8<VTInfo.info256.EltSize, CD8VH>;
3680 defm Z128 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3681 VTInfo.info128>, EVEX_V128,
3682 EVEX_CD8<VTInfo.info128.EltSize, CD8VF>;
3686 multiclass avx512_shift_types<bits<8> opcd, bits<8> opcq, bits<8> opcw,
3687 string OpcodeStr, SDNode OpNode> {
3688 defm D : avx512_shift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,
3689 avx512vl_i32_info, HasAVX512>;
3690 defm Q : avx512_shift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,
3691 avx512vl_i64_info, HasAVX512>, VEX_W;
3692 defm W : avx512_shift_sizes<opcw, OpcodeStr#"w", OpNode, v8i16, bc_v8i16,
3693 avx512vl_i16_info, HasBWI>;
3696 multiclass avx512_shift_rmi_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
3697 string OpcodeStr, SDNode OpNode,
3698 AVX512VLVectorVTInfo VTInfo> {
3699 let Predicates = [HasAVX512] in
3700 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3702 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3703 VTInfo.info512>, EVEX_V512;
3704 let Predicates = [HasAVX512, HasVLX] in {
3705 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3707 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3708 VTInfo.info256>, EVEX_V256;
3709 defm Z128: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3711 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3712 VTInfo.info128>, EVEX_V128;
3716 multiclass avx512_shift_rmi_w<bits<8> opcw,
3717 Format ImmFormR, Format ImmFormM,
3718 string OpcodeStr, SDNode OpNode> {
3719 let Predicates = [HasBWI] in
3720 defm WZ: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3721 v32i16_info>, EVEX_V512;
3722 let Predicates = [HasVLX, HasBWI] in {
3723 defm WZ256: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3724 v16i16x_info>, EVEX_V256;
3725 defm WZ128: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3726 v8i16x_info>, EVEX_V128;
3730 multiclass avx512_shift_rmi_dq<bits<8> opcd, bits<8> opcq,
3731 Format ImmFormR, Format ImmFormM,
3732 string OpcodeStr, SDNode OpNode> {
3733 defm D: avx512_shift_rmi_sizes<opcd, ImmFormR, ImmFormM, OpcodeStr#"d", OpNode,
3734 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
3735 defm Q: avx512_shift_rmi_sizes<opcq, ImmFormR, ImmFormM, OpcodeStr#"q", OpNode,
3736 avx512vl_i64_info>, EVEX_CD8<64, CD8VF>, VEX_W;
3739 defm VPSRL : avx512_shift_rmi_dq<0x72, 0x73, MRM2r, MRM2m, "vpsrl", X86vsrli>,
3740 avx512_shift_rmi_w<0x71, MRM2r, MRM2m, "vpsrlw", X86vsrli>;
3742 defm VPSLL : avx512_shift_rmi_dq<0x72, 0x73, MRM6r, MRM6m, "vpsll", X86vshli>,
3743 avx512_shift_rmi_w<0x71, MRM6r, MRM6m, "vpsllw", X86vshli>;
3745 defm VPSRA : avx512_shift_rmi_dq<0x72, 0x73, MRM4r, MRM4m, "vpsra", X86vsrai>,
3746 avx512_shift_rmi_w<0x71, MRM4r, MRM4m, "vpsraw", X86vsrai>;
3748 defm VPROR : avx512_shift_rmi_dq<0x72, 0x72, MRM0r, MRM0m, "vpror", rotr>;
3749 defm VPROL : avx512_shift_rmi_dq<0x72, 0x72, MRM1r, MRM1m, "vprol", rotl>;
3751 defm VPSLL : avx512_shift_types<0xF2, 0xF3, 0xF1, "vpsll", X86vshl>;
3752 defm VPSRA : avx512_shift_types<0xE2, 0xE2, 0xE1, "vpsra", X86vsra>;
3753 defm VPSRL : avx512_shift_types<0xD2, 0xD3, 0xD1, "vpsrl", X86vsrl>;
3755 //===-------------------------------------------------------------------===//
3756 // Variable Bit Shifts
3757 //===-------------------------------------------------------------------===//
3758 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3759 X86VectorVTInfo _> {
3760 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3761 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3762 "$src2, $src1", "$src1, $src2",
3763 (_.VT (OpNode _.RC:$src1, (_.VT _.RC:$src2))),
3764 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX5128IBase, EVEX_4V;
3766 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3767 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3768 "$src2, $src1", "$src1, $src2",
3769 (_.VT (OpNode _.RC:$src1, (_.LdFrag addr:$src2))),
3770 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_4V,
3771 EVEX_CD8<_.EltSize, CD8VF>;
3774 multiclass avx512_var_shift_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3775 X86VectorVTInfo _> {
3777 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3778 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3779 "${src2}"##_.BroadcastStr##", $src1",
3780 "$src1, ${src2}"##_.BroadcastStr,
3781 (_.VT (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3782 (_.ScalarLdFrag addr:$src2))))),
3783 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_B,
3784 EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
3786 multiclass avx512_var_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3787 AVX512VLVectorVTInfo _> {
3788 let Predicates = [HasAVX512] in
3789 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
3790 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3792 let Predicates = [HasAVX512, HasVLX] in {
3793 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
3794 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
3795 defm Z128 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info128>,
3796 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
3800 multiclass avx512_var_shift_types<bits<8> opc, string OpcodeStr,
3802 defm D : avx512_var_shift_sizes<opc, OpcodeStr#"d", OpNode,
3804 defm Q : avx512_var_shift_sizes<opc, OpcodeStr#"q", OpNode,
3805 avx512vl_i64_info>, VEX_W;
3808 multiclass avx512_var_shift_w<bits<8> opc, string OpcodeStr,
3810 let Predicates = [HasBWI] in
3811 defm WZ: avx512_var_shift<opc, OpcodeStr, OpNode, v32i16_info>,
3813 let Predicates = [HasVLX, HasBWI] in {
3815 defm WZ256: avx512_var_shift<opc, OpcodeStr, OpNode, v16i16x_info>,
3817 defm WZ128: avx512_var_shift<opc, OpcodeStr, OpNode, v8i16x_info>,
3822 defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl>,
3823 avx512_var_shift_w<0x12, "vpsllvw", shl>;
3824 defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra>,
3825 avx512_var_shift_w<0x11, "vpsravw", sra>;
3826 defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl>,
3827 avx512_var_shift_w<0x10, "vpsrlvw", srl>;
3828 defm VPRORV : avx512_var_shift_types<0x14, "vprorv", rotr>;
3829 defm VPROLV : avx512_var_shift_types<0x15, "vprolv", rotl>;
3831 //===----------------------------------------------------------------------===//
3832 // AVX-512 - MOVDDUP
3833 //===----------------------------------------------------------------------===//
3835 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3836 X86MemOperand x86memop, PatFrag memop_frag> {
3837 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3838 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3839 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3840 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3841 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3843 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3846 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, loadv8f64>,
3847 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3848 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3849 (VMOVDDUPZrm addr:$src)>;
3851 //===---------------------------------------------------------------------===//
3852 // Replicate Single FP - MOVSHDUP and MOVSLDUP
3853 //===---------------------------------------------------------------------===//
3854 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3855 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3856 X86MemOperand x86memop> {
3857 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3858 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3859 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3861 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3862 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3863 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3866 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3867 v16f32, VR512, loadv16f32, f512mem>, EVEX_V512,
3868 EVEX_CD8<32, CD8VF>;
3869 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3870 v16f32, VR512, loadv16f32, f512mem>, EVEX_V512,
3871 EVEX_CD8<32, CD8VF>;
3873 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3874 def : Pat<(v16i32 (X86Movshdup (loadv16i32 addr:$src))),
3875 (VMOVSHDUPZrm addr:$src)>;
3876 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3877 def : Pat<(v16i32 (X86Movsldup (loadv16i32 addr:$src))),
3878 (VMOVSLDUPZrm addr:$src)>;
3880 //===----------------------------------------------------------------------===//
3881 // Move Low to High and High to Low packed FP Instructions
3882 //===----------------------------------------------------------------------===//
3883 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3884 (ins VR128X:$src1, VR128X:$src2),
3885 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3886 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3887 IIC_SSE_MOV_LH>, EVEX_4V;
3888 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3889 (ins VR128X:$src1, VR128X:$src2),
3890 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3891 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3892 IIC_SSE_MOV_LH>, EVEX_4V;
3894 let Predicates = [HasAVX512] in {
3896 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3897 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3898 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3899 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
3902 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3903 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3906 //===----------------------------------------------------------------------===//
3907 // FMA - Fused Multiply Operations
3910 let Constraints = "$src1 = $dst" in {
3911 // Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
3912 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
3913 SDPatternOperator OpNode = null_frag> {
3914 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3915 (ins _.RC:$src2, _.RC:$src3),
3916 OpcodeStr, "$src3, $src2", "$src2, $src3",
3917 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
3921 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
3922 (ins _.RC:$src2, _.MemOp:$src3),
3923 OpcodeStr, "$src3, $src2", "$src2, $src3",
3924 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (_.LdFrag addr:$src3)))>,
3927 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
3928 (ins _.RC:$src2, _.ScalarMemOp:$src3),
3929 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
3930 !strconcat("$src2, ${src3}", _.BroadcastStr ),
3932 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))>,
3933 AVX512FMA3Base, EVEX_B;
3935 } // Constraints = "$src1 = $dst"
3937 let Constraints = "$src1 = $dst" in {
3938 // Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
3939 multiclass avx512_fma3_round_rrb<bits<8> opc, string OpcodeStr,
3941 SDPatternOperator OpNode> {
3942 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3943 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
3944 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
3945 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
3946 AVX512FMA3Base, EVEX_B, EVEX_RC;
3948 } // Constraints = "$src1 = $dst"
3950 multiclass avx512_fma3_round_forms<bits<8> opc213, string OpcodeStr,
3951 X86VectorVTInfo VTI, SDPatternOperator OpNode> {
3952 defm v213r : avx512_fma3_round_rrb<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
3953 VTI, OpNode>, EVEX_CD8<VTI.EltSize, CD8VF>;
3956 multiclass avx512_fma3p_forms<bits<8> opc213, bits<8> opc231,
3957 string OpcodeStr, X86VectorVTInfo VTI,
3958 SDPatternOperator OpNode> {
3959 defm v213r : avx512_fma3p_rm<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
3960 VTI, OpNode>, EVEX_CD8<VTI.EltSize, CD8VF>;
3961 defm v231r : avx512_fma3p_rm<opc231, !strconcat(OpcodeStr, "231", VTI.Suffix),
3962 VTI>, EVEX_CD8<VTI.EltSize, CD8VF>;
3965 multiclass avx512_fma3p<bits<8> opc213, bits<8> opc231,
3967 SDPatternOperator OpNode,
3968 SDPatternOperator OpNodeRnd> {
3969 let ExeDomain = SSEPackedSingle in {
3970 defm NAME##PSZ : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3971 v16f32_info, OpNode>,
3972 avx512_fma3_round_forms<opc213, OpcodeStr,
3973 v16f32_info, OpNodeRnd>, EVEX_V512;
3974 defm NAME##PSZ256 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3975 v8f32x_info, OpNode>, EVEX_V256;
3976 defm NAME##PSZ128 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3977 v4f32x_info, OpNode>, EVEX_V128;
3979 let ExeDomain = SSEPackedDouble in {
3980 defm NAME##PDZ : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3981 v8f64_info, OpNode>,
3982 avx512_fma3_round_forms<opc213, OpcodeStr, v8f64_info,
3983 OpNodeRnd>, EVEX_V512, VEX_W;
3984 defm NAME##PDZ256 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3985 v4f64x_info, OpNode>,
3987 defm NAME##PDZ128 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3988 v2f64x_info, OpNode>,
3993 defm VFMADD : avx512_fma3p<0xA8, 0xB8, "vfmadd", X86Fmadd, X86FmaddRnd>;
3994 defm VFMSUB : avx512_fma3p<0xAA, 0xBA, "vfmsub", X86Fmsub, X86FmsubRnd>;
3995 defm VFMADDSUB : avx512_fma3p<0xA6, 0xB6, "vfmaddsub", X86Fmaddsub, X86FmaddsubRnd>;
3996 defm VFMSUBADD : avx512_fma3p<0xA7, 0xB7, "vfmsubadd", X86Fmsubadd, X86FmsubaddRnd>;
3997 defm VFNMADD : avx512_fma3p<0xAC, 0xBC, "vfnmadd", X86Fnmadd, X86FnmaddRnd>;
3998 defm VFNMSUB : avx512_fma3p<0xAE, 0xBE, "vfnmsub", X86Fnmsub, X86FnmsubRnd>;
4000 let Constraints = "$src1 = $dst" in {
4001 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
4002 X86VectorVTInfo _> {
4004 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
4005 (ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2),
4006 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
4007 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.LdFrag addr:$src2),
4009 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
4010 (ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2),
4011 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr,
4012 ", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"),
4014 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
4015 (_.ScalarLdFrag addr:$src2))),
4016 _.RC:$src3))]>, EVEX_B;
4018 } // Constraints = "$src1 = $dst"
4020 multiclass avx512_fma3p_m132_f<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4022 let ExeDomain = SSEPackedSingle in {
4023 defm NAME##PSZ : avx512_fma3p_m132<opc, OpcodeStr##ps,
4024 OpNode,v16f32_info>, EVEX_V512,
4025 EVEX_CD8<32, CD8VF>;
4026 defm NAME##PSZ256 : avx512_fma3p_m132<opc, OpcodeStr##ps,
4027 OpNode, v8f32x_info>, EVEX_V256,
4028 EVEX_CD8<32, CD8VF>;
4029 defm NAME##PSZ128 : avx512_fma3p_m132<opc, OpcodeStr##ps,
4030 OpNode, v4f32x_info>, EVEX_V128,
4031 EVEX_CD8<32, CD8VF>;
4033 let ExeDomain = SSEPackedDouble in {
4034 defm NAME##PDZ : avx512_fma3p_m132<opc, OpcodeStr##pd,
4035 OpNode, v8f64_info>, EVEX_V512,
4036 VEX_W, EVEX_CD8<32, CD8VF>;
4037 defm NAME##PDZ256 : avx512_fma3p_m132<opc, OpcodeStr##pd,
4038 OpNode, v4f64x_info>, EVEX_V256,
4039 VEX_W, EVEX_CD8<32, CD8VF>;
4040 defm NAME##PDZ128 : avx512_fma3p_m132<opc, OpcodeStr##pd,
4041 OpNode, v2f64x_info>, EVEX_V128,
4042 VEX_W, EVEX_CD8<32, CD8VF>;
4046 defm VFMADD132 : avx512_fma3p_m132_f<0x98, "vfmadd132", X86Fmadd>;
4047 defm VFMSUB132 : avx512_fma3p_m132_f<0x9A, "vfmsub132", X86Fmsub>;
4048 defm VFMADDSUB132 : avx512_fma3p_m132_f<0x96, "vfmaddsub132", X86Fmaddsub>;
4049 defm VFMSUBADD132 : avx512_fma3p_m132_f<0x97, "vfmsubadd132", X86Fmsubadd>;
4050 defm VFNMADD132 : avx512_fma3p_m132_f<0x9C, "vfnmadd132", X86Fnmadd>;
4051 defm VFNMSUB132 : avx512_fma3p_m132_f<0x9E, "vfnmsub132", X86Fnmsub>;
4054 let Constraints = "$src1 = $dst" in {
4055 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4056 RegisterClass RC, ValueType OpVT,
4057 X86MemOperand x86memop, Operand memop,
4059 let isCommutable = 1 in
4060 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
4061 (ins RC:$src1, RC:$src2, RC:$src3),
4062 !strconcat(OpcodeStr,
4063 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4065 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
4067 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
4068 (ins RC:$src1, RC:$src2, f128mem:$src3),
4069 !strconcat(OpcodeStr,
4070 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4072 (OpVT (OpNode RC:$src2, RC:$src1,
4073 (mem_frag addr:$src3))))]>;
4075 } // Constraints = "$src1 = $dst"
4077 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
4078 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
4079 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
4080 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
4081 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
4082 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
4083 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
4084 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
4085 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
4086 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
4087 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
4088 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
4089 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
4090 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
4091 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
4092 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
4094 //===----------------------------------------------------------------------===//
4095 // AVX-512 Scalar convert from sign integer to float/double
4096 //===----------------------------------------------------------------------===//
4098 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
4099 X86MemOperand x86memop, string asm> {
4100 let hasSideEffects = 0 in {
4101 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
4102 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4105 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
4106 (ins DstRC:$src1, x86memop:$src),
4107 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4109 } // hasSideEffects = 0
4112 let Predicates = [HasAVX512] in {
4113 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
4114 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
4115 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
4116 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
4117 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
4118 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
4119 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
4120 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
4122 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
4123 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4124 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
4125 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4126 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
4127 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4128 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
4129 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4131 def : Pat<(f32 (sint_to_fp GR32:$src)),
4132 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4133 def : Pat<(f32 (sint_to_fp GR64:$src)),
4134 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4135 def : Pat<(f64 (sint_to_fp GR32:$src)),
4136 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4137 def : Pat<(f64 (sint_to_fp GR64:$src)),
4138 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4140 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
4141 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
4142 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
4143 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
4144 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
4145 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
4146 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
4147 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
4149 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
4150 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4151 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
4152 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4153 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
4154 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4155 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
4156 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4158 def : Pat<(f32 (uint_to_fp GR32:$src)),
4159 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4160 def : Pat<(f32 (uint_to_fp GR64:$src)),
4161 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4162 def : Pat<(f64 (uint_to_fp GR32:$src)),
4163 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4164 def : Pat<(f64 (uint_to_fp GR64:$src)),
4165 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4168 //===----------------------------------------------------------------------===//
4169 // AVX-512 Scalar convert from float/double to integer
4170 //===----------------------------------------------------------------------===//
4171 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
4172 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
4174 let hasSideEffects = 0 in {
4175 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4176 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4177 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
4178 Requires<[HasAVX512]>;
4180 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
4181 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
4182 Requires<[HasAVX512]>;
4183 } // hasSideEffects = 0
4185 let Predicates = [HasAVX512] in {
4186 // Convert float/double to signed/unsigned int 32/64
4187 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
4188 ssmem, sse_load_f32, "cvtss2si">,
4189 XS, EVEX_CD8<32, CD8VT1>;
4190 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
4191 ssmem, sse_load_f32, "cvtss2si">,
4192 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
4193 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
4194 ssmem, sse_load_f32, "cvtss2usi">,
4195 XS, EVEX_CD8<32, CD8VT1>;
4196 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
4197 int_x86_avx512_cvtss2usi64, ssmem,
4198 sse_load_f32, "cvtss2usi">, XS, VEX_W,
4199 EVEX_CD8<32, CD8VT1>;
4200 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
4201 sdmem, sse_load_f64, "cvtsd2si">,
4202 XD, EVEX_CD8<64, CD8VT1>;
4203 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
4204 sdmem, sse_load_f64, "cvtsd2si">,
4205 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4206 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
4207 sdmem, sse_load_f64, "cvtsd2usi">,
4208 XD, EVEX_CD8<64, CD8VT1>;
4209 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
4210 int_x86_avx512_cvtsd2usi64, sdmem,
4211 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
4212 EVEX_CD8<64, CD8VT1>;
4214 let isCodeGenOnly = 1 in {
4215 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4216 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
4217 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
4218 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4219 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
4220 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
4221 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4222 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
4223 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4224 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4225 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
4226 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
4228 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4229 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
4230 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
4231 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4232 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
4233 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
4234 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4235 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
4236 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4237 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4238 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
4239 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
4240 } // isCodeGenOnly = 1
4242 // Convert float/double to signed/unsigned int 32/64 with truncation
4243 let isCodeGenOnly = 1 in {
4244 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
4245 ssmem, sse_load_f32, "cvttss2si">,
4246 XS, EVEX_CD8<32, CD8VT1>;
4247 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
4248 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
4249 "cvttss2si">, XS, VEX_W,
4250 EVEX_CD8<32, CD8VT1>;
4251 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
4252 sdmem, sse_load_f64, "cvttsd2si">, XD,
4253 EVEX_CD8<64, CD8VT1>;
4254 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
4255 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
4256 "cvttsd2si">, XD, VEX_W,
4257 EVEX_CD8<64, CD8VT1>;
4258 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
4259 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
4260 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
4261 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
4262 int_x86_avx512_cvttss2usi64, ssmem,
4263 sse_load_f32, "cvttss2usi">, XS, VEX_W,
4264 EVEX_CD8<32, CD8VT1>;
4265 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
4266 int_x86_avx512_cvttsd2usi,
4267 sdmem, sse_load_f64, "cvttsd2usi">, XD,
4268 EVEX_CD8<64, CD8VT1>;
4269 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
4270 int_x86_avx512_cvttsd2usi64, sdmem,
4271 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
4272 EVEX_CD8<64, CD8VT1>;
4273 } // isCodeGenOnly = 1
4275 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
4276 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
4278 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4279 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4280 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
4281 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4282 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4283 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
4286 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
4287 loadf32, "cvttss2si">, XS,
4288 EVEX_CD8<32, CD8VT1>;
4289 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
4290 loadf32, "cvttss2usi">, XS,
4291 EVEX_CD8<32, CD8VT1>;
4292 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
4293 loadf32, "cvttss2si">, XS, VEX_W,
4294 EVEX_CD8<32, CD8VT1>;
4295 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
4296 loadf32, "cvttss2usi">, XS, VEX_W,
4297 EVEX_CD8<32, CD8VT1>;
4298 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
4299 loadf64, "cvttsd2si">, XD,
4300 EVEX_CD8<64, CD8VT1>;
4301 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
4302 loadf64, "cvttsd2usi">, XD,
4303 EVEX_CD8<64, CD8VT1>;
4304 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
4305 loadf64, "cvttsd2si">, XD, VEX_W,
4306 EVEX_CD8<64, CD8VT1>;
4307 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
4308 loadf64, "cvttsd2usi">, XD, VEX_W,
4309 EVEX_CD8<64, CD8VT1>;
4311 //===----------------------------------------------------------------------===//
4312 // AVX-512 Convert form float to double and back
4313 //===----------------------------------------------------------------------===//
4314 let hasSideEffects = 0 in {
4315 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
4316 (ins FR32X:$src1, FR32X:$src2),
4317 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4318 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
4320 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
4321 (ins FR32X:$src1, f32mem:$src2),
4322 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4323 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
4324 EVEX_CD8<32, CD8VT1>;
4326 // Convert scalar double to scalar single
4327 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
4328 (ins FR64X:$src1, FR64X:$src2),
4329 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4330 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
4332 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
4333 (ins FR64X:$src1, f64mem:$src2),
4334 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4335 []>, EVEX_4V, VEX_LIG, VEX_W,
4336 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
4339 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
4340 Requires<[HasAVX512]>;
4341 def : Pat<(fextend (loadf32 addr:$src)),
4342 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
4344 def : Pat<(extloadf32 addr:$src),
4345 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4346 Requires<[HasAVX512, OptForSize]>;
4348 def : Pat<(extloadf32 addr:$src),
4349 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
4350 Requires<[HasAVX512, OptForSpeed]>;
4352 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
4353 Requires<[HasAVX512]>;
4355 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
4356 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
4357 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
4359 let hasSideEffects = 0 in {
4360 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4361 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4363 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
4364 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4365 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
4366 [], d>, EVEX, EVEX_B, EVEX_RC;
4368 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4369 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4371 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
4372 } // hasSideEffects = 0
4375 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
4376 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
4377 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
4379 let hasSideEffects = 0 in {
4380 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4381 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4383 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
4385 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4386 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4388 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
4389 } // hasSideEffects = 0
4392 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
4393 loadv8f64, f512mem, v8f32, v8f64,
4394 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
4395 EVEX_CD8<64, CD8VF>;
4397 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
4398 loadv4f64, f256mem, v8f64, v8f32,
4399 SSEPackedDouble>, EVEX_V512, PS,
4400 EVEX_CD8<32, CD8VH>;
4401 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
4402 (VCVTPS2PDZrm addr:$src)>;
4404 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
4405 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
4406 (VCVTPD2PSZrr VR512:$src)>;
4408 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
4409 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
4410 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
4412 //===----------------------------------------------------------------------===//
4413 // AVX-512 Vector convert from sign integer to float/double
4414 //===----------------------------------------------------------------------===//
4416 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
4417 loadv8i64, i512mem, v16f32, v16i32,
4418 SSEPackedSingle>, EVEX_V512, PS,
4419 EVEX_CD8<32, CD8VF>;
4421 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
4422 loadv4i64, i256mem, v8f64, v8i32,
4423 SSEPackedDouble>, EVEX_V512, XS,
4424 EVEX_CD8<32, CD8VH>;
4426 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
4427 loadv16f32, f512mem, v16i32, v16f32,
4428 SSEPackedSingle>, EVEX_V512, XS,
4429 EVEX_CD8<32, CD8VF>;
4431 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
4432 loadv8f64, f512mem, v8i32, v8f64,
4433 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
4434 EVEX_CD8<64, CD8VF>;
4436 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
4437 loadv16f32, f512mem, v16i32, v16f32,
4438 SSEPackedSingle>, EVEX_V512, PS,
4439 EVEX_CD8<32, CD8VF>;
4441 // cvttps2udq (src, 0, mask-all-ones, sae-current)
4442 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
4443 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
4444 (VCVTTPS2UDQZrr VR512:$src)>;
4446 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
4447 loadv8f64, f512mem, v8i32, v8f64,
4448 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
4449 EVEX_CD8<64, CD8VF>;
4451 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
4452 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
4453 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
4454 (VCVTTPD2UDQZrr VR512:$src)>;
4456 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
4457 loadv4i64, f256mem, v8f64, v8i32,
4458 SSEPackedDouble>, EVEX_V512, XS,
4459 EVEX_CD8<32, CD8VH>;
4461 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
4462 loadv16i32, f512mem, v16f32, v16i32,
4463 SSEPackedSingle>, EVEX_V512, XD,
4464 EVEX_CD8<32, CD8VF>;
4466 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
4467 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
4468 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
4470 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
4471 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
4472 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
4474 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
4475 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
4476 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
4478 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
4479 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
4480 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
4482 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
4483 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
4484 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
4486 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
4487 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
4488 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
4489 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
4490 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4491 (VCVTDQ2PDZrr VR256X:$src)>;
4492 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
4493 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
4494 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
4495 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
4496 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4497 (VCVTUDQ2PDZrr VR256X:$src)>;
4499 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
4500 RegisterClass DstRC, PatFrag mem_frag,
4501 X86MemOperand x86memop, Domain d> {
4502 let hasSideEffects = 0 in {
4503 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4504 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4506 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4507 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
4508 [], d>, EVEX, EVEX_B, EVEX_RC;
4510 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4511 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4513 } // hasSideEffects = 0
4516 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
4517 loadv16f32, f512mem, SSEPackedSingle>, PD,
4518 EVEX_V512, EVEX_CD8<32, CD8VF>;
4519 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
4520 loadv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
4521 EVEX_V512, EVEX_CD8<64, CD8VF>;
4523 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
4524 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4525 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
4527 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
4528 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4529 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
4531 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
4532 loadv16f32, f512mem, SSEPackedSingle>,
4533 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4534 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
4535 loadv8f64, f512mem, SSEPackedDouble>, VEX_W,
4536 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
4538 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
4539 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4540 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
4542 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
4543 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4544 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
4546 let Predicates = [HasAVX512] in {
4547 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
4548 (VCVTPD2PSZrm addr:$src)>;
4549 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
4550 (VCVTPS2PDZrm addr:$src)>;
4553 //===----------------------------------------------------------------------===//
4554 // Half precision conversion instructions
4555 //===----------------------------------------------------------------------===//
4556 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
4557 X86MemOperand x86memop> {
4558 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
4559 "vcvtph2ps\t{$src, $dst|$dst, $src}",
4561 let hasSideEffects = 0, mayLoad = 1 in
4562 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
4563 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
4566 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
4567 X86MemOperand x86memop> {
4568 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
4569 (ins srcRC:$src1, i32u8imm:$src2),
4570 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4572 let hasSideEffects = 0, mayStore = 1 in
4573 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
4574 (ins x86memop:$dst, srcRC:$src1, i32u8imm:$src2),
4575 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
4578 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
4579 EVEX_CD8<32, CD8VH>;
4580 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
4581 EVEX_CD8<32, CD8VH>;
4583 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
4584 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
4585 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
4587 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
4588 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
4589 (VCVTPH2PSZrr VR256X:$src)>;
4591 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
4592 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
4593 "ucomiss">, PS, EVEX, VEX_LIG,
4594 EVEX_CD8<32, CD8VT1>;
4595 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
4596 "ucomisd">, PD, EVEX,
4597 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4598 let Pattern = []<dag> in {
4599 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
4600 "comiss">, PS, EVEX, VEX_LIG,
4601 EVEX_CD8<32, CD8VT1>;
4602 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
4603 "comisd">, PD, EVEX,
4604 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4606 let isCodeGenOnly = 1 in {
4607 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
4608 load, "ucomiss">, PS, EVEX, VEX_LIG,
4609 EVEX_CD8<32, CD8VT1>;
4610 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
4611 load, "ucomisd">, PD, EVEX,
4612 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4614 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
4615 load, "comiss">, PS, EVEX, VEX_LIG,
4616 EVEX_CD8<32, CD8VT1>;
4617 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
4618 load, "comisd">, PD, EVEX,
4619 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4623 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
4624 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4625 X86MemOperand x86memop> {
4626 let hasSideEffects = 0 in {
4627 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4628 (ins RC:$src1, RC:$src2),
4629 !strconcat(OpcodeStr,
4630 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4631 let mayLoad = 1 in {
4632 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4633 (ins RC:$src1, x86memop:$src2),
4634 !strconcat(OpcodeStr,
4635 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4640 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
4641 EVEX_CD8<32, CD8VT1>;
4642 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
4643 VEX_W, EVEX_CD8<64, CD8VT1>;
4644 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
4645 EVEX_CD8<32, CD8VT1>;
4646 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
4647 VEX_W, EVEX_CD8<64, CD8VT1>;
4649 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
4650 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4651 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4652 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4654 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
4655 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4656 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4657 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4659 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
4660 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4661 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4662 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4664 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
4665 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4666 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4667 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4669 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
4670 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
4671 X86VectorVTInfo _> {
4672 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4673 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4674 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
4675 let mayLoad = 1 in {
4676 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4677 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4679 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
4680 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4681 (ins _.ScalarMemOp:$src), OpcodeStr,
4682 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4684 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4689 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4690 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
4691 EVEX_V512, EVEX_CD8<32, CD8VF>;
4692 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
4693 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4695 // Define only if AVX512VL feature is present.
4696 let Predicates = [HasVLX] in {
4697 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4698 OpNode, v4f32x_info>,
4699 EVEX_V128, EVEX_CD8<32, CD8VF>;
4700 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4701 OpNode, v8f32x_info>,
4702 EVEX_V256, EVEX_CD8<32, CD8VF>;
4703 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4704 OpNode, v2f64x_info>,
4705 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
4706 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4707 OpNode, v4f64x_info>,
4708 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
4712 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
4713 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
4715 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
4716 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4717 (VRSQRT14PSZr VR512:$src)>;
4718 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
4719 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4720 (VRSQRT14PDZr VR512:$src)>;
4722 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
4723 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4724 (VRCP14PSZr VR512:$src)>;
4725 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
4726 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4727 (VRCP14PDZr VR512:$src)>;
4729 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
4730 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
4733 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4734 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4735 "$src2, $src1", "$src1, $src2",
4736 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4737 (i32 FROUND_CURRENT))>;
4739 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4740 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4741 "$src2, $src1", "$src1, $src2",
4742 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4743 (i32 FROUND_NO_EXC)), "{sae}">, EVEX_B;
4745 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4746 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
4747 "$src2, $src1", "$src1, $src2",
4748 (OpNode (_.VT _.RC:$src1),
4749 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
4750 (i32 FROUND_CURRENT))>;
4753 multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4754 defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
4755 EVEX_CD8<32, CD8VT1>;
4756 defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>,
4757 EVEX_CD8<64, CD8VT1>, VEX_W;
4760 let hasSideEffects = 0, Predicates = [HasERI] in {
4761 defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V;
4762 defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V;
4764 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
4766 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4769 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4770 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4771 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
4773 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4774 (ins _.RC:$src), OpcodeStr,
4776 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC)),
4779 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4780 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4782 (bitconvert (_.LdFrag addr:$src))),
4783 (i32 FROUND_CURRENT))>;
4785 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4786 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4788 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
4789 (i32 FROUND_CURRENT))>, EVEX_B;
4792 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4793 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
4794 EVEX_CD8<32, CD8VF>;
4795 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
4796 VEX_W, EVEX_CD8<32, CD8VF>;
4799 let Predicates = [HasERI], hasSideEffects = 0 in {
4801 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX, EVEX_V512, T8PD;
4802 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX, EVEX_V512, T8PD;
4803 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX, EVEX_V512, T8PD;
4806 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
4807 SDNode OpNode, X86VectorVTInfo _>{
4808 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4809 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4810 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
4811 let mayLoad = 1 in {
4812 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4813 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4815 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
4817 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4818 (ins _.ScalarMemOp:$src), OpcodeStr,
4819 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4821 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4826 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
4827 Intrinsic F32Int, Intrinsic F64Int,
4828 OpndItins itins_s, OpndItins itins_d> {
4829 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
4830 (ins FR32X:$src1, FR32X:$src2),
4831 !strconcat(OpcodeStr,
4832 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4833 [], itins_s.rr>, XS, EVEX_4V;
4834 let isCodeGenOnly = 1 in
4835 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4836 (ins VR128X:$src1, VR128X:$src2),
4837 !strconcat(OpcodeStr,
4838 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4840 (F32Int VR128X:$src1, VR128X:$src2))],
4841 itins_s.rr>, XS, EVEX_4V;
4842 let mayLoad = 1 in {
4843 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
4844 (ins FR32X:$src1, f32mem:$src2),
4845 !strconcat(OpcodeStr,
4846 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4847 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4848 let isCodeGenOnly = 1 in
4849 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4850 (ins VR128X:$src1, ssmem:$src2),
4851 !strconcat(OpcodeStr,
4852 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4854 (F32Int VR128X:$src1, sse_load_f32:$src2))],
4855 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4857 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
4858 (ins FR64X:$src1, FR64X:$src2),
4859 !strconcat(OpcodeStr,
4860 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4862 let isCodeGenOnly = 1 in
4863 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4864 (ins VR128X:$src1, VR128X:$src2),
4865 !strconcat(OpcodeStr,
4866 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4868 (F64Int VR128X:$src1, VR128X:$src2))],
4869 itins_s.rr>, XD, EVEX_4V, VEX_W;
4870 let mayLoad = 1 in {
4871 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
4872 (ins FR64X:$src1, f64mem:$src2),
4873 !strconcat(OpcodeStr,
4874 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4875 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4876 let isCodeGenOnly = 1 in
4877 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4878 (ins VR128X:$src1, sdmem:$src2),
4879 !strconcat(OpcodeStr,
4880 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4882 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
4883 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4887 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
4889 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
4891 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
4892 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
4894 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4895 // Define only if AVX512VL feature is present.
4896 let Predicates = [HasVLX] in {
4897 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4898 OpNode, v4f32x_info>,
4899 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
4900 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4901 OpNode, v8f32x_info>,
4902 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
4903 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4904 OpNode, v2f64x_info>,
4905 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4906 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4907 OpNode, v4f64x_info>,
4908 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4912 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>;
4914 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
4915 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
4916 SSE_SQRTSS, SSE_SQRTSD>;
4918 let Predicates = [HasAVX512] in {
4919 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
4920 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
4921 (VSQRTPSZr VR512:$src1)>;
4922 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
4923 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
4924 (VSQRTPDZr VR512:$src1)>;
4926 def : Pat<(f32 (fsqrt FR32X:$src)),
4927 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4928 def : Pat<(f32 (fsqrt (load addr:$src))),
4929 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
4930 Requires<[OptForSize]>;
4931 def : Pat<(f64 (fsqrt FR64X:$src)),
4932 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
4933 def : Pat<(f64 (fsqrt (load addr:$src))),
4934 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
4935 Requires<[OptForSize]>;
4937 def : Pat<(f32 (X86frsqrt FR32X:$src)),
4938 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4939 def : Pat<(f32 (X86frsqrt (load addr:$src))),
4940 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4941 Requires<[OptForSize]>;
4943 def : Pat<(f32 (X86frcp FR32X:$src)),
4944 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4945 def : Pat<(f32 (X86frcp (load addr:$src))),
4946 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4947 Requires<[OptForSize]>;
4949 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
4950 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
4951 (COPY_TO_REGCLASS VR128X:$src, FR32)),
4953 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
4954 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
4956 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
4957 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
4958 (COPY_TO_REGCLASS VR128X:$src, FR64)),
4960 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
4961 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
4965 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
4966 X86MemOperand x86memop, RegisterClass RC,
4967 PatFrag mem_frag, Domain d> {
4968 let ExeDomain = d in {
4969 // Intrinsic operation, reg.
4970 // Vector intrinsic operation, reg
4971 def r : AVX512AIi8<opc, MRMSrcReg,
4972 (outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
4973 !strconcat(OpcodeStr,
4974 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4977 // Vector intrinsic operation, mem
4978 def m : AVX512AIi8<opc, MRMSrcMem,
4979 (outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
4980 !strconcat(OpcodeStr,
4981 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4986 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
4987 loadv16f32, SSEPackedSingle>, EVEX_V512,
4988 EVEX_CD8<32, CD8VF>;
4990 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
4991 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
4993 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
4996 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
4997 loadv8f64, SSEPackedDouble>, EVEX_V512,
4998 VEX_W, EVEX_CD8<64, CD8VF>;
5000 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
5001 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
5003 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
5006 avx512_rndscale_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
5008 let ExeDomain = _.ExeDomain in {
5009 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5010 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5011 "$src3, $src2, $src1", "$src1, $src2, $src3",
5012 (_.VT (X86RndScale (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5013 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5015 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5016 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5017 "$src3, $src2, $src1", "$src1, $src2, $src3",
5018 (_.VT (X86RndScale (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5019 (i32 imm:$src3), (i32 FROUND_NO_EXC))), "{sae}">, EVEX_B;
5022 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5023 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3), OpcodeStr,
5024 "$src3, $src2, $src1", "$src1, $src2, $src3",
5025 (_.VT (X86RndScale (_.VT _.RC:$src1),
5026 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
5027 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5029 let Predicates = [HasAVX512] in {
5030 def : Pat<(ffloor _.FRC:$src), (COPY_TO_REGCLASS
5031 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5032 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x1))), _.FRC)>;
5033 def : Pat<(fceil _.FRC:$src), (COPY_TO_REGCLASS
5034 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5035 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x2))), _.FRC)>;
5036 def : Pat<(ftrunc _.FRC:$src), (COPY_TO_REGCLASS
5037 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5038 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x3))), _.FRC)>;
5039 def : Pat<(frint _.FRC:$src), (COPY_TO_REGCLASS
5040 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5041 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x4))), _.FRC)>;
5042 def : Pat<(fnearbyint _.FRC:$src), (COPY_TO_REGCLASS
5043 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5044 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0xc))), _.FRC)>;
5046 def : Pat<(ffloor (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5047 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5048 addr:$src, (i32 0x1))), _.FRC)>;
5049 def : Pat<(fceil (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5050 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5051 addr:$src, (i32 0x2))), _.FRC)>;
5052 def : Pat<(ftrunc (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5053 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5054 addr:$src, (i32 0x3))), _.FRC)>;
5055 def : Pat<(frint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5056 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5057 addr:$src, (i32 0x4))), _.FRC)>;
5058 def : Pat<(fnearbyint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5059 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5060 addr:$src, (i32 0xc))), _.FRC)>;
5064 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", f32x_info>,
5065 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VT1>;
5067 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", f64x_info>, VEX_W,
5068 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VT1>;
5070 let Predicates = [HasAVX512] in {
5071 def : Pat<(v16f32 (ffloor VR512:$src)),
5072 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
5073 def : Pat<(v16f32 (fnearbyint VR512:$src)),
5074 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
5075 def : Pat<(v16f32 (fceil VR512:$src)),
5076 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
5077 def : Pat<(v16f32 (frint VR512:$src)),
5078 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
5079 def : Pat<(v16f32 (ftrunc VR512:$src)),
5080 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
5082 def : Pat<(v8f64 (ffloor VR512:$src)),
5083 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
5084 def : Pat<(v8f64 (fnearbyint VR512:$src)),
5085 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
5086 def : Pat<(v8f64 (fceil VR512:$src)),
5087 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
5088 def : Pat<(v8f64 (frint VR512:$src)),
5089 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
5090 def : Pat<(v8f64 (ftrunc VR512:$src)),
5091 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
5093 //-------------------------------------------------
5094 // Integer truncate and extend operations
5095 //-------------------------------------------------
5097 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
5098 RegisterClass dstRC, RegisterClass srcRC,
5099 RegisterClass KRC, X86MemOperand x86memop> {
5100 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
5102 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
5105 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
5106 (ins KRC:$mask, srcRC:$src),
5107 !strconcat(OpcodeStr,
5108 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
5111 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
5112 (ins KRC:$mask, srcRC:$src),
5113 !strconcat(OpcodeStr,
5114 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5117 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
5118 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5121 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
5122 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
5123 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
5127 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
5128 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
5129 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
5130 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
5131 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
5132 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
5133 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
5134 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
5135 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
5136 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
5137 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
5138 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
5139 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
5140 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
5141 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
5142 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
5143 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
5144 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
5145 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
5146 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
5147 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
5148 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
5149 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
5150 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
5151 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
5152 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
5153 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
5154 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
5155 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
5156 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
5158 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
5159 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
5160 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
5161 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
5162 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
5164 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
5165 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
5166 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
5167 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
5168 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
5169 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
5170 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
5171 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
5174 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
5175 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
5176 PatFrag mem_frag, X86MemOperand x86memop,
5177 ValueType OpVT, ValueType InVT> {
5179 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
5181 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5182 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
5184 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
5185 (ins KRC:$mask, SrcRC:$src),
5186 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
5189 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
5190 (ins KRC:$mask, SrcRC:$src),
5191 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5194 let mayLoad = 1 in {
5195 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
5196 (ins x86memop:$src),
5197 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
5199 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
5202 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
5203 (ins KRC:$mask, x86memop:$src),
5204 !strconcat(OpcodeStr,"\t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
5208 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
5209 (ins KRC:$mask, x86memop:$src),
5210 !strconcat(OpcodeStr,"\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5216 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
5217 loadv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
5219 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
5220 loadv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
5222 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
5223 loadv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
5224 EVEX_CD8<16, CD8VH>;
5225 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
5226 loadv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
5227 EVEX_CD8<16, CD8VQ>;
5228 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
5229 loadv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
5230 EVEX_CD8<32, CD8VH>;
5232 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
5233 loadv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
5235 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
5236 loadv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
5238 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
5239 loadv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
5240 EVEX_CD8<16, CD8VH>;
5241 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
5242 loadv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
5243 EVEX_CD8<16, CD8VQ>;
5244 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
5245 loadv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
5246 EVEX_CD8<32, CD8VH>;
5248 //===----------------------------------------------------------------------===//
5249 // GATHER - SCATTER Operations
5251 multiclass avx512_gather<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5252 X86MemOperand memop, PatFrag GatherNode> {
5253 let Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
5254 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst, _.KRCWM:$mask_wb),
5255 (ins _.RC:$src1, _.KRCWM:$mask, memop:$src2),
5256 !strconcat(OpcodeStr,
5257 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5258 [(set _.RC:$dst, _.KRCWM:$mask_wb,
5259 (GatherNode (_.VT _.RC:$src1), _.KRCWM:$mask,
5260 vectoraddr:$src2))]>, EVEX, EVEX_K,
5261 EVEX_CD8<_.EltSize, CD8VT1>;
5264 let ExeDomain = SSEPackedDouble in {
5265 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", v8f64_info, vy64xmem,
5266 mgatherv8i32>, EVEX_V512, VEX_W;
5267 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", v8f64_info, vz64mem,
5268 mgatherv8i64>, EVEX_V512, VEX_W;
5271 let ExeDomain = SSEPackedSingle in {
5272 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", v16f32_info, vz32mem,
5273 mgatherv16i32>, EVEX_V512;
5274 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", v8f32x_info, vz64mem,
5275 mgatherv8i64>, EVEX_V512;
5278 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", v8i64_info, vy64xmem,
5279 mgatherv8i32>, EVEX_V512, VEX_W;
5280 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", v16i32_info, vz32mem,
5281 mgatherv16i32>, EVEX_V512;
5283 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", v8i64_info, vz64mem,
5284 mgatherv8i64>, EVEX_V512, VEX_W;
5285 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", v8i32x_info, vz64mem,
5286 mgatherv8i64>, EVEX_V512;
5288 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5289 X86MemOperand memop, PatFrag ScatterNode> {
5291 let mayStore = 1, Constraints = "$mask = $mask_wb" in
5293 def mr : AVX5128I<opc, MRMDestMem, (outs _.KRCWM:$mask_wb),
5294 (ins memop:$dst, _.KRCWM:$mask, _.RC:$src),
5295 !strconcat(OpcodeStr,
5296 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
5297 [(set _.KRCWM:$mask_wb, (ScatterNode (_.VT _.RC:$src),
5298 _.KRCWM:$mask, vectoraddr:$dst))]>,
5299 EVEX, EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
5302 let ExeDomain = SSEPackedDouble in {
5303 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", v8f64_info, vy64xmem,
5304 mscatterv8i32>, EVEX_V512, VEX_W;
5305 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", v8f64_info, vz64mem,
5306 mscatterv8i64>, EVEX_V512, VEX_W;
5309 let ExeDomain = SSEPackedSingle in {
5310 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", v16f32_info, vz32mem,
5311 mscatterv16i32>, EVEX_V512;
5312 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", v8f32x_info, vz64mem,
5313 mscatterv8i64>, EVEX_V512;
5316 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", v8i64_info, vy64xmem,
5317 mscatterv8i32>, EVEX_V512, VEX_W;
5318 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", v16i32_info, vz32mem,
5319 mscatterv16i32>, EVEX_V512;
5321 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", v8i64_info, vz64mem,
5322 mscatterv8i64>, EVEX_V512, VEX_W;
5323 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", v8i32x_info, vz64mem,
5324 mscatterv8i64>, EVEX_V512;
5327 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
5328 RegisterClass KRC, X86MemOperand memop> {
5329 let Predicates = [HasPFI], hasSideEffects = 1 in
5330 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
5331 !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"),
5335 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
5336 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5338 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
5339 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5341 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
5342 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5344 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
5345 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5347 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
5348 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5350 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
5351 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5353 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
5354 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5356 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
5357 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5359 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
5360 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5362 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
5363 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5365 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
5366 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5368 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
5369 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5371 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
5372 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5374 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
5375 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5377 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
5378 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5380 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
5381 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5382 //===----------------------------------------------------------------------===//
5383 // VSHUFPS - VSHUFPD Operations
5385 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
5386 ValueType vt, string OpcodeStr, PatFrag mem_frag,
5388 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
5389 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
5390 !strconcat(OpcodeStr,
5391 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5392 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
5393 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
5394 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
5395 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
5396 (ins RC:$src1, RC:$src2, u8imm:$src3),
5397 !strconcat(OpcodeStr,
5398 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5399 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
5400 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
5401 EVEX_4V, Sched<[WriteShuffle]>;
5404 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", loadv16f32,
5405 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
5406 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", loadv8f64,
5407 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
5409 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
5410 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
5411 def : Pat<(v16i32 (X86Shufp VR512:$src1,
5412 (loadv16i32 addr:$src2), (i8 imm:$imm))),
5413 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
5415 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
5416 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
5417 def : Pat<(v8i64 (X86Shufp VR512:$src1,
5418 (loadv8i64 addr:$src2), (i8 imm:$imm))),
5419 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
5421 multiclass avx512_valign<X86VectorVTInfo _> {
5422 defm rri : AVX512_maskable<0x03, MRMSrcReg, _, (outs _.RC:$dst),
5423 (ins _.RC:$src1, _.RC:$src2, u8imm:$src3),
5425 "$src3, $src2, $src1", "$src1, $src2, $src3",
5426 (_.VT (X86VAlign _.RC:$src2, _.RC:$src1,
5428 AVX512AIi8Base, EVEX_4V;
5430 // Also match valign of packed floats.
5431 def : Pat<(_.FloatVT (X86VAlign _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
5432 (!cast<Instruction>(NAME##rri) _.RC:$src2, _.RC:$src1, imm:$imm)>;
5435 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs _.RC:$dst),
5436 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$src3),
5437 !strconcat("valign"##_.Suffix,
5438 "\t{$src3, $src2, $src1, $dst|"
5439 "$dst, $src1, $src2, $src3}"),
5442 defm VALIGND : avx512_valign<v16i32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
5443 defm VALIGNQ : avx512_valign<v8i64_info>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
5445 // Helper fragments to match sext vXi1 to vXiY.
5446 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
5447 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
5449 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
5450 RegisterClass KRC, RegisterClass RC,
5451 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
5453 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
5454 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5456 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5457 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
5459 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5460 !strconcat(OpcodeStr,
5461 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5463 let mayLoad = 1 in {
5464 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5465 (ins x86memop:$src),
5466 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5468 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5469 (ins KRC:$mask, x86memop:$src),
5470 !strconcat(OpcodeStr,
5471 "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
5473 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5474 (ins KRC:$mask, x86memop:$src),
5475 !strconcat(OpcodeStr,
5476 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5478 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5479 (ins x86scalar_mop:$src),
5480 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5481 ", $dst|$dst, ${src}", BrdcstStr, "}"),
5483 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5484 (ins KRC:$mask, x86scalar_mop:$src),
5485 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5486 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
5487 []>, EVEX, EVEX_B, EVEX_K;
5488 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5489 (ins KRC:$mask, x86scalar_mop:$src),
5490 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5491 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
5493 []>, EVEX, EVEX_B, EVEX_KZ;
5497 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
5498 i512mem, i32mem, "{1to16}">, EVEX_V512,
5499 EVEX_CD8<32, CD8VF>;
5500 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
5501 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
5502 EVEX_CD8<64, CD8VF>;
5505 (bc_v16i32 (v16i1sextv16i32)),
5506 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
5507 (VPABSDZrr VR512:$src)>;
5509 (bc_v8i64 (v8i1sextv8i64)),
5510 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
5511 (VPABSQZrr VR512:$src)>;
5513 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
5514 (v16i32 immAllZerosV), (i16 -1))),
5515 (VPABSDZrr VR512:$src)>;
5516 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
5517 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
5518 (VPABSQZrr VR512:$src)>;
5520 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
5521 RegisterClass RC, RegisterClass KRC,
5522 X86MemOperand x86memop,
5523 X86MemOperand x86scalar_mop, string BrdcstStr> {
5524 let hasSideEffects = 0 in {
5525 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5527 !strconcat(OpcodeStr, "\t{$src, ${dst} |${dst}, $src}"),
5530 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5531 (ins x86memop:$src),
5532 !strconcat(OpcodeStr, "\t{$src, ${dst}|${dst}, $src}"),
5535 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5536 (ins x86scalar_mop:$src),
5537 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5538 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
5540 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5541 (ins KRC:$mask, RC:$src),
5542 !strconcat(OpcodeStr,
5543 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5546 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5547 (ins KRC:$mask, x86memop:$src),
5548 !strconcat(OpcodeStr,
5549 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5552 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5553 (ins KRC:$mask, x86scalar_mop:$src),
5554 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5555 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
5557 []>, EVEX, EVEX_KZ, EVEX_B;
5559 let Constraints = "$src1 = $dst" in {
5560 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5561 (ins RC:$src1, KRC:$mask, RC:$src2),
5562 !strconcat(OpcodeStr,
5563 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5566 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5567 (ins RC:$src1, KRC:$mask, x86memop:$src2),
5568 !strconcat(OpcodeStr,
5569 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5572 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5573 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
5574 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
5575 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
5576 []>, EVEX, EVEX_K, EVEX_B;
5581 let Predicates = [HasCDI] in {
5582 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
5583 i512mem, i32mem, "{1to16}">,
5584 EVEX_V512, EVEX_CD8<32, CD8VF>;
5587 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
5588 i512mem, i64mem, "{1to8}">,
5589 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5593 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
5595 (VPCONFLICTDrrk VR512:$src1,
5596 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5598 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
5600 (VPCONFLICTQrrk VR512:$src1,
5601 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5603 let Predicates = [HasCDI] in {
5604 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
5605 i512mem, i32mem, "{1to16}">,
5606 EVEX_V512, EVEX_CD8<32, CD8VF>;
5609 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
5610 i512mem, i64mem, "{1to8}">,
5611 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5615 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
5617 (VPLZCNTDrrk VR512:$src1,
5618 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5620 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
5622 (VPLZCNTQrrk VR512:$src1,
5623 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5625 def : Pat<(v16i32 (ctlz (loadv16i32 addr:$src))),
5626 (VPLZCNTDrm addr:$src)>;
5627 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
5628 (VPLZCNTDrr VR512:$src)>;
5629 def : Pat<(v8i64 (ctlz (loadv8i64 addr:$src))),
5630 (VPLZCNTQrm addr:$src)>;
5631 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
5632 (VPLZCNTQrr VR512:$src)>;
5634 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5635 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5636 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
5638 def : Pat<(store VK1:$src, addr:$dst),
5640 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)),
5641 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
5643 def : Pat<(store VK8:$src, addr:$dst),
5645 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
5646 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
5648 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
5649 (truncstore node:$val, node:$ptr), [{
5650 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
5653 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
5654 (MOV8mr addr:$dst, GR8:$src)>;
5656 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
5657 def rr : AVX512XS8I<opc, MRMSrcReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
5658 !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
5659 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
5662 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
5663 string OpcodeStr, Predicate prd> {
5664 let Predicates = [prd] in
5665 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5667 let Predicates = [prd, HasVLX] in {
5668 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5669 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5673 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
5674 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
5676 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
5678 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
5680 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
5684 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;
5686 multiclass convert_vector_to_mask_common<bits<8> opc, X86VectorVTInfo _, string OpcodeStr > {
5687 def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.KRC:$dst), (ins _.RC:$src),
5688 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5689 [(set _.KRC:$dst, (trunc (_.VT _.RC:$src)))]>, EVEX;
5692 multiclass avx512_convert_vector_to_mask<bits<8> opc, string OpcodeStr,
5693 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
5694 let Predicates = [prd] in
5695 defm Z : convert_vector_to_mask_common <opc, VTInfo.info512, OpcodeStr>,
5698 let Predicates = [prd, HasVLX] in {
5699 defm Z256 : convert_vector_to_mask_common<opc, VTInfo.info256, OpcodeStr>,
5701 defm Z128 : convert_vector_to_mask_common<opc, VTInfo.info128, OpcodeStr>,
5706 defm VPMOVB2M : avx512_convert_vector_to_mask<0x29, "vpmovb2m",
5707 avx512vl_i8_info, HasBWI>;
5708 defm VPMOVW2M : avx512_convert_vector_to_mask<0x29, "vpmovw2m",
5709 avx512vl_i16_info, HasBWI>, VEX_W;
5710 defm VPMOVD2M : avx512_convert_vector_to_mask<0x39, "vpmovd2m",
5711 avx512vl_i32_info, HasDQI>;
5712 defm VPMOVQ2M : avx512_convert_vector_to_mask<0x39, "vpmovq2m",
5713 avx512vl_i64_info, HasDQI>, VEX_W;
5715 //===----------------------------------------------------------------------===//
5716 // AVX-512 - COMPRESS and EXPAND
5718 multiclass compress_by_vec_width<bits<8> opc, X86VectorVTInfo _,
5720 def rrkz : AVX5128I<opc, MRMDestReg, (outs _.RC:$dst),
5721 (ins _.KRCWM:$mask, _.RC:$src),
5722 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5723 [(set _.RC:$dst, (_.VT (X86compress _.KRCWM:$mask, _.RC:$src,
5724 _.ImmAllZerosV)))]>, EVEX_KZ;
5726 let Constraints = "$src0 = $dst" in
5727 def rrk : AVX5128I<opc, MRMDestReg, (outs _.RC:$dst),
5728 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src),
5729 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5730 [(set _.RC:$dst, (_.VT (X86compress _.KRCWM:$mask, _.RC:$src,
5731 _.RC:$src0)))]>, EVEX_K;
5733 let mayStore = 1 in {
5734 def mrk : AVX5128I<opc, MRMDestMem, (outs),
5735 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
5736 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5737 [(store (_.VT (X86compress _.KRCWM:$mask, _.RC:$src, undef)),
5739 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
5743 multiclass compress_by_elt_width<bits<8> opc, string OpcodeStr,
5744 AVX512VLVectorVTInfo VTInfo> {
5745 defm Z : compress_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5747 let Predicates = [HasVLX] in {
5748 defm Z256 : compress_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5749 defm Z128 : compress_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5753 defm VPCOMPRESSD : compress_by_elt_width <0x8B, "vpcompressd", avx512vl_i32_info>,
5755 defm VPCOMPRESSQ : compress_by_elt_width <0x8B, "vpcompressq", avx512vl_i64_info>,
5757 defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", avx512vl_f32_info>,
5759 defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", avx512vl_f64_info>,
5763 multiclass expand_by_vec_width<bits<8> opc, X86VectorVTInfo _,
5765 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
5766 (ins _.KRCWM:$mask, _.RC:$src),
5767 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5768 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask, (_.VT _.RC:$src),
5769 _.ImmAllZerosV)))]>, EVEX_KZ;
5771 let Constraints = "$src0 = $dst" in
5772 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
5773 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src),
5774 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5775 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5776 (_.VT _.RC:$src), _.RC:$src0)))]>, EVEX_K;
5778 let mayLoad = 1, Constraints = "$src0 = $dst" in
5779 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
5780 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src),
5781 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5782 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5784 (_.LdFrag addr:$src))),
5786 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
5789 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
5790 (ins _.KRCWM:$mask, _.MemOp:$src),
5791 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5792 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5793 (_.VT (bitconvert (_.LdFrag addr:$src))),
5794 _.ImmAllZerosV)))]>,
5795 EVEX_KZ, EVEX_CD8<_.EltSize, CD8VT1>;
5799 multiclass expand_by_elt_width<bits<8> opc, string OpcodeStr,
5800 AVX512VLVectorVTInfo VTInfo> {
5801 defm Z : expand_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5803 let Predicates = [HasVLX] in {
5804 defm Z256 : expand_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5805 defm Z128 : expand_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5809 defm VPEXPANDD : expand_by_elt_width <0x89, "vpexpandd", avx512vl_i32_info>,
5811 defm VPEXPANDQ : expand_by_elt_width <0x89, "vpexpandq", avx512vl_i64_info>,
5813 defm VEXPANDPS : expand_by_elt_width <0x88, "vexpandps", avx512vl_f32_info>,
5815 defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", avx512vl_f64_info>,