1 // Bitcasts between 512-bit vector types. Return the original type since
2 // no instruction is needed for the conversion
3 let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
49 // Bitcasts between 256-bit vector types. Return the original type since
50 // no instruction is needed for the conversion
51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
84 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
87 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
88 isPseudo = 1, Predicates = [HasAVX512] in {
89 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
90 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
93 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
94 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
95 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
96 def : Pat<(v16f32 immAllZerosV), (AVX512_512_SET0)>;
98 //===----------------------------------------------------------------------===//
99 // AVX-512 - VECTOR INSERT
102 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
103 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
104 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
105 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
106 []>, EVEX_4V, EVEX_V512;
108 def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
109 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
110 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
111 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
114 // -- 64x4 fp form --
115 let neverHasSideEffects = 1, ExeDomain = SSEPackedDouble in {
116 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
117 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
118 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
119 []>, EVEX_4V, EVEX_V512, VEX_W;
121 def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
122 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
123 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
124 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
126 // -- 32x4 integer form --
127 let neverHasSideEffects = 1 in {
128 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
129 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
130 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
131 []>, EVEX_4V, EVEX_V512;
133 def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
134 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
135 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
136 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
140 let neverHasSideEffects = 1 in {
142 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
143 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
144 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
145 []>, EVEX_4V, EVEX_V512, VEX_W;
147 def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
148 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
149 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
150 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
153 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
154 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
155 (INSERT_get_vinsert128_imm VR512:$ins))>;
156 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
157 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
158 (INSERT_get_vinsert128_imm VR512:$ins))>;
159 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
160 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
161 (INSERT_get_vinsert128_imm VR512:$ins))>;
162 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
163 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
164 (INSERT_get_vinsert128_imm VR512:$ins))>;
166 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
167 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
168 (INSERT_get_vinsert128_imm VR512:$ins))>;
169 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
170 (bc_v4i32 (loadv2i64 addr:$src2)),
171 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
172 (INSERT_get_vinsert128_imm VR512:$ins))>;
173 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
174 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
175 (INSERT_get_vinsert128_imm VR512:$ins))>;
176 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
177 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
178 (INSERT_get_vinsert128_imm VR512:$ins))>;
180 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
181 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
182 (INSERT_get_vinsert256_imm VR512:$ins))>;
183 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
184 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
185 (INSERT_get_vinsert256_imm VR512:$ins))>;
186 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
187 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
188 (INSERT_get_vinsert256_imm VR512:$ins))>;
189 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
190 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
191 (INSERT_get_vinsert256_imm VR512:$ins))>;
193 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
194 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
195 (INSERT_get_vinsert256_imm VR512:$ins))>;
196 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
197 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
198 (INSERT_get_vinsert256_imm VR512:$ins))>;
199 def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
200 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
201 (INSERT_get_vinsert256_imm VR512:$ins))>;
202 def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
203 (bc_v8i32 (loadv4i64 addr:$src2)),
204 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
205 (INSERT_get_vinsert256_imm VR512:$ins))>;
207 // vinsertps - insert f32 to XMM
208 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
209 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
210 "vinsertps{z}\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
211 [(set VR128X:$dst, (X86insrtps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
213 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
214 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
215 "vinsertps{z}\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
216 [(set VR128X:$dst, (X86insrtps VR128X:$src1,
217 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
218 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
220 //===----------------------------------------------------------------------===//
221 // AVX-512 VECTOR EXTRACT
223 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
225 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
226 (ins VR512:$src1, i8imm:$src2),
227 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
228 []>, EVEX, EVEX_V512;
229 def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
230 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
231 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
232 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
235 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
236 (ins VR512:$src1, i8imm:$src2),
237 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
238 []>, EVEX, EVEX_V512, VEX_W;
240 def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
241 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
242 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
243 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
246 let neverHasSideEffects = 1 in {
248 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
249 (ins VR512:$src1, i8imm:$src2),
250 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
251 []>, EVEX, EVEX_V512;
252 def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
253 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
254 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
255 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
258 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
259 (ins VR512:$src1, i8imm:$src2),
260 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
261 []>, EVEX, EVEX_V512, VEX_W;
263 def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
264 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
265 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
266 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
269 def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
270 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
271 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
273 def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
274 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
275 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
277 def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
278 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
279 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
281 def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
282 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
283 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
286 def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
287 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
288 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
290 def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
291 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
292 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
294 def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
295 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
296 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
298 def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
299 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
300 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
302 // A 256-bit subvector extract from the first 512-bit vector position
303 // is a subregister copy that needs no instruction.
304 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
305 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
306 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
307 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
308 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
309 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
310 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
311 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
314 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
315 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
316 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
317 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
318 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
319 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
320 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
321 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
324 // A 128-bit subvector insert to the first 512-bit vector position
325 // is a subregister copy that needs no instruction.
326 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
327 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
328 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
330 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
331 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
332 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
334 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
335 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
336 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
338 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
339 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
340 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
343 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
344 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
345 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
346 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
347 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
348 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
349 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
350 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
352 // vextractps - extract 32 bits from XMM
353 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
354 (ins VR128X:$src1, u32u8imm:$src2),
355 "vextractps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
356 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
359 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
360 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
361 "vextractps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
362 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
365 //===---------------------------------------------------------------------===//
368 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
369 RegisterClass DestRC,
370 RegisterClass SrcRC, X86MemOperand x86memop> {
371 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
372 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
374 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
375 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),[]>, EVEX;
377 let ExeDomain = SSEPackedSingle in {
378 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss{z}", VR512,
380 EVEX_V512, EVEX_CD8<32, CD8VT1>;
383 let ExeDomain = SSEPackedDouble in {
384 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd{z}", VR512,
386 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
389 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
390 (VBROADCASTSSZrm addr:$src)>;
391 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
392 (VBROADCASTSDZrm addr:$src)>;
394 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
395 (VBROADCASTSSZrm addr:$src)>;
396 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
397 (VBROADCASTSDZrm addr:$src)>;
399 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
400 RegisterClass SrcRC, RegisterClass KRC> {
401 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
402 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
403 []>, EVEX, EVEX_V512;
404 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
405 (ins KRC:$mask, SrcRC:$src),
406 !strconcat(OpcodeStr,
407 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
408 []>, EVEX, EVEX_V512, EVEX_KZ;
411 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
412 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
415 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
416 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
418 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
419 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
421 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
422 (VPBROADCASTDrZrr GR32:$src)>;
423 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
424 (VPBROADCASTQrZrr GR64:$src)>;
425 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
426 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
428 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
429 X86MemOperand x86memop, PatFrag ld_frag,
430 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
432 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
433 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
435 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
436 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
438 !strconcat(OpcodeStr,
439 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
441 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
444 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
445 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
447 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
448 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
450 !strconcat(OpcodeStr,
451 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
452 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
453 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
457 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
458 loadi32, VR512, v16i32, v4i32, VK16WM>,
459 EVEX_V512, EVEX_CD8<32, CD8VT1>;
460 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
461 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
462 EVEX_CD8<64, CD8VT1>;
464 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
465 (VBROADCASTSSZrr VR128X:$src)>;
466 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
467 (VBROADCASTSDZrr VR128X:$src)>;
469 // Provide fallback in case the load node that is used in the patterns above
470 // is used by additional users, which prevents the pattern selection.
471 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
472 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
473 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
474 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
477 let Predicates = [HasAVX512] in {
478 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
480 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
481 addr:$src)), sub_ymm)>;
483 //===----------------------------------------------------------------------===//
484 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
487 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
488 RegisterClass DstRC, RegisterClass KRC,
489 ValueType OpVT, ValueType SrcVT> {
490 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
491 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
495 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
496 VK16, v16i32, v16i1>, EVEX_V512;
497 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
498 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
500 //===----------------------------------------------------------------------===//
503 // -- immediate form --
504 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
505 SDNode OpNode, PatFrag mem_frag,
506 X86MemOperand x86memop, ValueType OpVT> {
507 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
508 (ins RC:$src1, i8imm:$src2),
509 !strconcat(OpcodeStr,
510 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
512 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
514 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
515 (ins x86memop:$src1, i8imm:$src2),
516 !strconcat(OpcodeStr,
517 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
519 (OpVT (OpNode (mem_frag addr:$src1),
520 (i8 imm:$src2))))]>, EVEX;
523 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
524 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
525 let ExeDomain = SSEPackedDouble in
526 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
527 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
529 // -- VPERM - register form --
530 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
531 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
533 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
534 (ins RC:$src1, RC:$src2),
535 !strconcat(OpcodeStr,
536 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
538 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
540 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
541 (ins RC:$src1, x86memop:$src2),
542 !strconcat(OpcodeStr,
543 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
545 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
549 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
550 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
551 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
552 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
553 let ExeDomain = SSEPackedSingle in
554 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
555 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
556 let ExeDomain = SSEPackedDouble in
557 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
558 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
560 // -- VPERM2I - 3 source operands form --
561 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
562 PatFrag mem_frag, X86MemOperand x86memop,
564 let Constraints = "$src1 = $dst" in {
565 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
566 (ins RC:$src1, RC:$src2, RC:$src3),
567 !strconcat(OpcodeStr,
568 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
570 (OpVT (X86VPermv3 RC:$src1, RC:$src2, RC:$src3)))]>,
573 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
574 (ins RC:$src1, RC:$src2, x86memop:$src3),
575 !strconcat(OpcodeStr,
576 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
578 (OpVT (X86VPermv3 RC:$src1, RC:$src2,
579 (mem_frag addr:$src3))))]>, EVEX_4V;
582 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem,
583 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
584 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem,
585 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
586 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem,
587 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
588 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
589 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
591 //===----------------------------------------------------------------------===//
592 // AVX-512 - BLEND using mask
594 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
595 RegisterClass KRC, RegisterClass RC,
596 X86MemOperand x86memop, PatFrag mem_frag,
597 SDNode OpNode, ValueType vt> {
598 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
599 (ins KRC:$mask, RC:$src1, RC:$src2),
600 !strconcat(OpcodeStr,
601 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
602 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
603 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
605 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
606 (ins KRC:$mask, RC:$src1, x86memop:$src2),
607 !strconcat(OpcodeStr,
608 "\t{$src2, $src1, $mask, $dst|$dst, $mask, $src1, $src2}"),
613 let ExeDomain = SSEPackedSingle in
614 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps", VK16WM, VR512, f512mem,
615 memopv16f32, vselect, v16f32>,
616 EVEX_CD8<32, CD8VF>, EVEX_V512;
617 let ExeDomain = SSEPackedDouble in
618 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd", VK8WM, VR512, f512mem,
619 memopv8f64, vselect, v8f64>,
620 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
622 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd", VK16WM, VR512, f512mem,
623 memopv8i64, vselect, v16i32>,
624 EVEX_CD8<32, CD8VF>, EVEX_V512;
626 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq", VK8WM, VR512, f512mem,
627 memopv8i64, vselect, v8i64>, VEX_W,
628 EVEX_CD8<64, CD8VF>, EVEX_V512;
630 let Predicates = [HasAVX512] in {
631 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
632 (v8f32 VR256X:$src2))),
634 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
635 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
636 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
638 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
639 (v8i32 VR256X:$src2))),
641 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
642 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
643 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
646 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
647 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
648 SDNode OpNode, ValueType vt> {
649 def rr : AVX512BI<opc, MRMSrcReg,
650 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
651 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
652 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
653 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
654 def rm : AVX512BI<opc, MRMSrcMem,
655 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
656 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
657 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
658 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
661 defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
662 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512;
663 defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
664 memopv8i64, X86pcmpeqm, v8i64>, T8, EVEX_V512, VEX_W;
666 defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
667 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512;
668 defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
669 memopv8i64, X86pcmpgtm, v8i64>, T8, EVEX_V512, VEX_W;
671 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
672 (COPY_TO_REGCLASS (VPCMPGTDZrr
673 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
674 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
676 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
677 (COPY_TO_REGCLASS (VPCMPEQDZrr
678 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
679 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
681 multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
682 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
683 SDNode OpNode, ValueType vt, Operand CC, string asm,
685 def rri : AVX512AIi8<opc, MRMSrcReg,
686 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
687 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
688 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
689 def rmi : AVX512AIi8<opc, MRMSrcMem,
690 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
691 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
692 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
693 // Accept explicit immediate argument form instead of comparison code.
694 let neverHasSideEffects = 1 in {
695 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
696 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
697 asm_alt, [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
698 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
699 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
700 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
704 defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv16i32,
705 X86cmpm, v16i32, AVXCC,
706 "vpcmp${cc}d\t{$src2, $src1, $dst|$dst, $src1, $src2}",
707 "vpcmpd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
708 EVEX_V512, EVEX_CD8<32, CD8VF>;
709 defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv16i32,
710 X86cmpmu, v16i32, AVXCC,
711 "vpcmp${cc}ud\t{$src2, $src1, $dst|$dst, $src1, $src2}",
712 "vpcmpud\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
713 EVEX_V512, EVEX_CD8<32, CD8VF>;
715 defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64,
716 X86cmpm, v8i64, AVXCC,
717 "vpcmp${cc}q\t{$src2, $src1, $dst|$dst, $src1, $src2}",
718 "vpcmpq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
719 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
720 defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64,
721 X86cmpmu, v8i64, AVXCC,
722 "vpcmp${cc}uq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
723 "vpcmpuq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
724 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
726 // avx512_cmp_packed - sse 1 & 2 compare packed instructions
727 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
728 X86MemOperand x86memop, Operand CC,
729 SDNode OpNode, ValueType vt, string asm,
730 string asm_alt, Domain d> {
731 def rri : AVX512PIi8<0xC2, MRMSrcReg,
732 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
733 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
734 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
735 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
737 (OpNode (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
739 // Accept explicit immediate argument form instead of comparison code.
740 let neverHasSideEffects = 1 in {
741 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
742 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
744 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
745 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
750 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, AVXCC, X86cmpm, v16f32,
751 "vcmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
752 "vcmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
753 SSEPackedSingle>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VF>;
754 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, AVXCC, X86cmpm, v8f64,
755 "vcmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
756 "vcmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
757 SSEPackedDouble>, OpSize, EVEX_4V, VEX_W, EVEX_V512,
760 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
761 (COPY_TO_REGCLASS (VCMPPSZrri
762 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
763 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
765 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
766 (COPY_TO_REGCLASS (VPCMPDZrri
767 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
768 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
770 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
771 (COPY_TO_REGCLASS (VPCMPUDZrri
772 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
773 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
776 // Mask register copy, including
777 // - copy between mask registers
778 // - load/store mask registers
779 // - copy from GPR to mask register and vice versa
781 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
782 string OpcodeStr, RegisterClass KRC,
783 ValueType vt, X86MemOperand x86memop> {
784 let neverHasSideEffects = 1 in {
785 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
786 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
788 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
789 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
790 [(set KRC:$dst, (vt (load addr:$src)))]>;
792 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
793 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
797 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
799 RegisterClass KRC, RegisterClass GRC> {
800 let neverHasSideEffects = 1 in {
801 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
802 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
803 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
804 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
808 let Predicates = [HasAVX512] in {
809 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
811 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
815 let Predicates = [HasAVX512] in {
816 // GR16 from/to 16-bit mask
817 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
818 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
819 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
820 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
822 // Store kreg in memory
823 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
824 (KMOVWmk addr:$dst, VK16:$src)>;
826 def : Pat<(store (v8i1 VK8:$src), addr:$dst),
827 (KMOVWmk addr:$dst, (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16)))>;
829 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
830 let Predicates = [HasAVX512] in {
831 // GR from/to 8-bit mask without native support
832 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
834 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
836 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
838 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
842 // Mask unary operation
844 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
845 RegisterClass KRC, SDPatternOperator OpNode> {
846 let Predicates = [HasAVX512] in
847 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
848 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
849 [(set KRC:$dst, (OpNode KRC:$src))]>;
852 multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
853 SDPatternOperator OpNode> {
854 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
858 defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
860 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
861 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
862 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
864 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
865 def : Pat<(not VK8:$src),
867 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
869 // Mask binary operation
870 // - KADD, KAND, KANDN, KOR, KXNOR, KXOR
871 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
872 RegisterClass KRC, SDPatternOperator OpNode> {
873 let Predicates = [HasAVX512] in
874 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
875 !strconcat(OpcodeStr,
876 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
877 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
880 multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
881 SDPatternOperator OpNode> {
882 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
886 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
887 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
889 let isCommutable = 1 in {
890 defm KADD : avx512_mask_binop_w<0x4a, "kadd", add>;
891 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
892 let isCommutable = 0 in
893 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
894 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
895 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
896 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
899 multiclass avx512_mask_binop_int<string IntName, string InstName> {
900 let Predicates = [HasAVX512] in
901 def : Pat<(!cast<Intrinsic>("int_x86_"##IntName##"_v16i1")
902 VK16:$src1, VK16:$src2),
903 (!cast<Instruction>(InstName##"Wrr") VK16:$src1, VK16:$src2)>;
906 defm : avx512_mask_binop_int<"kadd", "KADD">;
907 defm : avx512_mask_binop_int<"kand", "KAND">;
908 defm : avx512_mask_binop_int<"kandn", "KANDN">;
909 defm : avx512_mask_binop_int<"kor", "KOR">;
910 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
911 defm : avx512_mask_binop_int<"kxor", "KXOR">;
912 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
913 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
914 let Predicates = [HasAVX512] in
915 def : Pat<(OpNode VK8:$src1, VK8:$src2),
917 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
918 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
921 defm : avx512_binop_pat<and, KANDWrr>;
922 defm : avx512_binop_pat<andn, KANDNWrr>;
923 defm : avx512_binop_pat<or, KORWrr>;
924 defm : avx512_binop_pat<xnor, KXNORWrr>;
925 defm : avx512_binop_pat<xor, KXORWrr>;
928 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
929 RegisterClass KRC1, RegisterClass KRC2> {
930 let Predicates = [HasAVX512] in
931 def rr : I<opc, MRMSrcReg, (outs KRC1:$dst), (ins KRC2:$src1, KRC2:$src2),
932 !strconcat(OpcodeStr,
933 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
936 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
937 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16, VK8>,
938 VEX_4V, VEX_L, OpSize, TB;
941 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
943 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
944 let Predicates = [HasAVX512] in
945 def : Pat<(!cast<Intrinsic>("int_x86_"##IntName##"_v16i1")
946 VK8:$src1, VK8:$src2),
947 (!cast<Instruction>(InstName##"BWrr") VK8:$src1, VK8:$src2)>;
950 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
952 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
954 let Predicates = [HasAVX512], Defs = [EFLAGS] in
955 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
956 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
957 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
960 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
961 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
965 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
966 defm KTEST : avx512_mask_testop_w<0x99, "ktest", X86ktest>;
969 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
971 let Predicates = [HasAVX512] in
972 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
973 !strconcat(OpcodeStr,
974 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
975 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
978 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
980 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
981 VEX, OpSize, TA, VEX_W;
984 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", shl>;
985 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", srl>;
987 // Mask setting all 0s or 1s
988 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
989 let Predicates = [HasAVX512] in
990 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
991 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
992 [(set KRC:$dst, (VT Val))]>;
995 multiclass avx512_mask_setop_w<PatFrag Val> {
996 defm B : avx512_mask_setop<VK8, v8i1, Val>;
997 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1000 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1001 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1003 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1004 let Predicates = [HasAVX512] in {
1005 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1006 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1008 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1009 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1011 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1012 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1014 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1015 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1017 //===----------------------------------------------------------------------===//
1018 // AVX-512 - Aligned and unaligned load and store
1021 multiclass avx512_mov_packed<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1022 X86MemOperand x86memop, PatFrag ld_frag,
1023 string asm, Domain d> {
1024 let neverHasSideEffects = 1 in
1025 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1026 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>,
1028 let canFoldAsLoad = 1 in
1029 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1030 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1031 [(set RC:$dst, (ld_frag addr:$src))], d>, EVEX;
1032 let Constraints = "$src1 = $dst" in {
1033 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1034 (ins RC:$src1, KRC:$mask, RC:$src2),
1036 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1038 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1039 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1041 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1042 [], d>, EVEX, EVEX_K;
1046 defm VMOVAPSZ : avx512_mov_packed<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1047 "vmovaps", SSEPackedSingle>,
1048 EVEX_V512, EVEX_CD8<32, CD8VF>;
1049 defm VMOVAPDZ : avx512_mov_packed<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1050 "vmovapd", SSEPackedDouble>,
1051 OpSize, EVEX_V512, VEX_W,
1052 EVEX_CD8<64, CD8VF>;
1053 defm VMOVUPSZ : avx512_mov_packed<0x10, VR512, VK16WM, f512mem, loadv16f32,
1054 "vmovups", SSEPackedSingle>,
1055 EVEX_V512, EVEX_CD8<32, CD8VF>;
1056 defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64,
1057 "vmovupd", SSEPackedDouble>,
1058 OpSize, EVEX_V512, VEX_W,
1059 EVEX_CD8<64, CD8VF>;
1060 def VMOVAPSZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1061 "vmovaps\t{$src, $dst|$dst, $src}",
1062 [(alignedstore512 (v16f32 VR512:$src), addr:$dst)],
1063 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1064 def VMOVAPDZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1065 "vmovapd\t{$src, $dst|$dst, $src}",
1066 [(alignedstore512 (v8f64 VR512:$src), addr:$dst)],
1067 SSEPackedDouble>, EVEX, EVEX_V512,
1068 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1069 def VMOVUPSZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1070 "vmovups\t{$src, $dst|$dst, $src}",
1071 [(store (v16f32 VR512:$src), addr:$dst)],
1072 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1073 def VMOVUPDZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1074 "vmovupd\t{$src, $dst|$dst, $src}",
1075 [(store (v8f64 VR512:$src), addr:$dst)],
1076 SSEPackedDouble>, EVEX, EVEX_V512,
1077 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1079 let neverHasSideEffects = 1 in {
1080 def VMOVDQA32rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1082 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1084 def VMOVDQA64rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1086 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1087 EVEX, EVEX_V512, VEX_W;
1088 let mayStore = 1 in {
1089 def VMOVDQA32mr : AVX512BI<0x7F, MRMDestMem, (outs),
1090 (ins i512mem:$dst, VR512:$src),
1091 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1092 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1093 def VMOVDQA64mr : AVX512BI<0x7F, MRMDestMem, (outs),
1094 (ins i512mem:$dst, VR512:$src),
1095 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1096 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1098 let mayLoad = 1 in {
1099 def VMOVDQA32rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1101 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1102 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1103 def VMOVDQA64rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1105 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1106 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1110 // 512-bit aligned load/store
1111 def : Pat<(alignedloadv8i64 addr:$src), (VMOVDQA64rm addr:$src)>;
1112 def : Pat<(alignedloadv16i32 addr:$src), (VMOVDQA32rm addr:$src)>;
1114 def : Pat<(alignedstore512 (v8i64 VR512:$src), addr:$dst),
1115 (VMOVDQA64mr addr:$dst, VR512:$src)>;
1116 def : Pat<(alignedstore512 (v16i32 VR512:$src), addr:$dst),
1117 (VMOVDQA32mr addr:$dst, VR512:$src)>;
1119 multiclass avx512_mov_int<bits<8> load_opc, bits<8> store_opc, string asm,
1120 RegisterClass RC, RegisterClass KRC,
1121 PatFrag ld_frag, X86MemOperand x86memop> {
1122 let neverHasSideEffects = 1 in
1123 def rr : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1124 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>, EVEX;
1125 let canFoldAsLoad = 1 in
1126 def rm : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1127 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1128 [(set RC:$dst, (ld_frag addr:$src))]>, EVEX;
1130 def mr : AVX512XSI<store_opc, MRMDestMem, (outs),
1131 (ins x86memop:$dst, VR512:$src),
1132 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>, EVEX;
1133 let Constraints = "$src1 = $dst" in {
1134 def rrk : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst),
1135 (ins RC:$src1, KRC:$mask, RC:$src2),
1137 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), []>,
1139 def rmk : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst),
1140 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1142 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1147 defm VMOVDQU32 : avx512_mov_int<0x6F, 0x7F, "vmovdqu32", VR512, VK16WM,
1148 memopv16i32, i512mem>,
1149 EVEX_V512, EVEX_CD8<32, CD8VF>;
1150 defm VMOVDQU64 : avx512_mov_int<0x6F, 0x7F, "vmovdqu64", VR512, VK8WM,
1151 memopv8i64, i512mem>,
1152 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1154 // 512-bit unaligned load/store
1155 def : Pat<(loadv8i64 addr:$src), (VMOVDQU64rm addr:$src)>;
1156 def : Pat<(loadv16i32 addr:$src), (VMOVDQU32rm addr:$src)>;
1158 def : Pat<(store (v8i64 VR512:$src), addr:$dst),
1159 (VMOVDQU64mr addr:$dst, VR512:$src)>;
1160 def : Pat<(store (v16i32 VR512:$src), addr:$dst),
1161 (VMOVDQU32mr addr:$dst, VR512:$src)>;
1163 let AddedComplexity = 20 in {
1164 def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1165 (v16f32 VR512:$src2))),
1166 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1167 def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1168 (v8f64 VR512:$src2))),
1169 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1170 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1171 (v16i32 VR512:$src2))),
1172 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1173 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1174 (v8i64 VR512:$src2))),
1175 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1177 // Move Int Doubleword to Packed Double Int
1179 def VMOVDI2PDIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1180 "vmovd{z}\t{$src, $dst|$dst, $src}",
1182 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1184 def VMOVDI2PDIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1185 "vmovd{z}\t{$src, $dst|$dst, $src}",
1187 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1188 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1189 def VMOV64toPQIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1190 "vmovq{z}\t{$src, $dst|$dst, $src}",
1192 (v2i64 (scalar_to_vector GR64:$src)))],
1193 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
1194 let isCodeGenOnly = 1 in {
1195 def VMOV64toSDZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1196 "vmovq{z}\t{$src, $dst|$dst, $src}",
1197 [(set FR64:$dst, (bitconvert GR64:$src))],
1198 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1199 def VMOVSDto64Zrr : AVX512SI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1200 "vmovq{z}\t{$src, $dst|$dst, $src}",
1201 [(set GR64:$dst, (bitconvert FR64:$src))],
1202 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1204 def VMOVSDto64Zmr : AVX512SI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1205 "vmovq{z}\t{$src, $dst|$dst, $src}",
1206 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1207 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1208 EVEX_CD8<64, CD8VT1>;
1210 // Move Int Doubleword to Single Scalar
1212 let isCodeGenOnly = 1 in {
1213 def VMOVDI2SSZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1214 "vmovd{z}\t{$src, $dst|$dst, $src}",
1215 [(set FR32X:$dst, (bitconvert GR32:$src))],
1216 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1218 def VMOVDI2SSZrm : AVX512SI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1219 "vmovd{z}\t{$src, $dst|$dst, $src}",
1220 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1221 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1224 // Move Packed Doubleword Int to Packed Double Int
1226 def VMOVPDI2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1227 "vmovd{z}\t{$src, $dst|$dst, $src}",
1228 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1229 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1231 def VMOVPDI2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1232 (ins i32mem:$dst, VR128X:$src),
1233 "vmovd{z}\t{$src, $dst|$dst, $src}",
1234 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1235 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1236 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1238 // Move Packed Doubleword Int first element to Doubleword Int
1240 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1241 "vmovq{z}\t{$src, $dst|$dst, $src}",
1242 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1244 IIC_SSE_MOVD_ToGP>, TB, OpSize, EVEX, VEX_LIG, VEX_W,
1245 Requires<[HasAVX512, In64BitMode]>;
1247 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
1248 (ins i64mem:$dst, VR128X:$src),
1249 "vmovq{z}\t{$src, $dst|$dst, $src}",
1250 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1251 addr:$dst)], IIC_SSE_MOVDQ>,
1252 EVEX, OpSize, VEX_LIG, VEX_W, TB, EVEX_CD8<64, CD8VT1>,
1253 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1255 // Move Scalar Single to Double Int
1257 let isCodeGenOnly = 1 in {
1258 def VMOVSS2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst),
1260 "vmovd{z}\t{$src, $dst|$dst, $src}",
1261 [(set GR32:$dst, (bitconvert FR32X:$src))],
1262 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1263 def VMOVSS2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1264 (ins i32mem:$dst, FR32X:$src),
1265 "vmovd{z}\t{$src, $dst|$dst, $src}",
1266 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1267 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1270 // Move Quadword Int to Packed Quadword Int
1272 def VMOVQI2PQIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst),
1274 "vmovq{z}\t{$src, $dst|$dst, $src}",
1276 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1277 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1279 //===----------------------------------------------------------------------===//
1280 // AVX-512 MOVSS, MOVSD
1281 //===----------------------------------------------------------------------===//
1283 multiclass avx512_move_scalar <string asm, RegisterClass RC,
1284 SDNode OpNode, ValueType vt,
1285 X86MemOperand x86memop, PatFrag mem_pat> {
1286 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1287 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1288 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1289 (scalar_to_vector RC:$src2))))],
1290 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1291 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1292 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1293 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1295 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1296 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1297 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1301 let ExeDomain = SSEPackedSingle in
1302 defm VMOVSSZ : avx512_move_scalar<"movss{z}", FR32X, X86Movss, v4f32, f32mem,
1303 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1305 let ExeDomain = SSEPackedDouble in
1306 defm VMOVSDZ : avx512_move_scalar<"movsd{z}", FR64X, X86Movsd, v2f64, f64mem,
1307 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1310 // For the disassembler
1311 let isCodeGenOnly = 1 in {
1312 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1313 (ins VR128X:$src1, FR32X:$src2),
1314 "movss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1316 XS, EVEX_4V, VEX_LIG;
1317 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1318 (ins VR128X:$src1, FR64X:$src2),
1319 "movsd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1321 XD, EVEX_4V, VEX_LIG, VEX_W;
1324 let Predicates = [HasAVX512] in {
1325 let AddedComplexity = 15 in {
1326 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1327 // MOVS{S,D} to the lower bits.
1328 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1329 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1330 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1331 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1332 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1333 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1334 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1335 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1337 // Move low f32 and clear high bits.
1338 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1339 (SUBREG_TO_REG (i32 0),
1340 (VMOVSSZrr (v4f32 (V_SET0)),
1341 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1342 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1343 (SUBREG_TO_REG (i32 0),
1344 (VMOVSSZrr (v4i32 (V_SET0)),
1345 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1348 let AddedComplexity = 20 in {
1349 // MOVSSrm zeros the high parts of the register; represent this
1350 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1351 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1352 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1353 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1354 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1355 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1356 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1358 // MOVSDrm zeros the high parts of the register; represent this
1359 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1360 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1361 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1362 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1363 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1364 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1365 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1366 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1367 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1368 def : Pat<(v2f64 (X86vzload addr:$src)),
1369 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1371 // Represent the same patterns above but in the form they appear for
1373 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1374 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
1375 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
1376 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1377 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1378 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1379 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1380 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1381 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1383 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1384 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1385 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1386 FR32X:$src)), sub_xmm)>;
1387 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1388 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1389 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1390 FR64X:$src)), sub_xmm)>;
1391 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1392 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
1393 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
1395 // Move low f64 and clear high bits.
1396 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1397 (SUBREG_TO_REG (i32 0),
1398 (VMOVSDZrr (v2f64 (V_SET0)),
1399 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1401 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1402 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1403 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1405 // Extract and store.
1406 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1408 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1409 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1411 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1413 // Shuffle with VMOVSS
1414 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1415 (VMOVSSZrr (v4i32 VR128X:$src1),
1416 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1417 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1418 (VMOVSSZrr (v4f32 VR128X:$src1),
1419 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1422 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1423 (SUBREG_TO_REG (i32 0),
1424 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1425 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1427 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1428 (SUBREG_TO_REG (i32 0),
1429 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1430 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1433 // Shuffle with VMOVSD
1434 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1435 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1436 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1437 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1438 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1439 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1440 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1441 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1444 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1445 (SUBREG_TO_REG (i32 0),
1446 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1447 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1449 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1450 (SUBREG_TO_REG (i32 0),
1451 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1452 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1455 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1456 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1457 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1458 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1459 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1460 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1461 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1462 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1465 let AddedComplexity = 15 in
1466 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1468 "vmovq{z}\t{$src, $dst|$dst, $src}",
1469 [(set VR128X:$dst, (v2i64 (X86vzmovl
1470 (v2i64 VR128X:$src))))],
1471 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1473 let AddedComplexity = 20 in
1474 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1476 "vmovq{z}\t{$src, $dst|$dst, $src}",
1477 [(set VR128X:$dst, (v2i64 (X86vzmovl
1478 (loadv2i64 addr:$src))))],
1479 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1480 EVEX_CD8<8, CD8VT8>;
1482 let Predicates = [HasAVX512] in {
1483 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1484 let AddedComplexity = 20 in {
1485 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1486 (VMOVDI2PDIZrm addr:$src)>;
1487 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
1488 (VMOV64toPQIZrr GR64:$src)>;
1489 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
1490 (VMOVDI2PDIZrr GR32:$src)>;
1492 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1493 (VMOVDI2PDIZrm addr:$src)>;
1494 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1495 (VMOVDI2PDIZrm addr:$src)>;
1496 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1497 (VMOVZPQILo2PQIZrm addr:$src)>;
1498 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1499 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1502 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1503 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1504 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1505 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1506 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1507 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1508 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1511 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
1512 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1514 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
1515 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1517 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
1518 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1520 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
1521 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1523 //===----------------------------------------------------------------------===//
1524 // AVX-512 - Integer arithmetic
1526 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1527 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1528 X86MemOperand x86memop, PatFrag scalar_mfrag,
1529 X86MemOperand x86scalar_mop, string BrdcstStr,
1530 OpndItins itins, bit IsCommutable = 0> {
1531 let isCommutable = IsCommutable in
1532 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1533 (ins RC:$src1, RC:$src2),
1534 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1535 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1537 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1538 (ins RC:$src1, x86memop:$src2),
1539 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1540 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
1542 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1543 (ins RC:$src1, x86scalar_mop:$src2),
1544 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1545 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1546 [(set RC:$dst, (OpNode RC:$src1,
1547 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1548 itins.rm>, EVEX_4V, EVEX_B;
1550 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr,
1551 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
1552 PatFrag memop_frag, X86MemOperand x86memop,
1554 bit IsCommutable = 0> {
1555 let isCommutable = IsCommutable in
1556 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1557 (ins RC:$src1, RC:$src2),
1558 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1559 []>, EVEX_4V, VEX_W;
1560 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1561 (ins RC:$src1, x86memop:$src2),
1562 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1563 []>, EVEX_4V, VEX_W;
1566 defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VR512, memopv16i32,
1567 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1568 EVEX_V512, EVEX_CD8<32, CD8VF>;
1570 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VR512, memopv16i32,
1571 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 0>,
1572 EVEX_V512, EVEX_CD8<32, CD8VF>;
1574 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VR512, memopv16i32,
1575 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1576 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1578 defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VR512, memopv8i64,
1579 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 1>,
1580 EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
1582 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VR512, memopv8i64,
1583 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1584 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1586 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32,
1587 VR512, memopv8i64, i512mem, SSE_INTALU_ITINS_P, 1>, T8,
1588 EVEX_V512, EVEX_CD8<64, CD8VF>;
1590 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32,
1591 VR512, memopv8i64, i512mem, SSE_INTMUL_ITINS_P, 1>, EVEX_V512,
1592 EVEX_CD8<64, CD8VF>;
1594 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
1595 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1597 //===----------------------------------------------------------------------===//
1598 // AVX-512 - Unpack Instructions
1599 //===----------------------------------------------------------------------===//
1601 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
1602 PatFrag mem_frag, RegisterClass RC,
1603 X86MemOperand x86memop, string asm,
1605 def rr : AVX512PI<opc, MRMSrcReg,
1606 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1608 (vt (OpNode RC:$src1, RC:$src2)))],
1610 def rm : AVX512PI<opc, MRMSrcMem,
1611 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1613 (vt (OpNode RC:$src1,
1614 (bitconvert (mem_frag addr:$src2)))))],
1618 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
1619 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1620 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1621 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
1622 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1623 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1624 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
1625 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1626 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1627 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
1628 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1629 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1631 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
1632 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1633 X86MemOperand x86memop> {
1634 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1635 (ins RC:$src1, RC:$src2),
1636 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1637 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1638 IIC_SSE_UNPCK>, EVEX_4V;
1639 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1640 (ins RC:$src1, x86memop:$src2),
1641 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1642 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
1643 (bitconvert (memop_frag addr:$src2)))))],
1644 IIC_SSE_UNPCK>, EVEX_4V;
1646 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
1647 VR512, memopv16i32, i512mem>, EVEX_V512,
1648 EVEX_CD8<32, CD8VF>;
1649 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
1650 VR512, memopv8i64, i512mem>, EVEX_V512,
1651 VEX_W, EVEX_CD8<64, CD8VF>;
1652 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
1653 VR512, memopv16i32, i512mem>, EVEX_V512,
1654 EVEX_CD8<32, CD8VF>;
1655 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
1656 VR512, memopv8i64, i512mem>, EVEX_V512,
1657 VEX_W, EVEX_CD8<64, CD8VF>;
1658 //===----------------------------------------------------------------------===//
1662 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
1663 SDNode OpNode, PatFrag mem_frag,
1664 X86MemOperand x86memop, ValueType OpVT> {
1665 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
1666 (ins RC:$src1, i8imm:$src2),
1667 !strconcat(OpcodeStr,
1668 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1670 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
1672 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
1673 (ins x86memop:$src1, i8imm:$src2),
1674 !strconcat(OpcodeStr,
1675 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1677 (OpVT (OpNode (mem_frag addr:$src1),
1678 (i8 imm:$src2))))]>, EVEX;
1681 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
1682 i512mem, v16i32>, OpSize, EVEX_V512, EVEX_CD8<32, CD8VF>;
1684 let ExeDomain = SSEPackedSingle in
1685 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
1686 memopv16f32, i512mem, v16f32>, OpSize, TA, EVEX_V512,
1687 EVEX_CD8<32, CD8VF>;
1688 let ExeDomain = SSEPackedDouble in
1689 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
1690 memopv8f64, i512mem, v8f64>, OpSize, TA, EVEX_V512,
1691 VEX_W, EVEX_CD8<32, CD8VF>;
1693 def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1694 (VPERMILPSZri VR512:$src1, imm:$imm)>;
1695 def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1696 (VPERMILPDZri VR512:$src1, imm:$imm)>;
1698 //===----------------------------------------------------------------------===//
1699 // AVX-512 Logical Instructions
1700 //===----------------------------------------------------------------------===//
1702 defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VR512, memopv16i32,
1703 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1704 EVEX_V512, EVEX_CD8<32, CD8VF>;
1705 defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VR512, memopv8i64,
1706 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1707 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1708 defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VR512, memopv16i32,
1709 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1710 EVEX_V512, EVEX_CD8<32, CD8VF>;
1711 defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VR512, memopv8i64,
1712 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1713 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1714 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VR512, memopv16i32,
1715 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1716 EVEX_V512, EVEX_CD8<32, CD8VF>;
1717 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VR512, memopv8i64,
1718 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1719 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1720 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VR512,
1721 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1722 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1723 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VR512, memopv8i64,
1724 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 0>,
1725 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1727 //===----------------------------------------------------------------------===//
1728 // AVX-512 FP arithmetic
1729 //===----------------------------------------------------------------------===//
1731 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1733 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss{z}"), OpNode, FR32X,
1734 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
1735 EVEX_CD8<32, CD8VT1>;
1736 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd{z}"), OpNode, FR64X,
1737 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
1738 EVEX_CD8<64, CD8VT1>;
1741 let isCommutable = 1 in {
1742 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
1743 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
1744 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
1745 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
1747 let isCommutable = 0 in {
1748 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
1749 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
1752 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1753 RegisterClass RC, ValueType vt,
1754 X86MemOperand x86memop, PatFrag mem_frag,
1755 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
1757 Domain d, OpndItins itins, bit commutable> {
1758 let isCommutable = commutable in
1759 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1760 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1761 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
1763 let mayLoad = 1 in {
1764 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1765 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1766 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
1767 itins.rm, d>, EVEX_4V, TB;
1768 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
1769 (ins RC:$src1, x86scalar_mop:$src2),
1770 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1771 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1772 [(set RC:$dst, (OpNode RC:$src1,
1773 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1774 itins.rm, d>, EVEX_4V, EVEX_B, TB;
1778 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VR512, v16f32, f512mem,
1779 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1780 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1782 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VR512, v8f64, f512mem,
1783 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1784 SSE_ALU_ITINS_P.d, 1>,
1785 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1787 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VR512, v16f32, f512mem,
1788 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1789 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1790 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VR512, v8f64, f512mem,
1791 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1792 SSE_ALU_ITINS_P.d, 1>,
1793 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1795 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VR512, v16f32, f512mem,
1796 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1797 SSE_ALU_ITINS_P.s, 1>,
1798 EVEX_V512, EVEX_CD8<32, CD8VF>;
1799 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VR512, v16f32, f512mem,
1800 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1801 SSE_ALU_ITINS_P.s, 1>,
1802 EVEX_V512, EVEX_CD8<32, CD8VF>;
1804 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VR512, v8f64, f512mem,
1805 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1806 SSE_ALU_ITINS_P.d, 1>,
1807 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1808 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VR512, v8f64, f512mem,
1809 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1810 SSE_ALU_ITINS_P.d, 1>,
1811 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1813 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VR512, v16f32, f512mem,
1814 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1815 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1816 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VR512, v16f32, f512mem,
1817 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1818 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1820 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VR512, v8f64, f512mem,
1821 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1822 SSE_ALU_ITINS_P.d, 0>,
1823 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1824 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VR512, v8f64, f512mem,
1825 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1826 SSE_ALU_ITINS_P.d, 0>,
1827 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1829 //===----------------------------------------------------------------------===//
1830 // AVX-512 VPTESTM instructions
1831 //===----------------------------------------------------------------------===//
1833 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1834 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
1835 SDNode OpNode, ValueType vt> {
1836 def rr : AVX5128I<opc, MRMSrcReg,
1837 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
1838 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1839 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))]>, EVEX_4V;
1840 def rm : AVX5128I<opc, MRMSrcMem,
1841 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
1842 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1843 [(set KRC:$dst, (OpNode (vt RC:$src1),
1844 (bitconvert (memop_frag addr:$src2))))]>, EVEX_4V;
1847 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
1848 memopv16i32, X86testm, v16i32>, EVEX_V512,
1849 EVEX_CD8<32, CD8VF>;
1850 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
1851 memopv8i64, X86testm, v8i64>, EVEX_V512, VEX_W,
1852 EVEX_CD8<64, CD8VF>;
1854 //===----------------------------------------------------------------------===//
1855 // AVX-512 Shift instructions
1856 //===----------------------------------------------------------------------===//
1857 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
1858 string OpcodeStr, SDNode OpNode, RegisterClass RC,
1859 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
1860 RegisterClass KRC> {
1861 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
1862 (ins RC:$src1, i8imm:$src2),
1863 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1864 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
1865 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
1866 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
1867 (ins KRC:$mask, RC:$src1, i8imm:$src2),
1868 !strconcat(OpcodeStr,
1869 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1870 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
1871 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
1872 (ins x86memop:$src1, i8imm:$src2),
1873 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1874 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
1875 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
1876 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
1877 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
1878 !strconcat(OpcodeStr,
1879 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1880 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
1883 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1884 RegisterClass RC, ValueType vt, ValueType SrcVT,
1885 PatFrag bc_frag, RegisterClass KRC> {
1886 // src2 is always 128-bit
1887 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1888 (ins RC:$src1, VR128X:$src2),
1889 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1890 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
1891 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
1892 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1893 (ins KRC:$mask, RC:$src1, VR128X:$src2),
1894 !strconcat(OpcodeStr,
1895 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1896 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
1897 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1898 (ins RC:$src1, i128mem:$src2),
1899 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1900 [(set RC:$dst, (vt (OpNode RC:$src1,
1901 (bc_frag (memopv2i64 addr:$src2)))))],
1902 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
1903 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1904 (ins KRC:$mask, RC:$src1, i128mem:$src2),
1905 !strconcat(OpcodeStr,
1906 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1907 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
1910 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
1911 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
1912 EVEX_V512, EVEX_CD8<32, CD8VF>;
1913 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
1914 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
1915 EVEX_CD8<32, CD8VQ>;
1917 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
1918 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
1919 EVEX_CD8<64, CD8VF>, VEX_W;
1920 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
1921 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
1922 EVEX_CD8<64, CD8VQ>, VEX_W;
1924 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
1925 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
1926 EVEX_CD8<32, CD8VF>;
1927 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
1928 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
1929 EVEX_CD8<32, CD8VQ>;
1931 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
1932 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
1933 EVEX_CD8<64, CD8VF>, VEX_W;
1934 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
1935 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
1936 EVEX_CD8<64, CD8VQ>, VEX_W;
1938 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
1939 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
1940 EVEX_V512, EVEX_CD8<32, CD8VF>;
1941 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
1942 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
1943 EVEX_CD8<32, CD8VQ>;
1945 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
1946 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
1947 EVEX_CD8<64, CD8VF>, VEX_W;
1948 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
1949 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
1950 EVEX_CD8<64, CD8VQ>, VEX_W;
1952 //===-------------------------------------------------------------------===//
1953 // Variable Bit Shifts
1954 //===-------------------------------------------------------------------===//
1955 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
1956 RegisterClass RC, ValueType vt,
1957 X86MemOperand x86memop, PatFrag mem_frag> {
1958 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
1959 (ins RC:$src1, RC:$src2),
1960 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1962 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
1964 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1965 (ins RC:$src1, x86memop:$src2),
1966 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1968 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
1972 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
1973 i512mem, memopv16i32>, EVEX_V512,
1974 EVEX_CD8<32, CD8VF>;
1975 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
1976 i512mem, memopv8i64>, EVEX_V512, VEX_W,
1977 EVEX_CD8<64, CD8VF>;
1978 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
1979 i512mem, memopv16i32>, EVEX_V512,
1980 EVEX_CD8<32, CD8VF>;
1981 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
1982 i512mem, memopv8i64>, EVEX_V512, VEX_W,
1983 EVEX_CD8<64, CD8VF>;
1984 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
1985 i512mem, memopv16i32>, EVEX_V512,
1986 EVEX_CD8<32, CD8VF>;
1987 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
1988 i512mem, memopv8i64>, EVEX_V512, VEX_W,
1989 EVEX_CD8<64, CD8VF>;
1991 //===----------------------------------------------------------------------===//
1992 // AVX-512 - MOVDDUP
1993 //===----------------------------------------------------------------------===//
1995 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
1996 X86MemOperand x86memop, PatFrag memop_frag> {
1997 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1998 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1999 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
2000 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2001 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2003 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
2006 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
2007 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
2008 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
2009 (VMOVDDUPZrm addr:$src)>;
2011 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
2012 (ins VR128X:$src1, VR128X:$src2),
2013 "vmovlhps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2014 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2015 IIC_SSE_MOV_LH>, EVEX_4V;
2016 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2017 (ins VR128X:$src1, VR128X:$src2),
2018 "vmovhlps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2019 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2020 IIC_SSE_MOV_LH>, EVEX_4V;
2022 let Predicates = [HasAVX512] in {
2024 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2025 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2026 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2027 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
2030 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2031 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2034 //===----------------------------------------------------------------------===//
2035 // FMA - Fused Multiply Operations
2037 let Constraints = "$src1 = $dst" in {
2038 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2039 RegisterClass RC, X86MemOperand x86memop,
2040 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2041 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2042 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2043 (ins RC:$src1, RC:$src2, RC:$src3),
2044 !strconcat(OpcodeStr,"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2045 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2048 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2049 (ins RC:$src1, RC:$src2, x86memop:$src3),
2050 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2051 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2052 (mem_frag addr:$src3))))]>;
2053 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2054 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2055 !strconcat(OpcodeStr, "\t{${src3}", BrdcstStr,
2056 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2057 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2058 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2060 } // Constraints = "$src1 = $dst"
2062 let ExeDomain = SSEPackedSingle in {
2063 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2064 memopv16f32, f32mem, loadf32, "{1to16}",
2065 X86Fmadd, v16f32>, EVEX_V512,
2066 EVEX_CD8<32, CD8VF>;
2067 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2068 memopv16f32, f32mem, loadf32, "{1to16}",
2069 X86Fmsub, v16f32>, EVEX_V512,
2070 EVEX_CD8<32, CD8VF>;
2071 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2072 memopv16f32, f32mem, loadf32, "{1to16}",
2073 X86Fmaddsub, v16f32>,
2074 EVEX_V512, EVEX_CD8<32, CD8VF>;
2075 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2076 memopv16f32, f32mem, loadf32, "{1to16}",
2077 X86Fmsubadd, v16f32>,
2078 EVEX_V512, EVEX_CD8<32, CD8VF>;
2079 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2080 memopv16f32, f32mem, loadf32, "{1to16}",
2081 X86Fnmadd, v16f32>, EVEX_V512,
2082 EVEX_CD8<32, CD8VF>;
2083 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2084 memopv16f32, f32mem, loadf32, "{1to16}",
2085 X86Fnmsub, v16f32>, EVEX_V512,
2086 EVEX_CD8<32, CD8VF>;
2088 let ExeDomain = SSEPackedDouble in {
2089 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2090 memopv8f64, f64mem, loadf64, "{1to8}",
2091 X86Fmadd, v8f64>, EVEX_V512,
2092 VEX_W, EVEX_CD8<64, CD8VF>;
2093 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2094 memopv8f64, f64mem, loadf64, "{1to8}",
2095 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2096 EVEX_CD8<64, CD8VF>;
2097 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2098 memopv8f64, f64mem, loadf64, "{1to8}",
2099 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2100 EVEX_CD8<64, CD8VF>;
2101 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2102 memopv8f64, f64mem, loadf64, "{1to8}",
2103 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2104 EVEX_CD8<64, CD8VF>;
2105 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2106 memopv8f64, f64mem, loadf64, "{1to8}",
2107 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2108 EVEX_CD8<64, CD8VF>;
2109 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2110 memopv8f64, f64mem, loadf64, "{1to8}",
2111 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2112 EVEX_CD8<64, CD8VF>;
2115 let Constraints = "$src1 = $dst" in {
2116 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2117 RegisterClass RC, X86MemOperand x86memop,
2118 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2119 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2121 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2122 (ins RC:$src1, RC:$src3, x86memop:$src2),
2123 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2124 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2125 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2126 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2127 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2128 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2129 [(set RC:$dst, (OpNode RC:$src1,
2130 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2132 } // Constraints = "$src1 = $dst"
2135 let ExeDomain = SSEPackedSingle in {
2136 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2137 memopv16f32, f32mem, loadf32, "{1to16}",
2138 X86Fmadd, v16f32>, EVEX_V512,
2139 EVEX_CD8<32, CD8VF>;
2140 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2141 memopv16f32, f32mem, loadf32, "{1to16}",
2142 X86Fmsub, v16f32>, EVEX_V512,
2143 EVEX_CD8<32, CD8VF>;
2144 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
2145 memopv16f32, f32mem, loadf32, "{1to16}",
2146 X86Fmaddsub, v16f32>,
2147 EVEX_V512, EVEX_CD8<32, CD8VF>;
2148 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
2149 memopv16f32, f32mem, loadf32, "{1to16}",
2150 X86Fmsubadd, v16f32>,
2151 EVEX_V512, EVEX_CD8<32, CD8VF>;
2152 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
2153 memopv16f32, f32mem, loadf32, "{1to16}",
2154 X86Fnmadd, v16f32>, EVEX_V512,
2155 EVEX_CD8<32, CD8VF>;
2156 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
2157 memopv16f32, f32mem, loadf32, "{1to16}",
2158 X86Fnmsub, v16f32>, EVEX_V512,
2159 EVEX_CD8<32, CD8VF>;
2161 let ExeDomain = SSEPackedDouble in {
2162 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
2163 memopv8f64, f64mem, loadf64, "{1to8}",
2164 X86Fmadd, v8f64>, EVEX_V512,
2165 VEX_W, EVEX_CD8<64, CD8VF>;
2166 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
2167 memopv8f64, f64mem, loadf64, "{1to8}",
2168 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2169 EVEX_CD8<64, CD8VF>;
2170 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
2171 memopv8f64, f64mem, loadf64, "{1to8}",
2172 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2173 EVEX_CD8<64, CD8VF>;
2174 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
2175 memopv8f64, f64mem, loadf64, "{1to8}",
2176 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2177 EVEX_CD8<64, CD8VF>;
2178 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
2179 memopv8f64, f64mem, loadf64, "{1to8}",
2180 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2181 EVEX_CD8<64, CD8VF>;
2182 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
2183 memopv8f64, f64mem, loadf64, "{1to8}",
2184 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2185 EVEX_CD8<64, CD8VF>;
2189 let Constraints = "$src1 = $dst" in {
2190 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2191 RegisterClass RC, ValueType OpVT,
2192 X86MemOperand x86memop, Operand memop,
2194 let isCommutable = 1 in
2195 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2196 (ins RC:$src1, RC:$src2, RC:$src3),
2197 !strconcat(OpcodeStr,
2198 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2200 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
2202 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2203 (ins RC:$src1, RC:$src2, f128mem:$src3),
2204 !strconcat(OpcodeStr,
2205 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2207 (OpVT (OpNode RC:$src2, RC:$src1,
2208 (mem_frag addr:$src3))))]>;
2211 } // Constraints = "$src1 = $dst"
2213 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss{z}", X86Fmadd, FR32X,
2214 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2215 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd{z}", X86Fmadd, FR64X,
2216 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2217 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss{z}", X86Fmsub, FR32X,
2218 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2219 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd{z}", X86Fmsub, FR64X,
2220 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2221 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss{z}", X86Fnmadd, FR32X,
2222 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2223 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd{z}", X86Fnmadd, FR64X,
2224 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2225 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss{z}", X86Fnmsub, FR32X,
2226 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2227 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd{z}", X86Fnmsub, FR64X,
2228 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2230 //===----------------------------------------------------------------------===//
2231 // AVX-512 Scalar convert from sign integer to float/double
2232 //===----------------------------------------------------------------------===//
2234 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2235 X86MemOperand x86memop, string asm> {
2236 let neverHasSideEffects = 1 in {
2237 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
2238 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2241 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
2242 (ins DstRC:$src1, x86memop:$src),
2243 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2245 } // neverHasSideEffects = 1
2247 let Predicates = [HasAVX512] in {
2248 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}{z}">,
2249 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2250 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}{z}">,
2251 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2252 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}{z}">,
2253 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2254 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}{z}">,
2255 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2257 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
2258 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2259 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
2260 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2261 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
2262 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2263 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
2264 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2266 def : Pat<(f32 (sint_to_fp GR32:$src)),
2267 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2268 def : Pat<(f32 (sint_to_fp GR64:$src)),
2269 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2270 def : Pat<(f64 (sint_to_fp GR32:$src)),
2271 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2272 def : Pat<(f64 (sint_to_fp GR64:$src)),
2273 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2275 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}{z}">,
2276 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2277 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}{z}">,
2278 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2279 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}{z}">,
2280 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2281 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}{z}">,
2282 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2284 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
2285 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2286 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
2287 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2288 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
2289 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2290 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
2291 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2293 def : Pat<(f32 (uint_to_fp GR32:$src)),
2294 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2295 def : Pat<(f32 (uint_to_fp GR64:$src)),
2296 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2297 def : Pat<(f64 (uint_to_fp GR32:$src)),
2298 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2299 def : Pat<(f64 (uint_to_fp GR64:$src)),
2300 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2303 //===----------------------------------------------------------------------===//
2304 // AVX-512 Scalar convert from float/double to integer
2305 //===----------------------------------------------------------------------===//
2306 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2307 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
2309 let neverHasSideEffects = 1 in {
2310 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2311 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2312 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG;
2314 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
2315 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG;
2316 } // neverHasSideEffects = 1
2318 let Predicates = [HasAVX512] in {
2319 // Convert float/double to signed/unsigned int 32/64
2320 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
2321 ssmem, sse_load_f32, "cvtss2si{z}">,
2322 XS, EVEX_CD8<32, CD8VT1>;
2323 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
2324 ssmem, sse_load_f32, "cvtss2si{z}">,
2325 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
2326 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
2327 ssmem, sse_load_f32, "cvtss2usi{z}">,
2328 XS, EVEX_CD8<32, CD8VT1>;
2329 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2330 int_x86_avx512_cvtss2usi64, ssmem,
2331 sse_load_f32, "cvtss2usi{z}">, XS, VEX_W,
2332 EVEX_CD8<32, CD8VT1>;
2333 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
2334 sdmem, sse_load_f64, "cvtsd2si{z}">,
2335 XD, EVEX_CD8<64, CD8VT1>;
2336 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
2337 sdmem, sse_load_f64, "cvtsd2si{z}">,
2338 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2339 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
2340 sdmem, sse_load_f64, "cvtsd2usi{z}">,
2341 XD, EVEX_CD8<64, CD8VT1>;
2342 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2343 int_x86_avx512_cvtsd2usi64, sdmem,
2344 sse_load_f64, "cvtsd2usi{z}">, XD, VEX_W,
2345 EVEX_CD8<64, CD8VT1>;
2347 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2348 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}{z}",
2349 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2350 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2351 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}{z}",
2352 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2353 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2354 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}{z}",
2355 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2356 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2357 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}{z}",
2358 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2360 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2361 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}{z}",
2362 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2363 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2364 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}{z}",
2365 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2366 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2367 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}{z}",
2368 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2369 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2370 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}{z}",
2371 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2373 // Convert float/double to signed/unsigned int 32/64 with truncation
2374 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
2375 ssmem, sse_load_f32, "cvttss2si{z}">,
2376 XS, EVEX_CD8<32, CD8VT1>;
2377 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2378 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
2379 "cvttss2si{z}">, XS, VEX_W,
2380 EVEX_CD8<32, CD8VT1>;
2381 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
2382 sdmem, sse_load_f64, "cvttsd2si{z}">, XD,
2383 EVEX_CD8<64, CD8VT1>;
2384 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2385 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
2386 "cvttsd2si{z}">, XD, VEX_W,
2387 EVEX_CD8<64, CD8VT1>;
2388 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2389 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
2390 "cvttss2si{z}">, XS, EVEX_CD8<32, CD8VT1>;
2391 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2392 int_x86_avx512_cvttss2usi64, ssmem,
2393 sse_load_f32, "cvttss2usi{z}">, XS, VEX_W,
2394 EVEX_CD8<32, CD8VT1>;
2395 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2396 int_x86_avx512_cvttsd2usi,
2397 sdmem, sse_load_f64, "cvttsd2usi{z}">, XD,
2398 EVEX_CD8<64, CD8VT1>;
2399 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2400 int_x86_avx512_cvttsd2usi64, sdmem,
2401 sse_load_f64, "cvttsd2usi{z}">, XD, VEX_W,
2402 EVEX_CD8<64, CD8VT1>;
2405 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2406 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
2408 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2409 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2410 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
2411 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2412 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2413 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
2416 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
2417 loadf32, "cvttss2si{z}">, XS,
2418 EVEX_CD8<32, CD8VT1>;
2419 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
2420 loadf32, "cvttss2usi{z}">, XS,
2421 EVEX_CD8<32, CD8VT1>;
2422 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
2423 loadf32, "cvttss2si{z}">, XS, VEX_W,
2424 EVEX_CD8<32, CD8VT1>;
2425 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
2426 loadf32, "cvttss2usi{z}">, XS, VEX_W,
2427 EVEX_CD8<32, CD8VT1>;
2428 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
2429 loadf64, "cvttsd2si{z}">, XD,
2430 EVEX_CD8<64, CD8VT1>;
2431 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
2432 loadf64, "cvttsd2usi{z}">, XD,
2433 EVEX_CD8<64, CD8VT1>;
2434 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
2435 loadf64, "cvttsd2si{z}">, XD, VEX_W,
2436 EVEX_CD8<64, CD8VT1>;
2437 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
2438 loadf64, "cvttsd2usi{z}">, XD, VEX_W,
2439 EVEX_CD8<64, CD8VT1>;
2440 //===----------------------------------------------------------------------===//
2441 // AVX-512 Convert form float to double and back
2442 //===----------------------------------------------------------------------===//
2443 let neverHasSideEffects = 1 in {
2444 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
2445 (ins FR32X:$src1, FR32X:$src2),
2446 "vcvtss2sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2447 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
2449 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
2450 (ins FR32X:$src1, f32mem:$src2),
2451 "vcvtss2sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2452 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
2453 EVEX_CD8<32, CD8VT1>;
2455 // Convert scalar double to scalar single
2456 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
2457 (ins FR64X:$src1, FR64X:$src2),
2458 "vcvtsd2ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2459 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
2461 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
2462 (ins FR64X:$src1, f64mem:$src2),
2463 "vcvtsd2ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2464 []>, EVEX_4V, VEX_LIG, VEX_W,
2465 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
2468 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
2469 Requires<[HasAVX512]>;
2470 def : Pat<(fextend (loadf32 addr:$src)),
2471 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
2473 def : Pat<(extloadf32 addr:$src),
2474 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
2475 Requires<[HasAVX512, OptForSize]>;
2477 def : Pat<(extloadf32 addr:$src),
2478 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
2479 Requires<[HasAVX512, OptForSpeed]>;
2481 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
2482 Requires<[HasAVX512]>;
2484 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
2485 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2486 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2488 let neverHasSideEffects = 1 in {
2489 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2490 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2492 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2494 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2495 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2497 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2498 } // neverHasSideEffects = 1
2501 defm VCVTPD2PSZ : avx512_vcvt_fp<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
2502 memopv8f64, f512mem, v8f32, v8f64,
2503 SSEPackedSingle>, EVEX_V512, VEX_W, OpSize,
2504 EVEX_CD8<64, CD8VF>;
2506 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
2507 memopv4f64, f256mem, v8f64, v8f32,
2508 SSEPackedDouble>, EVEX_V512, EVEX_CD8<32, CD8VH>;
2509 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2510 (VCVTPS2PDZrm addr:$src)>;
2512 //===----------------------------------------------------------------------===//
2513 // AVX-512 Vector convert from sign integer to float/double
2514 //===----------------------------------------------------------------------===//
2516 defm VCVTDQ2PSZ : avx512_vcvt_fp<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
2517 memopv8i64, i512mem, v16f32, v16i32,
2518 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2520 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
2521 memopv4i64, i256mem, v8f64, v8i32,
2522 SSEPackedDouble>, EVEX_V512, XS,
2523 EVEX_CD8<32, CD8VH>;
2525 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
2526 memopv16f32, f512mem, v16i32, v16f32,
2527 SSEPackedSingle>, EVEX_V512, XS,
2528 EVEX_CD8<32, CD8VF>;
2530 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
2531 memopv8f64, f512mem, v8i32, v8f64,
2532 SSEPackedDouble>, EVEX_V512, OpSize, VEX_W,
2533 EVEX_CD8<64, CD8VF>;
2535 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
2536 memopv16f32, f512mem, v16i32, v16f32,
2537 SSEPackedSingle>, EVEX_V512,
2538 EVEX_CD8<32, CD8VF>;
2540 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
2541 memopv8f64, f512mem, v8i32, v8f64,
2542 SSEPackedDouble>, EVEX_V512, VEX_W,
2543 EVEX_CD8<64, CD8VF>;
2545 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
2546 memopv4i64, f256mem, v8f64, v8i32,
2547 SSEPackedDouble>, EVEX_V512, XS,
2548 EVEX_CD8<32, CD8VH>;
2550 defm VCVTUDQ2PSZ : avx512_vcvt_fp<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
2551 memopv16i32, f512mem, v16f32, v16i32,
2552 SSEPackedSingle>, EVEX_V512, XD,
2553 EVEX_CD8<32, CD8VF>;
2555 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
2556 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
2557 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
2560 def : Pat<(int_x86_avx512_cvtdq2_ps_512 VR512:$src),
2561 (VCVTDQ2PSZrr VR512:$src)>;
2562 def : Pat<(int_x86_avx512_cvtdq2_ps_512 (bitconvert (memopv8i64 addr:$src))),
2563 (VCVTDQ2PSZrm addr:$src)>;
2565 def VCVTPS2DQZrr : AVX512BI<0x5B, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2566 "vcvtps2dq\t{$src, $dst|$dst, $src}",
2568 (int_x86_avx512_cvt_ps2dq_512 VR512:$src))],
2569 IIC_SSE_CVT_PS_RR>, EVEX, EVEX_V512;
2570 def VCVTPS2DQZrm : AVX512BI<0x5B, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2571 "vcvtps2dq\t{$src, $dst|$dst, $src}",
2573 (int_x86_avx512_cvt_ps2dq_512 (memopv16f32 addr:$src)))],
2574 IIC_SSE_CVT_PS_RM>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2577 let Predicates = [HasAVX512] in {
2578 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
2579 (VCVTPD2PSZrm addr:$src)>;
2580 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2581 (VCVTPS2PDZrm addr:$src)>;
2584 //===----------------------------------------------------------------------===//
2585 // Half precision conversion instructions
2586 //===----------------------------------------------------------------------===//
2587 multiclass avx512_f16c_ph2ps<RegisterClass destRC, RegisterClass srcRC,
2588 X86MemOperand x86memop, Intrinsic Int> {
2589 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
2590 "vcvtph2ps\t{$src, $dst|$dst, $src}",
2591 [(set destRC:$dst, (Int srcRC:$src))]>, EVEX;
2592 let neverHasSideEffects = 1, mayLoad = 1 in
2593 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
2594 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
2597 multiclass avx512_f16c_ps2ph<RegisterClass destRC, RegisterClass srcRC,
2598 X86MemOperand x86memop, Intrinsic Int> {
2599 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
2600 (ins srcRC:$src1, i32i8imm:$src2),
2601 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2602 [(set destRC:$dst, (Int srcRC:$src1, imm:$src2))]>, EVEX;
2603 let neverHasSideEffects = 1, mayStore = 1 in
2604 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
2605 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
2606 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
2609 defm VCVTPH2PSZ : avx512_f16c_ph2ps<VR512, VR256X, f256mem,
2610 int_x86_avx512_vcvtph2ps_512>, EVEX_V512,
2611 EVEX_CD8<32, CD8VH>;
2612 defm VCVTPS2PHZ : avx512_f16c_ps2ph<VR256X, VR512, f256mem,
2613 int_x86_avx512_vcvtps2ph_512>, EVEX_V512,
2614 EVEX_CD8<32, CD8VH>;
2616 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
2617 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
2618 "ucomiss{z}">, TB, EVEX, VEX_LIG,
2619 EVEX_CD8<32, CD8VT1>;
2620 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
2621 "ucomisd{z}">, TB, OpSize, EVEX,
2622 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2623 let Pattern = []<dag> in {
2624 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
2625 "comiss{z}">, TB, EVEX, VEX_LIG,
2626 EVEX_CD8<32, CD8VT1>;
2627 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
2628 "comisd{z}">, TB, OpSize, EVEX,
2629 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2631 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
2632 load, "ucomiss">, TB, EVEX, VEX_LIG,
2633 EVEX_CD8<32, CD8VT1>;
2634 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
2635 load, "ucomisd">, TB, OpSize, EVEX,
2636 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2638 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
2639 load, "comiss">, TB, EVEX, VEX_LIG,
2640 EVEX_CD8<32, CD8VT1>;
2641 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
2642 load, "comisd">, TB, OpSize, EVEX,
2643 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2646 /// avx512_unop_p - AVX-512 unops in packed form.
2647 multiclass avx512_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2648 def PSZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2649 !strconcat(OpcodeStr,
2650 "ps\t{$src, $dst|$dst, $src}"),
2651 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))]>,
2653 def PSZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f256mem:$src),
2654 !strconcat(OpcodeStr,
2655 "ps\t{$src, $dst|$dst, $src}"),
2656 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
2657 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2658 def PDZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2659 !strconcat(OpcodeStr,
2660 "pd\t{$src, $dst|$dst, $src}"),
2661 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))]>,
2662 EVEX, EVEX_V512, VEX_W;
2663 def PDZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2664 !strconcat(OpcodeStr,
2665 "pd\t{$src, $dst|$dst, $src}"),
2666 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
2667 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2670 /// avx512_fp_unop_p_int - AVX-512 intrinsics unops in packed forms.
2671 multiclass avx512_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2672 Intrinsic V16F32Int, Intrinsic V8F64Int> {
2673 def PSZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2674 !strconcat(OpcodeStr,
2675 "ps\t{$src, $dst|$dst, $src}"),
2676 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
2678 def PSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2679 !strconcat(OpcodeStr,
2680 "ps\t{$src, $dst|$dst, $src}"),
2682 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
2683 EVEX_V512, EVEX_CD8<32, CD8VF>;
2684 def PDZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2685 !strconcat(OpcodeStr,
2686 "pd\t{$src, $dst|$dst, $src}"),
2687 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
2688 EVEX, EVEX_V512, VEX_W;
2689 def PDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2690 !strconcat(OpcodeStr,
2691 "pd\t{$src, $dst|$dst, $src}"),
2693 (V8F64Int (memopv8f64 addr:$src)))]>,
2694 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2697 /// avx512_fp_unop_s - AVX-512 unops in scalar form.
2698 multiclass avx512_fp_unop_s<bits<8> opc, string OpcodeStr> {
2699 let hasSideEffects = 0 in {
2700 def SSZr : AVX5128I<opc, MRMSrcReg, (outs FR32X:$dst),
2701 (ins FR32X:$src1, FR32X:$src2),
2702 !strconcat(OpcodeStr,
2703 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2705 let mayLoad = 1 in {
2706 def SSZm : AVX5128I<opc, MRMSrcMem, (outs FR32X:$dst),
2707 (ins FR32X:$src1, f32mem:$src2),
2708 !strconcat(OpcodeStr,
2709 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2710 []>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2711 def SSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
2712 (ins VR128X:$src1, ssmem:$src2),
2713 !strconcat(OpcodeStr,
2714 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2715 []>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2717 def SDZr : AVX5128I<opc, MRMSrcReg, (outs FR64X:$dst),
2718 (ins FR64X:$src1, FR64X:$src2),
2719 !strconcat(OpcodeStr,
2720 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2722 let mayLoad = 1 in {
2723 def SDZm : AVX5128I<opc, MRMSrcMem, (outs FR64X:$dst),
2724 (ins FR64X:$src1, f64mem:$src2),
2725 !strconcat(OpcodeStr,
2726 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2727 EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
2728 def SDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
2729 (ins VR128X:$src1, sdmem:$src2),
2730 !strconcat(OpcodeStr,
2731 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2732 []>, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
2737 defm VRCP14 : avx512_fp_unop_s<0x4D, "vrcp14">,
2738 avx512_fp_unop_p<0x4C, "vrcp14", X86frcp>,
2739 avx512_fp_unop_p_int<0x4C, "vrcp14",
2740 int_x86_avx512_rcp14_ps_512, int_x86_avx512_rcp14_pd_512>;
2742 defm VRSQRT14 : avx512_fp_unop_s<0x4F, "vrsqrt14">,
2743 avx512_fp_unop_p<0x4E, "vrsqrt14", X86frsqrt>,
2744 avx512_fp_unop_p_int<0x4E, "vrsqrt14",
2745 int_x86_avx512_rsqrt14_ps_512, int_x86_avx512_rsqrt14_pd_512>;
2747 def : Pat<(int_x86_avx512_rsqrt14_ss VR128X:$src),
2748 (COPY_TO_REGCLASS (VRSQRT14SSZr (f32 (IMPLICIT_DEF)),
2749 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2751 def : Pat<(int_x86_avx512_rsqrt14_ss sse_load_f32:$src),
2752 (VRSQRT14SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2754 def : Pat<(int_x86_avx512_rcp14_ss VR128X:$src),
2755 (COPY_TO_REGCLASS (VRCP14SSZr (f32 (IMPLICIT_DEF)),
2756 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2758 def : Pat<(int_x86_avx512_rcp14_ss sse_load_f32:$src),
2759 (VRCP14SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2761 let AddedComplexity = 20, Predicates = [HasERI] in {
2762 defm VRCP28 : avx512_fp_unop_s<0xCB, "vrcp28">,
2763 avx512_fp_unop_p<0xCA, "vrcp28", X86frcp>,
2764 avx512_fp_unop_p_int<0xCA, "vrcp28",
2765 int_x86_avx512_rcp28_ps_512, int_x86_avx512_rcp28_pd_512>;
2767 defm VRSQRT28 : avx512_fp_unop_s<0xCD, "vrsqrt28">,
2768 avx512_fp_unop_p<0xCC, "vrsqrt28", X86frsqrt>,
2769 avx512_fp_unop_p_int<0xCC, "vrsqrt28",
2770 int_x86_avx512_rsqrt28_ps_512, int_x86_avx512_rsqrt28_pd_512>;
2773 let Predicates = [HasERI] in {
2774 def : Pat<(int_x86_avx512_rsqrt28_ss VR128X:$src),
2775 (COPY_TO_REGCLASS (VRSQRT28SSZr (f32 (IMPLICIT_DEF)),
2776 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2778 def : Pat<(int_x86_avx512_rsqrt28_ss sse_load_f32:$src),
2779 (VRSQRT28SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2781 def : Pat<(int_x86_avx512_rcp28_ss VR128X:$src),
2782 (COPY_TO_REGCLASS (VRCP28SSZr (f32 (IMPLICIT_DEF)),
2783 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2785 def : Pat<(int_x86_avx512_rcp28_ss sse_load_f32:$src),
2786 (VRCP28SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2788 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2789 Intrinsic V16F32Int, Intrinsic V8F64Int,
2790 OpndItins itins_s, OpndItins itins_d> {
2791 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2792 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2793 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
2797 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2798 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2800 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
2801 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2803 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2804 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2805 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
2809 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2810 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2811 [(set VR512:$dst, (OpNode
2812 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
2813 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
2815 def PSZr_Int : AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2816 !strconcat(OpcodeStr,
2817 "ps\t{$src, $dst|$dst, $src}"),
2818 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
2820 def PSZm_Int : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2821 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2823 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
2824 EVEX_V512, EVEX_CD8<32, CD8VF>;
2825 def PDZr_Int : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2826 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2827 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
2828 EVEX, EVEX_V512, VEX_W;
2829 def PDZm_Int : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2830 !strconcat(OpcodeStr,
2831 "pd\t{$src, $dst|$dst, $src}"),
2832 [(set VR512:$dst, (V8F64Int (memopv8f64 addr:$src)))]>,
2833 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2836 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
2837 Intrinsic F32Int, Intrinsic F64Int,
2838 OpndItins itins_s, OpndItins itins_d> {
2839 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
2840 (ins FR32X:$src1, FR32X:$src2),
2841 !strconcat(OpcodeStr,
2842 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2843 [], itins_s.rr>, XS, EVEX_4V;
2844 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
2845 (ins VR128X:$src1, VR128X:$src2),
2846 !strconcat(OpcodeStr,
2847 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2849 (F32Int VR128X:$src1, VR128X:$src2))],
2850 itins_s.rr>, XS, EVEX_4V;
2851 let mayLoad = 1 in {
2852 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
2853 (ins FR32X:$src1, f32mem:$src2),
2854 !strconcat(OpcodeStr,
2855 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2856 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2857 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
2858 (ins VR128X:$src1, ssmem:$src2),
2859 !strconcat(OpcodeStr,
2860 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2862 (F32Int VR128X:$src1, sse_load_f32:$src2))],
2863 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2865 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
2866 (ins FR64X:$src1, FR64X:$src2),
2867 !strconcat(OpcodeStr,
2868 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2870 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
2871 (ins VR128X:$src1, VR128X:$src2),
2872 !strconcat(OpcodeStr,
2873 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2875 (F64Int VR128X:$src1, VR128X:$src2))],
2876 itins_s.rr>, XD, EVEX_4V, VEX_W;
2877 let mayLoad = 1 in {
2878 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
2879 (ins FR64X:$src1, f64mem:$src2),
2880 !strconcat(OpcodeStr,
2881 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2882 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
2883 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
2884 (ins VR128X:$src1, sdmem:$src2),
2885 !strconcat(OpcodeStr,
2886 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2888 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
2889 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
2894 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
2895 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
2896 SSE_SQRTSS, SSE_SQRTSD>,
2897 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
2898 int_x86_avx512_sqrt_ps_512, int_x86_avx512_sqrt_pd_512,
2899 SSE_SQRTPS, SSE_SQRTPD>;
2901 let Predicates = [HasAVX512] in {
2902 def : Pat<(f32 (fsqrt FR32X:$src)),
2903 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
2904 def : Pat<(f32 (fsqrt (load addr:$src))),
2905 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
2906 Requires<[OptForSize]>;
2907 def : Pat<(f64 (fsqrt FR64X:$src)),
2908 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
2909 def : Pat<(f64 (fsqrt (load addr:$src))),
2910 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
2911 Requires<[OptForSize]>;
2913 def : Pat<(f32 (X86frsqrt FR32X:$src)),
2914 (VRSQRT14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
2915 def : Pat<(f32 (X86frsqrt (load addr:$src))),
2916 (VRSQRT14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
2917 Requires<[OptForSize]>;
2919 def : Pat<(f32 (X86frcp FR32X:$src)),
2920 (VRCP14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
2921 def : Pat<(f32 (X86frcp (load addr:$src))),
2922 (VRCP14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
2923 Requires<[OptForSize]>;
2925 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
2926 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
2927 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2929 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
2930 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2932 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
2933 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
2934 (COPY_TO_REGCLASS VR128X:$src, FR64)),
2936 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
2937 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
2941 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
2942 X86MemOperand x86memop, RegisterClass RC,
2943 PatFrag mem_frag32, PatFrag mem_frag64,
2944 Intrinsic V4F32Int, Intrinsic V2F64Int,
2946 let ExeDomain = SSEPackedSingle in {
2947 // Intrinsic operation, reg.
2948 // Vector intrinsic operation, reg
2949 def PSr : AVX512AIi8<opcps, MRMSrcReg,
2950 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
2951 !strconcat(OpcodeStr,
2952 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2953 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
2955 // Vector intrinsic operation, mem
2956 def PSm : AVX512AIi8<opcps, MRMSrcMem,
2957 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
2958 !strconcat(OpcodeStr,
2959 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2961 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
2962 EVEX_CD8<32, VForm>;
2963 } // ExeDomain = SSEPackedSingle
2965 let ExeDomain = SSEPackedDouble in {
2966 // Vector intrinsic operation, reg
2967 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
2968 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
2969 !strconcat(OpcodeStr,
2970 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2971 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
2973 // Vector intrinsic operation, mem
2974 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
2975 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
2976 !strconcat(OpcodeStr,
2977 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2979 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
2980 EVEX_CD8<64, VForm>;
2981 } // ExeDomain = SSEPackedDouble
2984 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
2988 let ExeDomain = GenericDomain in {
2990 let hasSideEffects = 0 in
2991 def SSr : AVX512AIi8<opcss, MRMSrcReg,
2992 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
2993 !strconcat(OpcodeStr,
2994 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2997 // Intrinsic operation, reg.
2998 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
2999 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3000 !strconcat(OpcodeStr,
3001 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3002 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
3004 // Intrinsic operation, mem.
3005 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
3006 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
3007 !strconcat(OpcodeStr,
3008 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3009 [(set VR128X:$dst, (F32Int VR128X:$src1,
3010 sse_load_f32:$src2, imm:$src3))]>,
3011 EVEX_CD8<32, CD8VT1>;
3014 let hasSideEffects = 0 in
3015 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
3016 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
3017 !strconcat(OpcodeStr,
3018 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3021 // Intrinsic operation, reg.
3022 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
3023 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3024 !strconcat(OpcodeStr,
3025 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3026 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
3029 // Intrinsic operation, mem.
3030 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
3031 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
3032 !strconcat(OpcodeStr,
3033 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3035 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
3036 VEX_W, EVEX_CD8<64, CD8VT1>;
3037 } // ExeDomain = GenericDomain
3040 let Predicates = [HasAVX512] in {
3041 defm VRNDSCALE : avx512_fp_binop_rm<0x0A, 0x0B, "vrndscale",
3042 int_x86_avx512_rndscale_ss,
3043 int_x86_avx512_rndscale_sd>, EVEX_4V;
3045 defm VRNDSCALEZ : avx512_fp_unop_rm<0x08, 0x09, "vrndscale", f256mem, VR512,
3046 memopv16f32, memopv8f64,
3047 int_x86_avx512_rndscale_ps_512,
3048 int_x86_avx512_rndscale_pd_512, CD8VF>,
3052 def : Pat<(ffloor FR32X:$src),
3053 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
3054 def : Pat<(f64 (ffloor FR64X:$src)),
3055 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
3056 def : Pat<(f32 (fnearbyint FR32X:$src)),
3057 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
3058 def : Pat<(f64 (fnearbyint FR64X:$src)),
3059 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
3060 def : Pat<(f32 (fceil FR32X:$src)),
3061 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
3062 def : Pat<(f64 (fceil FR64X:$src)),
3063 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
3064 def : Pat<(f32 (frint FR32X:$src)),
3065 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
3066 def : Pat<(f64 (frint FR64X:$src)),
3067 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
3068 def : Pat<(f32 (ftrunc FR32X:$src)),
3069 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
3070 def : Pat<(f64 (ftrunc FR64X:$src)),
3071 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
3073 def : Pat<(v16f32 (ffloor VR512:$src)),
3074 (VRNDSCALEZPSr VR512:$src, (i32 0x1))>;
3075 def : Pat<(v16f32 (fnearbyint VR512:$src)),
3076 (VRNDSCALEZPSr VR512:$src, (i32 0xC))>;
3077 def : Pat<(v16f32 (fceil VR512:$src)),
3078 (VRNDSCALEZPSr VR512:$src, (i32 0x2))>;
3079 def : Pat<(v16f32 (frint VR512:$src)),
3080 (VRNDSCALEZPSr VR512:$src, (i32 0x4))>;
3081 def : Pat<(v16f32 (ftrunc VR512:$src)),
3082 (VRNDSCALEZPSr VR512:$src, (i32 0x3))>;
3084 def : Pat<(v8f64 (ffloor VR512:$src)),
3085 (VRNDSCALEZPDr VR512:$src, (i32 0x1))>;
3086 def : Pat<(v8f64 (fnearbyint VR512:$src)),
3087 (VRNDSCALEZPDr VR512:$src, (i32 0xC))>;
3088 def : Pat<(v8f64 (fceil VR512:$src)),
3089 (VRNDSCALEZPDr VR512:$src, (i32 0x2))>;
3090 def : Pat<(v8f64 (frint VR512:$src)),
3091 (VRNDSCALEZPDr VR512:$src, (i32 0x4))>;
3092 def : Pat<(v8f64 (ftrunc VR512:$src)),
3093 (VRNDSCALEZPDr VR512:$src, (i32 0x3))>;
3095 //-------------------------------------------------
3096 // Integer truncate and extend operations
3097 //-------------------------------------------------
3099 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
3100 RegisterClass dstRC, RegisterClass srcRC,
3101 RegisterClass KRC, X86MemOperand x86memop> {
3102 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3104 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
3107 def krr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3108 (ins KRC:$mask, srcRC:$src),
3109 !strconcat(OpcodeStr,
3110 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3113 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
3114 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3117 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
3118 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3119 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
3120 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3121 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
3122 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3123 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
3124 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3125 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
3126 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3127 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
3128 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3129 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
3130 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3131 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
3132 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3133 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
3134 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3135 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
3136 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3137 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
3138 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3139 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
3140 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3141 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
3142 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3143 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
3144 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3145 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
3146 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3148 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
3149 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
3150 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
3151 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
3152 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
3154 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3155 (VPMOVDBkrr VK16WM:$mask, VR512:$src)>;
3156 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3157 (VPMOVDWkrr VK16WM:$mask, VR512:$src)>;
3158 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3159 (VPMOVQWkrr VK8WM:$mask, VR512:$src)>;
3160 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3161 (VPMOVQDkrr VK8WM:$mask, VR512:$src)>;
3164 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass DstRC,
3165 RegisterClass SrcRC, SDNode OpNode, PatFrag mem_frag,
3166 X86MemOperand x86memop, ValueType OpVT, ValueType InVT> {
3168 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
3170 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3171 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
3172 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
3173 (ins x86memop:$src),
3174 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
3176 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
3180 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VR512, VR128X, X86vzext,
3181 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3183 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VR512, VR128X, X86vzext,
3184 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3186 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VR512, VR256X, X86vzext,
3187 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3188 EVEX_CD8<16, CD8VH>;
3189 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VR512, VR128X, X86vzext,
3190 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3191 EVEX_CD8<16, CD8VQ>;
3192 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VR512, VR256X, X86vzext,
3193 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3194 EVEX_CD8<32, CD8VH>;
3196 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VR512, VR128X, X86vsext,
3197 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3199 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VR512, VR128X, X86vsext,
3200 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3202 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VR512, VR256X, X86vsext,
3203 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3204 EVEX_CD8<16, CD8VH>;
3205 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VR512, VR128X, X86vsext,
3206 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3207 EVEX_CD8<16, CD8VQ>;
3208 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VR512, VR256X, X86vsext,
3209 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3210 EVEX_CD8<32, CD8VH>;
3212 //===----------------------------------------------------------------------===//
3213 // GATHER - SCATTER Operations
3215 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3216 RegisterClass RC, X86MemOperand memop> {
3218 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
3219 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
3220 (ins RC:$src1, KRC:$mask, memop:$src2),
3221 !strconcat(OpcodeStr,
3222 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3225 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
3226 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3227 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
3228 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3230 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
3231 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3232 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
3233 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3235 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
3236 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3237 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
3238 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3240 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
3241 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3242 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
3243 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3245 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3246 RegisterClass RC, X86MemOperand memop> {
3247 let mayStore = 1, Constraints = "$mask = $mask_wb" in
3248 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
3249 (ins memop:$dst, KRC:$mask, RC:$src2),
3250 !strconcat(OpcodeStr,
3251 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3255 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
3256 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3257 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
3258 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3260 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
3261 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3262 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
3263 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3265 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
3266 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3267 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
3268 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3270 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
3271 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3272 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
3273 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3275 //===----------------------------------------------------------------------===//
3276 // VSHUFPS - VSHUFPD Operations
3278 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
3279 ValueType vt, string OpcodeStr, PatFrag mem_frag,
3281 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
3282 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3283 !strconcat(OpcodeStr,
3284 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3285 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
3286 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3287 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
3288 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
3289 (ins RC:$src1, RC:$src2, i8imm:$src3),
3290 !strconcat(OpcodeStr,
3291 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3292 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
3293 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3294 EVEX_4V, Sched<[WriteShuffle]>;
3297 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
3298 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3299 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
3300 SSEPackedDouble>, OpSize, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3302 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3303 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3304 def : Pat<(v16i32 (X86Shufp VR512:$src1,
3305 (memopv16i32 addr:$src2), (i8 imm:$imm))),
3306 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3308 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3309 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3310 def : Pat<(v8i64 (X86Shufp VR512:$src1,
3311 (memopv8i64 addr:$src2), (i8 imm:$imm))),
3312 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3314 multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
3315 X86MemOperand x86memop> {
3316 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
3317 (ins RC:$src1, RC:$src2, i8imm:$src3),
3318 !strconcat(OpcodeStr,
3319 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3321 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
3322 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3323 !strconcat(OpcodeStr,
3324 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3327 defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
3328 EVEX_V512, EVEX_CD8<32, CD8VF>;
3329 defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
3330 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3332 def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3333 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3334 def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3335 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3336 def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3337 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3338 def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3339 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3341 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, RegisterClass RC,
3342 X86MemOperand x86memop> {
3343 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3344 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3346 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
3347 (ins x86memop:$src),
3348 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3352 defm VPABSD : avx512_vpabs<0x1E, "vpabsd", VR512, i512mem>, EVEX_V512,
3353 EVEX_CD8<32, CD8VF>;
3354 defm VPABSQ : avx512_vpabs<0x1F, "vpabsq", VR512, i512mem>, EVEX_V512, VEX_W,
3355 EVEX_CD8<64, CD8VF>;