1 // Bitcasts between 512-bit vector types. Return the original type since
2 // no instruction is needed for the conversion
3 let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
49 // Bitcasts between 256-bit vector types. Return the original type since
50 // no instruction is needed for the conversion
51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
84 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
87 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
88 isPseudo = 1, Predicates = [HasAVX512] in {
89 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
90 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
93 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
94 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
95 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
96 def : Pat<(v16f32 immAllZerosV), (AVX512_512_SET0)>;
98 //===----------------------------------------------------------------------===//
99 // AVX-512 - VECTOR INSERT
102 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
103 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
104 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
105 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
106 []>, EVEX_4V, EVEX_V512;
108 def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
109 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
110 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
111 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
114 // -- 64x4 fp form --
115 let neverHasSideEffects = 1, ExeDomain = SSEPackedDouble in {
116 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
117 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
118 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
119 []>, EVEX_4V, EVEX_V512, VEX_W;
121 def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
122 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
123 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
124 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
126 // -- 32x4 integer form --
127 let neverHasSideEffects = 1 in {
128 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
129 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
130 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
131 []>, EVEX_4V, EVEX_V512;
133 def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
134 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
135 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
136 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
140 let neverHasSideEffects = 1 in {
142 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
143 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
144 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
145 []>, EVEX_4V, EVEX_V512, VEX_W;
147 def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
148 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
149 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
150 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
153 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
154 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
155 (INSERT_get_vinsert128_imm VR512:$ins))>;
156 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
157 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
158 (INSERT_get_vinsert128_imm VR512:$ins))>;
159 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
160 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
161 (INSERT_get_vinsert128_imm VR512:$ins))>;
162 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
163 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
164 (INSERT_get_vinsert128_imm VR512:$ins))>;
166 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
167 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
168 (INSERT_get_vinsert128_imm VR512:$ins))>;
169 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
170 (bc_v4i32 (loadv2i64 addr:$src2)),
171 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
172 (INSERT_get_vinsert128_imm VR512:$ins))>;
173 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
174 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
175 (INSERT_get_vinsert128_imm VR512:$ins))>;
176 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
177 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
178 (INSERT_get_vinsert128_imm VR512:$ins))>;
180 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
181 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
182 (INSERT_get_vinsert256_imm VR512:$ins))>;
183 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
184 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
185 (INSERT_get_vinsert256_imm VR512:$ins))>;
186 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
187 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
188 (INSERT_get_vinsert256_imm VR512:$ins))>;
189 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
190 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
191 (INSERT_get_vinsert256_imm VR512:$ins))>;
193 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
194 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
195 (INSERT_get_vinsert256_imm VR512:$ins))>;
196 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
197 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
198 (INSERT_get_vinsert256_imm VR512:$ins))>;
199 def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
200 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
201 (INSERT_get_vinsert256_imm VR512:$ins))>;
202 def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
203 (bc_v8i32 (loadv4i64 addr:$src2)),
204 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
205 (INSERT_get_vinsert256_imm VR512:$ins))>;
207 // vinsertps - insert f32 to XMM
208 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
209 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
210 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
211 [(set VR128X:$dst, (X86insrtps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
213 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
214 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
215 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
216 [(set VR128X:$dst, (X86insrtps VR128X:$src1,
217 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
218 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
220 //===----------------------------------------------------------------------===//
221 // AVX-512 VECTOR EXTRACT
223 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
225 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
226 (ins VR512:$src1, i8imm:$src2),
227 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
228 []>, EVEX, EVEX_V512;
229 def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
230 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
231 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
232 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
235 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
236 (ins VR512:$src1, i8imm:$src2),
237 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
238 []>, EVEX, EVEX_V512, VEX_W;
240 def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
241 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
242 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
243 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
246 let neverHasSideEffects = 1 in {
248 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
249 (ins VR512:$src1, i8imm:$src2),
250 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
251 []>, EVEX, EVEX_V512;
252 def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
253 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
254 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
255 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
258 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
259 (ins VR512:$src1, i8imm:$src2),
260 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
261 []>, EVEX, EVEX_V512, VEX_W;
263 def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
264 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
265 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
266 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
269 def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
270 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
271 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
273 def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
274 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
275 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
277 def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
278 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
279 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
281 def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
282 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
283 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
286 def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
287 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
288 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
290 def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
291 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
292 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
294 def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
295 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
296 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
298 def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
299 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
300 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
302 // A 256-bit subvector extract from the first 512-bit vector position
303 // is a subregister copy that needs no instruction.
304 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
305 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
306 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
307 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
308 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
309 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
310 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
311 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
314 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
315 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
316 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
317 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
318 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
319 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
320 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
321 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
324 // A 128-bit subvector insert to the first 512-bit vector position
325 // is a subregister copy that needs no instruction.
326 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
327 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
328 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
330 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
331 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
332 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
334 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
335 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
336 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
338 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
339 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
340 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
343 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
344 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
345 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
346 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
347 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
348 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
349 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
350 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
352 // vextractps - extract 32 bits from XMM
353 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
354 (ins VR128X:$src1, u32u8imm:$src2),
355 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
356 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
359 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
360 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
361 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
362 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
365 //===---------------------------------------------------------------------===//
368 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
369 RegisterClass DestRC,
370 RegisterClass SrcRC, X86MemOperand x86memop> {
371 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
372 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
374 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
375 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),[]>, EVEX;
377 let ExeDomain = SSEPackedSingle in {
378 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
380 EVEX_V512, EVEX_CD8<32, CD8VT1>;
383 let ExeDomain = SSEPackedDouble in {
384 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
386 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
389 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
390 (VBROADCASTSSZrm addr:$src)>;
391 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
392 (VBROADCASTSDZrm addr:$src)>;
394 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
395 (VBROADCASTSSZrm addr:$src)>;
396 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
397 (VBROADCASTSDZrm addr:$src)>;
399 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
400 RegisterClass SrcRC, RegisterClass KRC> {
401 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
402 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
403 []>, EVEX, EVEX_V512;
404 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
405 (ins KRC:$mask, SrcRC:$src),
406 !strconcat(OpcodeStr,
407 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
408 []>, EVEX, EVEX_V512, EVEX_KZ;
411 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
412 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
415 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
416 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
418 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
419 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
421 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
422 (VPBROADCASTDrZrr GR32:$src)>;
423 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
424 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
425 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
426 (VPBROADCASTQrZrr GR64:$src)>;
427 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
428 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
430 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
431 (VPBROADCASTDrZrr GR32:$src)>;
432 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
433 (VPBROADCASTQrZrr GR64:$src)>;
435 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
436 X86MemOperand x86memop, PatFrag ld_frag,
437 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
439 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
440 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
442 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
443 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
445 !strconcat(OpcodeStr,
446 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
448 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
451 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
452 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
454 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
455 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
457 !strconcat(OpcodeStr,
458 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
459 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
460 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
464 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
465 loadi32, VR512, v16i32, v4i32, VK16WM>,
466 EVEX_V512, EVEX_CD8<32, CD8VT1>;
467 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
468 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
469 EVEX_CD8<64, CD8VT1>;
471 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
472 (VPBROADCASTDZrr VR128X:$src)>;
473 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
474 (VPBROADCASTQZrr VR128X:$src)>;
476 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
477 (VBROADCASTSSZrr VR128X:$src)>;
478 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
479 (VBROADCASTSDZrr VR128X:$src)>;
481 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
482 (VBROADCASTSSZrr VR128X:$src)>;
483 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
484 (VBROADCASTSDZrr VR128X:$src)>;
486 // Provide fallback in case the load node that is used in the patterns above
487 // is used by additional users, which prevents the pattern selection.
488 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
489 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
490 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
491 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
494 let Predicates = [HasAVX512] in {
495 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
497 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
498 addr:$src)), sub_ymm)>;
500 //===----------------------------------------------------------------------===//
501 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
504 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
505 RegisterClass DstRC, RegisterClass KRC,
506 ValueType OpVT, ValueType SrcVT> {
507 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
508 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
512 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
513 VK16, v16i32, v16i1>, EVEX_V512;
514 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
515 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
517 //===----------------------------------------------------------------------===//
520 // -- immediate form --
521 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
522 SDNode OpNode, PatFrag mem_frag,
523 X86MemOperand x86memop, ValueType OpVT> {
524 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
525 (ins RC:$src1, i8imm:$src2),
526 !strconcat(OpcodeStr,
527 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
529 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
531 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
532 (ins x86memop:$src1, i8imm:$src2),
533 !strconcat(OpcodeStr,
534 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
536 (OpVT (OpNode (mem_frag addr:$src1),
537 (i8 imm:$src2))))]>, EVEX;
540 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
541 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
542 let ExeDomain = SSEPackedDouble in
543 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
544 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
546 // -- VPERM - register form --
547 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
548 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
550 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
551 (ins RC:$src1, RC:$src2),
552 !strconcat(OpcodeStr,
553 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
555 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
557 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
558 (ins RC:$src1, x86memop:$src2),
559 !strconcat(OpcodeStr,
560 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
562 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
566 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
567 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
568 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
569 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
570 let ExeDomain = SSEPackedSingle in
571 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
572 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
573 let ExeDomain = SSEPackedDouble in
574 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
575 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
577 // -- VPERM2I - 3 source operands form --
578 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
579 PatFrag mem_frag, X86MemOperand x86memop,
581 let Constraints = "$src1 = $dst" in {
582 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
583 (ins RC:$src1, RC:$src2, RC:$src3),
584 !strconcat(OpcodeStr,
585 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
587 (OpVT (X86VPermv3 RC:$src1, RC:$src2, RC:$src3)))]>,
590 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
591 (ins RC:$src1, RC:$src2, x86memop:$src3),
592 !strconcat(OpcodeStr,
593 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
595 (OpVT (X86VPermv3 RC:$src1, RC:$src2,
596 (mem_frag addr:$src3))))]>, EVEX_4V;
599 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem,
600 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
601 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem,
602 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
603 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem,
604 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
605 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
606 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
608 //===----------------------------------------------------------------------===//
609 // AVX-512 - BLEND using mask
611 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, Intrinsic Int,
612 RegisterClass KRC, RegisterClass RC,
613 X86MemOperand x86memop, PatFrag mem_frag,
614 SDNode OpNode, ValueType vt> {
615 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
616 (ins KRC:$mask, RC:$src1, RC:$src2),
617 !strconcat(OpcodeStr,
618 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
619 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
620 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
621 let isCodeGenOnly = 1 in
622 def rr_Int : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
623 (ins KRC:$mask, RC:$src1, RC:$src2),
624 !strconcat(OpcodeStr,
625 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
626 [(set RC:$dst, (Int KRC:$mask, (vt RC:$src2),
627 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
630 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
631 (ins KRC:$mask, RC:$src1, x86memop:$src2),
632 !strconcat(OpcodeStr,
633 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
637 let isCodeGenOnly = 1 in
638 def rm_Int : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
639 (ins KRC:$mask, RC:$src1, x86memop:$src2),
640 !strconcat(OpcodeStr,
641 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
642 [(set RC:$dst, (Int KRC:$mask, (vt RC:$src1),
643 (mem_frag addr:$src2)))]>,
648 let ExeDomain = SSEPackedSingle in
649 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
650 int_x86_avx512_mask_blend_ps_512,
651 VK16WM, VR512, f512mem,
652 memopv16f32, vselect, v16f32>,
653 EVEX_CD8<32, CD8VF>, EVEX_V512;
654 let ExeDomain = SSEPackedDouble in
655 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
656 int_x86_avx512_mask_blend_pd_512,
657 VK8WM, VR512, f512mem,
658 memopv8f64, vselect, v8f64>,
659 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
661 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
662 int_x86_avx512_mask_blend_d_512,
663 VK16WM, VR512, f512mem,
664 memopv16i32, vselect, v16i32>,
665 EVEX_CD8<32, CD8VF>, EVEX_V512;
667 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
668 int_x86_avx512_mask_blend_q_512,
669 VK8WM, VR512, f512mem,
670 memopv8i64, vselect, v8i64>,
671 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
673 let Predicates = [HasAVX512] in {
674 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
675 (v8f32 VR256X:$src2))),
677 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
678 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
679 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
681 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
682 (v8i32 VR256X:$src2))),
684 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
685 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
686 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
688 //===----------------------------------------------------------------------===//
689 // Compare Instructions
690 //===----------------------------------------------------------------------===//
692 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
693 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
694 Operand CC, SDNode OpNode, ValueType VT,
695 PatFrag ld_frag, string asm, string asm_alt> {
696 def rr : AVX512Ii8<0xC2, MRMSrcReg,
697 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
698 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
699 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
700 def rm : AVX512Ii8<0xC2, MRMSrcMem,
701 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
702 [(set VK1:$dst, (OpNode (VT RC:$src1),
703 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
704 let isAsmParserOnly = 1, hasSideEffects = 0 in {
705 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
706 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
707 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
708 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
709 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
710 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
714 let Predicates = [HasAVX512] in {
715 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
716 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
717 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
719 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
720 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
721 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
725 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
726 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
727 SDNode OpNode, ValueType vt> {
728 def rr : AVX512BI<opc, MRMSrcReg,
729 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
730 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
731 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
732 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
733 def rm : AVX512BI<opc, MRMSrcMem,
734 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
735 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
736 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
737 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
740 defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
741 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512;
742 defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
743 memopv8i64, X86pcmpeqm, v8i64>, T8, EVEX_V512, VEX_W;
745 defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
746 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512;
747 defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
748 memopv8i64, X86pcmpgtm, v8i64>, T8, EVEX_V512, VEX_W;
750 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
751 (COPY_TO_REGCLASS (VPCMPGTDZrr
752 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
753 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
755 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
756 (COPY_TO_REGCLASS (VPCMPEQDZrr
757 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
758 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
760 multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
761 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
762 SDNode OpNode, ValueType vt, Operand CC, string asm,
764 def rri : AVX512AIi8<opc, MRMSrcReg,
765 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
766 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
767 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
768 def rmi : AVX512AIi8<opc, MRMSrcMem,
769 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
770 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
771 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
772 // Accept explicit immediate argument form instead of comparison code.
773 let isAsmParserOnly = 1, hasSideEffects = 0 in {
774 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
775 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
776 asm_alt, [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
777 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
778 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
779 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
783 defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv16i32,
784 X86cmpm, v16i32, AVXCC,
785 "vpcmp${cc}d\t{$src2, $src1, $dst|$dst, $src1, $src2}",
786 "vpcmpd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
787 EVEX_V512, EVEX_CD8<32, CD8VF>;
788 defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv16i32,
789 X86cmpmu, v16i32, AVXCC,
790 "vpcmp${cc}ud\t{$src2, $src1, $dst|$dst, $src1, $src2}",
791 "vpcmpud\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
792 EVEX_V512, EVEX_CD8<32, CD8VF>;
794 defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64,
795 X86cmpm, v8i64, AVXCC,
796 "vpcmp${cc}q\t{$src2, $src1, $dst|$dst, $src1, $src2}",
797 "vpcmpq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
798 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
799 defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64,
800 X86cmpmu, v8i64, AVXCC,
801 "vpcmp${cc}uq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
802 "vpcmpuq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
803 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
805 // avx512_cmp_packed - sse 1 & 2 compare packed instructions
806 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
807 X86MemOperand x86memop, ValueType vt,
808 string suffix, Domain d> {
809 def rri : AVX512PIi8<0xC2, MRMSrcReg,
810 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
811 !strconcat("vcmp${cc}", suffix,
812 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
813 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
814 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
815 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc, i32imm:$sae),
816 !strconcat("vcmp${cc}", suffix,
817 "\t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
819 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
820 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
821 !strconcat("vcmp", suffix,
822 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
824 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
826 // Accept explicit immediate argument form instead of comparison code.
827 let isAsmParserOnly = 1, hasSideEffects = 0 in {
828 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
829 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
830 !strconcat("vcmp", suffix,
831 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
832 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
833 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
834 !strconcat("vcmp", suffix,
835 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
839 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
840 "ps", SSEPackedSingle>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VF>;
841 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
842 "pd", SSEPackedDouble>, OpSize, EVEX_4V, VEX_W, EVEX_V512,
845 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
846 (COPY_TO_REGCLASS (VCMPPSZrri
847 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
848 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
850 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
851 (COPY_TO_REGCLASS (VPCMPDZrri
852 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
853 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
855 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
856 (COPY_TO_REGCLASS (VPCMPUDZrri
857 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
858 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
861 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
862 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
864 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
865 (I8Imm imm:$cc), (i32 0)), GR16)>;
867 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
868 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
870 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
871 (I8Imm imm:$cc), (i32 0)), GR8)>;
873 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
874 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
876 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
877 (I8Imm imm:$cc)), GR16)>;
879 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
880 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
882 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
883 (I8Imm imm:$cc)), GR8)>;
885 // Mask register copy, including
886 // - copy between mask registers
887 // - load/store mask registers
888 // - copy from GPR to mask register and vice versa
890 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
891 string OpcodeStr, RegisterClass KRC,
892 ValueType vt, X86MemOperand x86memop> {
893 let neverHasSideEffects = 1 in {
894 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
895 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
897 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
898 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
899 [(set KRC:$dst, (vt (load addr:$src)))]>;
901 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
902 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
906 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
908 RegisterClass KRC, RegisterClass GRC> {
909 let neverHasSideEffects = 1 in {
910 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
911 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
912 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
913 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
917 let Predicates = [HasAVX512] in {
918 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
920 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
924 let Predicates = [HasAVX512] in {
925 // GR16 from/to 16-bit mask
926 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
927 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
928 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
929 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
931 // Store kreg in memory
932 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
933 (KMOVWmk addr:$dst, VK16:$src)>;
935 def : Pat<(store VK8:$src, addr:$dst),
936 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
938 def : Pat<(i1 (load addr:$src)),
939 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
941 def : Pat<(v8i1 (load addr:$src)),
942 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
944 def : Pat<(i1 (trunc (i32 GR32:$src))),
945 (COPY_TO_REGCLASS (KMOVWkr $src), VK1)>;
947 def : Pat<(i1 (trunc (i8 GR8:$src))),
949 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)), VK1)>;
951 def : Pat<(i32 (zext VK1:$src)), (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16))>;
952 def : Pat<(i8 (zext VK1:$src)),
954 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_8bit)>;
956 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
957 let Predicates = [HasAVX512] in {
958 // GR from/to 8-bit mask without native support
959 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
961 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
963 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
965 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
968 def : Pat<(i1 (extractelt VK16:$src, (iPTR 0))),
969 (COPY_TO_REGCLASS VK16:$src, VK1)>;
970 def : Pat<(i1 (extractelt VK8:$src, (iPTR 0))),
971 (COPY_TO_REGCLASS VK8:$src, VK1)>;
975 // Mask unary operation
977 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
978 RegisterClass KRC, SDPatternOperator OpNode> {
979 let Predicates = [HasAVX512] in
980 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
981 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
982 [(set KRC:$dst, (OpNode KRC:$src))]>;
985 multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
986 SDPatternOperator OpNode> {
987 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
991 defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
993 multiclass avx512_mask_unop_int<string IntName, string InstName> {
994 let Predicates = [HasAVX512] in
995 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
997 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
998 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1000 defm : avx512_mask_unop_int<"knot", "KNOT">;
1002 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1003 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1004 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1006 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1007 def : Pat<(not VK8:$src),
1009 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1011 // Mask binary operation
1012 // - KAND, KANDN, KOR, KXNOR, KXOR
1013 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1014 RegisterClass KRC, SDPatternOperator OpNode> {
1015 let Predicates = [HasAVX512] in
1016 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1017 !strconcat(OpcodeStr,
1018 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1019 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1022 multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
1023 SDPatternOperator OpNode> {
1024 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1028 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1029 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1031 let isCommutable = 1 in {
1032 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
1033 let isCommutable = 0 in
1034 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
1035 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
1036 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
1037 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
1040 def : Pat<(xor VK1:$src1, VK1:$src2),
1041 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1042 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1044 def : Pat<(or VK1:$src1, VK1:$src2),
1045 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1046 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1048 def : Pat<(not VK1:$src),
1049 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src, VK16),
1050 (COPY_TO_REGCLASS (VCMPSSZrr (f32 (IMPLICIT_DEF)),
1051 (f32 (IMPLICIT_DEF)), (i8 0)), VK16)), VK1)>;
1053 def : Pat<(and VK1:$src1, VK1:$src2),
1054 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1055 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1057 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1058 let Predicates = [HasAVX512] in
1059 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1060 (i16 GR16:$src1), (i16 GR16:$src2)),
1061 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1062 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1063 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1066 defm : avx512_mask_binop_int<"kand", "KAND">;
1067 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1068 defm : avx512_mask_binop_int<"kor", "KOR">;
1069 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1070 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1072 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1073 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1074 let Predicates = [HasAVX512] in
1075 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1077 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1078 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1081 defm : avx512_binop_pat<and, KANDWrr>;
1082 defm : avx512_binop_pat<andn, KANDNWrr>;
1083 defm : avx512_binop_pat<or, KORWrr>;
1084 defm : avx512_binop_pat<xnor, KXNORWrr>;
1085 defm : avx512_binop_pat<xor, KXORWrr>;
1088 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1089 RegisterClass KRC> {
1090 let Predicates = [HasAVX512] in
1091 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1092 !strconcat(OpcodeStr,
1093 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1096 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1097 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1098 VEX_4V, VEX_L, OpSize, TB;
1101 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1102 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1103 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1104 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1107 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1108 let Predicates = [HasAVX512] in
1109 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1110 (i16 GR16:$src1), (i16 GR16:$src2)),
1111 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1112 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1113 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1115 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1118 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1120 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1121 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1122 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1123 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1126 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1127 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1131 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1133 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1134 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1135 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1138 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1140 let Predicates = [HasAVX512] in
1141 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1142 !strconcat(OpcodeStr,
1143 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
1144 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1147 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1149 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1150 VEX, OpSize, TA, VEX_W;
1153 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1154 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1156 // Mask setting all 0s or 1s
1157 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1158 let Predicates = [HasAVX512] in
1159 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1160 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1161 [(set KRC:$dst, (VT Val))]>;
1164 multiclass avx512_mask_setop_w<PatFrag Val> {
1165 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1166 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1169 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1170 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1172 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1173 let Predicates = [HasAVX512] in {
1174 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1175 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1177 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1178 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1180 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1181 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1183 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1184 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1186 //===----------------------------------------------------------------------===//
1187 // AVX-512 - Aligned and unaligned load and store
1190 multiclass avx512_mov_packed<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1191 X86MemOperand x86memop, PatFrag ld_frag,
1192 string asm, Domain d> {
1193 let neverHasSideEffects = 1 in
1194 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1195 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>,
1197 let canFoldAsLoad = 1 in
1198 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1199 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1200 [(set RC:$dst, (ld_frag addr:$src))], d>, EVEX;
1201 let Constraints = "$src1 = $dst" in {
1202 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1203 (ins RC:$src1, KRC:$mask, RC:$src2),
1205 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1207 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1208 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1210 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1211 [], d>, EVEX, EVEX_K;
1215 defm VMOVAPSZ : avx512_mov_packed<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1216 "vmovaps", SSEPackedSingle>,
1217 EVEX_V512, EVEX_CD8<32, CD8VF>;
1218 defm VMOVAPDZ : avx512_mov_packed<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1219 "vmovapd", SSEPackedDouble>,
1220 OpSize, EVEX_V512, VEX_W,
1221 EVEX_CD8<64, CD8VF>;
1222 defm VMOVUPSZ : avx512_mov_packed<0x10, VR512, VK16WM, f512mem, loadv16f32,
1223 "vmovups", SSEPackedSingle>,
1224 EVEX_V512, EVEX_CD8<32, CD8VF>;
1225 defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64,
1226 "vmovupd", SSEPackedDouble>,
1227 OpSize, EVEX_V512, VEX_W,
1228 EVEX_CD8<64, CD8VF>;
1229 def VMOVAPSZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1230 "vmovaps\t{$src, $dst|$dst, $src}",
1231 [(alignedstore512 (v16f32 VR512:$src), addr:$dst)],
1232 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1233 def VMOVAPDZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1234 "vmovapd\t{$src, $dst|$dst, $src}",
1235 [(alignedstore512 (v8f64 VR512:$src), addr:$dst)],
1236 SSEPackedDouble>, EVEX, EVEX_V512,
1237 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1238 def VMOVUPSZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1239 "vmovups\t{$src, $dst|$dst, $src}",
1240 [(store (v16f32 VR512:$src), addr:$dst)],
1241 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1242 def VMOVUPDZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1243 "vmovupd\t{$src, $dst|$dst, $src}",
1244 [(store (v8f64 VR512:$src), addr:$dst)],
1245 SSEPackedDouble>, EVEX, EVEX_V512,
1246 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1248 let neverHasSideEffects = 1 in {
1249 def VMOVDQA32rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1251 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1253 def VMOVDQA64rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1255 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1256 EVEX, EVEX_V512, VEX_W;
1257 let mayStore = 1 in {
1258 def VMOVDQA32mr : AVX512BI<0x7F, MRMDestMem, (outs),
1259 (ins i512mem:$dst, VR512:$src),
1260 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1261 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1262 def VMOVDQA64mr : AVX512BI<0x7F, MRMDestMem, (outs),
1263 (ins i512mem:$dst, VR512:$src),
1264 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1265 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1267 let mayLoad = 1 in {
1268 def VMOVDQA32rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1270 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1271 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1272 def VMOVDQA64rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1274 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1275 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1279 // 512-bit aligned load/store
1280 def : Pat<(alignedloadv8i64 addr:$src), (VMOVDQA64rm addr:$src)>;
1281 def : Pat<(alignedloadv16i32 addr:$src), (VMOVDQA32rm addr:$src)>;
1283 def : Pat<(alignedstore512 (v8i64 VR512:$src), addr:$dst),
1284 (VMOVDQA64mr addr:$dst, VR512:$src)>;
1285 def : Pat<(alignedstore512 (v16i32 VR512:$src), addr:$dst),
1286 (VMOVDQA32mr addr:$dst, VR512:$src)>;
1288 multiclass avx512_mov_int<bits<8> load_opc, bits<8> store_opc, string asm,
1289 RegisterClass RC, RegisterClass KRC,
1290 PatFrag ld_frag, X86MemOperand x86memop> {
1291 let neverHasSideEffects = 1 in
1292 def rr : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1293 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>, EVEX;
1294 let canFoldAsLoad = 1 in
1295 def rm : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1296 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1297 [(set RC:$dst, (ld_frag addr:$src))]>, EVEX;
1299 def mr : AVX512XSI<store_opc, MRMDestMem, (outs),
1300 (ins x86memop:$dst, VR512:$src),
1301 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>, EVEX;
1302 let Constraints = "$src1 = $dst" in {
1303 def rrk : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst),
1304 (ins RC:$src1, KRC:$mask, RC:$src2),
1306 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), []>,
1308 def rmk : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst),
1309 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1311 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1316 defm VMOVDQU32 : avx512_mov_int<0x6F, 0x7F, "vmovdqu32", VR512, VK16WM,
1317 memopv16i32, i512mem>,
1318 EVEX_V512, EVEX_CD8<32, CD8VF>;
1319 defm VMOVDQU64 : avx512_mov_int<0x6F, 0x7F, "vmovdqu64", VR512, VK8WM,
1320 memopv8i64, i512mem>,
1321 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1323 // 512-bit unaligned load/store
1324 def : Pat<(loadv8i64 addr:$src), (VMOVDQU64rm addr:$src)>;
1325 def : Pat<(loadv16i32 addr:$src), (VMOVDQU32rm addr:$src)>;
1327 def : Pat<(store (v8i64 VR512:$src), addr:$dst),
1328 (VMOVDQU64mr addr:$dst, VR512:$src)>;
1329 def : Pat<(store (v16i32 VR512:$src), addr:$dst),
1330 (VMOVDQU32mr addr:$dst, VR512:$src)>;
1332 let AddedComplexity = 20 in {
1333 def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1334 (v16f32 VR512:$src2))),
1335 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1336 def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1337 (v8f64 VR512:$src2))),
1338 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1339 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1340 (v16i32 VR512:$src2))),
1341 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1342 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1343 (v8i64 VR512:$src2))),
1344 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1346 // Move Int Doubleword to Packed Double Int
1348 def VMOVDI2PDIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1349 "vmovd\t{$src, $dst|$dst, $src}",
1351 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1353 def VMOVDI2PDIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1354 "vmovd\t{$src, $dst|$dst, $src}",
1356 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1357 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1358 def VMOV64toPQIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1359 "vmovq\t{$src, $dst|$dst, $src}",
1361 (v2i64 (scalar_to_vector GR64:$src)))],
1362 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
1363 let isCodeGenOnly = 1 in {
1364 def VMOV64toSDZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1365 "vmovq\t{$src, $dst|$dst, $src}",
1366 [(set FR64:$dst, (bitconvert GR64:$src))],
1367 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1368 def VMOVSDto64Zrr : AVX512SI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1369 "vmovq\t{$src, $dst|$dst, $src}",
1370 [(set GR64:$dst, (bitconvert FR64:$src))],
1371 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1373 def VMOVSDto64Zmr : AVX512SI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1374 "vmovq\t{$src, $dst|$dst, $src}",
1375 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1376 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1377 EVEX_CD8<64, CD8VT1>;
1379 // Move Int Doubleword to Single Scalar
1381 let isCodeGenOnly = 1 in {
1382 def VMOVDI2SSZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1383 "vmovd\t{$src, $dst|$dst, $src}",
1384 [(set FR32X:$dst, (bitconvert GR32:$src))],
1385 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1387 def VMOVDI2SSZrm : AVX512SI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1388 "vmovd\t{$src, $dst|$dst, $src}",
1389 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1390 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1393 // Move Packed Doubleword Int to Packed Double Int
1395 def VMOVPDI2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1396 "vmovd\t{$src, $dst|$dst, $src}",
1397 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1398 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1400 def VMOVPDI2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1401 (ins i32mem:$dst, VR128X:$src),
1402 "vmovd\t{$src, $dst|$dst, $src}",
1403 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1404 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1405 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1407 // Move Packed Doubleword Int first element to Doubleword Int
1409 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1410 "vmovq\t{$src, $dst|$dst, $src}",
1411 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1413 IIC_SSE_MOVD_ToGP>, TB, OpSize, EVEX, VEX_LIG, VEX_W,
1414 Requires<[HasAVX512, In64BitMode]>;
1416 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
1417 (ins i64mem:$dst, VR128X:$src),
1418 "vmovq\t{$src, $dst|$dst, $src}",
1419 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1420 addr:$dst)], IIC_SSE_MOVDQ>,
1421 EVEX, OpSize, VEX_LIG, VEX_W, TB, EVEX_CD8<64, CD8VT1>,
1422 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1424 // Move Scalar Single to Double Int
1426 let isCodeGenOnly = 1 in {
1427 def VMOVSS2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst),
1429 "vmovd\t{$src, $dst|$dst, $src}",
1430 [(set GR32:$dst, (bitconvert FR32X:$src))],
1431 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1432 def VMOVSS2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1433 (ins i32mem:$dst, FR32X:$src),
1434 "vmovd\t{$src, $dst|$dst, $src}",
1435 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1436 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1439 // Move Quadword Int to Packed Quadword Int
1441 def VMOVQI2PQIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst),
1443 "vmovq\t{$src, $dst|$dst, $src}",
1445 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1446 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1448 //===----------------------------------------------------------------------===//
1449 // AVX-512 MOVSS, MOVSD
1450 //===----------------------------------------------------------------------===//
1452 multiclass avx512_move_scalar <string asm, RegisterClass RC,
1453 SDNode OpNode, ValueType vt,
1454 X86MemOperand x86memop, PatFrag mem_pat> {
1455 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1456 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1457 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1458 (scalar_to_vector RC:$src2))))],
1459 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1460 let Constraints = "$src1 = $dst" in
1461 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
1462 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
1464 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
1465 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
1466 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1467 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1468 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1470 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1471 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1472 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1476 let ExeDomain = SSEPackedSingle in
1477 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
1478 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1480 let ExeDomain = SSEPackedDouble in
1481 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
1482 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1484 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
1485 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
1486 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
1488 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
1489 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
1490 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
1492 // For the disassembler
1493 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
1494 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1495 (ins VR128X:$src1, FR32X:$src2),
1496 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1498 XS, EVEX_4V, VEX_LIG;
1499 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1500 (ins VR128X:$src1, FR64X:$src2),
1501 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1503 XD, EVEX_4V, VEX_LIG, VEX_W;
1506 let Predicates = [HasAVX512] in {
1507 let AddedComplexity = 15 in {
1508 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1509 // MOVS{S,D} to the lower bits.
1510 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1511 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1512 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1513 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1514 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1515 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1516 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1517 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1519 // Move low f32 and clear high bits.
1520 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1521 (SUBREG_TO_REG (i32 0),
1522 (VMOVSSZrr (v4f32 (V_SET0)),
1523 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1524 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1525 (SUBREG_TO_REG (i32 0),
1526 (VMOVSSZrr (v4i32 (V_SET0)),
1527 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1530 let AddedComplexity = 20 in {
1531 // MOVSSrm zeros the high parts of the register; represent this
1532 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1533 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1534 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1535 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1536 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1537 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1538 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1540 // MOVSDrm zeros the high parts of the register; represent this
1541 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1542 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1543 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1544 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1545 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1546 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1547 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1548 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1549 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1550 def : Pat<(v2f64 (X86vzload addr:$src)),
1551 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1553 // Represent the same patterns above but in the form they appear for
1555 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1556 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
1557 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
1558 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1559 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1560 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1561 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1562 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1563 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1565 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1566 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1567 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1568 FR32X:$src)), sub_xmm)>;
1569 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1570 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1571 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1572 FR64X:$src)), sub_xmm)>;
1573 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1574 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
1575 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
1577 // Move low f64 and clear high bits.
1578 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1579 (SUBREG_TO_REG (i32 0),
1580 (VMOVSDZrr (v2f64 (V_SET0)),
1581 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1583 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1584 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1585 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1587 // Extract and store.
1588 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1590 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1591 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1593 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1595 // Shuffle with VMOVSS
1596 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1597 (VMOVSSZrr (v4i32 VR128X:$src1),
1598 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1599 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1600 (VMOVSSZrr (v4f32 VR128X:$src1),
1601 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1604 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1605 (SUBREG_TO_REG (i32 0),
1606 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1607 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1609 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1610 (SUBREG_TO_REG (i32 0),
1611 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1612 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1615 // Shuffle with VMOVSD
1616 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1617 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1618 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1619 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1620 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1621 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1622 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1623 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1626 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1627 (SUBREG_TO_REG (i32 0),
1628 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1629 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1631 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1632 (SUBREG_TO_REG (i32 0),
1633 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1634 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1637 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1638 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1639 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1640 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1641 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1642 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1643 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1644 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1647 let AddedComplexity = 15 in
1648 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1650 "vmovq\t{$src, $dst|$dst, $src}",
1651 [(set VR128X:$dst, (v2i64 (X86vzmovl
1652 (v2i64 VR128X:$src))))],
1653 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1655 let AddedComplexity = 20 in
1656 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1658 "vmovq\t{$src, $dst|$dst, $src}",
1659 [(set VR128X:$dst, (v2i64 (X86vzmovl
1660 (loadv2i64 addr:$src))))],
1661 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1662 EVEX_CD8<8, CD8VT8>;
1664 let Predicates = [HasAVX512] in {
1665 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1666 let AddedComplexity = 20 in {
1667 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1668 (VMOVDI2PDIZrm addr:$src)>;
1669 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
1670 (VMOV64toPQIZrr GR64:$src)>;
1671 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
1672 (VMOVDI2PDIZrr GR32:$src)>;
1674 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1675 (VMOVDI2PDIZrm addr:$src)>;
1676 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1677 (VMOVDI2PDIZrm addr:$src)>;
1678 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1679 (VMOVZPQILo2PQIZrm addr:$src)>;
1680 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1681 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1682 def : Pat<(v2i64 (X86vzload addr:$src)),
1683 (VMOVZPQILo2PQIZrm addr:$src)>;
1686 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1687 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1688 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1689 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1690 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1691 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1692 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1695 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
1696 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1698 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
1699 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1701 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
1702 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1704 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
1705 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1707 //===----------------------------------------------------------------------===//
1708 // AVX-512 - Integer arithmetic
1710 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1711 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1712 X86MemOperand x86memop, PatFrag scalar_mfrag,
1713 X86MemOperand x86scalar_mop, string BrdcstStr,
1714 OpndItins itins, bit IsCommutable = 0> {
1715 let isCommutable = IsCommutable in
1716 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1717 (ins RC:$src1, RC:$src2),
1718 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1719 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1721 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1722 (ins RC:$src1, x86memop:$src2),
1723 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1724 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
1726 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1727 (ins RC:$src1, x86scalar_mop:$src2),
1728 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1729 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1730 [(set RC:$dst, (OpNode RC:$src1,
1731 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1732 itins.rm>, EVEX_4V, EVEX_B;
1734 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr,
1735 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
1736 PatFrag memop_frag, X86MemOperand x86memop,
1738 bit IsCommutable = 0> {
1739 let isCommutable = IsCommutable in
1740 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1741 (ins RC:$src1, RC:$src2),
1742 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1743 []>, EVEX_4V, VEX_W;
1744 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1745 (ins RC:$src1, x86memop:$src2),
1746 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1747 []>, EVEX_4V, VEX_W;
1750 defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VR512, memopv16i32,
1751 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1752 EVEX_V512, EVEX_CD8<32, CD8VF>;
1754 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VR512, memopv16i32,
1755 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 0>,
1756 EVEX_V512, EVEX_CD8<32, CD8VF>;
1758 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VR512, memopv16i32,
1759 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1760 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1762 defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VR512, memopv8i64,
1763 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 1>,
1764 EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
1766 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VR512, memopv8i64,
1767 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1768 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1770 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32,
1771 VR512, memopv8i64, i512mem, SSE_INTALU_ITINS_P, 1>, T8,
1772 EVEX_V512, EVEX_CD8<64, CD8VF>;
1774 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32,
1775 VR512, memopv8i64, i512mem, SSE_INTMUL_ITINS_P, 1>, EVEX_V512,
1776 EVEX_CD8<64, CD8VF>;
1778 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
1779 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1781 defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VR512, memopv16i32,
1782 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1783 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1784 defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VR512, memopv8i64,
1785 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1786 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1788 defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VR512, memopv16i32,
1789 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1790 EVEX_V512, EVEX_CD8<32, CD8VF>;
1791 defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VR512, memopv8i64,
1792 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1793 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1795 defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VR512, memopv16i32,
1796 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1797 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1798 defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VR512, memopv8i64,
1799 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1800 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1802 defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VR512, memopv16i32,
1803 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1804 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1805 defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VR512, memopv8i64,
1806 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1807 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1809 //===----------------------------------------------------------------------===//
1810 // AVX-512 - Unpack Instructions
1811 //===----------------------------------------------------------------------===//
1813 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
1814 PatFrag mem_frag, RegisterClass RC,
1815 X86MemOperand x86memop, string asm,
1817 def rr : AVX512PI<opc, MRMSrcReg,
1818 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1820 (vt (OpNode RC:$src1, RC:$src2)))],
1822 def rm : AVX512PI<opc, MRMSrcMem,
1823 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1825 (vt (OpNode RC:$src1,
1826 (bitconvert (mem_frag addr:$src2)))))],
1830 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
1831 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1832 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1833 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
1834 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1835 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1836 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
1837 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1838 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1839 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
1840 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1841 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1843 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
1844 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1845 X86MemOperand x86memop> {
1846 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1847 (ins RC:$src1, RC:$src2),
1848 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1849 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1850 IIC_SSE_UNPCK>, EVEX_4V;
1851 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1852 (ins RC:$src1, x86memop:$src2),
1853 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1854 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
1855 (bitconvert (memop_frag addr:$src2)))))],
1856 IIC_SSE_UNPCK>, EVEX_4V;
1858 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
1859 VR512, memopv16i32, i512mem>, EVEX_V512,
1860 EVEX_CD8<32, CD8VF>;
1861 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
1862 VR512, memopv8i64, i512mem>, EVEX_V512,
1863 VEX_W, EVEX_CD8<64, CD8VF>;
1864 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
1865 VR512, memopv16i32, i512mem>, EVEX_V512,
1866 EVEX_CD8<32, CD8VF>;
1867 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
1868 VR512, memopv8i64, i512mem>, EVEX_V512,
1869 VEX_W, EVEX_CD8<64, CD8VF>;
1870 //===----------------------------------------------------------------------===//
1874 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
1875 SDNode OpNode, PatFrag mem_frag,
1876 X86MemOperand x86memop, ValueType OpVT> {
1877 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
1878 (ins RC:$src1, i8imm:$src2),
1879 !strconcat(OpcodeStr,
1880 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1882 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
1884 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
1885 (ins x86memop:$src1, i8imm:$src2),
1886 !strconcat(OpcodeStr,
1887 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1889 (OpVT (OpNode (mem_frag addr:$src1),
1890 (i8 imm:$src2))))]>, EVEX;
1893 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
1894 i512mem, v16i32>, OpSize, EVEX_V512, EVEX_CD8<32, CD8VF>;
1896 let ExeDomain = SSEPackedSingle in
1897 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
1898 memopv16f32, i512mem, v16f32>, OpSize, TA, EVEX_V512,
1899 EVEX_CD8<32, CD8VF>;
1900 let ExeDomain = SSEPackedDouble in
1901 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
1902 memopv8f64, i512mem, v8f64>, OpSize, TA, EVEX_V512,
1903 VEX_W, EVEX_CD8<32, CD8VF>;
1905 def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1906 (VPERMILPSZri VR512:$src1, imm:$imm)>;
1907 def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1908 (VPERMILPDZri VR512:$src1, imm:$imm)>;
1910 //===----------------------------------------------------------------------===//
1911 // AVX-512 Logical Instructions
1912 //===----------------------------------------------------------------------===//
1914 defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VR512, memopv16i32,
1915 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1916 EVEX_V512, EVEX_CD8<32, CD8VF>;
1917 defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VR512, memopv8i64,
1918 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1919 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1920 defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VR512, memopv16i32,
1921 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1922 EVEX_V512, EVEX_CD8<32, CD8VF>;
1923 defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VR512, memopv8i64,
1924 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1925 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1926 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VR512, memopv16i32,
1927 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1928 EVEX_V512, EVEX_CD8<32, CD8VF>;
1929 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VR512, memopv8i64,
1930 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1931 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1932 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VR512,
1933 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1934 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1935 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VR512, memopv8i64,
1936 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 0>,
1937 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1939 //===----------------------------------------------------------------------===//
1940 // AVX-512 FP arithmetic
1941 //===----------------------------------------------------------------------===//
1943 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1945 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
1946 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
1947 EVEX_CD8<32, CD8VT1>;
1948 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
1949 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
1950 EVEX_CD8<64, CD8VT1>;
1953 let isCommutable = 1 in {
1954 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
1955 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
1956 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
1957 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
1959 let isCommutable = 0 in {
1960 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
1961 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
1964 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1965 RegisterClass RC, ValueType vt,
1966 X86MemOperand x86memop, PatFrag mem_frag,
1967 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
1969 Domain d, OpndItins itins, bit commutable> {
1970 let isCommutable = commutable in
1971 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1972 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1973 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
1975 let mayLoad = 1 in {
1976 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1977 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1978 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
1979 itins.rm, d>, EVEX_4V, TB;
1980 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
1981 (ins RC:$src1, x86scalar_mop:$src2),
1982 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1983 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1984 [(set RC:$dst, (OpNode RC:$src1,
1985 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1986 itins.rm, d>, EVEX_4V, EVEX_B, TB;
1990 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VR512, v16f32, f512mem,
1991 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1992 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1994 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VR512, v8f64, f512mem,
1995 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1996 SSE_ALU_ITINS_P.d, 1>,
1997 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1999 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VR512, v16f32, f512mem,
2000 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2001 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2002 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VR512, v8f64, f512mem,
2003 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2004 SSE_ALU_ITINS_P.d, 1>,
2005 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
2007 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VR512, v16f32, f512mem,
2008 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2009 SSE_ALU_ITINS_P.s, 1>,
2010 EVEX_V512, EVEX_CD8<32, CD8VF>;
2011 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VR512, v16f32, f512mem,
2012 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2013 SSE_ALU_ITINS_P.s, 1>,
2014 EVEX_V512, EVEX_CD8<32, CD8VF>;
2016 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VR512, v8f64, f512mem,
2017 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2018 SSE_ALU_ITINS_P.d, 1>,
2019 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
2020 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VR512, v8f64, f512mem,
2021 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2022 SSE_ALU_ITINS_P.d, 1>,
2023 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
2025 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VR512, v16f32, f512mem,
2026 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2027 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2028 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VR512, v16f32, f512mem,
2029 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2030 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2032 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VR512, v8f64, f512mem,
2033 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2034 SSE_ALU_ITINS_P.d, 0>,
2035 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
2036 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VR512, v8f64, f512mem,
2037 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2038 SSE_ALU_ITINS_P.d, 0>,
2039 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
2041 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
2042 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2043 (i16 -1), FROUND_CURRENT)),
2044 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
2046 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
2047 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2048 (i8 -1), FROUND_CURRENT)),
2049 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
2051 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
2052 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2053 (i16 -1), FROUND_CURRENT)),
2054 (VMINPSZrr VR512:$src1, VR512:$src2)>;
2056 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
2057 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2058 (i8 -1), FROUND_CURRENT)),
2059 (VMINPDZrr VR512:$src1, VR512:$src2)>;
2060 //===----------------------------------------------------------------------===//
2061 // AVX-512 VPTESTM instructions
2062 //===----------------------------------------------------------------------===//
2064 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2065 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
2066 SDNode OpNode, ValueType vt> {
2067 def rr : AVX5128I<opc, MRMSrcReg,
2068 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
2069 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2070 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))]>, EVEX_4V;
2071 def rm : AVX5128I<opc, MRMSrcMem,
2072 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
2073 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2074 [(set KRC:$dst, (OpNode (vt RC:$src1),
2075 (bitconvert (memop_frag addr:$src2))))]>, EVEX_4V;
2078 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
2079 memopv16i32, X86testm, v16i32>, EVEX_V512,
2080 EVEX_CD8<32, CD8VF>;
2081 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
2082 memopv8i64, X86testm, v8i64>, EVEX_V512, VEX_W,
2083 EVEX_CD8<64, CD8VF>;
2085 //===----------------------------------------------------------------------===//
2086 // AVX-512 Shift instructions
2087 //===----------------------------------------------------------------------===//
2088 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
2089 string OpcodeStr, SDNode OpNode, RegisterClass RC,
2090 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
2091 RegisterClass KRC> {
2092 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2093 (ins RC:$src1, i8imm:$src2),
2094 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2095 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
2096 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2097 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2098 (ins KRC:$mask, RC:$src1, i8imm:$src2),
2099 !strconcat(OpcodeStr,
2100 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2101 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2102 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2103 (ins x86memop:$src1, i8imm:$src2),
2104 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2105 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
2106 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2107 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2108 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
2109 !strconcat(OpcodeStr,
2110 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2111 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2114 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2115 RegisterClass RC, ValueType vt, ValueType SrcVT,
2116 PatFrag bc_frag, RegisterClass KRC> {
2117 // src2 is always 128-bit
2118 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2119 (ins RC:$src1, VR128X:$src2),
2120 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2121 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
2122 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2123 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2124 (ins KRC:$mask, RC:$src1, VR128X:$src2),
2125 !strconcat(OpcodeStr,
2126 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2127 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2128 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2129 (ins RC:$src1, i128mem:$src2),
2130 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2131 [(set RC:$dst, (vt (OpNode RC:$src1,
2132 (bc_frag (memopv2i64 addr:$src2)))))],
2133 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2134 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2135 (ins KRC:$mask, RC:$src1, i128mem:$src2),
2136 !strconcat(OpcodeStr,
2137 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2138 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2141 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
2142 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2143 EVEX_V512, EVEX_CD8<32, CD8VF>;
2144 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
2145 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2146 EVEX_CD8<32, CD8VQ>;
2148 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
2149 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2150 EVEX_CD8<64, CD8VF>, VEX_W;
2151 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
2152 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2153 EVEX_CD8<64, CD8VQ>, VEX_W;
2155 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
2156 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
2157 EVEX_CD8<32, CD8VF>;
2158 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
2159 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2160 EVEX_CD8<32, CD8VQ>;
2162 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
2163 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2164 EVEX_CD8<64, CD8VF>, VEX_W;
2165 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
2166 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2167 EVEX_CD8<64, CD8VQ>, VEX_W;
2169 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
2170 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2171 EVEX_V512, EVEX_CD8<32, CD8VF>;
2172 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
2173 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2174 EVEX_CD8<32, CD8VQ>;
2176 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
2177 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2178 EVEX_CD8<64, CD8VF>, VEX_W;
2179 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
2180 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2181 EVEX_CD8<64, CD8VQ>, VEX_W;
2183 //===-------------------------------------------------------------------===//
2184 // Variable Bit Shifts
2185 //===-------------------------------------------------------------------===//
2186 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
2187 RegisterClass RC, ValueType vt,
2188 X86MemOperand x86memop, PatFrag mem_frag> {
2189 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
2190 (ins RC:$src1, RC:$src2),
2191 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2193 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
2195 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
2196 (ins RC:$src1, x86memop:$src2),
2197 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2199 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
2203 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
2204 i512mem, memopv16i32>, EVEX_V512,
2205 EVEX_CD8<32, CD8VF>;
2206 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
2207 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2208 EVEX_CD8<64, CD8VF>;
2209 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
2210 i512mem, memopv16i32>, EVEX_V512,
2211 EVEX_CD8<32, CD8VF>;
2212 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
2213 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2214 EVEX_CD8<64, CD8VF>;
2215 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
2216 i512mem, memopv16i32>, EVEX_V512,
2217 EVEX_CD8<32, CD8VF>;
2218 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
2219 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2220 EVEX_CD8<64, CD8VF>;
2222 //===----------------------------------------------------------------------===//
2223 // AVX-512 - MOVDDUP
2224 //===----------------------------------------------------------------------===//
2226 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
2227 X86MemOperand x86memop, PatFrag memop_frag> {
2228 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2229 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2230 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
2231 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2232 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2234 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
2237 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
2238 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
2239 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
2240 (VMOVDDUPZrm addr:$src)>;
2242 //===---------------------------------------------------------------------===//
2243 // Replicate Single FP - MOVSHDUP and MOVSLDUP
2244 //===---------------------------------------------------------------------===//
2245 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
2246 ValueType vt, RegisterClass RC, PatFrag mem_frag,
2247 X86MemOperand x86memop> {
2248 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2249 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2250 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
2252 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2253 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2254 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
2257 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
2258 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2259 EVEX_CD8<32, CD8VF>;
2260 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
2261 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2262 EVEX_CD8<32, CD8VF>;
2264 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
2265 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
2266 (VMOVSHDUPZrm addr:$src)>;
2267 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
2268 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
2269 (VMOVSLDUPZrm addr:$src)>;
2271 //===----------------------------------------------------------------------===//
2272 // Move Low to High and High to Low packed FP Instructions
2273 //===----------------------------------------------------------------------===//
2274 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
2275 (ins VR128X:$src1, VR128X:$src2),
2276 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2277 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2278 IIC_SSE_MOV_LH>, EVEX_4V;
2279 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2280 (ins VR128X:$src1, VR128X:$src2),
2281 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2282 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2283 IIC_SSE_MOV_LH>, EVEX_4V;
2285 let Predicates = [HasAVX512] in {
2287 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2288 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2289 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2290 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
2293 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2294 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2297 //===----------------------------------------------------------------------===//
2298 // FMA - Fused Multiply Operations
2300 let Constraints = "$src1 = $dst" in {
2301 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2302 RegisterClass RC, X86MemOperand x86memop,
2303 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2304 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2305 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2306 (ins RC:$src1, RC:$src2, RC:$src3),
2307 !strconcat(OpcodeStr,"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2308 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2311 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2312 (ins RC:$src1, RC:$src2, x86memop:$src3),
2313 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2314 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2315 (mem_frag addr:$src3))))]>;
2316 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2317 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2318 !strconcat(OpcodeStr, "\t{${src3}", BrdcstStr,
2319 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2320 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2321 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2323 } // Constraints = "$src1 = $dst"
2325 let ExeDomain = SSEPackedSingle in {
2326 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2327 memopv16f32, f32mem, loadf32, "{1to16}",
2328 X86Fmadd, v16f32>, EVEX_V512,
2329 EVEX_CD8<32, CD8VF>;
2330 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2331 memopv16f32, f32mem, loadf32, "{1to16}",
2332 X86Fmsub, v16f32>, EVEX_V512,
2333 EVEX_CD8<32, CD8VF>;
2334 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2335 memopv16f32, f32mem, loadf32, "{1to16}",
2336 X86Fmaddsub, v16f32>,
2337 EVEX_V512, EVEX_CD8<32, CD8VF>;
2338 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2339 memopv16f32, f32mem, loadf32, "{1to16}",
2340 X86Fmsubadd, v16f32>,
2341 EVEX_V512, EVEX_CD8<32, CD8VF>;
2342 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2343 memopv16f32, f32mem, loadf32, "{1to16}",
2344 X86Fnmadd, v16f32>, EVEX_V512,
2345 EVEX_CD8<32, CD8VF>;
2346 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2347 memopv16f32, f32mem, loadf32, "{1to16}",
2348 X86Fnmsub, v16f32>, EVEX_V512,
2349 EVEX_CD8<32, CD8VF>;
2351 let ExeDomain = SSEPackedDouble in {
2352 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2353 memopv8f64, f64mem, loadf64, "{1to8}",
2354 X86Fmadd, v8f64>, EVEX_V512,
2355 VEX_W, EVEX_CD8<64, CD8VF>;
2356 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2357 memopv8f64, f64mem, loadf64, "{1to8}",
2358 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2359 EVEX_CD8<64, CD8VF>;
2360 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2361 memopv8f64, f64mem, loadf64, "{1to8}",
2362 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2363 EVEX_CD8<64, CD8VF>;
2364 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2365 memopv8f64, f64mem, loadf64, "{1to8}",
2366 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2367 EVEX_CD8<64, CD8VF>;
2368 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2369 memopv8f64, f64mem, loadf64, "{1to8}",
2370 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2371 EVEX_CD8<64, CD8VF>;
2372 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2373 memopv8f64, f64mem, loadf64, "{1to8}",
2374 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2375 EVEX_CD8<64, CD8VF>;
2378 let Constraints = "$src1 = $dst" in {
2379 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2380 RegisterClass RC, X86MemOperand x86memop,
2381 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2382 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2384 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2385 (ins RC:$src1, RC:$src3, x86memop:$src2),
2386 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2387 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2388 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2389 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2390 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2391 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2392 [(set RC:$dst, (OpNode RC:$src1,
2393 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2395 } // Constraints = "$src1 = $dst"
2398 let ExeDomain = SSEPackedSingle in {
2399 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2400 memopv16f32, f32mem, loadf32, "{1to16}",
2401 X86Fmadd, v16f32>, EVEX_V512,
2402 EVEX_CD8<32, CD8VF>;
2403 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2404 memopv16f32, f32mem, loadf32, "{1to16}",
2405 X86Fmsub, v16f32>, EVEX_V512,
2406 EVEX_CD8<32, CD8VF>;
2407 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
2408 memopv16f32, f32mem, loadf32, "{1to16}",
2409 X86Fmaddsub, v16f32>,
2410 EVEX_V512, EVEX_CD8<32, CD8VF>;
2411 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
2412 memopv16f32, f32mem, loadf32, "{1to16}",
2413 X86Fmsubadd, v16f32>,
2414 EVEX_V512, EVEX_CD8<32, CD8VF>;
2415 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
2416 memopv16f32, f32mem, loadf32, "{1to16}",
2417 X86Fnmadd, v16f32>, EVEX_V512,
2418 EVEX_CD8<32, CD8VF>;
2419 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
2420 memopv16f32, f32mem, loadf32, "{1to16}",
2421 X86Fnmsub, v16f32>, EVEX_V512,
2422 EVEX_CD8<32, CD8VF>;
2424 let ExeDomain = SSEPackedDouble in {
2425 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
2426 memopv8f64, f64mem, loadf64, "{1to8}",
2427 X86Fmadd, v8f64>, EVEX_V512,
2428 VEX_W, EVEX_CD8<64, CD8VF>;
2429 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
2430 memopv8f64, f64mem, loadf64, "{1to8}",
2431 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2432 EVEX_CD8<64, CD8VF>;
2433 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
2434 memopv8f64, f64mem, loadf64, "{1to8}",
2435 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2436 EVEX_CD8<64, CD8VF>;
2437 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
2438 memopv8f64, f64mem, loadf64, "{1to8}",
2439 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2440 EVEX_CD8<64, CD8VF>;
2441 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
2442 memopv8f64, f64mem, loadf64, "{1to8}",
2443 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2444 EVEX_CD8<64, CD8VF>;
2445 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
2446 memopv8f64, f64mem, loadf64, "{1to8}",
2447 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2448 EVEX_CD8<64, CD8VF>;
2452 let Constraints = "$src1 = $dst" in {
2453 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2454 RegisterClass RC, ValueType OpVT,
2455 X86MemOperand x86memop, Operand memop,
2457 let isCommutable = 1 in
2458 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2459 (ins RC:$src1, RC:$src2, RC:$src3),
2460 !strconcat(OpcodeStr,
2461 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2463 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
2465 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2466 (ins RC:$src1, RC:$src2, f128mem:$src3),
2467 !strconcat(OpcodeStr,
2468 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2470 (OpVT (OpNode RC:$src2, RC:$src1,
2471 (mem_frag addr:$src3))))]>;
2474 } // Constraints = "$src1 = $dst"
2476 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
2477 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2478 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
2479 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2480 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
2481 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2482 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
2483 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2484 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
2485 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2486 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
2487 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2488 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
2489 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2490 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
2491 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2493 //===----------------------------------------------------------------------===//
2494 // AVX-512 Scalar convert from sign integer to float/double
2495 //===----------------------------------------------------------------------===//
2497 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2498 X86MemOperand x86memop, string asm> {
2499 let neverHasSideEffects = 1 in {
2500 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
2501 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2504 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
2505 (ins DstRC:$src1, x86memop:$src),
2506 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2508 } // neverHasSideEffects = 1
2510 let Predicates = [HasAVX512] in {
2511 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
2512 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2513 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
2514 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2515 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
2516 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2517 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
2518 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2520 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
2521 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2522 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
2523 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2524 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
2525 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2526 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
2527 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2529 def : Pat<(f32 (sint_to_fp GR32:$src)),
2530 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2531 def : Pat<(f32 (sint_to_fp GR64:$src)),
2532 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2533 def : Pat<(f64 (sint_to_fp GR32:$src)),
2534 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2535 def : Pat<(f64 (sint_to_fp GR64:$src)),
2536 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2538 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
2539 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2540 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
2541 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2542 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
2543 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2544 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
2545 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2547 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
2548 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2549 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
2550 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2551 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
2552 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2553 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
2554 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2556 def : Pat<(f32 (uint_to_fp GR32:$src)),
2557 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2558 def : Pat<(f32 (uint_to_fp GR64:$src)),
2559 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2560 def : Pat<(f64 (uint_to_fp GR32:$src)),
2561 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2562 def : Pat<(f64 (uint_to_fp GR64:$src)),
2563 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2566 //===----------------------------------------------------------------------===//
2567 // AVX-512 Scalar convert from float/double to integer
2568 //===----------------------------------------------------------------------===//
2569 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2570 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
2572 let neverHasSideEffects = 1 in {
2573 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2574 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2575 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
2576 Requires<[HasAVX512]>;
2578 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
2579 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
2580 Requires<[HasAVX512]>;
2581 } // neverHasSideEffects = 1
2583 let Predicates = [HasAVX512] in {
2584 // Convert float/double to signed/unsigned int 32/64
2585 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
2586 ssmem, sse_load_f32, "cvtss2si">,
2587 XS, EVEX_CD8<32, CD8VT1>;
2588 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
2589 ssmem, sse_load_f32, "cvtss2si">,
2590 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
2591 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
2592 ssmem, sse_load_f32, "cvtss2usi">,
2593 XS, EVEX_CD8<32, CD8VT1>;
2594 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2595 int_x86_avx512_cvtss2usi64, ssmem,
2596 sse_load_f32, "cvtss2usi">, XS, VEX_W,
2597 EVEX_CD8<32, CD8VT1>;
2598 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
2599 sdmem, sse_load_f64, "cvtsd2si">,
2600 XD, EVEX_CD8<64, CD8VT1>;
2601 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
2602 sdmem, sse_load_f64, "cvtsd2si">,
2603 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2604 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
2605 sdmem, sse_load_f64, "cvtsd2usi">,
2606 XD, EVEX_CD8<64, CD8VT1>;
2607 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2608 int_x86_avx512_cvtsd2usi64, sdmem,
2609 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
2610 EVEX_CD8<64, CD8VT1>;
2612 let isCodeGenOnly = 1 in {
2613 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2614 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
2615 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2616 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2617 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
2618 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2619 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2620 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
2621 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2622 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2623 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
2624 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2626 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2627 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
2628 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2629 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2630 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
2631 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2632 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2633 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
2634 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2635 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2636 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
2637 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2638 } // isCodeGenOnly = 1
2640 // Convert float/double to signed/unsigned int 32/64 with truncation
2641 let isCodeGenOnly = 1 in {
2642 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
2643 ssmem, sse_load_f32, "cvttss2si">,
2644 XS, EVEX_CD8<32, CD8VT1>;
2645 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2646 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
2647 "cvttss2si">, XS, VEX_W,
2648 EVEX_CD8<32, CD8VT1>;
2649 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
2650 sdmem, sse_load_f64, "cvttsd2si">, XD,
2651 EVEX_CD8<64, CD8VT1>;
2652 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2653 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
2654 "cvttsd2si">, XD, VEX_W,
2655 EVEX_CD8<64, CD8VT1>;
2656 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2657 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
2658 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
2659 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2660 int_x86_avx512_cvttss2usi64, ssmem,
2661 sse_load_f32, "cvttss2usi">, XS, VEX_W,
2662 EVEX_CD8<32, CD8VT1>;
2663 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2664 int_x86_avx512_cvttsd2usi,
2665 sdmem, sse_load_f64, "cvttsd2usi">, XD,
2666 EVEX_CD8<64, CD8VT1>;
2667 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2668 int_x86_avx512_cvttsd2usi64, sdmem,
2669 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
2670 EVEX_CD8<64, CD8VT1>;
2671 } // isCodeGenOnly = 1
2673 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2674 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
2676 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2677 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2678 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
2679 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2680 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2681 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
2684 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
2685 loadf32, "cvttss2si">, XS,
2686 EVEX_CD8<32, CD8VT1>;
2687 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
2688 loadf32, "cvttss2usi">, XS,
2689 EVEX_CD8<32, CD8VT1>;
2690 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
2691 loadf32, "cvttss2si">, XS, VEX_W,
2692 EVEX_CD8<32, CD8VT1>;
2693 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
2694 loadf32, "cvttss2usi">, XS, VEX_W,
2695 EVEX_CD8<32, CD8VT1>;
2696 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
2697 loadf64, "cvttsd2si">, XD,
2698 EVEX_CD8<64, CD8VT1>;
2699 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
2700 loadf64, "cvttsd2usi">, XD,
2701 EVEX_CD8<64, CD8VT1>;
2702 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
2703 loadf64, "cvttsd2si">, XD, VEX_W,
2704 EVEX_CD8<64, CD8VT1>;
2705 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
2706 loadf64, "cvttsd2usi">, XD, VEX_W,
2707 EVEX_CD8<64, CD8VT1>;
2709 //===----------------------------------------------------------------------===//
2710 // AVX-512 Convert form float to double and back
2711 //===----------------------------------------------------------------------===//
2712 let neverHasSideEffects = 1 in {
2713 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
2714 (ins FR32X:$src1, FR32X:$src2),
2715 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2716 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
2718 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
2719 (ins FR32X:$src1, f32mem:$src2),
2720 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2721 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
2722 EVEX_CD8<32, CD8VT1>;
2724 // Convert scalar double to scalar single
2725 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
2726 (ins FR64X:$src1, FR64X:$src2),
2727 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2728 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
2730 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
2731 (ins FR64X:$src1, f64mem:$src2),
2732 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2733 []>, EVEX_4V, VEX_LIG, VEX_W,
2734 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
2737 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
2738 Requires<[HasAVX512]>;
2739 def : Pat<(fextend (loadf32 addr:$src)),
2740 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
2742 def : Pat<(extloadf32 addr:$src),
2743 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
2744 Requires<[HasAVX512, OptForSize]>;
2746 def : Pat<(extloadf32 addr:$src),
2747 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
2748 Requires<[HasAVX512, OptForSpeed]>;
2750 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
2751 Requires<[HasAVX512]>;
2753 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
2754 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2755 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2757 let neverHasSideEffects = 1 in {
2758 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2759 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2761 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2762 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
2763 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
2764 [], d>, EVEX, EVEX_B;
2766 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2767 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2769 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2770 } // neverHasSideEffects = 1
2773 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
2774 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2775 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2777 let neverHasSideEffects = 1 in {
2778 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2779 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2781 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2783 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2784 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2786 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2787 } // neverHasSideEffects = 1
2790 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
2791 memopv8f64, f512mem, v8f32, v8f64,
2792 SSEPackedSingle>, EVEX_V512, VEX_W, OpSize,
2793 EVEX_CD8<64, CD8VF>;
2795 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
2796 memopv4f64, f256mem, v8f64, v8f32,
2797 SSEPackedDouble>, EVEX_V512, EVEX_CD8<32, CD8VH>;
2798 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2799 (VCVTPS2PDZrm addr:$src)>;
2801 //===----------------------------------------------------------------------===//
2802 // AVX-512 Vector convert from sign integer to float/double
2803 //===----------------------------------------------------------------------===//
2805 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
2806 memopv8i64, i512mem, v16f32, v16i32,
2807 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2809 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
2810 memopv4i64, i256mem, v8f64, v8i32,
2811 SSEPackedDouble>, EVEX_V512, XS,
2812 EVEX_CD8<32, CD8VH>;
2814 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
2815 memopv16f32, f512mem, v16i32, v16f32,
2816 SSEPackedSingle>, EVEX_V512, XS,
2817 EVEX_CD8<32, CD8VF>;
2819 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
2820 memopv8f64, f512mem, v8i32, v8f64,
2821 SSEPackedDouble>, EVEX_V512, OpSize, VEX_W,
2822 EVEX_CD8<64, CD8VF>;
2824 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
2825 memopv16f32, f512mem, v16i32, v16f32,
2826 SSEPackedSingle>, EVEX_V512,
2827 EVEX_CD8<32, CD8VF>;
2829 // cvttps2udq (src, 0, mask-all-ones, sae-current)
2830 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
2831 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
2832 (VCVTTPS2UDQZrr VR512:$src)>;
2834 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
2835 memopv8f64, f512mem, v8i32, v8f64,
2836 SSEPackedDouble>, EVEX_V512, VEX_W,
2837 EVEX_CD8<64, CD8VF>;
2839 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
2840 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
2841 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
2842 (VCVTTPD2UDQZrr VR512:$src)>;
2844 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
2845 memopv4i64, f256mem, v8f64, v8i32,
2846 SSEPackedDouble>, EVEX_V512, XS,
2847 EVEX_CD8<32, CD8VH>;
2849 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
2850 memopv16i32, f512mem, v16f32, v16i32,
2851 SSEPackedSingle>, EVEX_V512, XD,
2852 EVEX_CD8<32, CD8VF>;
2854 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
2855 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
2856 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
2859 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
2860 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
2861 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
2862 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
2863 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2864 (VCVTDQ2PDZrr VR256X:$src)>;
2865 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
2866 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
2867 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
2868 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
2869 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2870 (VCVTUDQ2PDZrr VR256X:$src)>;
2872 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
2873 RegisterClass DstRC, PatFrag mem_frag,
2874 X86MemOperand x86memop, Domain d> {
2875 let neverHasSideEffects = 1 in {
2876 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2877 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2879 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
2880 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
2881 [], d>, EVEX, EVEX_B;
2883 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2884 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2886 } // neverHasSideEffects = 1
2889 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
2890 memopv16f32, f512mem, SSEPackedSingle>, OpSize,
2891 EVEX_V512, EVEX_CD8<32, CD8VF>;
2892 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
2893 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
2894 EVEX_V512, EVEX_CD8<64, CD8VF>;
2896 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
2897 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
2898 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
2900 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
2901 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
2902 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
2904 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
2905 memopv16f32, f512mem, SSEPackedSingle>,
2906 EVEX_V512, EVEX_CD8<32, CD8VF>;
2907 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
2908 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
2909 EVEX_V512, EVEX_CD8<64, CD8VF>;
2911 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
2912 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
2913 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
2915 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
2916 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
2917 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
2919 let Predicates = [HasAVX512] in {
2920 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
2921 (VCVTPD2PSZrm addr:$src)>;
2922 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2923 (VCVTPS2PDZrm addr:$src)>;
2926 //===----------------------------------------------------------------------===//
2927 // Half precision conversion instructions
2928 //===----------------------------------------------------------------------===//
2929 multiclass avx512_f16c_ph2ps<RegisterClass destRC, RegisterClass srcRC,
2930 X86MemOperand x86memop, Intrinsic Int> {
2931 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
2932 "vcvtph2ps\t{$src, $dst|$dst, $src}",
2933 [(set destRC:$dst, (Int srcRC:$src))]>, EVEX;
2934 let neverHasSideEffects = 1, mayLoad = 1 in
2935 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
2936 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
2939 multiclass avx512_f16c_ps2ph<RegisterClass destRC, RegisterClass srcRC,
2940 X86MemOperand x86memop, Intrinsic Int> {
2941 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
2942 (ins srcRC:$src1, i32i8imm:$src2),
2943 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2944 [(set destRC:$dst, (Int srcRC:$src1, imm:$src2))]>, EVEX;
2945 let neverHasSideEffects = 1, mayStore = 1 in
2946 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
2947 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
2948 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
2951 defm VCVTPH2PSZ : avx512_f16c_ph2ps<VR512, VR256X, f256mem,
2952 int_x86_avx512_vcvtph2ps_512>, EVEX_V512,
2953 EVEX_CD8<32, CD8VH>;
2954 defm VCVTPS2PHZ : avx512_f16c_ps2ph<VR256X, VR512, f256mem,
2955 int_x86_avx512_vcvtps2ph_512>, EVEX_V512,
2956 EVEX_CD8<32, CD8VH>;
2958 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
2959 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
2960 "ucomiss">, TB, EVEX, VEX_LIG,
2961 EVEX_CD8<32, CD8VT1>;
2962 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
2963 "ucomisd">, TB, OpSize, EVEX,
2964 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2965 let Pattern = []<dag> in {
2966 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
2967 "comiss">, TB, EVEX, VEX_LIG,
2968 EVEX_CD8<32, CD8VT1>;
2969 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
2970 "comisd">, TB, OpSize, EVEX,
2971 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2973 let isCodeGenOnly = 1 in {
2974 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
2975 load, "ucomiss">, TB, EVEX, VEX_LIG,
2976 EVEX_CD8<32, CD8VT1>;
2977 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
2978 load, "ucomisd">, TB, OpSize, EVEX,
2979 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2981 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
2982 load, "comiss">, TB, EVEX, VEX_LIG,
2983 EVEX_CD8<32, CD8VT1>;
2984 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
2985 load, "comisd">, TB, OpSize, EVEX,
2986 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2990 /// avx512_unop_p - AVX-512 unops in packed form.
2991 multiclass avx512_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2992 def PSZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2993 !strconcat(OpcodeStr,
2994 "ps\t{$src, $dst|$dst, $src}"),
2995 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))]>,
2997 def PSZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f256mem:$src),
2998 !strconcat(OpcodeStr,
2999 "ps\t{$src, $dst|$dst, $src}"),
3000 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
3001 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
3002 def PDZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3003 !strconcat(OpcodeStr,
3004 "pd\t{$src, $dst|$dst, $src}"),
3005 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))]>,
3006 EVEX, EVEX_V512, VEX_W;
3007 def PDZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3008 !strconcat(OpcodeStr,
3009 "pd\t{$src, $dst|$dst, $src}"),
3010 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
3011 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3014 /// avx512_fp_unop_p_int - AVX-512 intrinsics unops in packed forms.
3015 multiclass avx512_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3016 Intrinsic V16F32Int, Intrinsic V8F64Int> {
3017 let isCodeGenOnly = 1 in {
3018 def PSZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3019 !strconcat(OpcodeStr,
3020 "ps\t{$src, $dst|$dst, $src}"),
3021 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
3023 def PSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3024 !strconcat(OpcodeStr,
3025 "ps\t{$src, $dst|$dst, $src}"),
3027 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
3028 EVEX_V512, EVEX_CD8<32, CD8VF>;
3029 def PDZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3030 !strconcat(OpcodeStr,
3031 "pd\t{$src, $dst|$dst, $src}"),
3032 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
3033 EVEX, EVEX_V512, VEX_W;
3034 def PDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3035 !strconcat(OpcodeStr,
3036 "pd\t{$src, $dst|$dst, $src}"),
3038 (V8F64Int (memopv8f64 addr:$src)))]>,
3039 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3040 } // isCodeGenOnly = 1
3043 /// avx512_fp_unop_s - AVX-512 unops in scalar form.
3044 multiclass avx512_fp_unop_s<bits<8> opc, string OpcodeStr> {
3045 let hasSideEffects = 0 in {
3046 def SSZr : AVX5128I<opc, MRMSrcReg, (outs FR32X:$dst),
3047 (ins FR32X:$src1, FR32X:$src2),
3048 !strconcat(OpcodeStr,
3049 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3051 let mayLoad = 1 in {
3052 def SSZm : AVX5128I<opc, MRMSrcMem, (outs FR32X:$dst),
3053 (ins FR32X:$src1, f32mem:$src2),
3054 !strconcat(OpcodeStr,
3055 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3056 []>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3057 let isCodeGenOnly = 1 in
3058 def SSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
3059 (ins VR128X:$src1, ssmem:$src2),
3060 !strconcat(OpcodeStr,
3061 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3062 []>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3064 def SDZr : AVX5128I<opc, MRMSrcReg, (outs FR64X:$dst),
3065 (ins FR64X:$src1, FR64X:$src2),
3066 !strconcat(OpcodeStr,
3067 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3069 let mayLoad = 1 in {
3070 def SDZm : AVX5128I<opc, MRMSrcMem, (outs FR64X:$dst),
3071 (ins FR64X:$src1, f64mem:$src2),
3072 !strconcat(OpcodeStr,
3073 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3074 EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3075 let isCodeGenOnly = 1 in
3076 def SDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
3077 (ins VR128X:$src1, sdmem:$src2),
3078 !strconcat(OpcodeStr,
3079 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3080 []>, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3085 defm VRCP14 : avx512_fp_unop_s<0x4D, "vrcp14">,
3086 avx512_fp_unop_p<0x4C, "vrcp14", X86frcp>,
3087 avx512_fp_unop_p_int<0x4C, "vrcp14",
3088 int_x86_avx512_rcp14_ps_512, int_x86_avx512_rcp14_pd_512>;
3090 defm VRSQRT14 : avx512_fp_unop_s<0x4F, "vrsqrt14">,
3091 avx512_fp_unop_p<0x4E, "vrsqrt14", X86frsqrt>,
3092 avx512_fp_unop_p_int<0x4E, "vrsqrt14",
3093 int_x86_avx512_rsqrt14_ps_512, int_x86_avx512_rsqrt14_pd_512>;
3095 def : Pat<(int_x86_avx512_rsqrt14_ss VR128X:$src),
3096 (COPY_TO_REGCLASS (VRSQRT14SSZr (f32 (IMPLICIT_DEF)),
3097 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3099 def : Pat<(int_x86_avx512_rsqrt14_ss sse_load_f32:$src),
3100 (VRSQRT14SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3102 def : Pat<(int_x86_avx512_rcp14_ss VR128X:$src),
3103 (COPY_TO_REGCLASS (VRCP14SSZr (f32 (IMPLICIT_DEF)),
3104 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3106 def : Pat<(int_x86_avx512_rcp14_ss sse_load_f32:$src),
3107 (VRCP14SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3109 let AddedComplexity = 20, Predicates = [HasERI] in {
3110 defm VRCP28 : avx512_fp_unop_s<0xCB, "vrcp28">,
3111 avx512_fp_unop_p<0xCA, "vrcp28", X86frcp>,
3112 avx512_fp_unop_p_int<0xCA, "vrcp28",
3113 int_x86_avx512_rcp28_ps_512, int_x86_avx512_rcp28_pd_512>;
3115 defm VRSQRT28 : avx512_fp_unop_s<0xCD, "vrsqrt28">,
3116 avx512_fp_unop_p<0xCC, "vrsqrt28", X86frsqrt>,
3117 avx512_fp_unop_p_int<0xCC, "vrsqrt28",
3118 int_x86_avx512_rsqrt28_ps_512, int_x86_avx512_rsqrt28_pd_512>;
3121 let Predicates = [HasERI] in {
3122 def : Pat<(int_x86_avx512_rsqrt28_ss VR128X:$src),
3123 (COPY_TO_REGCLASS (VRSQRT28SSZr (f32 (IMPLICIT_DEF)),
3124 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3126 def : Pat<(int_x86_avx512_rsqrt28_ss sse_load_f32:$src),
3127 (VRSQRT28SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3129 def : Pat<(int_x86_avx512_rcp28_ss VR128X:$src),
3130 (COPY_TO_REGCLASS (VRCP28SSZr (f32 (IMPLICIT_DEF)),
3131 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3133 def : Pat<(int_x86_avx512_rcp28_ss sse_load_f32:$src),
3134 (VRCP28SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3136 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3137 Intrinsic V16F32Int, Intrinsic V8F64Int,
3138 OpndItins itins_s, OpndItins itins_d> {
3139 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3140 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3141 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
3145 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3146 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3148 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
3149 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
3151 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3152 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3153 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
3157 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3158 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3159 [(set VR512:$dst, (OpNode
3160 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
3161 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
3163 let isCodeGenOnly = 1 in {
3164 def PSZr_Int : AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3165 !strconcat(OpcodeStr,
3166 "ps\t{$src, $dst|$dst, $src}"),
3167 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
3169 def PSZm_Int : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3170 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3172 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
3173 EVEX_V512, EVEX_CD8<32, CD8VF>;
3174 def PDZr_Int : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3175 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3176 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
3177 EVEX, EVEX_V512, VEX_W;
3178 def PDZm_Int : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3179 !strconcat(OpcodeStr,
3180 "pd\t{$src, $dst|$dst, $src}"),
3181 [(set VR512:$dst, (V8F64Int (memopv8f64 addr:$src)))]>,
3182 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3183 } // isCodeGenOnly = 1
3186 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
3187 Intrinsic F32Int, Intrinsic F64Int,
3188 OpndItins itins_s, OpndItins itins_d> {
3189 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
3190 (ins FR32X:$src1, FR32X:$src2),
3191 !strconcat(OpcodeStr,
3192 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3193 [], itins_s.rr>, XS, EVEX_4V;
3194 let isCodeGenOnly = 1 in
3195 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3196 (ins VR128X:$src1, VR128X:$src2),
3197 !strconcat(OpcodeStr,
3198 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3200 (F32Int VR128X:$src1, VR128X:$src2))],
3201 itins_s.rr>, XS, EVEX_4V;
3202 let mayLoad = 1 in {
3203 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
3204 (ins FR32X:$src1, f32mem:$src2),
3205 !strconcat(OpcodeStr,
3206 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3207 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3208 let isCodeGenOnly = 1 in
3209 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3210 (ins VR128X:$src1, ssmem:$src2),
3211 !strconcat(OpcodeStr,
3212 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3214 (F32Int VR128X:$src1, sse_load_f32:$src2))],
3215 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3217 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
3218 (ins FR64X:$src1, FR64X:$src2),
3219 !strconcat(OpcodeStr,
3220 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3222 let isCodeGenOnly = 1 in
3223 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3224 (ins VR128X:$src1, VR128X:$src2),
3225 !strconcat(OpcodeStr,
3226 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3228 (F64Int VR128X:$src1, VR128X:$src2))],
3229 itins_s.rr>, XD, EVEX_4V, VEX_W;
3230 let mayLoad = 1 in {
3231 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
3232 (ins FR64X:$src1, f64mem:$src2),
3233 !strconcat(OpcodeStr,
3234 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3235 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3236 let isCodeGenOnly = 1 in
3237 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3238 (ins VR128X:$src1, sdmem:$src2),
3239 !strconcat(OpcodeStr,
3240 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3242 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
3243 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3248 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
3249 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
3250 SSE_SQRTSS, SSE_SQRTSD>,
3251 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
3252 int_x86_avx512_sqrt_ps_512, int_x86_avx512_sqrt_pd_512,
3253 SSE_SQRTPS, SSE_SQRTPD>;
3255 let Predicates = [HasAVX512] in {
3256 def : Pat<(f32 (fsqrt FR32X:$src)),
3257 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3258 def : Pat<(f32 (fsqrt (load addr:$src))),
3259 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3260 Requires<[OptForSize]>;
3261 def : Pat<(f64 (fsqrt FR64X:$src)),
3262 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
3263 def : Pat<(f64 (fsqrt (load addr:$src))),
3264 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
3265 Requires<[OptForSize]>;
3267 def : Pat<(f32 (X86frsqrt FR32X:$src)),
3268 (VRSQRT14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3269 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3270 (VRSQRT14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3271 Requires<[OptForSize]>;
3273 def : Pat<(f32 (X86frcp FR32X:$src)),
3274 (VRCP14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3275 def : Pat<(f32 (X86frcp (load addr:$src))),
3276 (VRCP14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3277 Requires<[OptForSize]>;
3279 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
3280 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
3281 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3283 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3284 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3286 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
3287 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
3288 (COPY_TO_REGCLASS VR128X:$src, FR64)),
3290 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3291 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3295 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
3296 X86MemOperand x86memop, RegisterClass RC,
3297 PatFrag mem_frag32, PatFrag mem_frag64,
3298 Intrinsic V4F32Int, Intrinsic V2F64Int,
3300 let ExeDomain = SSEPackedSingle in {
3301 // Intrinsic operation, reg.
3302 // Vector intrinsic operation, reg
3303 def PSr : AVX512AIi8<opcps, MRMSrcReg,
3304 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3305 !strconcat(OpcodeStr,
3306 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3307 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
3309 // Vector intrinsic operation, mem
3310 def PSm : AVX512AIi8<opcps, MRMSrcMem,
3311 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3312 !strconcat(OpcodeStr,
3313 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3315 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
3316 EVEX_CD8<32, VForm>;
3317 } // ExeDomain = SSEPackedSingle
3319 let ExeDomain = SSEPackedDouble in {
3320 // Vector intrinsic operation, reg
3321 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
3322 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3323 !strconcat(OpcodeStr,
3324 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3325 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
3327 // Vector intrinsic operation, mem
3328 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
3329 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3330 !strconcat(OpcodeStr,
3331 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3333 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
3334 EVEX_CD8<64, VForm>;
3335 } // ExeDomain = SSEPackedDouble
3338 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3342 let ExeDomain = GenericDomain in {
3344 let hasSideEffects = 0 in
3345 def SSr : AVX512AIi8<opcss, MRMSrcReg,
3346 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
3347 !strconcat(OpcodeStr,
3348 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3351 // Intrinsic operation, reg.
3352 let isCodeGenOnly = 1 in
3353 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
3354 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3355 !strconcat(OpcodeStr,
3356 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3357 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
3359 // Intrinsic operation, mem.
3360 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
3361 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
3362 !strconcat(OpcodeStr,
3363 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3364 [(set VR128X:$dst, (F32Int VR128X:$src1,
3365 sse_load_f32:$src2, imm:$src3))]>,
3366 EVEX_CD8<32, CD8VT1>;
3369 let hasSideEffects = 0 in
3370 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
3371 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
3372 !strconcat(OpcodeStr,
3373 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3376 // Intrinsic operation, reg.
3377 let isCodeGenOnly = 1 in
3378 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
3379 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3380 !strconcat(OpcodeStr,
3381 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3382 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
3385 // Intrinsic operation, mem.
3386 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
3387 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
3388 !strconcat(OpcodeStr,
3389 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3391 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
3392 VEX_W, EVEX_CD8<64, CD8VT1>;
3393 } // ExeDomain = GenericDomain
3396 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
3397 X86MemOperand x86memop, RegisterClass RC,
3398 PatFrag mem_frag, Domain d> {
3399 let ExeDomain = d in {
3400 // Intrinsic operation, reg.
3401 // Vector intrinsic operation, reg
3402 def r : AVX512AIi8<opc, MRMSrcReg,
3403 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3404 !strconcat(OpcodeStr,
3405 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3408 // Vector intrinsic operation, mem
3409 def m : AVX512AIi8<opc, MRMSrcMem,
3410 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3411 !strconcat(OpcodeStr,
3412 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3418 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
3419 memopv16f32, SSEPackedSingle>, EVEX_V512,
3420 EVEX_CD8<32, CD8VF>;
3422 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
3423 imm:$src2, (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1),
3425 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
3428 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
3429 memopv8f64, SSEPackedDouble>, EVEX_V512,
3430 VEX_W, EVEX_CD8<64, CD8VF>;
3432 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
3433 imm:$src2, (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1),
3435 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
3437 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
3438 Operand x86memop, RegisterClass RC, Domain d> {
3439 let ExeDomain = d in {
3440 def r : AVX512AIi8<opc, MRMSrcReg,
3441 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
3442 !strconcat(OpcodeStr,
3443 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3446 def m : AVX512AIi8<opc, MRMSrcMem,
3447 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
3448 !strconcat(OpcodeStr,
3449 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3454 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
3455 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
3457 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
3458 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
3460 def : Pat<(ffloor FR32X:$src),
3461 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
3462 def : Pat<(f64 (ffloor FR64X:$src)),
3463 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
3464 def : Pat<(f32 (fnearbyint FR32X:$src)),
3465 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
3466 def : Pat<(f64 (fnearbyint FR64X:$src)),
3467 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
3468 def : Pat<(f32 (fceil FR32X:$src)),
3469 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
3470 def : Pat<(f64 (fceil FR64X:$src)),
3471 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
3472 def : Pat<(f32 (frint FR32X:$src)),
3473 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
3474 def : Pat<(f64 (frint FR64X:$src)),
3475 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
3476 def : Pat<(f32 (ftrunc FR32X:$src)),
3477 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
3478 def : Pat<(f64 (ftrunc FR64X:$src)),
3479 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
3481 def : Pat<(v16f32 (ffloor VR512:$src)),
3482 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
3483 def : Pat<(v16f32 (fnearbyint VR512:$src)),
3484 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
3485 def : Pat<(v16f32 (fceil VR512:$src)),
3486 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
3487 def : Pat<(v16f32 (frint VR512:$src)),
3488 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
3489 def : Pat<(v16f32 (ftrunc VR512:$src)),
3490 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
3492 def : Pat<(v8f64 (ffloor VR512:$src)),
3493 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
3494 def : Pat<(v8f64 (fnearbyint VR512:$src)),
3495 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
3496 def : Pat<(v8f64 (fceil VR512:$src)),
3497 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
3498 def : Pat<(v8f64 (frint VR512:$src)),
3499 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
3500 def : Pat<(v8f64 (ftrunc VR512:$src)),
3501 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
3503 //-------------------------------------------------
3504 // Integer truncate and extend operations
3505 //-------------------------------------------------
3507 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
3508 RegisterClass dstRC, RegisterClass srcRC,
3509 RegisterClass KRC, X86MemOperand x86memop> {
3510 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3512 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
3515 def krr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3516 (ins KRC:$mask, srcRC:$src),
3517 !strconcat(OpcodeStr,
3518 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3521 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
3522 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3525 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
3526 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3527 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
3528 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3529 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
3530 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3531 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
3532 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3533 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
3534 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3535 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
3536 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3537 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
3538 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3539 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
3540 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3541 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
3542 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3543 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
3544 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3545 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
3546 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3547 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
3548 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3549 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
3550 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3551 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
3552 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3553 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
3554 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3556 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
3557 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
3558 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
3559 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
3560 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
3562 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3563 (VPMOVDBkrr VK16WM:$mask, VR512:$src)>;
3564 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3565 (VPMOVDWkrr VK16WM:$mask, VR512:$src)>;
3566 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3567 (VPMOVQWkrr VK8WM:$mask, VR512:$src)>;
3568 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3569 (VPMOVQDkrr VK8WM:$mask, VR512:$src)>;
3572 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass DstRC,
3573 RegisterClass SrcRC, SDNode OpNode, PatFrag mem_frag,
3574 X86MemOperand x86memop, ValueType OpVT, ValueType InVT> {
3576 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
3578 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3579 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
3580 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
3581 (ins x86memop:$src),
3582 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
3584 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
3588 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VR512, VR128X, X86vzext,
3589 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3591 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VR512, VR128X, X86vzext,
3592 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3594 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VR512, VR256X, X86vzext,
3595 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3596 EVEX_CD8<16, CD8VH>;
3597 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VR512, VR128X, X86vzext,
3598 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3599 EVEX_CD8<16, CD8VQ>;
3600 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VR512, VR256X, X86vzext,
3601 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3602 EVEX_CD8<32, CD8VH>;
3604 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VR512, VR128X, X86vsext,
3605 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3607 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VR512, VR128X, X86vsext,
3608 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3610 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VR512, VR256X, X86vsext,
3611 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3612 EVEX_CD8<16, CD8VH>;
3613 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VR512, VR128X, X86vsext,
3614 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3615 EVEX_CD8<16, CD8VQ>;
3616 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VR512, VR256X, X86vsext,
3617 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3618 EVEX_CD8<32, CD8VH>;
3620 //===----------------------------------------------------------------------===//
3621 // GATHER - SCATTER Operations
3623 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3624 RegisterClass RC, X86MemOperand memop> {
3626 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
3627 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
3628 (ins RC:$src1, KRC:$mask, memop:$src2),
3629 !strconcat(OpcodeStr,
3630 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3633 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
3634 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3635 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
3636 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3638 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
3639 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3640 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
3641 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3643 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
3644 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3645 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
3646 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3648 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
3649 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3650 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
3651 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3653 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3654 RegisterClass RC, X86MemOperand memop> {
3655 let mayStore = 1, Constraints = "$mask = $mask_wb" in
3656 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
3657 (ins memop:$dst, KRC:$mask, RC:$src2),
3658 !strconcat(OpcodeStr,
3659 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3663 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
3664 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3665 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
3666 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3668 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
3669 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3670 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
3671 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3673 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
3674 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3675 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
3676 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3678 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
3679 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3680 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
3681 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3683 //===----------------------------------------------------------------------===//
3684 // VSHUFPS - VSHUFPD Operations
3686 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
3687 ValueType vt, string OpcodeStr, PatFrag mem_frag,
3689 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
3690 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3691 !strconcat(OpcodeStr,
3692 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3693 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
3694 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3695 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
3696 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
3697 (ins RC:$src1, RC:$src2, i8imm:$src3),
3698 !strconcat(OpcodeStr,
3699 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3700 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
3701 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3702 EVEX_4V, Sched<[WriteShuffle]>;
3705 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
3706 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3707 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
3708 SSEPackedDouble>, OpSize, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3710 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3711 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3712 def : Pat<(v16i32 (X86Shufp VR512:$src1,
3713 (memopv16i32 addr:$src2), (i8 imm:$imm))),
3714 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3716 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3717 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3718 def : Pat<(v8i64 (X86Shufp VR512:$src1,
3719 (memopv8i64 addr:$src2), (i8 imm:$imm))),
3720 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3722 multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
3723 X86MemOperand x86memop> {
3724 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
3725 (ins RC:$src1, RC:$src2, i8imm:$src3),
3726 !strconcat(OpcodeStr,
3727 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3730 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
3731 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3732 !strconcat(OpcodeStr,
3733 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3736 defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
3737 EVEX_V512, EVEX_CD8<32, CD8VF>;
3738 defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
3739 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3741 def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3742 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3743 def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3744 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3745 def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3746 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3747 def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3748 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3750 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, RegisterClass RC,
3751 X86MemOperand x86memop> {
3752 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3753 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3755 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
3756 (ins x86memop:$src),
3757 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3761 defm VPABSD : avx512_vpabs<0x1E, "vpabsd", VR512, i512mem>, EVEX_V512,
3762 EVEX_CD8<32, CD8VF>;
3763 defm VPABSQ : avx512_vpabs<0x1F, "vpabsq", VR512, i512mem>, EVEX_V512, VEX_W,
3764 EVEX_CD8<64, CD8VF>;
3766 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
3767 RegisterClass RC, RegisterClass KRC,
3768 X86MemOperand x86memop,
3769 X86MemOperand x86scalar_mop, string BrdcstStr> {
3770 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3772 !strconcat(OpcodeStr, "\t{$src, ${dst} |${dst}, $src}"),
3774 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3775 (ins x86memop:$src),
3776 !strconcat(OpcodeStr, "\t{$src, ${dst}|${dst}, $src}"),
3778 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3779 (ins x86scalar_mop:$src),
3780 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
3781 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
3783 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3784 (ins KRC:$mask, RC:$src),
3785 !strconcat(OpcodeStr,
3786 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3788 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3789 (ins KRC:$mask, x86memop:$src),
3790 !strconcat(OpcodeStr,
3791 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3793 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3794 (ins KRC:$mask, x86scalar_mop:$src),
3795 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
3796 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
3798 []>, EVEX, EVEX_KZ, EVEX_B;
3800 let Constraints = "$src1 = $dst" in {
3801 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3802 (ins RC:$src1, KRC:$mask, RC:$src2),
3803 !strconcat(OpcodeStr,
3804 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3806 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3807 (ins RC:$src1, KRC:$mask, x86memop:$src2),
3808 !strconcat(OpcodeStr,
3809 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3811 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3812 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
3813 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
3814 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
3815 []>, EVEX, EVEX_K, EVEX_B;
3819 let Predicates = [HasCDI] in {
3820 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
3821 i512mem, i32mem, "{1to16}">,
3822 EVEX_V512, EVEX_CD8<32, CD8VF>;
3825 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
3826 i512mem, i64mem, "{1to8}">,
3827 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3831 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
3833 (VPCONFLICTDrrk VR512:$src1,
3834 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
3836 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
3838 (VPCONFLICTQrrk VR512:$src1,
3839 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;