1 // Bitcasts between 512-bit vector types. Return the original type since
2 // no instruction is needed for the conversion
3 let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
49 // Bitcasts between 256-bit vector types. Return the original type since
50 // no instruction is needed for the conversion
51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
84 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
87 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
88 isPseudo = 1, Predicates = [HasAVX512] in {
89 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
90 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
93 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
94 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
95 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
96 def : Pat<(v16f32 immAllZerosV), (AVX512_512_SET0)>;
98 //===----------------------------------------------------------------------===//
99 // AVX-512 - VECTOR INSERT
102 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
103 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
104 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
105 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
106 []>, EVEX_4V, EVEX_V512;
108 def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
109 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
110 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
111 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
114 // -- 64x4 fp form --
115 let neverHasSideEffects = 1, ExeDomain = SSEPackedDouble in {
116 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
117 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
118 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
119 []>, EVEX_4V, EVEX_V512, VEX_W;
121 def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
122 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
123 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
124 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
126 // -- 32x4 integer form --
127 let neverHasSideEffects = 1 in {
128 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
129 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
130 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
131 []>, EVEX_4V, EVEX_V512;
133 def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
134 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
135 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
136 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
140 let neverHasSideEffects = 1 in {
142 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
143 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
144 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
145 []>, EVEX_4V, EVEX_V512, VEX_W;
147 def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
148 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
149 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
150 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
153 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
154 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
155 (INSERT_get_vinsert128_imm VR512:$ins))>;
156 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
157 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
158 (INSERT_get_vinsert128_imm VR512:$ins))>;
159 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
160 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
161 (INSERT_get_vinsert128_imm VR512:$ins))>;
162 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
163 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
164 (INSERT_get_vinsert128_imm VR512:$ins))>;
166 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
167 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
168 (INSERT_get_vinsert128_imm VR512:$ins))>;
169 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
170 (bc_v4i32 (loadv2i64 addr:$src2)),
171 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
172 (INSERT_get_vinsert128_imm VR512:$ins))>;
173 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
174 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
175 (INSERT_get_vinsert128_imm VR512:$ins))>;
176 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
177 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
178 (INSERT_get_vinsert128_imm VR512:$ins))>;
180 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
181 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
182 (INSERT_get_vinsert256_imm VR512:$ins))>;
183 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
184 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
185 (INSERT_get_vinsert256_imm VR512:$ins))>;
186 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
187 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
188 (INSERT_get_vinsert256_imm VR512:$ins))>;
189 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
190 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
191 (INSERT_get_vinsert256_imm VR512:$ins))>;
193 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
194 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
195 (INSERT_get_vinsert256_imm VR512:$ins))>;
196 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
197 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
198 (INSERT_get_vinsert256_imm VR512:$ins))>;
199 def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
200 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
201 (INSERT_get_vinsert256_imm VR512:$ins))>;
202 def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
203 (bc_v8i32 (loadv4i64 addr:$src2)),
204 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
205 (INSERT_get_vinsert256_imm VR512:$ins))>;
207 // vinsertps - insert f32 to XMM
208 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
209 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
210 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
211 [(set VR128X:$dst, (X86insrtps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
213 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
214 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
215 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
216 [(set VR128X:$dst, (X86insrtps VR128X:$src1,
217 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
218 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
220 //===----------------------------------------------------------------------===//
221 // AVX-512 VECTOR EXTRACT
223 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
225 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
226 (ins VR512:$src1, i8imm:$src2),
227 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
228 []>, EVEX, EVEX_V512;
229 def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
230 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
231 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
232 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
235 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
236 (ins VR512:$src1, i8imm:$src2),
237 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
238 []>, EVEX, EVEX_V512, VEX_W;
240 def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
241 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
242 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
243 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
246 let neverHasSideEffects = 1 in {
248 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
249 (ins VR512:$src1, i8imm:$src2),
250 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
251 []>, EVEX, EVEX_V512;
252 def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
253 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
254 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
255 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
258 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
259 (ins VR512:$src1, i8imm:$src2),
260 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
261 []>, EVEX, EVEX_V512, VEX_W;
263 def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
264 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
265 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
266 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
269 def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
270 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
271 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
273 def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
274 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
275 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
277 def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
278 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
279 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
281 def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
282 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
283 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
286 def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
287 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
288 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
290 def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
291 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
292 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
294 def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
295 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
296 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
298 def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
299 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
300 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
302 // A 256-bit subvector extract from the first 512-bit vector position
303 // is a subregister copy that needs no instruction.
304 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
305 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
306 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
307 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
308 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
309 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
310 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
311 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
314 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
315 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
316 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
317 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
318 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
319 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
320 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
321 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
324 // A 128-bit subvector insert to the first 512-bit vector position
325 // is a subregister copy that needs no instruction.
326 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
327 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
328 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
330 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
331 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
332 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
334 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
335 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
336 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
338 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
339 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
340 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
343 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
344 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
345 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
346 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
347 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
348 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
349 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
350 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
352 // vextractps - extract 32 bits from XMM
353 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
354 (ins VR128X:$src1, u32u8imm:$src2),
355 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
356 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
359 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
360 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
361 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
362 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
365 //===---------------------------------------------------------------------===//
368 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
369 RegisterClass DestRC,
370 RegisterClass SrcRC, X86MemOperand x86memop> {
371 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
372 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
374 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
375 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),[]>, EVEX;
377 let ExeDomain = SSEPackedSingle in {
378 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
380 EVEX_V512, EVEX_CD8<32, CD8VT1>;
383 let ExeDomain = SSEPackedDouble in {
384 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
386 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
389 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
390 (VBROADCASTSSZrm addr:$src)>;
391 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
392 (VBROADCASTSDZrm addr:$src)>;
394 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
395 (VBROADCASTSSZrm addr:$src)>;
396 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
397 (VBROADCASTSDZrm addr:$src)>;
399 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
400 RegisterClass SrcRC, RegisterClass KRC> {
401 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
402 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
403 []>, EVEX, EVEX_V512;
404 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
405 (ins KRC:$mask, SrcRC:$src),
406 !strconcat(OpcodeStr,
407 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
408 []>, EVEX, EVEX_V512, EVEX_KZ;
411 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
412 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
415 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
416 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
418 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
419 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
421 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
422 (VPBROADCASTDrZrr GR32:$src)>;
423 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
424 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
425 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
426 (VPBROADCASTQrZrr GR64:$src)>;
427 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
428 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
430 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
431 (VPBROADCASTDrZrr GR32:$src)>;
432 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
433 (VPBROADCASTQrZrr GR64:$src)>;
435 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
436 X86MemOperand x86memop, PatFrag ld_frag,
437 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
439 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
440 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
442 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
443 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
445 !strconcat(OpcodeStr,
446 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
448 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
451 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
452 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
454 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
455 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
457 !strconcat(OpcodeStr,
458 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
459 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
460 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
464 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
465 loadi32, VR512, v16i32, v4i32, VK16WM>,
466 EVEX_V512, EVEX_CD8<32, CD8VT1>;
467 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
468 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
469 EVEX_CD8<64, CD8VT1>;
471 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
472 (VPBROADCASTDZrr VR128X:$src)>;
473 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
474 (VPBROADCASTQZrr VR128X:$src)>;
476 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
477 (VBROADCASTSSZrr VR128X:$src)>;
478 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
479 (VBROADCASTSDZrr VR128X:$src)>;
481 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
482 (VBROADCASTSSZrr VR128X:$src)>;
483 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
484 (VBROADCASTSDZrr VR128X:$src)>;
486 // Provide fallback in case the load node that is used in the patterns above
487 // is used by additional users, which prevents the pattern selection.
488 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
489 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
490 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
491 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
494 let Predicates = [HasAVX512] in {
495 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
497 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
498 addr:$src)), sub_ymm)>;
500 //===----------------------------------------------------------------------===//
501 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
504 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
505 RegisterClass DstRC, RegisterClass KRC,
506 ValueType OpVT, ValueType SrcVT> {
507 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
508 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
512 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
513 VK16, v16i32, v16i1>, EVEX_V512;
514 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
515 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
517 //===----------------------------------------------------------------------===//
520 // -- immediate form --
521 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
522 SDNode OpNode, PatFrag mem_frag,
523 X86MemOperand x86memop, ValueType OpVT> {
524 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
525 (ins RC:$src1, i8imm:$src2),
526 !strconcat(OpcodeStr,
527 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
529 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
531 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
532 (ins x86memop:$src1, i8imm:$src2),
533 !strconcat(OpcodeStr,
534 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
536 (OpVT (OpNode (mem_frag addr:$src1),
537 (i8 imm:$src2))))]>, EVEX;
540 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
541 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
542 let ExeDomain = SSEPackedDouble in
543 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
544 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
546 // -- VPERM - register form --
547 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
548 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
550 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
551 (ins RC:$src1, RC:$src2),
552 !strconcat(OpcodeStr,
553 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
555 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
557 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
558 (ins RC:$src1, x86memop:$src2),
559 !strconcat(OpcodeStr,
560 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
562 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
566 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
567 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
568 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
569 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
570 let ExeDomain = SSEPackedSingle in
571 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
572 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
573 let ExeDomain = SSEPackedDouble in
574 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
575 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
577 // -- VPERM2I - 3 source operands form --
578 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
579 PatFrag mem_frag, X86MemOperand x86memop,
581 let Constraints = "$src1 = $dst" in {
582 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
583 (ins RC:$src1, RC:$src2, RC:$src3),
584 !strconcat(OpcodeStr,
585 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
587 (OpVT (X86VPermv3 RC:$src1, RC:$src2, RC:$src3)))]>,
590 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
591 (ins RC:$src1, RC:$src2, x86memop:$src3),
592 !strconcat(OpcodeStr,
593 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
595 (OpVT (X86VPermv3 RC:$src1, RC:$src2,
596 (mem_frag addr:$src3))))]>, EVEX_4V;
599 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem,
600 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
601 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem,
602 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
603 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem,
604 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
605 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
606 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
608 //===----------------------------------------------------------------------===//
609 // AVX-512 - BLEND using mask
611 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, Intrinsic Int,
612 RegisterClass KRC, RegisterClass RC,
613 X86MemOperand x86memop, PatFrag mem_frag,
614 SDNode OpNode, ValueType vt> {
615 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
616 (ins KRC:$mask, RC:$src1, RC:$src2),
617 !strconcat(OpcodeStr,
618 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
619 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
620 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
621 def rr_Int : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
622 (ins KRC:$mask, RC:$src1, RC:$src2),
623 !strconcat(OpcodeStr,
624 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
625 [(set RC:$dst, (Int KRC:$mask, (vt RC:$src2),
626 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
629 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
630 (ins KRC:$mask, RC:$src1, x86memop:$src2),
631 !strconcat(OpcodeStr,
632 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
636 def rm_Int : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
637 (ins KRC:$mask, RC:$src1, x86memop:$src2),
638 !strconcat(OpcodeStr,
639 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
640 [(set RC:$dst, (Int KRC:$mask, (vt RC:$src1),
641 (mem_frag addr:$src2)))]>,
646 let ExeDomain = SSEPackedSingle in
647 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
648 int_x86_avx512_mask_blend_ps_512,
649 VK16WM, VR512, f512mem,
650 memopv16f32, vselect, v16f32>,
651 EVEX_CD8<32, CD8VF>, EVEX_V512;
652 let ExeDomain = SSEPackedDouble in
653 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
654 int_x86_avx512_mask_blend_pd_512,
655 VK8WM, VR512, f512mem,
656 memopv8f64, vselect, v8f64>,
657 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
659 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
660 int_x86_avx512_mask_blend_d_512,
661 VK16WM, VR512, f512mem,
662 memopv16i32, vselect, v16i32>,
663 EVEX_CD8<32, CD8VF>, EVEX_V512;
665 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
666 int_x86_avx512_mask_blend_q_512,
667 VK8WM, VR512, f512mem,
668 memopv8i64, vselect, v8i64>,
669 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
671 let Predicates = [HasAVX512] in {
672 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
673 (v8f32 VR256X:$src2))),
675 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
676 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
677 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
679 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
680 (v8i32 VR256X:$src2))),
682 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
683 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
684 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
686 //===----------------------------------------------------------------------===//
687 // Compare Instructions
688 //===----------------------------------------------------------------------===//
690 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
691 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
692 Operand CC, SDNode OpNode, ValueType VT,
693 PatFrag ld_frag, string asm, string asm_alt> {
694 def rr : AVX512Ii8<0xC2, MRMSrcReg,
695 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
696 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
697 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
698 def rm : AVX512Ii8<0xC2, MRMSrcMem,
699 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
700 [(set VK1:$dst, (OpNode (VT RC:$src1),
701 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
702 let neverHasSideEffects = 1 in {
703 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
704 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
705 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
706 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
707 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
708 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
712 let Predicates = [HasAVX512] in {
713 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
714 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
715 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
717 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
718 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
719 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
723 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
724 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
725 SDNode OpNode, ValueType vt> {
726 def rr : AVX512BI<opc, MRMSrcReg,
727 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
728 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
729 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
730 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
731 def rm : AVX512BI<opc, MRMSrcMem,
732 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
733 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
734 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
735 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
738 defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
739 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512;
740 defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
741 memopv8i64, X86pcmpeqm, v8i64>, T8, EVEX_V512, VEX_W;
743 defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
744 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512;
745 defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
746 memopv8i64, X86pcmpgtm, v8i64>, T8, EVEX_V512, VEX_W;
748 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
749 (COPY_TO_REGCLASS (VPCMPGTDZrr
750 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
751 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
753 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
754 (COPY_TO_REGCLASS (VPCMPEQDZrr
755 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
756 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
758 multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
759 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
760 SDNode OpNode, ValueType vt, Operand CC, string asm,
762 def rri : AVX512AIi8<opc, MRMSrcReg,
763 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
764 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
765 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
766 def rmi : AVX512AIi8<opc, MRMSrcMem,
767 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
768 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
769 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
770 // Accept explicit immediate argument form instead of comparison code.
771 let neverHasSideEffects = 1 in {
772 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
773 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
774 asm_alt, [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
775 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
776 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
777 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
781 defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv16i32,
782 X86cmpm, v16i32, AVXCC,
783 "vpcmp${cc}d\t{$src2, $src1, $dst|$dst, $src1, $src2}",
784 "vpcmpd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
785 EVEX_V512, EVEX_CD8<32, CD8VF>;
786 defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv16i32,
787 X86cmpmu, v16i32, AVXCC,
788 "vpcmp${cc}ud\t{$src2, $src1, $dst|$dst, $src1, $src2}",
789 "vpcmpud\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
790 EVEX_V512, EVEX_CD8<32, CD8VF>;
792 defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64,
793 X86cmpm, v8i64, AVXCC,
794 "vpcmp${cc}q\t{$src2, $src1, $dst|$dst, $src1, $src2}",
795 "vpcmpq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
796 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
797 defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64,
798 X86cmpmu, v8i64, AVXCC,
799 "vpcmp${cc}uq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
800 "vpcmpuq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
801 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
803 // avx512_cmp_packed - sse 1 & 2 compare packed instructions
804 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
805 X86MemOperand x86memop, ValueType vt,
806 string suffix, Domain d> {
807 def rri : AVX512PIi8<0xC2, MRMSrcReg,
808 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
809 !strconcat("vcmp${cc}", suffix,
810 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
811 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
812 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
813 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc, i32imm:$sae),
814 !strconcat("vcmp${cc}", suffix,
815 "\t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
817 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
818 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
819 !strconcat("vcmp", suffix,
820 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
822 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
824 // Accept explicit immediate argument form instead of comparison code.
825 let neverHasSideEffects = 1 in {
826 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
827 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
828 !strconcat("vcmp", suffix,
829 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
830 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
831 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
832 !strconcat("vcmp", suffix,
833 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
837 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
838 "ps", SSEPackedSingle>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VF>;
839 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
840 "pd", SSEPackedDouble>, OpSize, EVEX_4V, VEX_W, EVEX_V512,
843 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
844 (COPY_TO_REGCLASS (VCMPPSZrri
845 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
846 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
848 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
849 (COPY_TO_REGCLASS (VPCMPDZrri
850 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
851 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
853 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
854 (COPY_TO_REGCLASS (VPCMPUDZrri
855 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
856 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
859 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
860 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
862 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
863 (I8Imm imm:$cc), (i32 0)), GR16)>;
865 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
866 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
868 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
869 (I8Imm imm:$cc), (i32 0)), GR8)>;
871 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
872 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
874 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
875 (I8Imm imm:$cc)), GR16)>;
877 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
878 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
880 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
881 (I8Imm imm:$cc)), GR8)>;
883 // Mask register copy, including
884 // - copy between mask registers
885 // - load/store mask registers
886 // - copy from GPR to mask register and vice versa
888 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
889 string OpcodeStr, RegisterClass KRC,
890 ValueType vt, X86MemOperand x86memop> {
891 let neverHasSideEffects = 1 in {
892 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
893 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
895 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
896 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
897 [(set KRC:$dst, (vt (load addr:$src)))]>;
899 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
900 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
904 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
906 RegisterClass KRC, RegisterClass GRC> {
907 let neverHasSideEffects = 1 in {
908 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
909 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
910 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
911 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
915 let Predicates = [HasAVX512] in {
916 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
918 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
922 let Predicates = [HasAVX512] in {
923 // GR16 from/to 16-bit mask
924 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
925 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
926 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
927 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
929 // Store kreg in memory
930 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
931 (KMOVWmk addr:$dst, VK16:$src)>;
933 def : Pat<(store VK8:$src, addr:$dst),
934 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
936 def : Pat<(i1 (load addr:$src)),
937 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
939 def : Pat<(v8i1 (load addr:$src)),
940 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
942 def : Pat<(i1 (trunc (i32 GR32:$src))),
943 (COPY_TO_REGCLASS (KMOVWkr $src), VK1)>;
945 def : Pat<(i1 (trunc (i8 GR8:$src))),
947 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)), VK1)>;
949 def : Pat<(i32 (zext VK1:$src)), (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16))>;
950 def : Pat<(i8 (zext VK1:$src)),
952 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_8bit)>;
954 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
955 let Predicates = [HasAVX512] in {
956 // GR from/to 8-bit mask without native support
957 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
959 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
961 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
963 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
966 def : Pat<(i1 (extractelt VK16:$src, (iPTR 0))),
967 (COPY_TO_REGCLASS VK16:$src, VK1)>;
968 def : Pat<(i1 (extractelt VK8:$src, (iPTR 0))),
969 (COPY_TO_REGCLASS VK8:$src, VK1)>;
973 // Mask unary operation
975 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
976 RegisterClass KRC, SDPatternOperator OpNode> {
977 let Predicates = [HasAVX512] in
978 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
979 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
980 [(set KRC:$dst, (OpNode KRC:$src))]>;
983 multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
984 SDPatternOperator OpNode> {
985 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
989 defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
991 multiclass avx512_mask_unop_int<string IntName, string InstName> {
992 let Predicates = [HasAVX512] in
993 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
995 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
996 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
998 defm : avx512_mask_unop_int<"knot", "KNOT">;
1000 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1001 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1002 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1004 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1005 def : Pat<(not VK8:$src),
1007 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1009 // Mask binary operation
1010 // - KAND, KANDN, KOR, KXNOR, KXOR
1011 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1012 RegisterClass KRC, SDPatternOperator OpNode> {
1013 let Predicates = [HasAVX512] in
1014 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1015 !strconcat(OpcodeStr,
1016 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1017 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1020 multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
1021 SDPatternOperator OpNode> {
1022 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1026 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1027 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1029 let isCommutable = 1 in {
1030 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
1031 let isCommutable = 0 in
1032 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
1033 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
1034 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
1035 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
1038 def : Pat<(xor VK1:$src1, VK1:$src2),
1039 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1040 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1042 def : Pat<(or VK1:$src1, VK1:$src2),
1043 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1044 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1046 def : Pat<(not VK1:$src),
1047 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src, VK16),
1048 (COPY_TO_REGCLASS (VCMPSSZrr (f32 (IMPLICIT_DEF)),
1049 (f32 (IMPLICIT_DEF)), (i8 0)), VK16)), VK1)>;
1051 def : Pat<(and VK1:$src1, VK1:$src2),
1052 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1053 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1055 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1056 let Predicates = [HasAVX512] in
1057 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1058 (i16 GR16:$src1), (i16 GR16:$src2)),
1059 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1060 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1061 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1064 defm : avx512_mask_binop_int<"kand", "KAND">;
1065 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1066 defm : avx512_mask_binop_int<"kor", "KOR">;
1067 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1068 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1070 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1071 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1072 let Predicates = [HasAVX512] in
1073 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1075 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1076 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1079 defm : avx512_binop_pat<and, KANDWrr>;
1080 defm : avx512_binop_pat<andn, KANDNWrr>;
1081 defm : avx512_binop_pat<or, KORWrr>;
1082 defm : avx512_binop_pat<xnor, KXNORWrr>;
1083 defm : avx512_binop_pat<xor, KXORWrr>;
1086 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1087 RegisterClass KRC> {
1088 let Predicates = [HasAVX512] in
1089 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1090 !strconcat(OpcodeStr,
1091 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1094 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1095 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1096 VEX_4V, VEX_L, OpSize, TB;
1099 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1100 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1101 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1102 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1105 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1106 let Predicates = [HasAVX512] in
1107 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1108 (i16 GR16:$src1), (i16 GR16:$src2)),
1109 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1110 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1111 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1113 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1116 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1118 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1119 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1120 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1121 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1124 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1125 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1129 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1131 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1132 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1133 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1136 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1138 let Predicates = [HasAVX512] in
1139 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1140 !strconcat(OpcodeStr,
1141 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
1142 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1145 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1147 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1148 VEX, OpSize, TA, VEX_W;
1151 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1152 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1154 // Mask setting all 0s or 1s
1155 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1156 let Predicates = [HasAVX512] in
1157 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1158 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1159 [(set KRC:$dst, (VT Val))]>;
1162 multiclass avx512_mask_setop_w<PatFrag Val> {
1163 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1164 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1167 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1168 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1170 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1171 let Predicates = [HasAVX512] in {
1172 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1173 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1175 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1176 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1178 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1179 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1181 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1182 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1184 //===----------------------------------------------------------------------===//
1185 // AVX-512 - Aligned and unaligned load and store
1188 multiclass avx512_mov_packed<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1189 X86MemOperand x86memop, PatFrag ld_frag,
1190 string asm, Domain d> {
1191 let neverHasSideEffects = 1 in
1192 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1193 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>,
1195 let canFoldAsLoad = 1 in
1196 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1197 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1198 [(set RC:$dst, (ld_frag addr:$src))], d>, EVEX;
1199 let Constraints = "$src1 = $dst" in {
1200 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1201 (ins RC:$src1, KRC:$mask, RC:$src2),
1203 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1205 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1206 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1208 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1209 [], d>, EVEX, EVEX_K;
1213 defm VMOVAPSZ : avx512_mov_packed<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1214 "vmovaps", SSEPackedSingle>,
1215 EVEX_V512, EVEX_CD8<32, CD8VF>;
1216 defm VMOVAPDZ : avx512_mov_packed<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1217 "vmovapd", SSEPackedDouble>,
1218 OpSize, EVEX_V512, VEX_W,
1219 EVEX_CD8<64, CD8VF>;
1220 defm VMOVUPSZ : avx512_mov_packed<0x10, VR512, VK16WM, f512mem, loadv16f32,
1221 "vmovups", SSEPackedSingle>,
1222 EVEX_V512, EVEX_CD8<32, CD8VF>;
1223 defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64,
1224 "vmovupd", SSEPackedDouble>,
1225 OpSize, EVEX_V512, VEX_W,
1226 EVEX_CD8<64, CD8VF>;
1227 def VMOVAPSZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1228 "vmovaps\t{$src, $dst|$dst, $src}",
1229 [(alignedstore512 (v16f32 VR512:$src), addr:$dst)],
1230 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1231 def VMOVAPDZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1232 "vmovapd\t{$src, $dst|$dst, $src}",
1233 [(alignedstore512 (v8f64 VR512:$src), addr:$dst)],
1234 SSEPackedDouble>, EVEX, EVEX_V512,
1235 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1236 def VMOVUPSZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1237 "vmovups\t{$src, $dst|$dst, $src}",
1238 [(store (v16f32 VR512:$src), addr:$dst)],
1239 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1240 def VMOVUPDZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1241 "vmovupd\t{$src, $dst|$dst, $src}",
1242 [(store (v8f64 VR512:$src), addr:$dst)],
1243 SSEPackedDouble>, EVEX, EVEX_V512,
1244 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1246 let neverHasSideEffects = 1 in {
1247 def VMOVDQA32rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1249 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1251 def VMOVDQA64rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1253 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1254 EVEX, EVEX_V512, VEX_W;
1255 let mayStore = 1 in {
1256 def VMOVDQA32mr : AVX512BI<0x7F, MRMDestMem, (outs),
1257 (ins i512mem:$dst, VR512:$src),
1258 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1259 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1260 def VMOVDQA64mr : AVX512BI<0x7F, MRMDestMem, (outs),
1261 (ins i512mem:$dst, VR512:$src),
1262 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1263 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1265 let mayLoad = 1 in {
1266 def VMOVDQA32rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1268 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1269 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1270 def VMOVDQA64rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1272 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1273 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1277 // 512-bit aligned load/store
1278 def : Pat<(alignedloadv8i64 addr:$src), (VMOVDQA64rm addr:$src)>;
1279 def : Pat<(alignedloadv16i32 addr:$src), (VMOVDQA32rm addr:$src)>;
1281 def : Pat<(alignedstore512 (v8i64 VR512:$src), addr:$dst),
1282 (VMOVDQA64mr addr:$dst, VR512:$src)>;
1283 def : Pat<(alignedstore512 (v16i32 VR512:$src), addr:$dst),
1284 (VMOVDQA32mr addr:$dst, VR512:$src)>;
1286 multiclass avx512_mov_int<bits<8> load_opc, bits<8> store_opc, string asm,
1287 RegisterClass RC, RegisterClass KRC,
1288 PatFrag ld_frag, X86MemOperand x86memop> {
1289 let neverHasSideEffects = 1 in
1290 def rr : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1291 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>, EVEX;
1292 let canFoldAsLoad = 1 in
1293 def rm : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1294 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1295 [(set RC:$dst, (ld_frag addr:$src))]>, EVEX;
1297 def mr : AVX512XSI<store_opc, MRMDestMem, (outs),
1298 (ins x86memop:$dst, VR512:$src),
1299 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>, EVEX;
1300 let Constraints = "$src1 = $dst" in {
1301 def rrk : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst),
1302 (ins RC:$src1, KRC:$mask, RC:$src2),
1304 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), []>,
1306 def rmk : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst),
1307 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1309 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1314 defm VMOVDQU32 : avx512_mov_int<0x6F, 0x7F, "vmovdqu32", VR512, VK16WM,
1315 memopv16i32, i512mem>,
1316 EVEX_V512, EVEX_CD8<32, CD8VF>;
1317 defm VMOVDQU64 : avx512_mov_int<0x6F, 0x7F, "vmovdqu64", VR512, VK8WM,
1318 memopv8i64, i512mem>,
1319 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1321 // 512-bit unaligned load/store
1322 def : Pat<(loadv8i64 addr:$src), (VMOVDQU64rm addr:$src)>;
1323 def : Pat<(loadv16i32 addr:$src), (VMOVDQU32rm addr:$src)>;
1325 def : Pat<(store (v8i64 VR512:$src), addr:$dst),
1326 (VMOVDQU64mr addr:$dst, VR512:$src)>;
1327 def : Pat<(store (v16i32 VR512:$src), addr:$dst),
1328 (VMOVDQU32mr addr:$dst, VR512:$src)>;
1330 let AddedComplexity = 20 in {
1331 def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1332 (v16f32 VR512:$src2))),
1333 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1334 def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1335 (v8f64 VR512:$src2))),
1336 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1337 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1338 (v16i32 VR512:$src2))),
1339 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1340 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1341 (v8i64 VR512:$src2))),
1342 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1344 // Move Int Doubleword to Packed Double Int
1346 def VMOVDI2PDIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1347 "vmovd\t{$src, $dst|$dst, $src}",
1349 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1351 def VMOVDI2PDIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1352 "vmovd\t{$src, $dst|$dst, $src}",
1354 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1355 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1356 def VMOV64toPQIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1357 "vmovq\t{$src, $dst|$dst, $src}",
1359 (v2i64 (scalar_to_vector GR64:$src)))],
1360 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
1361 let isCodeGenOnly = 1 in {
1362 def VMOV64toSDZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1363 "vmovq\t{$src, $dst|$dst, $src}",
1364 [(set FR64:$dst, (bitconvert GR64:$src))],
1365 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1366 def VMOVSDto64Zrr : AVX512SI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1367 "vmovq\t{$src, $dst|$dst, $src}",
1368 [(set GR64:$dst, (bitconvert FR64:$src))],
1369 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1371 def VMOVSDto64Zmr : AVX512SI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1372 "vmovq\t{$src, $dst|$dst, $src}",
1373 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1374 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1375 EVEX_CD8<64, CD8VT1>;
1377 // Move Int Doubleword to Single Scalar
1379 let isCodeGenOnly = 1 in {
1380 def VMOVDI2SSZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1381 "vmovd\t{$src, $dst|$dst, $src}",
1382 [(set FR32X:$dst, (bitconvert GR32:$src))],
1383 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1385 def VMOVDI2SSZrm : AVX512SI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1386 "vmovd\t{$src, $dst|$dst, $src}",
1387 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1388 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1391 // Move Packed Doubleword Int to Packed Double Int
1393 def VMOVPDI2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1394 "vmovd\t{$src, $dst|$dst, $src}",
1395 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1396 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1398 def VMOVPDI2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1399 (ins i32mem:$dst, VR128X:$src),
1400 "vmovd\t{$src, $dst|$dst, $src}",
1401 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1402 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1403 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1405 // Move Packed Doubleword Int first element to Doubleword Int
1407 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1408 "vmovq\t{$src, $dst|$dst, $src}",
1409 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1411 IIC_SSE_MOVD_ToGP>, TB, OpSize, EVEX, VEX_LIG, VEX_W,
1412 Requires<[HasAVX512, In64BitMode]>;
1414 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
1415 (ins i64mem:$dst, VR128X:$src),
1416 "vmovq\t{$src, $dst|$dst, $src}",
1417 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1418 addr:$dst)], IIC_SSE_MOVDQ>,
1419 EVEX, OpSize, VEX_LIG, VEX_W, TB, EVEX_CD8<64, CD8VT1>,
1420 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1422 // Move Scalar Single to Double Int
1424 let isCodeGenOnly = 1 in {
1425 def VMOVSS2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst),
1427 "vmovd\t{$src, $dst|$dst, $src}",
1428 [(set GR32:$dst, (bitconvert FR32X:$src))],
1429 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1430 def VMOVSS2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1431 (ins i32mem:$dst, FR32X:$src),
1432 "vmovd\t{$src, $dst|$dst, $src}",
1433 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1434 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1437 // Move Quadword Int to Packed Quadword Int
1439 def VMOVQI2PQIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst),
1441 "vmovq\t{$src, $dst|$dst, $src}",
1443 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1444 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1446 //===----------------------------------------------------------------------===//
1447 // AVX-512 MOVSS, MOVSD
1448 //===----------------------------------------------------------------------===//
1450 multiclass avx512_move_scalar <string asm, RegisterClass RC,
1451 SDNode OpNode, ValueType vt,
1452 X86MemOperand x86memop, PatFrag mem_pat> {
1453 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1454 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1455 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1456 (scalar_to_vector RC:$src2))))],
1457 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1458 let Constraints = "$src1 = $dst" in
1459 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
1460 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
1462 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
1463 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
1464 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1465 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1466 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1468 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1469 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1470 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1474 let ExeDomain = SSEPackedSingle in
1475 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
1476 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1478 let ExeDomain = SSEPackedDouble in
1479 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
1480 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1482 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
1483 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
1484 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
1486 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
1487 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
1488 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
1490 // For the disassembler
1491 let isCodeGenOnly = 1 in {
1492 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1493 (ins VR128X:$src1, FR32X:$src2),
1494 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1496 XS, EVEX_4V, VEX_LIG;
1497 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1498 (ins VR128X:$src1, FR64X:$src2),
1499 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1501 XD, EVEX_4V, VEX_LIG, VEX_W;
1504 let Predicates = [HasAVX512] in {
1505 let AddedComplexity = 15 in {
1506 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1507 // MOVS{S,D} to the lower bits.
1508 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1509 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1510 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1511 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1512 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1513 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1514 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1515 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1517 // Move low f32 and clear high bits.
1518 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1519 (SUBREG_TO_REG (i32 0),
1520 (VMOVSSZrr (v4f32 (V_SET0)),
1521 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1522 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1523 (SUBREG_TO_REG (i32 0),
1524 (VMOVSSZrr (v4i32 (V_SET0)),
1525 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1528 let AddedComplexity = 20 in {
1529 // MOVSSrm zeros the high parts of the register; represent this
1530 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1531 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1532 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1533 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1534 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1535 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1536 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1538 // MOVSDrm zeros the high parts of the register; represent this
1539 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1540 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1541 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1542 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1543 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1544 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1545 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1546 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1547 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1548 def : Pat<(v2f64 (X86vzload addr:$src)),
1549 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1551 // Represent the same patterns above but in the form they appear for
1553 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1554 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
1555 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
1556 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1557 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1558 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1559 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1560 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1561 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1563 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1564 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1565 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1566 FR32X:$src)), sub_xmm)>;
1567 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1568 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1569 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1570 FR64X:$src)), sub_xmm)>;
1571 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1572 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
1573 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
1575 // Move low f64 and clear high bits.
1576 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1577 (SUBREG_TO_REG (i32 0),
1578 (VMOVSDZrr (v2f64 (V_SET0)),
1579 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1581 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1582 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1583 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1585 // Extract and store.
1586 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1588 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1589 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1591 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1593 // Shuffle with VMOVSS
1594 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1595 (VMOVSSZrr (v4i32 VR128X:$src1),
1596 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1597 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1598 (VMOVSSZrr (v4f32 VR128X:$src1),
1599 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1602 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1603 (SUBREG_TO_REG (i32 0),
1604 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1605 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1607 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1608 (SUBREG_TO_REG (i32 0),
1609 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1610 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1613 // Shuffle with VMOVSD
1614 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1615 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1616 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1617 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1618 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1619 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1620 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1621 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1624 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1625 (SUBREG_TO_REG (i32 0),
1626 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1627 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1629 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1630 (SUBREG_TO_REG (i32 0),
1631 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1632 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1635 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1636 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1637 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1638 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1639 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1640 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1641 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1642 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1645 let AddedComplexity = 15 in
1646 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1648 "vmovq\t{$src, $dst|$dst, $src}",
1649 [(set VR128X:$dst, (v2i64 (X86vzmovl
1650 (v2i64 VR128X:$src))))],
1651 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1653 let AddedComplexity = 20 in
1654 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1656 "vmovq\t{$src, $dst|$dst, $src}",
1657 [(set VR128X:$dst, (v2i64 (X86vzmovl
1658 (loadv2i64 addr:$src))))],
1659 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1660 EVEX_CD8<8, CD8VT8>;
1662 let Predicates = [HasAVX512] in {
1663 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1664 let AddedComplexity = 20 in {
1665 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1666 (VMOVDI2PDIZrm addr:$src)>;
1667 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
1668 (VMOV64toPQIZrr GR64:$src)>;
1669 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
1670 (VMOVDI2PDIZrr GR32:$src)>;
1672 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1673 (VMOVDI2PDIZrm addr:$src)>;
1674 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1675 (VMOVDI2PDIZrm addr:$src)>;
1676 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1677 (VMOVZPQILo2PQIZrm addr:$src)>;
1678 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1679 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1680 def : Pat<(v2i64 (X86vzload addr:$src)),
1681 (VMOVZPQILo2PQIZrm addr:$src)>;
1684 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1685 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1686 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1687 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1688 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1689 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1690 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1693 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
1694 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1696 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
1697 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1699 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
1700 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1702 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
1703 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1705 //===----------------------------------------------------------------------===//
1706 // AVX-512 - Integer arithmetic
1708 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1709 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1710 X86MemOperand x86memop, PatFrag scalar_mfrag,
1711 X86MemOperand x86scalar_mop, string BrdcstStr,
1712 OpndItins itins, bit IsCommutable = 0> {
1713 let isCommutable = IsCommutable in
1714 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1715 (ins RC:$src1, RC:$src2),
1716 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1717 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1719 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1720 (ins RC:$src1, x86memop:$src2),
1721 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1722 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
1724 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1725 (ins RC:$src1, x86scalar_mop:$src2),
1726 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1727 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1728 [(set RC:$dst, (OpNode RC:$src1,
1729 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1730 itins.rm>, EVEX_4V, EVEX_B;
1732 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr,
1733 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
1734 PatFrag memop_frag, X86MemOperand x86memop,
1736 bit IsCommutable = 0> {
1737 let isCommutable = IsCommutable in
1738 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1739 (ins RC:$src1, RC:$src2),
1740 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1741 []>, EVEX_4V, VEX_W;
1742 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1743 (ins RC:$src1, x86memop:$src2),
1744 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1745 []>, EVEX_4V, VEX_W;
1748 defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VR512, memopv16i32,
1749 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1750 EVEX_V512, EVEX_CD8<32, CD8VF>;
1752 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VR512, memopv16i32,
1753 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 0>,
1754 EVEX_V512, EVEX_CD8<32, CD8VF>;
1756 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VR512, memopv16i32,
1757 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1758 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1760 defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VR512, memopv8i64,
1761 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 1>,
1762 EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
1764 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VR512, memopv8i64,
1765 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1766 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1768 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32,
1769 VR512, memopv8i64, i512mem, SSE_INTALU_ITINS_P, 1>, T8,
1770 EVEX_V512, EVEX_CD8<64, CD8VF>;
1772 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32,
1773 VR512, memopv8i64, i512mem, SSE_INTMUL_ITINS_P, 1>, EVEX_V512,
1774 EVEX_CD8<64, CD8VF>;
1776 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
1777 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1779 defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VR512, memopv16i32,
1780 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1781 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1782 defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VR512, memopv8i64,
1783 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1784 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1786 defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VR512, memopv16i32,
1787 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1788 EVEX_V512, EVEX_CD8<32, CD8VF>;
1789 defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VR512, memopv8i64,
1790 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1791 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1793 defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VR512, memopv16i32,
1794 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1795 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1796 defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VR512, memopv8i64,
1797 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1798 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1800 defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VR512, memopv16i32,
1801 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1802 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1803 defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VR512, memopv8i64,
1804 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1805 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1807 //===----------------------------------------------------------------------===//
1808 // AVX-512 - Unpack Instructions
1809 //===----------------------------------------------------------------------===//
1811 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
1812 PatFrag mem_frag, RegisterClass RC,
1813 X86MemOperand x86memop, string asm,
1815 def rr : AVX512PI<opc, MRMSrcReg,
1816 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1818 (vt (OpNode RC:$src1, RC:$src2)))],
1820 def rm : AVX512PI<opc, MRMSrcMem,
1821 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1823 (vt (OpNode RC:$src1,
1824 (bitconvert (mem_frag addr:$src2)))))],
1828 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
1829 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1830 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1831 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
1832 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1833 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1834 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
1835 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1836 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1837 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
1838 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1839 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1841 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
1842 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1843 X86MemOperand x86memop> {
1844 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1845 (ins RC:$src1, RC:$src2),
1846 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1847 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1848 IIC_SSE_UNPCK>, EVEX_4V;
1849 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1850 (ins RC:$src1, x86memop:$src2),
1851 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1852 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
1853 (bitconvert (memop_frag addr:$src2)))))],
1854 IIC_SSE_UNPCK>, EVEX_4V;
1856 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
1857 VR512, memopv16i32, i512mem>, EVEX_V512,
1858 EVEX_CD8<32, CD8VF>;
1859 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
1860 VR512, memopv8i64, i512mem>, EVEX_V512,
1861 VEX_W, EVEX_CD8<64, CD8VF>;
1862 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
1863 VR512, memopv16i32, i512mem>, EVEX_V512,
1864 EVEX_CD8<32, CD8VF>;
1865 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
1866 VR512, memopv8i64, i512mem>, EVEX_V512,
1867 VEX_W, EVEX_CD8<64, CD8VF>;
1868 //===----------------------------------------------------------------------===//
1872 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
1873 SDNode OpNode, PatFrag mem_frag,
1874 X86MemOperand x86memop, ValueType OpVT> {
1875 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
1876 (ins RC:$src1, i8imm:$src2),
1877 !strconcat(OpcodeStr,
1878 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1880 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
1882 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
1883 (ins x86memop:$src1, i8imm:$src2),
1884 !strconcat(OpcodeStr,
1885 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1887 (OpVT (OpNode (mem_frag addr:$src1),
1888 (i8 imm:$src2))))]>, EVEX;
1891 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
1892 i512mem, v16i32>, OpSize, EVEX_V512, EVEX_CD8<32, CD8VF>;
1894 let ExeDomain = SSEPackedSingle in
1895 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
1896 memopv16f32, i512mem, v16f32>, OpSize, TA, EVEX_V512,
1897 EVEX_CD8<32, CD8VF>;
1898 let ExeDomain = SSEPackedDouble in
1899 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
1900 memopv8f64, i512mem, v8f64>, OpSize, TA, EVEX_V512,
1901 VEX_W, EVEX_CD8<32, CD8VF>;
1903 def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1904 (VPERMILPSZri VR512:$src1, imm:$imm)>;
1905 def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1906 (VPERMILPDZri VR512:$src1, imm:$imm)>;
1908 //===----------------------------------------------------------------------===//
1909 // AVX-512 Logical Instructions
1910 //===----------------------------------------------------------------------===//
1912 defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VR512, memopv16i32,
1913 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1914 EVEX_V512, EVEX_CD8<32, CD8VF>;
1915 defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VR512, memopv8i64,
1916 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1917 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1918 defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VR512, memopv16i32,
1919 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1920 EVEX_V512, EVEX_CD8<32, CD8VF>;
1921 defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VR512, memopv8i64,
1922 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1923 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1924 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VR512, memopv16i32,
1925 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1926 EVEX_V512, EVEX_CD8<32, CD8VF>;
1927 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VR512, memopv8i64,
1928 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1929 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1930 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VR512,
1931 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1932 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1933 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VR512, memopv8i64,
1934 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 0>,
1935 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1937 //===----------------------------------------------------------------------===//
1938 // AVX-512 FP arithmetic
1939 //===----------------------------------------------------------------------===//
1941 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1943 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
1944 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
1945 EVEX_CD8<32, CD8VT1>;
1946 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
1947 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
1948 EVEX_CD8<64, CD8VT1>;
1951 let isCommutable = 1 in {
1952 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
1953 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
1954 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
1955 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
1957 let isCommutable = 0 in {
1958 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
1959 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
1962 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1963 RegisterClass RC, ValueType vt,
1964 X86MemOperand x86memop, PatFrag mem_frag,
1965 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
1967 Domain d, OpndItins itins, bit commutable> {
1968 let isCommutable = commutable in
1969 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1970 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1971 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
1973 let mayLoad = 1 in {
1974 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1975 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1976 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
1977 itins.rm, d>, EVEX_4V, TB;
1978 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
1979 (ins RC:$src1, x86scalar_mop:$src2),
1980 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1981 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1982 [(set RC:$dst, (OpNode RC:$src1,
1983 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1984 itins.rm, d>, EVEX_4V, EVEX_B, TB;
1988 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VR512, v16f32, f512mem,
1989 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1990 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1992 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VR512, v8f64, f512mem,
1993 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1994 SSE_ALU_ITINS_P.d, 1>,
1995 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1997 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VR512, v16f32, f512mem,
1998 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1999 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2000 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VR512, v8f64, f512mem,
2001 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2002 SSE_ALU_ITINS_P.d, 1>,
2003 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
2005 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VR512, v16f32, f512mem,
2006 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2007 SSE_ALU_ITINS_P.s, 1>,
2008 EVEX_V512, EVEX_CD8<32, CD8VF>;
2009 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VR512, v16f32, f512mem,
2010 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2011 SSE_ALU_ITINS_P.s, 1>,
2012 EVEX_V512, EVEX_CD8<32, CD8VF>;
2014 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VR512, v8f64, f512mem,
2015 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2016 SSE_ALU_ITINS_P.d, 1>,
2017 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
2018 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VR512, v8f64, f512mem,
2019 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2020 SSE_ALU_ITINS_P.d, 1>,
2021 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
2023 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VR512, v16f32, f512mem,
2024 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2025 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2026 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VR512, v16f32, f512mem,
2027 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2028 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2030 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VR512, v8f64, f512mem,
2031 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2032 SSE_ALU_ITINS_P.d, 0>,
2033 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
2034 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VR512, v8f64, f512mem,
2035 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2036 SSE_ALU_ITINS_P.d, 0>,
2037 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
2039 //===----------------------------------------------------------------------===//
2040 // AVX-512 VPTESTM instructions
2041 //===----------------------------------------------------------------------===//
2043 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2044 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
2045 SDNode OpNode, ValueType vt> {
2046 def rr : AVX5128I<opc, MRMSrcReg,
2047 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
2048 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2049 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))]>, EVEX_4V;
2050 def rm : AVX5128I<opc, MRMSrcMem,
2051 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
2052 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2053 [(set KRC:$dst, (OpNode (vt RC:$src1),
2054 (bitconvert (memop_frag addr:$src2))))]>, EVEX_4V;
2057 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
2058 memopv16i32, X86testm, v16i32>, EVEX_V512,
2059 EVEX_CD8<32, CD8VF>;
2060 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
2061 memopv8i64, X86testm, v8i64>, EVEX_V512, VEX_W,
2062 EVEX_CD8<64, CD8VF>;
2064 //===----------------------------------------------------------------------===//
2065 // AVX-512 Shift instructions
2066 //===----------------------------------------------------------------------===//
2067 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
2068 string OpcodeStr, SDNode OpNode, RegisterClass RC,
2069 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
2070 RegisterClass KRC> {
2071 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2072 (ins RC:$src1, i8imm:$src2),
2073 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2074 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
2075 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2076 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2077 (ins KRC:$mask, RC:$src1, i8imm:$src2),
2078 !strconcat(OpcodeStr,
2079 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2080 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2081 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2082 (ins x86memop:$src1, i8imm:$src2),
2083 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2084 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
2085 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2086 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2087 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
2088 !strconcat(OpcodeStr,
2089 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2090 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2093 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2094 RegisterClass RC, ValueType vt, ValueType SrcVT,
2095 PatFrag bc_frag, RegisterClass KRC> {
2096 // src2 is always 128-bit
2097 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2098 (ins RC:$src1, VR128X:$src2),
2099 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2100 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
2101 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2102 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2103 (ins KRC:$mask, RC:$src1, VR128X:$src2),
2104 !strconcat(OpcodeStr,
2105 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2106 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2107 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2108 (ins RC:$src1, i128mem:$src2),
2109 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2110 [(set RC:$dst, (vt (OpNode RC:$src1,
2111 (bc_frag (memopv2i64 addr:$src2)))))],
2112 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2113 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2114 (ins KRC:$mask, RC:$src1, i128mem:$src2),
2115 !strconcat(OpcodeStr,
2116 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2117 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2120 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
2121 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2122 EVEX_V512, EVEX_CD8<32, CD8VF>;
2123 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
2124 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2125 EVEX_CD8<32, CD8VQ>;
2127 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
2128 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2129 EVEX_CD8<64, CD8VF>, VEX_W;
2130 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
2131 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2132 EVEX_CD8<64, CD8VQ>, VEX_W;
2134 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
2135 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
2136 EVEX_CD8<32, CD8VF>;
2137 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
2138 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2139 EVEX_CD8<32, CD8VQ>;
2141 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
2142 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2143 EVEX_CD8<64, CD8VF>, VEX_W;
2144 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
2145 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2146 EVEX_CD8<64, CD8VQ>, VEX_W;
2148 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
2149 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2150 EVEX_V512, EVEX_CD8<32, CD8VF>;
2151 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
2152 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2153 EVEX_CD8<32, CD8VQ>;
2155 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
2156 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2157 EVEX_CD8<64, CD8VF>, VEX_W;
2158 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
2159 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2160 EVEX_CD8<64, CD8VQ>, VEX_W;
2162 //===-------------------------------------------------------------------===//
2163 // Variable Bit Shifts
2164 //===-------------------------------------------------------------------===//
2165 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
2166 RegisterClass RC, ValueType vt,
2167 X86MemOperand x86memop, PatFrag mem_frag> {
2168 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
2169 (ins RC:$src1, RC:$src2),
2170 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2172 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
2174 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
2175 (ins RC:$src1, x86memop:$src2),
2176 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2178 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
2182 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
2183 i512mem, memopv16i32>, EVEX_V512,
2184 EVEX_CD8<32, CD8VF>;
2185 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
2186 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2187 EVEX_CD8<64, CD8VF>;
2188 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
2189 i512mem, memopv16i32>, EVEX_V512,
2190 EVEX_CD8<32, CD8VF>;
2191 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
2192 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2193 EVEX_CD8<64, CD8VF>;
2194 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
2195 i512mem, memopv16i32>, EVEX_V512,
2196 EVEX_CD8<32, CD8VF>;
2197 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
2198 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2199 EVEX_CD8<64, CD8VF>;
2201 //===----------------------------------------------------------------------===//
2202 // AVX-512 - MOVDDUP
2203 //===----------------------------------------------------------------------===//
2205 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
2206 X86MemOperand x86memop, PatFrag memop_frag> {
2207 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2208 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2209 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
2210 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2211 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2213 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
2216 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
2217 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
2218 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
2219 (VMOVDDUPZrm addr:$src)>;
2221 //===---------------------------------------------------------------------===//
2222 // Replicate Single FP - MOVSHDUP and MOVSLDUP
2223 //===---------------------------------------------------------------------===//
2224 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
2225 ValueType vt, RegisterClass RC, PatFrag mem_frag,
2226 X86MemOperand x86memop> {
2227 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2228 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2229 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
2231 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2232 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2233 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
2236 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
2237 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2238 EVEX_CD8<32, CD8VF>;
2239 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
2240 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2241 EVEX_CD8<32, CD8VF>;
2243 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
2244 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
2245 (VMOVSHDUPZrm addr:$src)>;
2246 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
2247 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
2248 (VMOVSLDUPZrm addr:$src)>;
2250 //===----------------------------------------------------------------------===//
2251 // Move Low to High and High to Low packed FP Instructions
2252 //===----------------------------------------------------------------------===//
2253 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
2254 (ins VR128X:$src1, VR128X:$src2),
2255 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2256 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2257 IIC_SSE_MOV_LH>, EVEX_4V;
2258 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2259 (ins VR128X:$src1, VR128X:$src2),
2260 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2261 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2262 IIC_SSE_MOV_LH>, EVEX_4V;
2264 let Predicates = [HasAVX512] in {
2266 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2267 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2268 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2269 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
2272 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2273 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2276 //===----------------------------------------------------------------------===//
2277 // FMA - Fused Multiply Operations
2279 let Constraints = "$src1 = $dst" in {
2280 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2281 RegisterClass RC, X86MemOperand x86memop,
2282 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2283 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2284 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2285 (ins RC:$src1, RC:$src2, RC:$src3),
2286 !strconcat(OpcodeStr,"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2287 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2290 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2291 (ins RC:$src1, RC:$src2, x86memop:$src3),
2292 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2293 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2294 (mem_frag addr:$src3))))]>;
2295 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2296 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2297 !strconcat(OpcodeStr, "\t{${src3}", BrdcstStr,
2298 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2299 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2300 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2302 } // Constraints = "$src1 = $dst"
2304 let ExeDomain = SSEPackedSingle in {
2305 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2306 memopv16f32, f32mem, loadf32, "{1to16}",
2307 X86Fmadd, v16f32>, EVEX_V512,
2308 EVEX_CD8<32, CD8VF>;
2309 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2310 memopv16f32, f32mem, loadf32, "{1to16}",
2311 X86Fmsub, v16f32>, EVEX_V512,
2312 EVEX_CD8<32, CD8VF>;
2313 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2314 memopv16f32, f32mem, loadf32, "{1to16}",
2315 X86Fmaddsub, v16f32>,
2316 EVEX_V512, EVEX_CD8<32, CD8VF>;
2317 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2318 memopv16f32, f32mem, loadf32, "{1to16}",
2319 X86Fmsubadd, v16f32>,
2320 EVEX_V512, EVEX_CD8<32, CD8VF>;
2321 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2322 memopv16f32, f32mem, loadf32, "{1to16}",
2323 X86Fnmadd, v16f32>, EVEX_V512,
2324 EVEX_CD8<32, CD8VF>;
2325 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2326 memopv16f32, f32mem, loadf32, "{1to16}",
2327 X86Fnmsub, v16f32>, EVEX_V512,
2328 EVEX_CD8<32, CD8VF>;
2330 let ExeDomain = SSEPackedDouble in {
2331 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2332 memopv8f64, f64mem, loadf64, "{1to8}",
2333 X86Fmadd, v8f64>, EVEX_V512,
2334 VEX_W, EVEX_CD8<64, CD8VF>;
2335 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2336 memopv8f64, f64mem, loadf64, "{1to8}",
2337 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2338 EVEX_CD8<64, CD8VF>;
2339 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2340 memopv8f64, f64mem, loadf64, "{1to8}",
2341 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2342 EVEX_CD8<64, CD8VF>;
2343 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2344 memopv8f64, f64mem, loadf64, "{1to8}",
2345 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2346 EVEX_CD8<64, CD8VF>;
2347 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2348 memopv8f64, f64mem, loadf64, "{1to8}",
2349 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2350 EVEX_CD8<64, CD8VF>;
2351 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2352 memopv8f64, f64mem, loadf64, "{1to8}",
2353 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2354 EVEX_CD8<64, CD8VF>;
2357 let Constraints = "$src1 = $dst" in {
2358 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2359 RegisterClass RC, X86MemOperand x86memop,
2360 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2361 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2363 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2364 (ins RC:$src1, RC:$src3, x86memop:$src2),
2365 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2366 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2367 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2368 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2369 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2370 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2371 [(set RC:$dst, (OpNode RC:$src1,
2372 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2374 } // Constraints = "$src1 = $dst"
2377 let ExeDomain = SSEPackedSingle in {
2378 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2379 memopv16f32, f32mem, loadf32, "{1to16}",
2380 X86Fmadd, v16f32>, EVEX_V512,
2381 EVEX_CD8<32, CD8VF>;
2382 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2383 memopv16f32, f32mem, loadf32, "{1to16}",
2384 X86Fmsub, v16f32>, EVEX_V512,
2385 EVEX_CD8<32, CD8VF>;
2386 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
2387 memopv16f32, f32mem, loadf32, "{1to16}",
2388 X86Fmaddsub, v16f32>,
2389 EVEX_V512, EVEX_CD8<32, CD8VF>;
2390 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
2391 memopv16f32, f32mem, loadf32, "{1to16}",
2392 X86Fmsubadd, v16f32>,
2393 EVEX_V512, EVEX_CD8<32, CD8VF>;
2394 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
2395 memopv16f32, f32mem, loadf32, "{1to16}",
2396 X86Fnmadd, v16f32>, EVEX_V512,
2397 EVEX_CD8<32, CD8VF>;
2398 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
2399 memopv16f32, f32mem, loadf32, "{1to16}",
2400 X86Fnmsub, v16f32>, EVEX_V512,
2401 EVEX_CD8<32, CD8VF>;
2403 let ExeDomain = SSEPackedDouble in {
2404 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
2405 memopv8f64, f64mem, loadf64, "{1to8}",
2406 X86Fmadd, v8f64>, EVEX_V512,
2407 VEX_W, EVEX_CD8<64, CD8VF>;
2408 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
2409 memopv8f64, f64mem, loadf64, "{1to8}",
2410 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2411 EVEX_CD8<64, CD8VF>;
2412 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
2413 memopv8f64, f64mem, loadf64, "{1to8}",
2414 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2415 EVEX_CD8<64, CD8VF>;
2416 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
2417 memopv8f64, f64mem, loadf64, "{1to8}",
2418 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2419 EVEX_CD8<64, CD8VF>;
2420 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
2421 memopv8f64, f64mem, loadf64, "{1to8}",
2422 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2423 EVEX_CD8<64, CD8VF>;
2424 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
2425 memopv8f64, f64mem, loadf64, "{1to8}",
2426 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2427 EVEX_CD8<64, CD8VF>;
2431 let Constraints = "$src1 = $dst" in {
2432 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2433 RegisterClass RC, ValueType OpVT,
2434 X86MemOperand x86memop, Operand memop,
2436 let isCommutable = 1 in
2437 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2438 (ins RC:$src1, RC:$src2, RC:$src3),
2439 !strconcat(OpcodeStr,
2440 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2442 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
2444 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2445 (ins RC:$src1, RC:$src2, f128mem:$src3),
2446 !strconcat(OpcodeStr,
2447 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2449 (OpVT (OpNode RC:$src2, RC:$src1,
2450 (mem_frag addr:$src3))))]>;
2453 } // Constraints = "$src1 = $dst"
2455 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
2456 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2457 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
2458 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2459 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
2460 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2461 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
2462 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2463 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
2464 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2465 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
2466 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2467 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
2468 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2469 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
2470 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2472 //===----------------------------------------------------------------------===//
2473 // AVX-512 Scalar convert from sign integer to float/double
2474 //===----------------------------------------------------------------------===//
2476 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2477 X86MemOperand x86memop, string asm> {
2478 let neverHasSideEffects = 1 in {
2479 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
2480 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2483 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
2484 (ins DstRC:$src1, x86memop:$src),
2485 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2487 } // neverHasSideEffects = 1
2489 let Predicates = [HasAVX512] in {
2490 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
2491 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2492 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
2493 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2494 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
2495 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2496 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
2497 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2499 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
2500 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2501 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
2502 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2503 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
2504 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2505 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
2506 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2508 def : Pat<(f32 (sint_to_fp GR32:$src)),
2509 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2510 def : Pat<(f32 (sint_to_fp GR64:$src)),
2511 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2512 def : Pat<(f64 (sint_to_fp GR32:$src)),
2513 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2514 def : Pat<(f64 (sint_to_fp GR64:$src)),
2515 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2517 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
2518 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2519 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
2520 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2521 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
2522 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2523 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
2524 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2526 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
2527 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2528 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
2529 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2530 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
2531 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2532 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
2533 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2535 def : Pat<(f32 (uint_to_fp GR32:$src)),
2536 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2537 def : Pat<(f32 (uint_to_fp GR64:$src)),
2538 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2539 def : Pat<(f64 (uint_to_fp GR32:$src)),
2540 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2541 def : Pat<(f64 (uint_to_fp GR64:$src)),
2542 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2545 //===----------------------------------------------------------------------===//
2546 // AVX-512 Scalar convert from float/double to integer
2547 //===----------------------------------------------------------------------===//
2548 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2549 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
2551 let neverHasSideEffects = 1 in {
2552 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2553 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2554 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
2555 Requires<[HasAVX512]>;
2557 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
2558 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
2559 Requires<[HasAVX512]>;
2560 } // neverHasSideEffects = 1
2562 let Predicates = [HasAVX512] in {
2563 // Convert float/double to signed/unsigned int 32/64
2564 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
2565 ssmem, sse_load_f32, "cvtss2si">,
2566 XS, EVEX_CD8<32, CD8VT1>;
2567 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
2568 ssmem, sse_load_f32, "cvtss2si">,
2569 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
2570 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
2571 ssmem, sse_load_f32, "cvtss2usi">,
2572 XS, EVEX_CD8<32, CD8VT1>;
2573 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2574 int_x86_avx512_cvtss2usi64, ssmem,
2575 sse_load_f32, "cvtss2usi">, XS, VEX_W,
2576 EVEX_CD8<32, CD8VT1>;
2577 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
2578 sdmem, sse_load_f64, "cvtsd2si">,
2579 XD, EVEX_CD8<64, CD8VT1>;
2580 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
2581 sdmem, sse_load_f64, "cvtsd2si">,
2582 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2583 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
2584 sdmem, sse_load_f64, "cvtsd2usi">,
2585 XD, EVEX_CD8<64, CD8VT1>;
2586 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2587 int_x86_avx512_cvtsd2usi64, sdmem,
2588 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
2589 EVEX_CD8<64, CD8VT1>;
2591 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2592 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
2593 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2594 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2595 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
2596 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2597 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2598 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
2599 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2600 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2601 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
2602 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2604 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2605 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
2606 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2607 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2608 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
2609 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2610 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2611 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
2612 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2613 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2614 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
2615 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2617 // Convert float/double to signed/unsigned int 32/64 with truncation
2618 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
2619 ssmem, sse_load_f32, "cvttss2si">,
2620 XS, EVEX_CD8<32, CD8VT1>;
2621 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2622 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
2623 "cvttss2si">, XS, VEX_W,
2624 EVEX_CD8<32, CD8VT1>;
2625 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
2626 sdmem, sse_load_f64, "cvttsd2si">, XD,
2627 EVEX_CD8<64, CD8VT1>;
2628 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2629 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
2630 "cvttsd2si">, XD, VEX_W,
2631 EVEX_CD8<64, CD8VT1>;
2632 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2633 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
2634 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
2635 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2636 int_x86_avx512_cvttss2usi64, ssmem,
2637 sse_load_f32, "cvttss2usi">, XS, VEX_W,
2638 EVEX_CD8<32, CD8VT1>;
2639 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2640 int_x86_avx512_cvttsd2usi,
2641 sdmem, sse_load_f64, "cvttsd2usi">, XD,
2642 EVEX_CD8<64, CD8VT1>;
2643 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2644 int_x86_avx512_cvttsd2usi64, sdmem,
2645 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
2646 EVEX_CD8<64, CD8VT1>;
2648 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2649 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
2651 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2652 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2653 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
2654 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2655 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2656 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
2659 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
2660 loadf32, "cvttss2si">, XS,
2661 EVEX_CD8<32, CD8VT1>;
2662 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
2663 loadf32, "cvttss2usi">, XS,
2664 EVEX_CD8<32, CD8VT1>;
2665 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
2666 loadf32, "cvttss2si">, XS, VEX_W,
2667 EVEX_CD8<32, CD8VT1>;
2668 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
2669 loadf32, "cvttss2usi">, XS, VEX_W,
2670 EVEX_CD8<32, CD8VT1>;
2671 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
2672 loadf64, "cvttsd2si">, XD,
2673 EVEX_CD8<64, CD8VT1>;
2674 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
2675 loadf64, "cvttsd2usi">, XD,
2676 EVEX_CD8<64, CD8VT1>;
2677 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
2678 loadf64, "cvttsd2si">, XD, VEX_W,
2679 EVEX_CD8<64, CD8VT1>;
2680 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
2681 loadf64, "cvttsd2usi">, XD, VEX_W,
2682 EVEX_CD8<64, CD8VT1>;
2684 //===----------------------------------------------------------------------===//
2685 // AVX-512 Convert form float to double and back
2686 //===----------------------------------------------------------------------===//
2687 let neverHasSideEffects = 1 in {
2688 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
2689 (ins FR32X:$src1, FR32X:$src2),
2690 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2691 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
2693 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
2694 (ins FR32X:$src1, f32mem:$src2),
2695 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2696 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
2697 EVEX_CD8<32, CD8VT1>;
2699 // Convert scalar double to scalar single
2700 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
2701 (ins FR64X:$src1, FR64X:$src2),
2702 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2703 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
2705 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
2706 (ins FR64X:$src1, f64mem:$src2),
2707 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2708 []>, EVEX_4V, VEX_LIG, VEX_W,
2709 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
2712 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
2713 Requires<[HasAVX512]>;
2714 def : Pat<(fextend (loadf32 addr:$src)),
2715 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
2717 def : Pat<(extloadf32 addr:$src),
2718 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
2719 Requires<[HasAVX512, OptForSize]>;
2721 def : Pat<(extloadf32 addr:$src),
2722 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
2723 Requires<[HasAVX512, OptForSpeed]>;
2725 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
2726 Requires<[HasAVX512]>;
2728 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
2729 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2730 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2732 let neverHasSideEffects = 1 in {
2733 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2734 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2736 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2737 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
2738 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
2739 [], d>, EVEX, EVEX_B;
2741 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2742 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2744 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2745 } // neverHasSideEffects = 1
2748 multiclass avx512_vcvtt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
2749 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2750 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2752 let neverHasSideEffects = 1 in {
2753 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2754 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2756 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2758 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2759 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2761 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2762 } // neverHasSideEffects = 1
2766 defm VCVTPD2PSZ : avx512_vcvt_fp<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
2767 memopv8f64, f512mem, v8f32, v8f64,
2768 SSEPackedSingle>, EVEX_V512, VEX_W, OpSize,
2769 EVEX_CD8<64, CD8VF>;
2771 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
2772 memopv4f64, f256mem, v8f64, v8f32,
2773 SSEPackedDouble>, EVEX_V512, EVEX_CD8<32, CD8VH>;
2774 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2775 (VCVTPS2PDZrm addr:$src)>;
2777 //===----------------------------------------------------------------------===//
2778 // AVX-512 Vector convert from sign integer to float/double
2779 //===----------------------------------------------------------------------===//
2781 defm VCVTDQ2PSZ : avx512_vcvt_fp<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
2782 memopv8i64, i512mem, v16f32, v16i32,
2783 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2785 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
2786 memopv4i64, i256mem, v8f64, v8i32,
2787 SSEPackedDouble>, EVEX_V512, XS,
2788 EVEX_CD8<32, CD8VH>;
2790 defm VCVTTPS2DQZ : avx512_vcvtt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
2791 memopv16f32, f512mem, v16i32, v16f32,
2792 SSEPackedSingle>, EVEX_V512, XS,
2793 EVEX_CD8<32, CD8VF>;
2795 defm VCVTTPD2DQZ : avx512_vcvtt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
2796 memopv8f64, f512mem, v8i32, v8f64,
2797 SSEPackedDouble>, EVEX_V512, OpSize, VEX_W,
2798 EVEX_CD8<64, CD8VF>;
2800 defm VCVTTPS2UDQZ : avx512_vcvtt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
2801 memopv16f32, f512mem, v16i32, v16f32,
2802 SSEPackedSingle>, EVEX_V512,
2803 EVEX_CD8<32, CD8VF>;
2805 // cvttps2udq (src, 0, mask-all-ones, sae-current)
2806 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
2807 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
2808 (VCVTTPS2UDQZrr VR512:$src)>;
2810 defm VCVTTPD2UDQZ : avx512_vcvtt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
2811 memopv8f64, f512mem, v8i32, v8f64,
2812 SSEPackedDouble>, EVEX_V512, VEX_W,
2813 EVEX_CD8<64, CD8VF>;
2815 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
2816 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
2817 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
2818 (VCVTTPD2UDQZrr VR512:$src)>;
2820 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
2821 memopv4i64, f256mem, v8f64, v8i32,
2822 SSEPackedDouble>, EVEX_V512, XS,
2823 EVEX_CD8<32, CD8VH>;
2825 defm VCVTUDQ2PSZ : avx512_vcvt_fp<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
2826 memopv16i32, f512mem, v16f32, v16i32,
2827 SSEPackedSingle>, EVEX_V512, XD,
2828 EVEX_CD8<32, CD8VF>;
2830 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
2831 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
2832 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
2835 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
2836 (v16f32 immAllZerosV), (i16 -1), imm:$rc)),
2837 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
2840 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
2841 RegisterClass DstRC, PatFrag mem_frag,
2842 X86MemOperand x86memop, Domain d> {
2843 let neverHasSideEffects = 1 in {
2844 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2845 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2847 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
2848 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
2849 [], d>, EVEX, EVEX_B;
2851 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2852 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2854 } // neverHasSideEffects = 1
2857 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
2858 memopv16f32, f512mem, SSEPackedSingle>, OpSize,
2859 EVEX_V512, EVEX_CD8<32, CD8VF>;
2860 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
2861 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
2862 EVEX_V512, EVEX_CD8<64, CD8VF>;
2864 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
2865 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
2866 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
2868 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
2869 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
2870 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
2872 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
2873 memopv16f32, f512mem, SSEPackedSingle>,
2874 EVEX_V512, EVEX_CD8<32, CD8VF>;
2875 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
2876 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
2877 EVEX_V512, EVEX_CD8<64, CD8VF>;
2879 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
2880 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
2881 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
2883 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
2884 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
2885 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
2887 let Predicates = [HasAVX512] in {
2888 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
2889 (VCVTPD2PSZrm addr:$src)>;
2890 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2891 (VCVTPS2PDZrm addr:$src)>;
2894 //===----------------------------------------------------------------------===//
2895 // Half precision conversion instructions
2896 //===----------------------------------------------------------------------===//
2897 multiclass avx512_f16c_ph2ps<RegisterClass destRC, RegisterClass srcRC,
2898 X86MemOperand x86memop, Intrinsic Int> {
2899 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
2900 "vcvtph2ps\t{$src, $dst|$dst, $src}",
2901 [(set destRC:$dst, (Int srcRC:$src))]>, EVEX;
2902 let neverHasSideEffects = 1, mayLoad = 1 in
2903 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
2904 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
2907 multiclass avx512_f16c_ps2ph<RegisterClass destRC, RegisterClass srcRC,
2908 X86MemOperand x86memop, Intrinsic Int> {
2909 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
2910 (ins srcRC:$src1, i32i8imm:$src2),
2911 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2912 [(set destRC:$dst, (Int srcRC:$src1, imm:$src2))]>, EVEX;
2913 let neverHasSideEffects = 1, mayStore = 1 in
2914 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
2915 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
2916 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
2919 defm VCVTPH2PSZ : avx512_f16c_ph2ps<VR512, VR256X, f256mem,
2920 int_x86_avx512_vcvtph2ps_512>, EVEX_V512,
2921 EVEX_CD8<32, CD8VH>;
2922 defm VCVTPS2PHZ : avx512_f16c_ps2ph<VR256X, VR512, f256mem,
2923 int_x86_avx512_vcvtps2ph_512>, EVEX_V512,
2924 EVEX_CD8<32, CD8VH>;
2926 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
2927 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
2928 "ucomiss">, TB, EVEX, VEX_LIG,
2929 EVEX_CD8<32, CD8VT1>;
2930 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
2931 "ucomisd">, TB, OpSize, EVEX,
2932 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2933 let Pattern = []<dag> in {
2934 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
2935 "comiss">, TB, EVEX, VEX_LIG,
2936 EVEX_CD8<32, CD8VT1>;
2937 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
2938 "comisd">, TB, OpSize, EVEX,
2939 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2941 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
2942 load, "ucomiss">, TB, EVEX, VEX_LIG,
2943 EVEX_CD8<32, CD8VT1>;
2944 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
2945 load, "ucomisd">, TB, OpSize, EVEX,
2946 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2948 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
2949 load, "comiss">, TB, EVEX, VEX_LIG,
2950 EVEX_CD8<32, CD8VT1>;
2951 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
2952 load, "comisd">, TB, OpSize, EVEX,
2953 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2956 /// avx512_unop_p - AVX-512 unops in packed form.
2957 multiclass avx512_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2958 def PSZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2959 !strconcat(OpcodeStr,
2960 "ps\t{$src, $dst|$dst, $src}"),
2961 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))]>,
2963 def PSZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f256mem:$src),
2964 !strconcat(OpcodeStr,
2965 "ps\t{$src, $dst|$dst, $src}"),
2966 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
2967 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2968 def PDZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2969 !strconcat(OpcodeStr,
2970 "pd\t{$src, $dst|$dst, $src}"),
2971 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))]>,
2972 EVEX, EVEX_V512, VEX_W;
2973 def PDZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2974 !strconcat(OpcodeStr,
2975 "pd\t{$src, $dst|$dst, $src}"),
2976 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
2977 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2980 /// avx512_fp_unop_p_int - AVX-512 intrinsics unops in packed forms.
2981 multiclass avx512_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2982 Intrinsic V16F32Int, Intrinsic V8F64Int> {
2983 def PSZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2984 !strconcat(OpcodeStr,
2985 "ps\t{$src, $dst|$dst, $src}"),
2986 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
2988 def PSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2989 !strconcat(OpcodeStr,
2990 "ps\t{$src, $dst|$dst, $src}"),
2992 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
2993 EVEX_V512, EVEX_CD8<32, CD8VF>;
2994 def PDZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2995 !strconcat(OpcodeStr,
2996 "pd\t{$src, $dst|$dst, $src}"),
2997 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
2998 EVEX, EVEX_V512, VEX_W;
2999 def PDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3000 !strconcat(OpcodeStr,
3001 "pd\t{$src, $dst|$dst, $src}"),
3003 (V8F64Int (memopv8f64 addr:$src)))]>,
3004 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3007 /// avx512_fp_unop_s - AVX-512 unops in scalar form.
3008 multiclass avx512_fp_unop_s<bits<8> opc, string OpcodeStr> {
3009 let hasSideEffects = 0 in {
3010 def SSZr : AVX5128I<opc, MRMSrcReg, (outs FR32X:$dst),
3011 (ins FR32X:$src1, FR32X:$src2),
3012 !strconcat(OpcodeStr,
3013 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3015 let mayLoad = 1 in {
3016 def SSZm : AVX5128I<opc, MRMSrcMem, (outs FR32X:$dst),
3017 (ins FR32X:$src1, f32mem:$src2),
3018 !strconcat(OpcodeStr,
3019 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3020 []>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3021 def SSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
3022 (ins VR128X:$src1, ssmem:$src2),
3023 !strconcat(OpcodeStr,
3024 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3025 []>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3027 def SDZr : AVX5128I<opc, MRMSrcReg, (outs FR64X:$dst),
3028 (ins FR64X:$src1, FR64X:$src2),
3029 !strconcat(OpcodeStr,
3030 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3032 let mayLoad = 1 in {
3033 def SDZm : AVX5128I<opc, MRMSrcMem, (outs FR64X:$dst),
3034 (ins FR64X:$src1, f64mem:$src2),
3035 !strconcat(OpcodeStr,
3036 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3037 EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3038 def SDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
3039 (ins VR128X:$src1, sdmem:$src2),
3040 !strconcat(OpcodeStr,
3041 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3042 []>, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3047 defm VRCP14 : avx512_fp_unop_s<0x4D, "vrcp14">,
3048 avx512_fp_unop_p<0x4C, "vrcp14", X86frcp>,
3049 avx512_fp_unop_p_int<0x4C, "vrcp14",
3050 int_x86_avx512_rcp14_ps_512, int_x86_avx512_rcp14_pd_512>;
3052 defm VRSQRT14 : avx512_fp_unop_s<0x4F, "vrsqrt14">,
3053 avx512_fp_unop_p<0x4E, "vrsqrt14", X86frsqrt>,
3054 avx512_fp_unop_p_int<0x4E, "vrsqrt14",
3055 int_x86_avx512_rsqrt14_ps_512, int_x86_avx512_rsqrt14_pd_512>;
3057 def : Pat<(int_x86_avx512_rsqrt14_ss VR128X:$src),
3058 (COPY_TO_REGCLASS (VRSQRT14SSZr (f32 (IMPLICIT_DEF)),
3059 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3061 def : Pat<(int_x86_avx512_rsqrt14_ss sse_load_f32:$src),
3062 (VRSQRT14SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3064 def : Pat<(int_x86_avx512_rcp14_ss VR128X:$src),
3065 (COPY_TO_REGCLASS (VRCP14SSZr (f32 (IMPLICIT_DEF)),
3066 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3068 def : Pat<(int_x86_avx512_rcp14_ss sse_load_f32:$src),
3069 (VRCP14SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3071 let AddedComplexity = 20, Predicates = [HasERI] in {
3072 defm VRCP28 : avx512_fp_unop_s<0xCB, "vrcp28">,
3073 avx512_fp_unop_p<0xCA, "vrcp28", X86frcp>,
3074 avx512_fp_unop_p_int<0xCA, "vrcp28",
3075 int_x86_avx512_rcp28_ps_512, int_x86_avx512_rcp28_pd_512>;
3077 defm VRSQRT28 : avx512_fp_unop_s<0xCD, "vrsqrt28">,
3078 avx512_fp_unop_p<0xCC, "vrsqrt28", X86frsqrt>,
3079 avx512_fp_unop_p_int<0xCC, "vrsqrt28",
3080 int_x86_avx512_rsqrt28_ps_512, int_x86_avx512_rsqrt28_pd_512>;
3083 let Predicates = [HasERI] in {
3084 def : Pat<(int_x86_avx512_rsqrt28_ss VR128X:$src),
3085 (COPY_TO_REGCLASS (VRSQRT28SSZr (f32 (IMPLICIT_DEF)),
3086 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3088 def : Pat<(int_x86_avx512_rsqrt28_ss sse_load_f32:$src),
3089 (VRSQRT28SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3091 def : Pat<(int_x86_avx512_rcp28_ss VR128X:$src),
3092 (COPY_TO_REGCLASS (VRCP28SSZr (f32 (IMPLICIT_DEF)),
3093 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3095 def : Pat<(int_x86_avx512_rcp28_ss sse_load_f32:$src),
3096 (VRCP28SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3098 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3099 Intrinsic V16F32Int, Intrinsic V8F64Int,
3100 OpndItins itins_s, OpndItins itins_d> {
3101 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3102 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3103 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
3107 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3108 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3110 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
3111 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
3113 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3114 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3115 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
3119 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3120 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3121 [(set VR512:$dst, (OpNode
3122 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
3123 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
3125 def PSZr_Int : AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3126 !strconcat(OpcodeStr,
3127 "ps\t{$src, $dst|$dst, $src}"),
3128 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
3130 def PSZm_Int : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3131 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3133 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
3134 EVEX_V512, EVEX_CD8<32, CD8VF>;
3135 def PDZr_Int : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3136 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3137 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
3138 EVEX, EVEX_V512, VEX_W;
3139 def PDZm_Int : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3140 !strconcat(OpcodeStr,
3141 "pd\t{$src, $dst|$dst, $src}"),
3142 [(set VR512:$dst, (V8F64Int (memopv8f64 addr:$src)))]>,
3143 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3146 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
3147 Intrinsic F32Int, Intrinsic F64Int,
3148 OpndItins itins_s, OpndItins itins_d> {
3149 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
3150 (ins FR32X:$src1, FR32X:$src2),
3151 !strconcat(OpcodeStr,
3152 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3153 [], itins_s.rr>, XS, EVEX_4V;
3154 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3155 (ins VR128X:$src1, VR128X:$src2),
3156 !strconcat(OpcodeStr,
3157 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3159 (F32Int VR128X:$src1, VR128X:$src2))],
3160 itins_s.rr>, XS, EVEX_4V;
3161 let mayLoad = 1 in {
3162 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
3163 (ins FR32X:$src1, f32mem:$src2),
3164 !strconcat(OpcodeStr,
3165 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3166 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3167 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3168 (ins VR128X:$src1, ssmem:$src2),
3169 !strconcat(OpcodeStr,
3170 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3172 (F32Int VR128X:$src1, sse_load_f32:$src2))],
3173 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3175 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
3176 (ins FR64X:$src1, FR64X:$src2),
3177 !strconcat(OpcodeStr,
3178 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3180 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3181 (ins VR128X:$src1, VR128X:$src2),
3182 !strconcat(OpcodeStr,
3183 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3185 (F64Int VR128X:$src1, VR128X:$src2))],
3186 itins_s.rr>, XD, EVEX_4V, VEX_W;
3187 let mayLoad = 1 in {
3188 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
3189 (ins FR64X:$src1, f64mem:$src2),
3190 !strconcat(OpcodeStr,
3191 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3192 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3193 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3194 (ins VR128X:$src1, sdmem:$src2),
3195 !strconcat(OpcodeStr,
3196 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3198 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
3199 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3204 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
3205 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
3206 SSE_SQRTSS, SSE_SQRTSD>,
3207 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
3208 int_x86_avx512_sqrt_ps_512, int_x86_avx512_sqrt_pd_512,
3209 SSE_SQRTPS, SSE_SQRTPD>;
3211 let Predicates = [HasAVX512] in {
3212 def : Pat<(f32 (fsqrt FR32X:$src)),
3213 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3214 def : Pat<(f32 (fsqrt (load addr:$src))),
3215 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3216 Requires<[OptForSize]>;
3217 def : Pat<(f64 (fsqrt FR64X:$src)),
3218 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
3219 def : Pat<(f64 (fsqrt (load addr:$src))),
3220 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
3221 Requires<[OptForSize]>;
3223 def : Pat<(f32 (X86frsqrt FR32X:$src)),
3224 (VRSQRT14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3225 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3226 (VRSQRT14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3227 Requires<[OptForSize]>;
3229 def : Pat<(f32 (X86frcp FR32X:$src)),
3230 (VRCP14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3231 def : Pat<(f32 (X86frcp (load addr:$src))),
3232 (VRCP14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3233 Requires<[OptForSize]>;
3235 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
3236 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
3237 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3239 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3240 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3242 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
3243 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
3244 (COPY_TO_REGCLASS VR128X:$src, FR64)),
3246 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3247 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3251 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
3252 X86MemOperand x86memop, RegisterClass RC,
3253 PatFrag mem_frag32, PatFrag mem_frag64,
3254 Intrinsic V4F32Int, Intrinsic V2F64Int,
3256 let ExeDomain = SSEPackedSingle in {
3257 // Intrinsic operation, reg.
3258 // Vector intrinsic operation, reg
3259 def PSr : AVX512AIi8<opcps, MRMSrcReg,
3260 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3261 !strconcat(OpcodeStr,
3262 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3263 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
3265 // Vector intrinsic operation, mem
3266 def PSm : AVX512AIi8<opcps, MRMSrcMem,
3267 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3268 !strconcat(OpcodeStr,
3269 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3271 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
3272 EVEX_CD8<32, VForm>;
3273 } // ExeDomain = SSEPackedSingle
3275 let ExeDomain = SSEPackedDouble in {
3276 // Vector intrinsic operation, reg
3277 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
3278 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3279 !strconcat(OpcodeStr,
3280 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3281 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
3283 // Vector intrinsic operation, mem
3284 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
3285 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3286 !strconcat(OpcodeStr,
3287 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3289 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
3290 EVEX_CD8<64, VForm>;
3291 } // ExeDomain = SSEPackedDouble
3294 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3298 let ExeDomain = GenericDomain in {
3300 let hasSideEffects = 0 in
3301 def SSr : AVX512AIi8<opcss, MRMSrcReg,
3302 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
3303 !strconcat(OpcodeStr,
3304 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3307 // Intrinsic operation, reg.
3308 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
3309 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3310 !strconcat(OpcodeStr,
3311 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3312 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
3314 // Intrinsic operation, mem.
3315 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
3316 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
3317 !strconcat(OpcodeStr,
3318 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3319 [(set VR128X:$dst, (F32Int VR128X:$src1,
3320 sse_load_f32:$src2, imm:$src3))]>,
3321 EVEX_CD8<32, CD8VT1>;
3324 let hasSideEffects = 0 in
3325 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
3326 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
3327 !strconcat(OpcodeStr,
3328 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3331 // Intrinsic operation, reg.
3332 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
3333 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3334 !strconcat(OpcodeStr,
3335 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3336 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
3339 // Intrinsic operation, mem.
3340 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
3341 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
3342 !strconcat(OpcodeStr,
3343 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3345 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
3346 VEX_W, EVEX_CD8<64, CD8VT1>;
3347 } // ExeDomain = GenericDomain
3350 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
3351 X86MemOperand x86memop, RegisterClass RC,
3352 PatFrag mem_frag, Domain d> {
3353 let ExeDomain = d in {
3354 // Intrinsic operation, reg.
3355 // Vector intrinsic operation, reg
3356 def r : AVX512AIi8<opc, MRMSrcReg,
3357 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3358 !strconcat(OpcodeStr,
3359 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3362 // Vector intrinsic operation, mem
3363 def m : AVX512AIi8<opc, MRMSrcMem,
3364 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3365 !strconcat(OpcodeStr,
3366 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3372 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
3373 memopv16f32, SSEPackedSingle>, EVEX_V512,
3374 EVEX_CD8<32, CD8VF>;
3376 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
3377 imm:$src2, (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1),
3379 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
3382 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
3383 memopv8f64, SSEPackedDouble>, EVEX_V512,
3384 VEX_W, EVEX_CD8<64, CD8VF>;
3386 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
3387 imm:$src2, (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1),
3389 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
3391 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
3392 Operand x86memop, RegisterClass RC, Domain d> {
3393 let ExeDomain = d in {
3394 def r : AVX512AIi8<opc, MRMSrcReg,
3395 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
3396 !strconcat(OpcodeStr,
3397 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3400 def m : AVX512AIi8<opc, MRMSrcMem,
3401 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
3402 !strconcat(OpcodeStr,
3403 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3408 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
3409 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
3411 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
3412 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
3414 def : Pat<(ffloor FR32X:$src),
3415 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
3416 def : Pat<(f64 (ffloor FR64X:$src)),
3417 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
3418 def : Pat<(f32 (fnearbyint FR32X:$src)),
3419 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
3420 def : Pat<(f64 (fnearbyint FR64X:$src)),
3421 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
3422 def : Pat<(f32 (fceil FR32X:$src)),
3423 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
3424 def : Pat<(f64 (fceil FR64X:$src)),
3425 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
3426 def : Pat<(f32 (frint FR32X:$src)),
3427 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
3428 def : Pat<(f64 (frint FR64X:$src)),
3429 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
3430 def : Pat<(f32 (ftrunc FR32X:$src)),
3431 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
3432 def : Pat<(f64 (ftrunc FR64X:$src)),
3433 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
3435 def : Pat<(v16f32 (ffloor VR512:$src)),
3436 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
3437 def : Pat<(v16f32 (fnearbyint VR512:$src)),
3438 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
3439 def : Pat<(v16f32 (fceil VR512:$src)),
3440 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
3441 def : Pat<(v16f32 (frint VR512:$src)),
3442 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
3443 def : Pat<(v16f32 (ftrunc VR512:$src)),
3444 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
3446 def : Pat<(v8f64 (ffloor VR512:$src)),
3447 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
3448 def : Pat<(v8f64 (fnearbyint VR512:$src)),
3449 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
3450 def : Pat<(v8f64 (fceil VR512:$src)),
3451 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
3452 def : Pat<(v8f64 (frint VR512:$src)),
3453 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
3454 def : Pat<(v8f64 (ftrunc VR512:$src)),
3455 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
3457 //-------------------------------------------------
3458 // Integer truncate and extend operations
3459 //-------------------------------------------------
3461 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
3462 RegisterClass dstRC, RegisterClass srcRC,
3463 RegisterClass KRC, X86MemOperand x86memop> {
3464 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3466 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
3469 def krr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3470 (ins KRC:$mask, srcRC:$src),
3471 !strconcat(OpcodeStr,
3472 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3475 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
3476 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3479 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
3480 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3481 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
3482 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3483 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
3484 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3485 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
3486 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3487 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
3488 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3489 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
3490 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3491 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
3492 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3493 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
3494 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3495 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
3496 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3497 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
3498 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3499 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
3500 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3501 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
3502 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3503 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
3504 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3505 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
3506 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3507 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
3508 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3510 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
3511 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
3512 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
3513 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
3514 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
3516 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3517 (VPMOVDBkrr VK16WM:$mask, VR512:$src)>;
3518 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3519 (VPMOVDWkrr VK16WM:$mask, VR512:$src)>;
3520 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3521 (VPMOVQWkrr VK8WM:$mask, VR512:$src)>;
3522 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3523 (VPMOVQDkrr VK8WM:$mask, VR512:$src)>;
3526 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass DstRC,
3527 RegisterClass SrcRC, SDNode OpNode, PatFrag mem_frag,
3528 X86MemOperand x86memop, ValueType OpVT, ValueType InVT> {
3530 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
3532 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3533 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
3534 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
3535 (ins x86memop:$src),
3536 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
3538 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
3542 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VR512, VR128X, X86vzext,
3543 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3545 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VR512, VR128X, X86vzext,
3546 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3548 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VR512, VR256X, X86vzext,
3549 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3550 EVEX_CD8<16, CD8VH>;
3551 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VR512, VR128X, X86vzext,
3552 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3553 EVEX_CD8<16, CD8VQ>;
3554 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VR512, VR256X, X86vzext,
3555 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3556 EVEX_CD8<32, CD8VH>;
3558 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VR512, VR128X, X86vsext,
3559 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3561 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VR512, VR128X, X86vsext,
3562 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3564 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VR512, VR256X, X86vsext,
3565 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3566 EVEX_CD8<16, CD8VH>;
3567 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VR512, VR128X, X86vsext,
3568 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3569 EVEX_CD8<16, CD8VQ>;
3570 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VR512, VR256X, X86vsext,
3571 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3572 EVEX_CD8<32, CD8VH>;
3574 //===----------------------------------------------------------------------===//
3575 // GATHER - SCATTER Operations
3577 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3578 RegisterClass RC, X86MemOperand memop> {
3580 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
3581 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
3582 (ins RC:$src1, KRC:$mask, memop:$src2),
3583 !strconcat(OpcodeStr,
3584 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3587 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
3588 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3589 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
3590 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3592 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
3593 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3594 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
3595 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3597 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
3598 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3599 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
3600 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3602 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
3603 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3604 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
3605 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3607 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3608 RegisterClass RC, X86MemOperand memop> {
3609 let mayStore = 1, Constraints = "$mask = $mask_wb" in
3610 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
3611 (ins memop:$dst, KRC:$mask, RC:$src2),
3612 !strconcat(OpcodeStr,
3613 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3617 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
3618 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3619 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
3620 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3622 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
3623 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3624 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
3625 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3627 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
3628 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3629 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
3630 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3632 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
3633 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3634 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
3635 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3637 //===----------------------------------------------------------------------===//
3638 // VSHUFPS - VSHUFPD Operations
3640 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
3641 ValueType vt, string OpcodeStr, PatFrag mem_frag,
3643 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
3644 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3645 !strconcat(OpcodeStr,
3646 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3647 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
3648 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3649 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
3650 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
3651 (ins RC:$src1, RC:$src2, i8imm:$src3),
3652 !strconcat(OpcodeStr,
3653 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3654 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
3655 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3656 EVEX_4V, Sched<[WriteShuffle]>;
3659 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
3660 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3661 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
3662 SSEPackedDouble>, OpSize, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3664 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3665 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3666 def : Pat<(v16i32 (X86Shufp VR512:$src1,
3667 (memopv16i32 addr:$src2), (i8 imm:$imm))),
3668 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3670 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3671 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3672 def : Pat<(v8i64 (X86Shufp VR512:$src1,
3673 (memopv8i64 addr:$src2), (i8 imm:$imm))),
3674 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3676 multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
3677 X86MemOperand x86memop> {
3678 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
3679 (ins RC:$src1, RC:$src2, i8imm:$src3),
3680 !strconcat(OpcodeStr,
3681 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3684 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
3685 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3686 !strconcat(OpcodeStr,
3687 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3690 defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
3691 EVEX_V512, EVEX_CD8<32, CD8VF>;
3692 defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
3693 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3695 def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3696 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3697 def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3698 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3699 def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3700 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3701 def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3702 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3704 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, RegisterClass RC,
3705 X86MemOperand x86memop> {
3706 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3707 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3709 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
3710 (ins x86memop:$src),
3711 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3715 defm VPABSD : avx512_vpabs<0x1E, "vpabsd", VR512, i512mem>, EVEX_V512,
3716 EVEX_CD8<32, CD8VF>;
3717 defm VPABSQ : avx512_vpabs<0x1F, "vpabsq", VR512, i512mem>, EVEX_V512, VEX_W,
3718 EVEX_CD8<64, CD8VF>;
3720 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
3721 RegisterClass RC, RegisterClass KRC,
3722 X86MemOperand x86memop,
3723 X86MemOperand x86scalar_mop, string BrdcstStr> {
3724 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3726 !strconcat(OpcodeStr, "\t{$src, ${dst} |${dst}, $src}"),
3728 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3729 (ins x86memop:$src),
3730 !strconcat(OpcodeStr, "\t{$src, ${dst}|${dst}, $src}"),
3732 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3733 (ins x86scalar_mop:$src),
3734 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
3735 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
3737 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3738 (ins KRC:$mask, RC:$src),
3739 !strconcat(OpcodeStr,
3740 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3742 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3743 (ins KRC:$mask, x86memop:$src),
3744 !strconcat(OpcodeStr,
3745 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3747 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3748 (ins KRC:$mask, x86scalar_mop:$src),
3749 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
3750 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
3752 []>, EVEX, EVEX_KZ, EVEX_B;
3754 let Constraints = "$src1 = $dst" in {
3755 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3756 (ins RC:$src1, KRC:$mask, RC:$src2),
3757 !strconcat(OpcodeStr,
3758 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3760 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3761 (ins RC:$src1, KRC:$mask, x86memop:$src2),
3762 !strconcat(OpcodeStr,
3763 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3765 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3766 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
3767 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
3768 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
3769 []>, EVEX, EVEX_K, EVEX_B;
3773 let Predicates = [HasCDI] in {
3774 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
3775 i512mem, i32mem, "{1to16}">,
3776 EVEX_V512, EVEX_CD8<32, CD8VF>;
3779 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
3780 i512mem, i64mem, "{1to8}">,
3781 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3785 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
3787 (VPCONFLICTDrrk VR512:$src1,
3788 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
3790 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
3792 (VPCONFLICTQrrk VR512:$src1,
3793 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;