1 // Bitcasts between 512-bit vector types. Return the original type since
2 // no instruction is needed for the conversion
3 let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
8 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
11 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
12 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
13 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
14 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
15 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
16 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
17 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
18 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
19 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
20 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
21 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
22 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
23 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
24 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
25 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
26 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
27 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
28 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
29 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
30 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
31 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
32 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
33 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
35 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
36 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
37 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
38 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
39 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
40 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
41 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
42 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
43 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
44 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
45 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
46 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
47 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
48 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
49 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
50 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
51 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
52 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
53 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
54 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
55 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
56 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
57 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
58 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
59 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
60 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
61 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
62 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
63 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
64 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
66 // Bitcasts between 256-bit vector types. Return the original type since
67 // no instruction is needed for the conversion
68 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
69 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
70 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
71 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
72 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
73 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
74 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
75 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
76 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
77 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
78 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
79 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
80 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
81 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
82 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
83 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
84 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
85 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
86 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
87 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
88 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
89 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
90 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
91 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
92 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
93 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
94 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
95 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
96 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
97 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
101 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
104 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
105 isPseudo = 1, Predicates = [HasAVX512] in {
106 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
107 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
110 let Predicates = [HasAVX512] in {
111 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
112 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
113 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
116 //===----------------------------------------------------------------------===//
117 // AVX-512 - VECTOR INSERT
120 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
121 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
122 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
123 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
124 []>, EVEX_4V, EVEX_V512;
126 def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
127 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
128 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
129 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
132 // -- 64x4 fp form --
133 let hasSideEffects = 0, ExeDomain = SSEPackedDouble in {
134 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
135 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
136 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
137 []>, EVEX_4V, EVEX_V512, VEX_W;
139 def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
140 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
141 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
142 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
144 // -- 32x4 integer form --
145 let hasSideEffects = 0 in {
146 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
147 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
148 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
149 []>, EVEX_4V, EVEX_V512;
151 def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
152 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
153 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
154 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
157 let hasSideEffects = 0 in {
159 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
160 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
161 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
162 []>, EVEX_4V, EVEX_V512, VEX_W;
164 def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
165 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
166 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
167 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
170 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
171 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
172 (INSERT_get_vinsert128_imm VR512:$ins))>;
173 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
174 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
175 (INSERT_get_vinsert128_imm VR512:$ins))>;
176 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
177 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
178 (INSERT_get_vinsert128_imm VR512:$ins))>;
179 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
180 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
181 (INSERT_get_vinsert128_imm VR512:$ins))>;
183 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
184 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
185 (INSERT_get_vinsert128_imm VR512:$ins))>;
186 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
187 (bc_v4i32 (loadv2i64 addr:$src2)),
188 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
189 (INSERT_get_vinsert128_imm VR512:$ins))>;
190 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
191 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
192 (INSERT_get_vinsert128_imm VR512:$ins))>;
193 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
194 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
195 (INSERT_get_vinsert128_imm VR512:$ins))>;
197 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
198 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
199 (INSERT_get_vinsert256_imm VR512:$ins))>;
200 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
201 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
202 (INSERT_get_vinsert256_imm VR512:$ins))>;
203 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
204 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
205 (INSERT_get_vinsert256_imm VR512:$ins))>;
206 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
207 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
208 (INSERT_get_vinsert256_imm VR512:$ins))>;
210 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
211 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
212 (INSERT_get_vinsert256_imm VR512:$ins))>;
213 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
214 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
215 (INSERT_get_vinsert256_imm VR512:$ins))>;
216 def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
217 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
218 (INSERT_get_vinsert256_imm VR512:$ins))>;
219 def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
220 (bc_v8i32 (loadv4i64 addr:$src2)),
221 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
222 (INSERT_get_vinsert256_imm VR512:$ins))>;
224 // vinsertps - insert f32 to XMM
225 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
226 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
227 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
228 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
230 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
231 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
232 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
233 [(set VR128X:$dst, (X86insertps VR128X:$src1,
234 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
235 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
237 //===----------------------------------------------------------------------===//
238 // AVX-512 VECTOR EXTRACT
240 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
242 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
243 (ins VR512:$src1, i8imm:$src2),
244 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
245 []>, EVEX, EVEX_V512;
246 def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
247 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
248 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
249 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
252 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
253 (ins VR512:$src1, i8imm:$src2),
254 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
255 []>, EVEX, EVEX_V512, VEX_W;
257 def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
258 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
259 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
260 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
263 let hasSideEffects = 0 in {
265 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
266 (ins VR512:$src1, i8imm:$src2),
267 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
268 []>, EVEX, EVEX_V512;
269 def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
270 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
271 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
272 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
275 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
276 (ins VR512:$src1, i8imm:$src2),
277 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
278 []>, EVEX, EVEX_V512, VEX_W;
280 def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
281 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
282 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
283 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
286 def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
287 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
288 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
290 def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
291 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
292 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
294 def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
295 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
296 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
298 def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
299 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
300 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
303 def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
304 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
305 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
307 def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
308 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
309 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
311 def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
312 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
313 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
315 def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
316 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
317 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
319 // A 256-bit subvector extract from the first 512-bit vector position
320 // is a subregister copy that needs no instruction.
321 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
322 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
323 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
324 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
325 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
326 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
327 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
328 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
331 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
332 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
333 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
334 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
335 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
336 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
337 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
338 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
341 // A 128-bit subvector insert to the first 512-bit vector position
342 // is a subregister copy that needs no instruction.
343 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
344 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
345 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
347 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
348 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
349 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
351 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
352 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
353 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
355 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
356 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
357 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
360 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
361 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
362 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
363 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
364 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
365 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
366 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
367 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
369 // vextractps - extract 32 bits from XMM
370 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
371 (ins VR128X:$src1, u32u8imm:$src2),
372 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
373 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
376 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
377 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
378 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
379 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
380 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
382 //===---------------------------------------------------------------------===//
385 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
386 RegisterClass DestRC,
387 RegisterClass SrcRC, X86MemOperand x86memop> {
388 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
389 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
391 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
392 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),[]>, EVEX;
394 let ExeDomain = SSEPackedSingle in {
395 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
397 EVEX_V512, EVEX_CD8<32, CD8VT1>;
400 let ExeDomain = SSEPackedDouble in {
401 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
403 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
406 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
407 (VBROADCASTSSZrm addr:$src)>;
408 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
409 (VBROADCASTSDZrm addr:$src)>;
411 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
412 (VBROADCASTSSZrm addr:$src)>;
413 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
414 (VBROADCASTSDZrm addr:$src)>;
416 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
417 RegisterClass SrcRC, RegisterClass KRC> {
418 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
419 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
420 []>, EVEX, EVEX_V512;
421 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
422 (ins KRC:$mask, SrcRC:$src),
423 !strconcat(OpcodeStr,
424 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
425 []>, EVEX, EVEX_V512, EVEX_KZ;
428 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
429 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
432 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
433 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
435 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
436 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
438 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
439 (VPBROADCASTDrZrr GR32:$src)>;
440 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
441 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
442 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
443 (VPBROADCASTQrZrr GR64:$src)>;
444 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
445 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
447 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
448 (VPBROADCASTDrZrr GR32:$src)>;
449 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
450 (VPBROADCASTQrZrr GR64:$src)>;
452 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
453 (v16i32 immAllZerosV), (i16 GR16:$mask))),
454 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
455 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
456 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
457 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
459 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
460 X86MemOperand x86memop, PatFrag ld_frag,
461 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
463 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
464 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
466 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
467 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
469 !strconcat(OpcodeStr,
470 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
472 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
475 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
476 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
478 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
479 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
481 !strconcat(OpcodeStr,
482 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
483 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
484 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
488 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
489 loadi32, VR512, v16i32, v4i32, VK16WM>,
490 EVEX_V512, EVEX_CD8<32, CD8VT1>;
491 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
492 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
493 EVEX_CD8<64, CD8VT1>;
495 multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
496 X86MemOperand x86memop, PatFrag ld_frag,
499 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
500 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
502 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
504 !strconcat(OpcodeStr,
505 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
510 defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
511 i128mem, loadv2i64, VK16WM>,
512 EVEX_V512, EVEX_CD8<32, CD8VT4>;
513 defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
514 i256mem, loadv4i64, VK16WM>, VEX_W,
515 EVEX_V512, EVEX_CD8<64, CD8VT4>;
517 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
518 (VPBROADCASTDZrr VR128X:$src)>;
519 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
520 (VPBROADCASTQZrr VR128X:$src)>;
522 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
523 (VBROADCASTSSZrr VR128X:$src)>;
524 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
525 (VBROADCASTSDZrr VR128X:$src)>;
527 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
528 (VBROADCASTSSZrr VR128X:$src)>;
529 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
530 (VBROADCASTSDZrr VR128X:$src)>;
532 // Provide fallback in case the load node that is used in the patterns above
533 // is used by additional users, which prevents the pattern selection.
534 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
535 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
536 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
537 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
540 let Predicates = [HasAVX512] in {
541 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
543 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
544 addr:$src)), sub_ymm)>;
546 //===----------------------------------------------------------------------===//
547 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
550 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
551 RegisterClass DstRC, RegisterClass KRC,
552 ValueType OpVT, ValueType SrcVT> {
553 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
554 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
558 let Predicates = [HasCDI] in {
559 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
560 VK16, v16i32, v16i1>, EVEX_V512;
561 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
562 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
565 //===----------------------------------------------------------------------===//
568 // -- immediate form --
569 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
570 SDNode OpNode, PatFrag mem_frag,
571 X86MemOperand x86memop, ValueType OpVT> {
572 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
573 (ins RC:$src1, i8imm:$src2),
574 !strconcat(OpcodeStr,
575 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
577 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
579 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
580 (ins x86memop:$src1, i8imm:$src2),
581 !strconcat(OpcodeStr,
582 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
584 (OpVT (OpNode (mem_frag addr:$src1),
585 (i8 imm:$src2))))]>, EVEX;
588 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
589 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
590 let ExeDomain = SSEPackedDouble in
591 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
592 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
594 // -- VPERM - register form --
595 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
596 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
598 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
599 (ins RC:$src1, RC:$src2),
600 !strconcat(OpcodeStr,
601 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
603 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
605 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
606 (ins RC:$src1, x86memop:$src2),
607 !strconcat(OpcodeStr,
608 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
610 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
614 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
615 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
616 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
617 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
618 let ExeDomain = SSEPackedSingle in
619 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
620 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
621 let ExeDomain = SSEPackedDouble in
622 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
623 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
625 // -- VPERM2I - 3 source operands form --
626 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
627 PatFrag mem_frag, X86MemOperand x86memop,
628 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
629 let Constraints = "$src1 = $dst" in {
630 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
631 (ins RC:$src1, RC:$src2, RC:$src3),
632 !strconcat(OpcodeStr,
633 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
635 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
638 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
639 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
640 !strconcat(OpcodeStr,
641 " \t{$src3, $src2, $dst {${mask}}|"
642 "$dst {${mask}}, $src2, $src3}"),
643 [(set RC:$dst, (OpVT (vselect KRC:$mask,
644 (OpNode RC:$src1, RC:$src2,
649 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
650 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
651 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
652 !strconcat(OpcodeStr,
653 " \t{$src3, $src2, $dst {${mask}} {z} |",
654 "$dst {${mask}} {z}, $src2, $src3}"),
655 [(set RC:$dst, (OpVT (vselect KRC:$mask,
656 (OpNode RC:$src1, RC:$src2,
659 (v16i32 immAllZerosV))))))]>,
662 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
663 (ins RC:$src1, RC:$src2, x86memop:$src3),
664 !strconcat(OpcodeStr,
665 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
667 (OpVT (OpNode RC:$src1, RC:$src2,
668 (mem_frag addr:$src3))))]>, EVEX_4V;
670 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
671 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
672 !strconcat(OpcodeStr,
673 " \t{$src3, $src2, $dst {${mask}}|"
674 "$dst {${mask}}, $src2, $src3}"),
676 (OpVT (vselect KRC:$mask,
677 (OpNode RC:$src1, RC:$src2,
678 (mem_frag addr:$src3)),
682 let AddedComplexity = 10 in // Prefer over the rrkz variant
683 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
684 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
685 !strconcat(OpcodeStr,
686 " \t{$src3, $src2, $dst {${mask}} {z}|"
687 "$dst {${mask}} {z}, $src2, $src3}"),
689 (OpVT (vselect KRC:$mask,
690 (OpNode RC:$src1, RC:$src2,
691 (mem_frag addr:$src3)),
693 (v16i32 immAllZerosV))))))]>,
697 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32,
698 i512mem, X86VPermiv3, v16i32, VK16WM>,
699 EVEX_V512, EVEX_CD8<32, CD8VF>;
700 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64,
701 i512mem, X86VPermiv3, v8i64, VK8WM>,
702 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
703 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32,
704 i512mem, X86VPermiv3, v16f32, VK16WM>,
705 EVEX_V512, EVEX_CD8<32, CD8VF>;
706 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64,
707 i512mem, X86VPermiv3, v8f64, VK8WM>,
708 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
710 multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
711 PatFrag mem_frag, X86MemOperand x86memop,
712 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
713 ValueType MaskVT, RegisterClass MRC> :
714 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
716 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
717 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
718 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
720 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
721 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
722 (!cast<Instruction>(NAME#rrk) VR512:$src1,
723 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
726 defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, memopv16i32, i512mem,
727 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
728 EVEX_V512, EVEX_CD8<32, CD8VF>;
729 defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, memopv8i64, i512mem,
730 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
731 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
732 defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, memopv16f32, i512mem,
733 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
734 EVEX_V512, EVEX_CD8<32, CD8VF>;
735 defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, memopv8f64, i512mem,
736 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
737 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
739 //===----------------------------------------------------------------------===//
740 // AVX-512 - BLEND using mask
742 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
743 RegisterClass KRC, RegisterClass RC,
744 X86MemOperand x86memop, PatFrag mem_frag,
745 SDNode OpNode, ValueType vt> {
746 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
747 (ins KRC:$mask, RC:$src1, RC:$src2),
748 !strconcat(OpcodeStr,
749 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
750 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
751 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
753 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
754 (ins KRC:$mask, RC:$src1, x86memop:$src2),
755 !strconcat(OpcodeStr,
756 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
757 []>, EVEX_4V, EVEX_K;
760 let ExeDomain = SSEPackedSingle in
761 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
762 VK16WM, VR512, f512mem,
763 memopv16f32, vselect, v16f32>,
764 EVEX_CD8<32, CD8VF>, EVEX_V512;
765 let ExeDomain = SSEPackedDouble in
766 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
767 VK8WM, VR512, f512mem,
768 memopv8f64, vselect, v8f64>,
769 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
771 def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
772 (v16f32 VR512:$src2), (i16 GR16:$mask))),
773 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
774 VR512:$src1, VR512:$src2)>;
776 def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
777 (v8f64 VR512:$src2), (i8 GR8:$mask))),
778 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
779 VR512:$src1, VR512:$src2)>;
781 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
782 VK16WM, VR512, f512mem,
783 memopv16i32, vselect, v16i32>,
784 EVEX_CD8<32, CD8VF>, EVEX_V512;
786 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
787 VK8WM, VR512, f512mem,
788 memopv8i64, vselect, v8i64>,
789 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
791 def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
792 (v16i32 VR512:$src2), (i16 GR16:$mask))),
793 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
794 VR512:$src1, VR512:$src2)>;
796 def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
797 (v8i64 VR512:$src2), (i8 GR8:$mask))),
798 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
799 VR512:$src1, VR512:$src2)>;
801 let Predicates = [HasAVX512] in {
802 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
803 (v8f32 VR256X:$src2))),
805 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
806 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
807 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
809 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
810 (v8i32 VR256X:$src2))),
812 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
813 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
814 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
816 //===----------------------------------------------------------------------===//
817 // Compare Instructions
818 //===----------------------------------------------------------------------===//
820 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
821 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
822 Operand CC, SDNode OpNode, ValueType VT,
823 PatFrag ld_frag, string asm, string asm_alt> {
824 def rr : AVX512Ii8<0xC2, MRMSrcReg,
825 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
826 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
827 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
828 def rm : AVX512Ii8<0xC2, MRMSrcMem,
829 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
830 [(set VK1:$dst, (OpNode (VT RC:$src1),
831 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
832 let isAsmParserOnly = 1, hasSideEffects = 0 in {
833 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
834 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
835 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
836 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
837 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
838 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
842 let Predicates = [HasAVX512] in {
843 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
844 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
845 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
847 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
848 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
849 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
853 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
854 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
855 SDNode OpNode, ValueType vt> {
856 def rr : AVX512BI<opc, MRMSrcReg,
857 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
858 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
859 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
860 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
861 def rm : AVX512BI<opc, MRMSrcMem,
862 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
863 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
864 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
865 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
868 defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
869 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512,
871 defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
872 memopv8i64, X86pcmpeqm, v8i64>, T8PD, EVEX_V512,
873 VEX_W, EVEX_CD8<64, CD8VF>;
875 defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
876 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512,
878 defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
879 memopv8i64, X86pcmpgtm, v8i64>, T8PD, EVEX_V512,
880 VEX_W, EVEX_CD8<64, CD8VF>;
882 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
883 (COPY_TO_REGCLASS (VPCMPGTDZrr
884 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
885 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
887 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
888 (COPY_TO_REGCLASS (VPCMPEQDZrr
889 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
890 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
892 multiclass avx512_icmp_cc<bits<8> opc, RegisterClass WMRC, RegisterClass KRC,
893 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
894 SDNode OpNode, ValueType vt, Operand CC, string Suffix> {
895 def rri : AVX512AIi8<opc, MRMSrcReg,
896 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc),
897 !strconcat("vpcmp${cc}", Suffix,
898 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
899 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
900 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
901 def rmi : AVX512AIi8<opc, MRMSrcMem,
902 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc),
903 !strconcat("vpcmp${cc}", Suffix,
904 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
905 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
906 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
907 // Accept explicit immediate argument form instead of comparison code.
908 let isAsmParserOnly = 1, hasSideEffects = 0 in {
909 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
910 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
911 !strconcat("vpcmp", Suffix,
912 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
913 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
914 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
915 (outs KRC:$dst), (ins WMRC:$mask, RC:$src1, RC:$src2, i8imm:$cc),
916 !strconcat("vpcmp", Suffix,
917 "\t{$cc, $src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2, $cc}"),
918 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
919 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
920 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
921 !strconcat("vpcmp", Suffix,
922 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
923 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
924 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
925 (outs KRC:$dst), (ins WMRC:$mask, RC:$src1, x86memop:$src2, i8imm:$cc),
926 !strconcat("vpcmp", Suffix,
927 "\t{$cc, $src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2, $cc}"),
928 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
932 defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16WM, VK16, VR512, i512mem, memopv16i32,
933 X86cmpm, v16i32, AVXCC, "d">,
934 EVEX_V512, EVEX_CD8<32, CD8VF>;
935 defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16WM, VK16, VR512, i512mem, memopv16i32,
936 X86cmpmu, v16i32, AVXCC, "ud">,
937 EVEX_V512, EVEX_CD8<32, CD8VF>;
939 defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8WM, VK8, VR512, i512mem, memopv8i64,
940 X86cmpm, v8i64, AVXCC, "q">,
941 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
942 defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8WM, VK8, VR512, i512mem, memopv8i64,
943 X86cmpmu, v8i64, AVXCC, "uq">,
944 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
946 // avx512_cmp_packed - compare packed instructions
947 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
948 X86MemOperand x86memop, ValueType vt,
949 string suffix, Domain d> {
950 def rri : AVX512PIi8<0xC2, MRMSrcReg,
951 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
952 !strconcat("vcmp${cc}", suffix,
953 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
954 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
955 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
956 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
957 !strconcat("vcmp${cc}", suffix,
958 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
960 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
961 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
962 !strconcat("vcmp${cc}", suffix,
963 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
965 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
967 // Accept explicit immediate argument form instead of comparison code.
968 let isAsmParserOnly = 1, hasSideEffects = 0 in {
969 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
970 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
971 !strconcat("vcmp", suffix,
972 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
973 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
974 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
975 !strconcat("vcmp", suffix,
976 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
980 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
981 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
983 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
984 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
987 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
988 (COPY_TO_REGCLASS (VCMPPSZrri
989 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
990 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
992 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
993 (COPY_TO_REGCLASS (VPCMPDZrri
994 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
995 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
997 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
998 (COPY_TO_REGCLASS (VPCMPUDZrri
999 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1000 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1003 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1004 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1006 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
1007 (I8Imm imm:$cc)), GR16)>;
1009 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1010 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1012 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
1013 (I8Imm imm:$cc)), GR8)>;
1015 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1016 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1018 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1019 (I8Imm imm:$cc)), GR16)>;
1021 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1022 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1024 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1025 (I8Imm imm:$cc)), GR8)>;
1027 // Mask register copy, including
1028 // - copy between mask registers
1029 // - load/store mask registers
1030 // - copy from GPR to mask register and vice versa
1032 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1033 string OpcodeStr, RegisterClass KRC,
1034 ValueType vvt, ValueType ivt, X86MemOperand x86memop> {
1035 let hasSideEffects = 0 in {
1036 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1037 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1039 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1040 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1041 [(set KRC:$dst, (vvt (bitconvert (ivt (load addr:$src)))))]>;
1043 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1044 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1048 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1050 RegisterClass KRC, RegisterClass GRC> {
1051 let hasSideEffects = 0 in {
1052 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1053 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1054 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1055 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1059 let Predicates = [HasDQI] in
1060 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8,
1062 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1065 let Predicates = [HasAVX512] in
1066 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16,
1068 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1071 let Predicates = [HasBWI] in {
1072 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1, i32,
1073 i32mem>, VEX, PD, VEX_W;
1074 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1078 let Predicates = [HasBWI] in {
1079 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64,
1080 i64mem>, VEX, PS, VEX_W;
1081 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1085 // GR from/to mask register
1086 let Predicates = [HasDQI] in {
1087 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1088 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1089 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1090 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1092 let Predicates = [HasAVX512] in {
1093 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1094 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1095 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1096 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1098 let Predicates = [HasBWI] in {
1099 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1100 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1102 let Predicates = [HasBWI] in {
1103 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1104 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1108 let Predicates = [HasDQI] in {
1109 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1110 (KMOVBmk addr:$dst, VK8:$src)>;
1112 let Predicates = [HasAVX512] in {
1113 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1114 (KMOVWmk addr:$dst, VK16:$src)>;
1115 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1116 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1117 def : Pat<(i1 (load addr:$src)),
1118 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
1119 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1120 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1122 let Predicates = [HasBWI] in {
1123 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1124 (KMOVDmk addr:$dst, VK32:$src)>;
1126 let Predicates = [HasBWI] in {
1127 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1128 (KMOVQmk addr:$dst, VK64:$src)>;
1131 let Predicates = [HasAVX512] in {
1132 def : Pat<(i1 (trunc (i32 GR32:$src))),
1133 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1135 def : Pat<(i1 (trunc (i8 GR8:$src))),
1137 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1139 def : Pat<(i1 (trunc (i16 GR16:$src))),
1141 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1144 def : Pat<(i32 (zext VK1:$src)),
1145 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1146 def : Pat<(i8 (zext VK1:$src)),
1149 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1150 def : Pat<(i64 (zext VK1:$src)),
1151 (AND64ri8 (SUBREG_TO_REG (i64 0),
1152 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1153 def : Pat<(i16 (zext VK1:$src)),
1155 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1157 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1158 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1159 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1160 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1162 let Predicates = [HasBWI] in {
1163 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1164 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1165 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1166 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1170 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1171 let Predicates = [HasAVX512] in {
1172 // GR from/to 8-bit mask without native support
1173 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1175 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1177 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1179 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1182 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1183 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1184 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1185 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1187 let Predicates = [HasBWI] in {
1188 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1189 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1190 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1191 (COPY_TO_REGCLASS VK64:$src, VK1)>;
1194 // Mask unary operation
1196 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1197 RegisterClass KRC, SDPatternOperator OpNode,
1199 let Predicates = [prd] in
1200 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1201 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1202 [(set KRC:$dst, (OpNode KRC:$src))]>;
1205 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1206 SDPatternOperator OpNode> {
1207 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1209 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1210 HasAVX512>, VEX, PS;
1211 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1212 HasBWI>, VEX, PD, VEX_W;
1213 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1214 HasBWI>, VEX, PS, VEX_W;
1217 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
1219 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1220 let Predicates = [HasAVX512] in
1221 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1223 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1224 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1226 defm : avx512_mask_unop_int<"knot", "KNOT">;
1228 let Predicates = [HasDQI] in
1229 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1230 let Predicates = [HasAVX512] in
1231 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1232 let Predicates = [HasBWI] in
1233 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1234 let Predicates = [HasBWI] in
1235 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1237 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1238 let Predicates = [HasAVX512] in {
1239 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1240 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1242 def : Pat<(not VK8:$src),
1244 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1247 // Mask binary operation
1248 // - KAND, KANDN, KOR, KXNOR, KXOR
1249 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1250 RegisterClass KRC, SDPatternOperator OpNode,
1252 let Predicates = [prd] in
1253 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1254 !strconcat(OpcodeStr,
1255 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1256 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1259 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1260 SDPatternOperator OpNode> {
1261 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1262 HasDQI>, VEX_4V, VEX_L, PD;
1263 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1264 HasAVX512>, VEX_4V, VEX_L, PS;
1265 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1266 HasBWI>, VEX_4V, VEX_L, VEX_W, PD;
1267 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1268 HasBWI>, VEX_4V, VEX_L, VEX_W, PS;
1271 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1272 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1274 let isCommutable = 1 in {
1275 defm KAND : avx512_mask_binop_all<0x41, "kand", and>;
1276 defm KOR : avx512_mask_binop_all<0x45, "kor", or>;
1277 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>;
1278 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>;
1280 let isCommutable = 0 in
1281 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
1283 def : Pat<(xor VK1:$src1, VK1:$src2),
1284 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1285 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1287 def : Pat<(or VK1:$src1, VK1:$src2),
1288 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1289 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1291 def : Pat<(and VK1:$src1, VK1:$src2),
1292 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1293 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1295 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1296 let Predicates = [HasAVX512] in
1297 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1298 (i16 GR16:$src1), (i16 GR16:$src2)),
1299 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1300 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1301 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1304 defm : avx512_mask_binop_int<"kand", "KAND">;
1305 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1306 defm : avx512_mask_binop_int<"kor", "KOR">;
1307 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1308 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1310 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1311 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1312 let Predicates = [HasAVX512] in
1313 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1315 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1316 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1319 defm : avx512_binop_pat<and, KANDWrr>;
1320 defm : avx512_binop_pat<andn, KANDNWrr>;
1321 defm : avx512_binop_pat<or, KORWrr>;
1322 defm : avx512_binop_pat<xnor, KXNORWrr>;
1323 defm : avx512_binop_pat<xor, KXORWrr>;
1326 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1327 RegisterClass KRC> {
1328 let Predicates = [HasAVX512] in
1329 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1330 !strconcat(OpcodeStr,
1331 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1334 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1335 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1339 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1340 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1341 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1342 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1345 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1346 let Predicates = [HasAVX512] in
1347 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1348 (i16 GR16:$src1), (i16 GR16:$src2)),
1349 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1350 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1351 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1353 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1356 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1358 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1359 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1360 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"),
1361 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1364 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1365 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1369 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1371 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1372 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1373 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1376 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1378 let Predicates = [HasAVX512] in
1379 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1380 !strconcat(OpcodeStr,
1381 " \t{$imm, $src, $dst|$dst, $src, $imm}"),
1382 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1385 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1387 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1391 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1392 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1394 // Mask setting all 0s or 1s
1395 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1396 let Predicates = [HasAVX512] in
1397 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1398 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1399 [(set KRC:$dst, (VT Val))]>;
1402 multiclass avx512_mask_setop_w<PatFrag Val> {
1403 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1404 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1407 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1408 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1410 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1411 let Predicates = [HasAVX512] in {
1412 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1413 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1414 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1415 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1416 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1418 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1419 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1421 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1422 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1424 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1425 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1427 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1428 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1430 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1431 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1432 //===----------------------------------------------------------------------===//
1433 // AVX-512 - Aligned and unaligned load and store
1436 multiclass avx512_load<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1437 X86MemOperand x86memop, PatFrag ld_frag,
1438 string asm, Domain d,
1439 ValueType vt, bit IsReMaterializable = 1> {
1440 let hasSideEffects = 0 in {
1441 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1442 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), [], d>,
1444 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
1446 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1447 [], d>, EVEX, EVEX_KZ;
1449 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
1450 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1451 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1452 [(set (vt RC:$dst), (ld_frag addr:$src))], d>, EVEX;
1453 let Constraints = "$src1 = $dst", hasSideEffects = 0 in {
1454 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1455 (ins RC:$src1, KRC:$mask, RC:$src2),
1457 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1460 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1461 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1463 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1464 [], d>, EVEX, EVEX_K;
1467 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1468 (ins KRC:$mask, x86memop:$src2),
1470 " \t{$src2, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src2}"),
1471 [], d>, EVEX, EVEX_KZ;
1474 multiclass avx512_store<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1475 X86MemOperand x86memop, PatFrag store_frag,
1476 string asm, Domain d, ValueType vt> {
1477 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1478 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
1479 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), [], d>,
1481 let Constraints = "$src1 = $dst" in
1482 def alt_rrk : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1483 (ins RC:$src1, KRC:$mask, RC:$src2),
1485 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1487 def alt_rrkz : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1488 (ins KRC:$mask, RC:$src),
1490 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1491 [], d>, EVEX, EVEX_KZ;
1493 let mayStore = 1 in {
1494 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1495 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1496 [(store_frag (vt RC:$src), addr:$dst)], d>, EVEX;
1497 def mrk : AVX512PI<opc, MRMDestMem, (outs),
1498 (ins x86memop:$dst, KRC:$mask, RC:$src),
1500 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
1501 [], d>, EVEX, EVEX_K;
1502 def mrkz : AVX512PI<opc, MRMDestMem, (outs),
1503 (ins x86memop:$dst, KRC:$mask, RC:$src),
1505 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1506 [], d>, EVEX, EVEX_KZ;
1510 defm VMOVAPSZ : avx512_load<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1511 "vmovaps", SSEPackedSingle, v16f32>,
1512 avx512_store<0x29, VR512, VK16WM, f512mem, alignedstore512,
1513 "vmovaps", SSEPackedSingle, v16f32>,
1514 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1515 defm VMOVAPDZ : avx512_load<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1516 "vmovapd", SSEPackedDouble, v8f64>,
1517 avx512_store<0x29, VR512, VK8WM, f512mem, alignedstore512,
1518 "vmovapd", SSEPackedDouble, v8f64>,
1519 PD, EVEX_V512, VEX_W,
1520 EVEX_CD8<64, CD8VF>;
1521 defm VMOVUPSZ : avx512_load<0x10, VR512, VK16WM, f512mem, loadv16f32,
1522 "vmovups", SSEPackedSingle, v16f32>,
1523 avx512_store<0x11, VR512, VK16WM, f512mem, store,
1524 "vmovups", SSEPackedSingle, v16f32>,
1525 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1526 defm VMOVUPDZ : avx512_load<0x10, VR512, VK8WM, f512mem, loadv8f64,
1527 "vmovupd", SSEPackedDouble, v8f64, 0>,
1528 avx512_store<0x11, VR512, VK8WM, f512mem, store,
1529 "vmovupd", SSEPackedDouble, v8f64>,
1530 PD, EVEX_V512, VEX_W,
1531 EVEX_CD8<64, CD8VF>;
1532 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
1533 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
1534 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
1536 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
1537 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
1538 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
1540 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
1542 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
1544 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
1546 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
1549 defm VMOVDQA32: avx512_load<0x6F, VR512, VK16WM, i512mem, alignedloadv16i32,
1550 "vmovdqa32", SSEPackedInt, v16i32>,
1551 avx512_store<0x7F, VR512, VK16WM, i512mem, alignedstore512,
1552 "vmovdqa32", SSEPackedInt, v16i32>,
1553 PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1554 defm VMOVDQA64: avx512_load<0x6F, VR512, VK8WM, i512mem, alignedloadv8i64,
1555 "vmovdqa64", SSEPackedInt, v8i64>,
1556 avx512_store<0x7F, VR512, VK8WM, i512mem, alignedstore512,
1557 "vmovdqa64", SSEPackedInt, v8i64>,
1558 PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
1559 defm VMOVDQU32: avx512_load<0x6F, VR512, VK16WM, i512mem, load,
1560 "vmovdqu32", SSEPackedInt, v16i32>,
1561 avx512_store<0x7F, VR512, VK16WM, i512mem, store,
1562 "vmovdqu32", SSEPackedInt, v16i32>,
1563 XS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1564 defm VMOVDQU64: avx512_load<0x6F, VR512, VK8WM, i512mem, load,
1565 "vmovdqu64", SSEPackedInt, v8i64>,
1566 avx512_store<0x7F, VR512, VK8WM, i512mem, store,
1567 "vmovdqu64", SSEPackedInt, v8i64>,
1568 XS, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
1570 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
1571 (v16i32 immAllZerosV), GR16:$mask)),
1572 (VMOVDQU32rmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
1574 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
1575 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
1576 (VMOVDQU64rmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
1578 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
1580 (VMOVDQU32mrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
1582 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
1584 (VMOVDQU64mrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
1587 let AddedComplexity = 20 in {
1588 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
1589 (bc_v8i64 (v16i32 immAllZerosV)))),
1590 (VMOVDQU64rrkz VK8WM:$mask, VR512:$src)>;
1592 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
1593 (v8i64 VR512:$src))),
1594 (VMOVDQU64rrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
1597 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
1598 (v16i32 immAllZerosV))),
1599 (VMOVDQU32rrkz VK16WM:$mask, VR512:$src)>;
1601 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
1602 (v16i32 VR512:$src))),
1603 (VMOVDQU32rrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
1605 def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1606 (v16f32 VR512:$src2))),
1607 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1608 def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1609 (v8f64 VR512:$src2))),
1610 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1611 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1612 (v16i32 VR512:$src2))),
1613 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1614 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1615 (v8i64 VR512:$src2))),
1616 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1618 // Move Int Doubleword to Packed Double Int
1620 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1621 "vmovd\t{$src, $dst|$dst, $src}",
1623 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1625 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1626 "vmovd\t{$src, $dst|$dst, $src}",
1628 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1629 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1630 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1631 "vmovq\t{$src, $dst|$dst, $src}",
1633 (v2i64 (scalar_to_vector GR64:$src)))],
1634 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
1635 let isCodeGenOnly = 1 in {
1636 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1637 "vmovq\t{$src, $dst|$dst, $src}",
1638 [(set FR64:$dst, (bitconvert GR64:$src))],
1639 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1640 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1641 "vmovq\t{$src, $dst|$dst, $src}",
1642 [(set GR64:$dst, (bitconvert FR64:$src))],
1643 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1645 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1646 "vmovq\t{$src, $dst|$dst, $src}",
1647 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1648 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1649 EVEX_CD8<64, CD8VT1>;
1651 // Move Int Doubleword to Single Scalar
1653 let isCodeGenOnly = 1 in {
1654 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1655 "vmovd\t{$src, $dst|$dst, $src}",
1656 [(set FR32X:$dst, (bitconvert GR32:$src))],
1657 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1659 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1660 "vmovd\t{$src, $dst|$dst, $src}",
1661 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1662 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1665 // Move doubleword from xmm register to r/m32
1667 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1668 "vmovd\t{$src, $dst|$dst, $src}",
1669 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1670 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1672 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1673 (ins i32mem:$dst, VR128X:$src),
1674 "vmovd\t{$src, $dst|$dst, $src}",
1675 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1676 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1677 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1679 // Move quadword from xmm1 register to r/m64
1681 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1682 "vmovq\t{$src, $dst|$dst, $src}",
1683 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1685 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
1686 Requires<[HasAVX512, In64BitMode]>;
1688 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
1689 (ins i64mem:$dst, VR128X:$src),
1690 "vmovq\t{$src, $dst|$dst, $src}",
1691 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1692 addr:$dst)], IIC_SSE_MOVDQ>,
1693 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
1694 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1696 // Move Scalar Single to Double Int
1698 let isCodeGenOnly = 1 in {
1699 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
1701 "vmovd\t{$src, $dst|$dst, $src}",
1702 [(set GR32:$dst, (bitconvert FR32X:$src))],
1703 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1704 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1705 (ins i32mem:$dst, FR32X:$src),
1706 "vmovd\t{$src, $dst|$dst, $src}",
1707 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1708 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1711 // Move Quadword Int to Packed Quadword Int
1713 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
1715 "vmovq\t{$src, $dst|$dst, $src}",
1717 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1718 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1720 //===----------------------------------------------------------------------===//
1721 // AVX-512 MOVSS, MOVSD
1722 //===----------------------------------------------------------------------===//
1724 multiclass avx512_move_scalar <string asm, RegisterClass RC,
1725 SDNode OpNode, ValueType vt,
1726 X86MemOperand x86memop, PatFrag mem_pat> {
1727 let hasSideEffects = 0 in {
1728 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1729 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1730 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1731 (scalar_to_vector RC:$src2))))],
1732 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1733 let Constraints = "$src1 = $dst" in
1734 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
1735 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
1737 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
1738 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
1739 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1740 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1741 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1743 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1744 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1745 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1747 } //hasSideEffects = 0
1750 let ExeDomain = SSEPackedSingle in
1751 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
1752 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1754 let ExeDomain = SSEPackedDouble in
1755 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
1756 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1758 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
1759 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
1760 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
1762 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
1763 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
1764 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
1766 // For the disassembler
1767 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
1768 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1769 (ins VR128X:$src1, FR32X:$src2),
1770 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1772 XS, EVEX_4V, VEX_LIG;
1773 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1774 (ins VR128X:$src1, FR64X:$src2),
1775 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1777 XD, EVEX_4V, VEX_LIG, VEX_W;
1780 let Predicates = [HasAVX512] in {
1781 let AddedComplexity = 15 in {
1782 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1783 // MOVS{S,D} to the lower bits.
1784 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1785 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1786 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1787 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1788 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1789 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1790 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1791 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1793 // Move low f32 and clear high bits.
1794 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1795 (SUBREG_TO_REG (i32 0),
1796 (VMOVSSZrr (v4f32 (V_SET0)),
1797 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1798 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1799 (SUBREG_TO_REG (i32 0),
1800 (VMOVSSZrr (v4i32 (V_SET0)),
1801 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1804 let AddedComplexity = 20 in {
1805 // MOVSSrm zeros the high parts of the register; represent this
1806 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1807 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1808 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1809 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1810 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1811 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1812 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1814 // MOVSDrm zeros the high parts of the register; represent this
1815 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1816 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1817 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1818 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1819 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1820 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1821 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1822 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1823 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1824 def : Pat<(v2f64 (X86vzload addr:$src)),
1825 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1827 // Represent the same patterns above but in the form they appear for
1829 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1830 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
1831 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
1832 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1833 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1834 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1835 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1836 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1837 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1839 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1840 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1841 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1842 FR32X:$src)), sub_xmm)>;
1843 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1844 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1845 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1846 FR64X:$src)), sub_xmm)>;
1847 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1848 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
1849 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
1851 // Move low f64 and clear high bits.
1852 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1853 (SUBREG_TO_REG (i32 0),
1854 (VMOVSDZrr (v2f64 (V_SET0)),
1855 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1857 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1858 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1859 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1861 // Extract and store.
1862 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1864 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1865 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1867 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1869 // Shuffle with VMOVSS
1870 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1871 (VMOVSSZrr (v4i32 VR128X:$src1),
1872 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1873 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1874 (VMOVSSZrr (v4f32 VR128X:$src1),
1875 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1878 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1879 (SUBREG_TO_REG (i32 0),
1880 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1881 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1883 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1884 (SUBREG_TO_REG (i32 0),
1885 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1886 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1889 // Shuffle with VMOVSD
1890 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1891 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1892 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1893 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1894 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1895 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1896 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1897 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1900 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1901 (SUBREG_TO_REG (i32 0),
1902 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1903 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1905 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1906 (SUBREG_TO_REG (i32 0),
1907 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1908 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1911 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1912 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1913 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1914 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1915 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1916 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1917 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1918 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1921 let AddedComplexity = 15 in
1922 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1924 "vmovq\t{$src, $dst|$dst, $src}",
1925 [(set VR128X:$dst, (v2i64 (X86vzmovl
1926 (v2i64 VR128X:$src))))],
1927 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1929 let AddedComplexity = 20 in
1930 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1932 "vmovq\t{$src, $dst|$dst, $src}",
1933 [(set VR128X:$dst, (v2i64 (X86vzmovl
1934 (loadv2i64 addr:$src))))],
1935 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1936 EVEX_CD8<8, CD8VT8>;
1938 let Predicates = [HasAVX512] in {
1939 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1940 let AddedComplexity = 20 in {
1941 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1942 (VMOVDI2PDIZrm addr:$src)>;
1943 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
1944 (VMOV64toPQIZrr GR64:$src)>;
1945 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
1946 (VMOVDI2PDIZrr GR32:$src)>;
1948 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1949 (VMOVDI2PDIZrm addr:$src)>;
1950 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1951 (VMOVDI2PDIZrm addr:$src)>;
1952 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1953 (VMOVZPQILo2PQIZrm addr:$src)>;
1954 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1955 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1956 def : Pat<(v2i64 (X86vzload addr:$src)),
1957 (VMOVZPQILo2PQIZrm addr:$src)>;
1960 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1961 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1962 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1963 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1964 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1965 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1966 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1969 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
1970 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1972 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
1973 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1975 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
1976 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1978 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
1979 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1981 //===----------------------------------------------------------------------===//
1982 // AVX-512 - Non-temporals
1983 //===----------------------------------------------------------------------===//
1985 def VMOVNTDQAZrm : AVX5128I<0x2A, MRMSrcMem, (outs VR512:$dst),
1987 "vmovntdqa\t{$src, $dst|$dst, $src}",
1989 (int_x86_avx512_movntdqa addr:$src))]>,
1990 EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
1992 // Prefer non-temporal over temporal versions
1993 let AddedComplexity = 400, SchedRW = [WriteStore] in {
1995 def VMOVNTPSZmr : AVX512PSI<0x2B, MRMDestMem, (outs),
1996 (ins f512mem:$dst, VR512:$src),
1997 "vmovntps\t{$src, $dst|$dst, $src}",
1998 [(alignednontemporalstore (v16f32 VR512:$src),
2001 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2003 def VMOVNTPDZmr : AVX512PDI<0x2B, MRMDestMem, (outs),
2004 (ins f512mem:$dst, VR512:$src),
2005 "vmovntpd\t{$src, $dst|$dst, $src}",
2006 [(alignednontemporalstore (v8f64 VR512:$src),
2009 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2012 def VMOVNTDQZmr : AVX512BI<0xE7, MRMDestMem, (outs),
2013 (ins i512mem:$dst, VR512:$src),
2014 "vmovntdq\t{$src, $dst|$dst, $src}",
2015 [(alignednontemporalstore (v8i64 VR512:$src),
2018 EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
2021 //===----------------------------------------------------------------------===//
2022 // AVX-512 - Integer arithmetic
2024 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2025 ValueType OpVT, RegisterClass KRC,
2026 RegisterClass RC, PatFrag memop_frag,
2027 X86MemOperand x86memop, PatFrag scalar_mfrag,
2028 X86MemOperand x86scalar_mop, string BrdcstStr,
2029 OpndItins itins, bit IsCommutable = 0> {
2030 let isCommutable = IsCommutable in
2031 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2032 (ins RC:$src1, RC:$src2),
2033 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2034 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2036 let AddedComplexity = 30 in {
2037 let Constraints = "$src0 = $dst" in
2038 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2039 (ins RC:$src0, KRC:$mask, RC:$src1, RC:$src2),
2040 !strconcat(OpcodeStr,
2041 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2042 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2043 (OpNode (OpVT RC:$src1), (OpVT RC:$src2)),
2045 itins.rr>, EVEX_4V, EVEX_K;
2046 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2047 (ins KRC:$mask, RC:$src1, RC:$src2),
2048 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
2049 "|$dst {${mask}} {z}, $src1, $src2}"),
2050 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2051 (OpNode (OpVT RC:$src1), (OpVT RC:$src2)),
2052 (OpVT immAllZerosV))))],
2053 itins.rr>, EVEX_4V, EVEX_KZ;
2056 let mayLoad = 1 in {
2057 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2058 (ins RC:$src1, x86memop:$src2),
2059 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2060 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
2062 let AddedComplexity = 30 in {
2063 let Constraints = "$src0 = $dst" in
2064 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2065 (ins RC:$src0, KRC:$mask, RC:$src1, x86memop:$src2),
2066 !strconcat(OpcodeStr,
2067 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2068 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2069 (OpNode (OpVT RC:$src1), (memop_frag addr:$src2)),
2071 itins.rm>, EVEX_4V, EVEX_K;
2072 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2073 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2074 !strconcat(OpcodeStr,
2075 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2076 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2077 (OpNode (OpVT RC:$src1), (memop_frag addr:$src2)),
2078 (OpVT immAllZerosV))))],
2079 itins.rm>, EVEX_4V, EVEX_KZ;
2081 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2082 (ins RC:$src1, x86scalar_mop:$src2),
2083 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2084 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2085 [(set RC:$dst, (OpNode RC:$src1,
2086 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
2087 itins.rm>, EVEX_4V, EVEX_B;
2088 let AddedComplexity = 30 in {
2089 let Constraints = "$src0 = $dst" in
2090 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2091 (ins RC:$src0, KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2092 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2093 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2095 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2096 (OpNode (OpVT RC:$src1),
2097 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))),
2099 itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2100 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2101 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2102 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2103 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2105 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2106 (OpNode (OpVT RC:$src1),
2107 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))),
2108 (OpVT immAllZerosV))))],
2109 itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2114 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
2115 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
2116 PatFrag memop_frag, X86MemOperand x86memop,
2117 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
2118 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
2119 let isCommutable = IsCommutable in
2121 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2122 (ins RC:$src1, RC:$src2),
2123 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2125 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2126 (ins KRC:$mask, RC:$src1, RC:$src2),
2127 !strconcat(OpcodeStr,
2128 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2129 [], itins.rr>, EVEX_4V, EVEX_K;
2130 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2131 (ins KRC:$mask, RC:$src1, RC:$src2),
2132 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
2133 "|$dst {${mask}} {z}, $src1, $src2}"),
2134 [], itins.rr>, EVEX_4V, EVEX_KZ;
2136 let mayLoad = 1 in {
2137 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2138 (ins RC:$src1, x86memop:$src2),
2139 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2141 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2142 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2143 !strconcat(OpcodeStr,
2144 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2145 [], itins.rm>, EVEX_4V, EVEX_K;
2146 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2147 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2148 !strconcat(OpcodeStr,
2149 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2150 [], itins.rm>, EVEX_4V, EVEX_KZ;
2151 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2152 (ins RC:$src1, x86scalar_mop:$src2),
2153 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2154 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2155 [], itins.rm>, EVEX_4V, EVEX_B;
2156 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2157 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2158 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2159 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2161 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2162 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2163 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2164 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2165 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2167 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2171 defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VK16WM, VR512,
2172 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2173 SSE_INTALU_ITINS_P, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2175 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VK16WM, VR512,
2176 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2177 SSE_INTALU_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2179 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VK16WM, VR512,
2180 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2181 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2183 defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VK8WM, VR512,
2184 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2185 SSE_INTALU_ITINS_P, 1>, EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
2187 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VK8WM, VR512,
2188 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2189 SSE_INTALU_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2191 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
2192 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2193 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
2194 EVEX_CD8<64, CD8VF>, VEX_W;
2196 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
2197 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2198 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
2200 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
2201 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2203 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
2204 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2205 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2206 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
2207 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2208 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
2210 defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VK16WM, VR512,
2211 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2212 SSE_INTALU_ITINS_P, 1>,
2213 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2214 defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VK8WM, VR512,
2215 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2216 SSE_INTALU_ITINS_P, 0>,
2217 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2219 defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VK16WM, VR512,
2220 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2221 SSE_INTALU_ITINS_P, 1>,
2222 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2223 defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VK8WM, VR512,
2224 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2225 SSE_INTALU_ITINS_P, 0>,
2226 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2228 defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VK16WM, VR512,
2229 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2230 SSE_INTALU_ITINS_P, 1>,
2231 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2232 defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VK8WM, VR512,
2233 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2234 SSE_INTALU_ITINS_P, 0>,
2235 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2237 defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VK16WM, VR512,
2238 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2239 SSE_INTALU_ITINS_P, 1>,
2240 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2241 defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VK8WM, VR512,
2242 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2243 SSE_INTALU_ITINS_P, 0>,
2244 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2246 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
2247 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2248 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
2249 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
2250 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2251 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
2252 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
2253 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2254 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
2255 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
2256 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2257 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
2258 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
2259 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2260 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
2261 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
2262 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2263 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
2264 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
2265 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2266 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
2267 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
2268 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2269 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
2270 //===----------------------------------------------------------------------===//
2271 // AVX-512 - Unpack Instructions
2272 //===----------------------------------------------------------------------===//
2274 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
2275 PatFrag mem_frag, RegisterClass RC,
2276 X86MemOperand x86memop, string asm,
2278 def rr : AVX512PI<opc, MRMSrcReg,
2279 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2281 (vt (OpNode RC:$src1, RC:$src2)))],
2283 def rm : AVX512PI<opc, MRMSrcMem,
2284 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2286 (vt (OpNode RC:$src1,
2287 (bitconvert (mem_frag addr:$src2)))))],
2291 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
2292 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2293 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2294 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
2295 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2296 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2297 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
2298 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2299 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2300 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
2301 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2302 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2304 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
2305 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2306 X86MemOperand x86memop> {
2307 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2308 (ins RC:$src1, RC:$src2),
2309 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2310 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2311 IIC_SSE_UNPCK>, EVEX_4V;
2312 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2313 (ins RC:$src1, x86memop:$src2),
2314 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2315 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
2316 (bitconvert (memop_frag addr:$src2)))))],
2317 IIC_SSE_UNPCK>, EVEX_4V;
2319 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
2320 VR512, memopv16i32, i512mem>, EVEX_V512,
2321 EVEX_CD8<32, CD8VF>;
2322 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
2323 VR512, memopv8i64, i512mem>, EVEX_V512,
2324 VEX_W, EVEX_CD8<64, CD8VF>;
2325 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
2326 VR512, memopv16i32, i512mem>, EVEX_V512,
2327 EVEX_CD8<32, CD8VF>;
2328 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
2329 VR512, memopv8i64, i512mem>, EVEX_V512,
2330 VEX_W, EVEX_CD8<64, CD8VF>;
2331 //===----------------------------------------------------------------------===//
2335 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
2336 SDNode OpNode, PatFrag mem_frag,
2337 X86MemOperand x86memop, ValueType OpVT> {
2338 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
2339 (ins RC:$src1, i8imm:$src2),
2340 !strconcat(OpcodeStr,
2341 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2343 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
2345 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
2346 (ins x86memop:$src1, i8imm:$src2),
2347 !strconcat(OpcodeStr,
2348 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2350 (OpVT (OpNode (mem_frag addr:$src1),
2351 (i8 imm:$src2))))]>, EVEX;
2354 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
2355 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2357 let ExeDomain = SSEPackedSingle in
2358 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
2359 memopv16f32, i512mem, v16f32>, TAPD, EVEX_V512,
2360 EVEX_CD8<32, CD8VF>;
2361 let ExeDomain = SSEPackedDouble in
2362 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
2363 memopv8f64, i512mem, v8f64>, TAPD, EVEX_V512,
2364 VEX_W, EVEX_CD8<32, CD8VF>;
2366 def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
2367 (VPERMILPSZri VR512:$src1, imm:$imm)>;
2368 def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
2369 (VPERMILPDZri VR512:$src1, imm:$imm)>;
2371 //===----------------------------------------------------------------------===//
2372 // AVX-512 Logical Instructions
2373 //===----------------------------------------------------------------------===//
2375 defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VK16WM, VR512, memopv16i32,
2376 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2377 EVEX_V512, EVEX_CD8<32, CD8VF>;
2378 defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VK8WM, VR512, memopv8i64,
2379 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2380 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2381 defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VK16WM, VR512, memopv16i32,
2382 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2383 EVEX_V512, EVEX_CD8<32, CD8VF>;
2384 defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VK8WM, VR512, memopv8i64,
2385 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2386 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2387 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VK16WM, VR512, memopv16i32,
2388 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2389 EVEX_V512, EVEX_CD8<32, CD8VF>;
2390 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VK8WM, VR512, memopv8i64,
2391 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2392 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2393 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VK16WM, VR512,
2394 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2395 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2396 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VK8WM, VR512,
2397 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2398 SSE_BIT_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2400 //===----------------------------------------------------------------------===//
2401 // AVX-512 FP arithmetic
2402 //===----------------------------------------------------------------------===//
2404 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2406 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
2407 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
2408 EVEX_CD8<32, CD8VT1>;
2409 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
2410 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
2411 EVEX_CD8<64, CD8VT1>;
2414 let isCommutable = 1 in {
2415 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
2416 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
2417 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
2418 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
2420 let isCommutable = 0 in {
2421 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
2422 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
2425 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2427 RegisterClass RC, ValueType vt,
2428 X86MemOperand x86memop, PatFrag mem_frag,
2429 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2431 Domain d, OpndItins itins, bit commutable> {
2432 let isCommutable = commutable in {
2433 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2434 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2435 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
2438 def rrk: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2439 !strconcat(OpcodeStr,
2440 " \t{$src2, $src1, $dst {${mask}} |$dst {${mask}}, $src1, $src2}"),
2441 [], itins.rr, d>, EVEX_4V, EVEX_K;
2443 def rrkz: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2444 !strconcat(OpcodeStr,
2445 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2446 [], itins.rr, d>, EVEX_4V, EVEX_KZ;
2449 let mayLoad = 1 in {
2450 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2451 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2452 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
2453 itins.rm, d>, EVEX_4V;
2455 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
2456 (ins RC:$src1, x86scalar_mop:$src2),
2457 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2458 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2459 [(set RC:$dst, (OpNode RC:$src1,
2460 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
2461 itins.rm, d>, EVEX_4V, EVEX_B;
2463 def rmk : PI<opc, MRMSrcMem, (outs RC:$dst),
2464 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2465 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2466 [], itins.rm, d>, EVEX_4V, EVEX_K;
2468 def rmkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2469 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2470 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2471 [], itins.rm, d>, EVEX_4V, EVEX_KZ;
2473 def rmbk : PI<opc, MRMSrcMem, (outs RC:$dst),
2474 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2475 " \t{${src2}", BrdcstStr,
2476 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}", BrdcstStr, "}"),
2477 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_K;
2479 def rmbkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2480 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2481 " \t{${src2}", BrdcstStr,
2482 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2484 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_KZ;
2488 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VK16WM, VR512, v16f32, f512mem,
2489 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2490 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2492 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VK8WM, VR512, v8f64, f512mem,
2493 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2494 SSE_ALU_ITINS_P.d, 1>,
2495 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2497 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VK16WM, VR512, v16f32, f512mem,
2498 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2499 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2500 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VK8WM, VR512, v8f64, f512mem,
2501 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2502 SSE_ALU_ITINS_P.d, 1>,
2503 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2505 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VK16WM, VR512, v16f32, f512mem,
2506 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2507 SSE_ALU_ITINS_P.s, 1>,
2508 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2509 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VK16WM, VR512, v16f32, f512mem,
2510 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2511 SSE_ALU_ITINS_P.s, 1>,
2512 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2514 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VK8WM, VR512, v8f64, f512mem,
2515 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2516 SSE_ALU_ITINS_P.d, 1>,
2517 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2518 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VK8WM, VR512, v8f64, f512mem,
2519 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2520 SSE_ALU_ITINS_P.d, 1>,
2521 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2523 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VK16WM, VR512, v16f32, f512mem,
2524 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2525 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2526 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VK16WM, VR512, v16f32, f512mem,
2527 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2528 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2530 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VK8WM, VR512, v8f64, f512mem,
2531 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2532 SSE_ALU_ITINS_P.d, 0>,
2533 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2534 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VK8WM, VR512, v8f64, f512mem,
2535 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2536 SSE_ALU_ITINS_P.d, 0>,
2537 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2539 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
2540 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2541 (i16 -1), FROUND_CURRENT)),
2542 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
2544 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
2545 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2546 (i8 -1), FROUND_CURRENT)),
2547 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
2549 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
2550 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2551 (i16 -1), FROUND_CURRENT)),
2552 (VMINPSZrr VR512:$src1, VR512:$src2)>;
2554 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
2555 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2556 (i8 -1), FROUND_CURRENT)),
2557 (VMINPDZrr VR512:$src1, VR512:$src2)>;
2558 //===----------------------------------------------------------------------===//
2559 // AVX-512 VPTESTM instructions
2560 //===----------------------------------------------------------------------===//
2562 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2563 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
2564 SDNode OpNode, ValueType vt> {
2565 def rr : AVX512PI<opc, MRMSrcReg,
2566 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
2567 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2568 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
2569 SSEPackedInt>, EVEX_4V;
2570 def rm : AVX512PI<opc, MRMSrcMem,
2571 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
2572 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2573 [(set KRC:$dst, (OpNode (vt RC:$src1),
2574 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
2577 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
2578 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
2579 EVEX_CD8<32, CD8VF>;
2580 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
2581 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
2582 EVEX_CD8<64, CD8VF>;
2584 let Predicates = [HasCDI] in {
2585 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
2586 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
2587 EVEX_CD8<32, CD8VF>;
2588 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
2589 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
2590 EVEX_CD8<64, CD8VF>;
2593 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
2594 (v16i32 VR512:$src2), (i16 -1))),
2595 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
2597 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
2598 (v8i64 VR512:$src2), (i8 -1))),
2599 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
2600 //===----------------------------------------------------------------------===//
2601 // AVX-512 Shift instructions
2602 //===----------------------------------------------------------------------===//
2603 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
2604 string OpcodeStr, SDNode OpNode, RegisterClass RC,
2605 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
2606 RegisterClass KRC> {
2607 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2608 (ins RC:$src1, i8imm:$src2),
2609 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2610 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
2611 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2612 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2613 (ins KRC:$mask, RC:$src1, i8imm:$src2),
2614 !strconcat(OpcodeStr,
2615 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2616 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2617 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2618 (ins x86memop:$src1, i8imm:$src2),
2619 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2620 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
2621 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2622 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2623 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
2624 !strconcat(OpcodeStr,
2625 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2626 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2629 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2630 RegisterClass RC, ValueType vt, ValueType SrcVT,
2631 PatFrag bc_frag, RegisterClass KRC> {
2632 // src2 is always 128-bit
2633 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2634 (ins RC:$src1, VR128X:$src2),
2635 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2636 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
2637 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2638 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2639 (ins KRC:$mask, RC:$src1, VR128X:$src2),
2640 !strconcat(OpcodeStr,
2641 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2642 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2643 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2644 (ins RC:$src1, i128mem:$src2),
2645 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2646 [(set RC:$dst, (vt (OpNode RC:$src1,
2647 (bc_frag (memopv2i64 addr:$src2)))))],
2648 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2649 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2650 (ins KRC:$mask, RC:$src1, i128mem:$src2),
2651 !strconcat(OpcodeStr,
2652 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2653 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2656 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
2657 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2658 EVEX_V512, EVEX_CD8<32, CD8VF>;
2659 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
2660 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2661 EVEX_CD8<32, CD8VQ>;
2663 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
2664 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2665 EVEX_CD8<64, CD8VF>, VEX_W;
2666 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
2667 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2668 EVEX_CD8<64, CD8VQ>, VEX_W;
2670 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
2671 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
2672 EVEX_CD8<32, CD8VF>;
2673 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
2674 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2675 EVEX_CD8<32, CD8VQ>;
2677 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
2678 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2679 EVEX_CD8<64, CD8VF>, VEX_W;
2680 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
2681 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2682 EVEX_CD8<64, CD8VQ>, VEX_W;
2684 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
2685 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2686 EVEX_V512, EVEX_CD8<32, CD8VF>;
2687 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
2688 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2689 EVEX_CD8<32, CD8VQ>;
2691 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
2692 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2693 EVEX_CD8<64, CD8VF>, VEX_W;
2694 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
2695 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2696 EVEX_CD8<64, CD8VQ>, VEX_W;
2698 //===-------------------------------------------------------------------===//
2699 // Variable Bit Shifts
2700 //===-------------------------------------------------------------------===//
2701 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
2702 RegisterClass RC, ValueType vt,
2703 X86MemOperand x86memop, PatFrag mem_frag> {
2704 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
2705 (ins RC:$src1, RC:$src2),
2706 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2708 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
2710 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
2711 (ins RC:$src1, x86memop:$src2),
2712 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2714 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
2718 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
2719 i512mem, memopv16i32>, EVEX_V512,
2720 EVEX_CD8<32, CD8VF>;
2721 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
2722 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2723 EVEX_CD8<64, CD8VF>;
2724 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
2725 i512mem, memopv16i32>, EVEX_V512,
2726 EVEX_CD8<32, CD8VF>;
2727 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
2728 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2729 EVEX_CD8<64, CD8VF>;
2730 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
2731 i512mem, memopv16i32>, EVEX_V512,
2732 EVEX_CD8<32, CD8VF>;
2733 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
2734 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2735 EVEX_CD8<64, CD8VF>;
2737 //===----------------------------------------------------------------------===//
2738 // AVX-512 - MOVDDUP
2739 //===----------------------------------------------------------------------===//
2741 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
2742 X86MemOperand x86memop, PatFrag memop_frag> {
2743 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2744 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2745 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
2746 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2747 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2749 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
2752 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
2753 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
2754 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
2755 (VMOVDDUPZrm addr:$src)>;
2757 //===---------------------------------------------------------------------===//
2758 // Replicate Single FP - MOVSHDUP and MOVSLDUP
2759 //===---------------------------------------------------------------------===//
2760 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
2761 ValueType vt, RegisterClass RC, PatFrag mem_frag,
2762 X86MemOperand x86memop> {
2763 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2764 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2765 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
2767 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2768 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2769 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
2772 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
2773 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2774 EVEX_CD8<32, CD8VF>;
2775 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
2776 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2777 EVEX_CD8<32, CD8VF>;
2779 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
2780 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
2781 (VMOVSHDUPZrm addr:$src)>;
2782 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
2783 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
2784 (VMOVSLDUPZrm addr:$src)>;
2786 //===----------------------------------------------------------------------===//
2787 // Move Low to High and High to Low packed FP Instructions
2788 //===----------------------------------------------------------------------===//
2789 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
2790 (ins VR128X:$src1, VR128X:$src2),
2791 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2792 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2793 IIC_SSE_MOV_LH>, EVEX_4V;
2794 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2795 (ins VR128X:$src1, VR128X:$src2),
2796 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2797 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2798 IIC_SSE_MOV_LH>, EVEX_4V;
2800 let Predicates = [HasAVX512] in {
2802 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2803 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2804 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2805 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
2808 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2809 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2812 //===----------------------------------------------------------------------===//
2813 // FMA - Fused Multiply Operations
2815 let Constraints = "$src1 = $dst" in {
2816 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2817 RegisterClass RC, X86MemOperand x86memop,
2818 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2819 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2820 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2821 (ins RC:$src1, RC:$src2, RC:$src3),
2822 !strconcat(OpcodeStr," \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2823 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2826 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2827 (ins RC:$src1, RC:$src2, x86memop:$src3),
2828 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2829 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2830 (mem_frag addr:$src3))))]>;
2831 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2832 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2833 !strconcat(OpcodeStr, " \t{${src3}", BrdcstStr,
2834 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2835 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2836 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2838 } // Constraints = "$src1 = $dst"
2840 let ExeDomain = SSEPackedSingle in {
2841 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2842 memopv16f32, f32mem, loadf32, "{1to16}",
2843 X86Fmadd, v16f32>, EVEX_V512,
2844 EVEX_CD8<32, CD8VF>;
2845 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2846 memopv16f32, f32mem, loadf32, "{1to16}",
2847 X86Fmsub, v16f32>, EVEX_V512,
2848 EVEX_CD8<32, CD8VF>;
2849 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2850 memopv16f32, f32mem, loadf32, "{1to16}",
2851 X86Fmaddsub, v16f32>,
2852 EVEX_V512, EVEX_CD8<32, CD8VF>;
2853 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2854 memopv16f32, f32mem, loadf32, "{1to16}",
2855 X86Fmsubadd, v16f32>,
2856 EVEX_V512, EVEX_CD8<32, CD8VF>;
2857 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2858 memopv16f32, f32mem, loadf32, "{1to16}",
2859 X86Fnmadd, v16f32>, EVEX_V512,
2860 EVEX_CD8<32, CD8VF>;
2861 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2862 memopv16f32, f32mem, loadf32, "{1to16}",
2863 X86Fnmsub, v16f32>, EVEX_V512,
2864 EVEX_CD8<32, CD8VF>;
2866 let ExeDomain = SSEPackedDouble in {
2867 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2868 memopv8f64, f64mem, loadf64, "{1to8}",
2869 X86Fmadd, v8f64>, EVEX_V512,
2870 VEX_W, EVEX_CD8<64, CD8VF>;
2871 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2872 memopv8f64, f64mem, loadf64, "{1to8}",
2873 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2874 EVEX_CD8<64, CD8VF>;
2875 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2876 memopv8f64, f64mem, loadf64, "{1to8}",
2877 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2878 EVEX_CD8<64, CD8VF>;
2879 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2880 memopv8f64, f64mem, loadf64, "{1to8}",
2881 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2882 EVEX_CD8<64, CD8VF>;
2883 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2884 memopv8f64, f64mem, loadf64, "{1to8}",
2885 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2886 EVEX_CD8<64, CD8VF>;
2887 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2888 memopv8f64, f64mem, loadf64, "{1to8}",
2889 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2890 EVEX_CD8<64, CD8VF>;
2893 let Constraints = "$src1 = $dst" in {
2894 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2895 RegisterClass RC, X86MemOperand x86memop,
2896 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2897 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2899 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2900 (ins RC:$src1, RC:$src3, x86memop:$src2),
2901 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2902 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2903 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2904 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2905 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2906 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2907 [(set RC:$dst, (OpNode RC:$src1,
2908 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2910 } // Constraints = "$src1 = $dst"
2913 let ExeDomain = SSEPackedSingle in {
2914 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2915 memopv16f32, f32mem, loadf32, "{1to16}",
2916 X86Fmadd, v16f32>, EVEX_V512,
2917 EVEX_CD8<32, CD8VF>;
2918 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2919 memopv16f32, f32mem, loadf32, "{1to16}",
2920 X86Fmsub, v16f32>, EVEX_V512,
2921 EVEX_CD8<32, CD8VF>;
2922 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
2923 memopv16f32, f32mem, loadf32, "{1to16}",
2924 X86Fmaddsub, v16f32>,
2925 EVEX_V512, EVEX_CD8<32, CD8VF>;
2926 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
2927 memopv16f32, f32mem, loadf32, "{1to16}",
2928 X86Fmsubadd, v16f32>,
2929 EVEX_V512, EVEX_CD8<32, CD8VF>;
2930 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
2931 memopv16f32, f32mem, loadf32, "{1to16}",
2932 X86Fnmadd, v16f32>, EVEX_V512,
2933 EVEX_CD8<32, CD8VF>;
2934 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
2935 memopv16f32, f32mem, loadf32, "{1to16}",
2936 X86Fnmsub, v16f32>, EVEX_V512,
2937 EVEX_CD8<32, CD8VF>;
2939 let ExeDomain = SSEPackedDouble in {
2940 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
2941 memopv8f64, f64mem, loadf64, "{1to8}",
2942 X86Fmadd, v8f64>, EVEX_V512,
2943 VEX_W, EVEX_CD8<64, CD8VF>;
2944 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
2945 memopv8f64, f64mem, loadf64, "{1to8}",
2946 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2947 EVEX_CD8<64, CD8VF>;
2948 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
2949 memopv8f64, f64mem, loadf64, "{1to8}",
2950 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2951 EVEX_CD8<64, CD8VF>;
2952 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
2953 memopv8f64, f64mem, loadf64, "{1to8}",
2954 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2955 EVEX_CD8<64, CD8VF>;
2956 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
2957 memopv8f64, f64mem, loadf64, "{1to8}",
2958 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2959 EVEX_CD8<64, CD8VF>;
2960 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
2961 memopv8f64, f64mem, loadf64, "{1to8}",
2962 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2963 EVEX_CD8<64, CD8VF>;
2967 let Constraints = "$src1 = $dst" in {
2968 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2969 RegisterClass RC, ValueType OpVT,
2970 X86MemOperand x86memop, Operand memop,
2972 let isCommutable = 1 in
2973 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2974 (ins RC:$src1, RC:$src2, RC:$src3),
2975 !strconcat(OpcodeStr,
2976 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2978 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
2980 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2981 (ins RC:$src1, RC:$src2, f128mem:$src3),
2982 !strconcat(OpcodeStr,
2983 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2985 (OpVT (OpNode RC:$src2, RC:$src1,
2986 (mem_frag addr:$src3))))]>;
2989 } // Constraints = "$src1 = $dst"
2991 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
2992 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2993 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
2994 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2995 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
2996 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2997 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
2998 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2999 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
3000 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3001 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
3002 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3003 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
3004 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3005 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
3006 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3008 //===----------------------------------------------------------------------===//
3009 // AVX-512 Scalar convert from sign integer to float/double
3010 //===----------------------------------------------------------------------===//
3012 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3013 X86MemOperand x86memop, string asm> {
3014 let hasSideEffects = 0 in {
3015 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
3016 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3019 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
3020 (ins DstRC:$src1, x86memop:$src),
3021 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3023 } // hasSideEffects = 0
3025 let Predicates = [HasAVX512] in {
3026 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
3027 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3028 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
3029 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3030 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
3031 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3032 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
3033 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3035 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
3036 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3037 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
3038 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3039 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
3040 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3041 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
3042 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3044 def : Pat<(f32 (sint_to_fp GR32:$src)),
3045 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3046 def : Pat<(f32 (sint_to_fp GR64:$src)),
3047 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3048 def : Pat<(f64 (sint_to_fp GR32:$src)),
3049 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3050 def : Pat<(f64 (sint_to_fp GR64:$src)),
3051 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3053 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
3054 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3055 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
3056 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3057 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
3058 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3059 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
3060 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3062 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
3063 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3064 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
3065 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3066 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
3067 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3068 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
3069 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3071 def : Pat<(f32 (uint_to_fp GR32:$src)),
3072 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3073 def : Pat<(f32 (uint_to_fp GR64:$src)),
3074 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3075 def : Pat<(f64 (uint_to_fp GR32:$src)),
3076 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3077 def : Pat<(f64 (uint_to_fp GR64:$src)),
3078 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3081 //===----------------------------------------------------------------------===//
3082 // AVX-512 Scalar convert from float/double to integer
3083 //===----------------------------------------------------------------------===//
3084 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3085 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
3087 let hasSideEffects = 0 in {
3088 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3089 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3090 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
3091 Requires<[HasAVX512]>;
3093 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
3094 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
3095 Requires<[HasAVX512]>;
3096 } // hasSideEffects = 0
3098 let Predicates = [HasAVX512] in {
3099 // Convert float/double to signed/unsigned int 32/64
3100 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
3101 ssmem, sse_load_f32, "cvtss2si">,
3102 XS, EVEX_CD8<32, CD8VT1>;
3103 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
3104 ssmem, sse_load_f32, "cvtss2si">,
3105 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3106 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
3107 ssmem, sse_load_f32, "cvtss2usi">,
3108 XS, EVEX_CD8<32, CD8VT1>;
3109 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3110 int_x86_avx512_cvtss2usi64, ssmem,
3111 sse_load_f32, "cvtss2usi">, XS, VEX_W,
3112 EVEX_CD8<32, CD8VT1>;
3113 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
3114 sdmem, sse_load_f64, "cvtsd2si">,
3115 XD, EVEX_CD8<64, CD8VT1>;
3116 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
3117 sdmem, sse_load_f64, "cvtsd2si">,
3118 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3119 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
3120 sdmem, sse_load_f64, "cvtsd2usi">,
3121 XD, EVEX_CD8<64, CD8VT1>;
3122 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3123 int_x86_avx512_cvtsd2usi64, sdmem,
3124 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
3125 EVEX_CD8<64, CD8VT1>;
3127 let isCodeGenOnly = 1 in {
3128 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3129 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3130 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3131 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3132 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3133 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3134 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3135 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3136 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3137 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3138 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3139 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3141 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3142 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3143 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3144 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3145 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3146 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3147 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3148 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3149 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3150 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3151 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3152 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3153 } // isCodeGenOnly = 1
3155 // Convert float/double to signed/unsigned int 32/64 with truncation
3156 let isCodeGenOnly = 1 in {
3157 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3158 ssmem, sse_load_f32, "cvttss2si">,
3159 XS, EVEX_CD8<32, CD8VT1>;
3160 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3161 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3162 "cvttss2si">, XS, VEX_W,
3163 EVEX_CD8<32, CD8VT1>;
3164 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3165 sdmem, sse_load_f64, "cvttsd2si">, XD,
3166 EVEX_CD8<64, CD8VT1>;
3167 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3168 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3169 "cvttsd2si">, XD, VEX_W,
3170 EVEX_CD8<64, CD8VT1>;
3171 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3172 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3173 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3174 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3175 int_x86_avx512_cvttss2usi64, ssmem,
3176 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3177 EVEX_CD8<32, CD8VT1>;
3178 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3179 int_x86_avx512_cvttsd2usi,
3180 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3181 EVEX_CD8<64, CD8VT1>;
3182 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3183 int_x86_avx512_cvttsd2usi64, sdmem,
3184 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3185 EVEX_CD8<64, CD8VT1>;
3186 } // isCodeGenOnly = 1
3188 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3189 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3191 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3192 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3193 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3194 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3195 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3196 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3199 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
3200 loadf32, "cvttss2si">, XS,
3201 EVEX_CD8<32, CD8VT1>;
3202 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
3203 loadf32, "cvttss2usi">, XS,
3204 EVEX_CD8<32, CD8VT1>;
3205 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
3206 loadf32, "cvttss2si">, XS, VEX_W,
3207 EVEX_CD8<32, CD8VT1>;
3208 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
3209 loadf32, "cvttss2usi">, XS, VEX_W,
3210 EVEX_CD8<32, CD8VT1>;
3211 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
3212 loadf64, "cvttsd2si">, XD,
3213 EVEX_CD8<64, CD8VT1>;
3214 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
3215 loadf64, "cvttsd2usi">, XD,
3216 EVEX_CD8<64, CD8VT1>;
3217 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
3218 loadf64, "cvttsd2si">, XD, VEX_W,
3219 EVEX_CD8<64, CD8VT1>;
3220 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
3221 loadf64, "cvttsd2usi">, XD, VEX_W,
3222 EVEX_CD8<64, CD8VT1>;
3224 //===----------------------------------------------------------------------===//
3225 // AVX-512 Convert form float to double and back
3226 //===----------------------------------------------------------------------===//
3227 let hasSideEffects = 0 in {
3228 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3229 (ins FR32X:$src1, FR32X:$src2),
3230 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3231 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3233 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3234 (ins FR32X:$src1, f32mem:$src2),
3235 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3236 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3237 EVEX_CD8<32, CD8VT1>;
3239 // Convert scalar double to scalar single
3240 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3241 (ins FR64X:$src1, FR64X:$src2),
3242 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3243 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3245 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3246 (ins FR64X:$src1, f64mem:$src2),
3247 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3248 []>, EVEX_4V, VEX_LIG, VEX_W,
3249 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3252 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3253 Requires<[HasAVX512]>;
3254 def : Pat<(fextend (loadf32 addr:$src)),
3255 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3257 def : Pat<(extloadf32 addr:$src),
3258 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3259 Requires<[HasAVX512, OptForSize]>;
3261 def : Pat<(extloadf32 addr:$src),
3262 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3263 Requires<[HasAVX512, OptForSpeed]>;
3265 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3266 Requires<[HasAVX512]>;
3268 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
3269 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3270 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3272 let hasSideEffects = 0 in {
3273 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3274 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3276 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3277 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3278 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3279 [], d>, EVEX, EVEX_B, EVEX_RC;
3281 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3282 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3284 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3285 } // hasSideEffects = 0
3288 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
3289 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3290 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3292 let hasSideEffects = 0 in {
3293 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3294 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3296 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3298 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3299 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3301 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3302 } // hasSideEffects = 0
3305 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
3306 memopv8f64, f512mem, v8f32, v8f64,
3307 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
3308 EVEX_CD8<64, CD8VF>;
3310 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3311 memopv4f64, f256mem, v8f64, v8f32,
3312 SSEPackedDouble>, EVEX_V512, PS,
3313 EVEX_CD8<32, CD8VH>;
3314 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3315 (VCVTPS2PDZrm addr:$src)>;
3317 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3318 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3319 (VCVTPD2PSZrr VR512:$src)>;
3321 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3322 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3323 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
3325 //===----------------------------------------------------------------------===//
3326 // AVX-512 Vector convert from sign integer to float/double
3327 //===----------------------------------------------------------------------===//
3329 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
3330 memopv8i64, i512mem, v16f32, v16i32,
3331 SSEPackedSingle>, EVEX_V512, PS,
3332 EVEX_CD8<32, CD8VF>;
3334 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
3335 memopv4i64, i256mem, v8f64, v8i32,
3336 SSEPackedDouble>, EVEX_V512, XS,
3337 EVEX_CD8<32, CD8VH>;
3339 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
3340 memopv16f32, f512mem, v16i32, v16f32,
3341 SSEPackedSingle>, EVEX_V512, XS,
3342 EVEX_CD8<32, CD8VF>;
3344 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
3345 memopv8f64, f512mem, v8i32, v8f64,
3346 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
3347 EVEX_CD8<64, CD8VF>;
3349 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
3350 memopv16f32, f512mem, v16i32, v16f32,
3351 SSEPackedSingle>, EVEX_V512, PS,
3352 EVEX_CD8<32, CD8VF>;
3354 // cvttps2udq (src, 0, mask-all-ones, sae-current)
3355 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
3356 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
3357 (VCVTTPS2UDQZrr VR512:$src)>;
3359 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
3360 memopv8f64, f512mem, v8i32, v8f64,
3361 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
3362 EVEX_CD8<64, CD8VF>;
3364 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
3365 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
3366 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
3367 (VCVTTPD2UDQZrr VR512:$src)>;
3369 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
3370 memopv4i64, f256mem, v8f64, v8i32,
3371 SSEPackedDouble>, EVEX_V512, XS,
3372 EVEX_CD8<32, CD8VH>;
3374 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
3375 memopv16i32, f512mem, v16f32, v16i32,
3376 SSEPackedSingle>, EVEX_V512, XD,
3377 EVEX_CD8<32, CD8VF>;
3379 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
3380 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3381 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3383 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
3384 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3385 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3387 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
3388 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3389 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3391 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
3392 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3393 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3395 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
3396 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
3397 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
3399 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
3400 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3401 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
3402 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
3403 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3404 (VCVTDQ2PDZrr VR256X:$src)>;
3405 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
3406 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3407 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
3408 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
3409 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3410 (VCVTUDQ2PDZrr VR256X:$src)>;
3412 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
3413 RegisterClass DstRC, PatFrag mem_frag,
3414 X86MemOperand x86memop, Domain d> {
3415 let hasSideEffects = 0 in {
3416 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3417 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3419 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3420 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3421 [], d>, EVEX, EVEX_B, EVEX_RC;
3423 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3424 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3426 } // hasSideEffects = 0
3429 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
3430 memopv16f32, f512mem, SSEPackedSingle>, PD,
3431 EVEX_V512, EVEX_CD8<32, CD8VF>;
3432 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
3433 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
3434 EVEX_V512, EVEX_CD8<64, CD8VF>;
3436 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
3437 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3438 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
3440 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
3441 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3442 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
3444 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
3445 memopv16f32, f512mem, SSEPackedSingle>,
3446 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3447 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
3448 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
3449 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
3451 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
3452 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3453 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
3455 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
3456 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3457 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
3459 let Predicates = [HasAVX512] in {
3460 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
3461 (VCVTPD2PSZrm addr:$src)>;
3462 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3463 (VCVTPS2PDZrm addr:$src)>;
3466 //===----------------------------------------------------------------------===//
3467 // Half precision conversion instructions
3468 //===----------------------------------------------------------------------===//
3469 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
3470 X86MemOperand x86memop> {
3471 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
3472 "vcvtph2ps\t{$src, $dst|$dst, $src}",
3474 let hasSideEffects = 0, mayLoad = 1 in
3475 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
3476 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
3479 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
3480 X86MemOperand x86memop> {
3481 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
3482 (ins srcRC:$src1, i32i8imm:$src2),
3483 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}",
3485 let hasSideEffects = 0, mayStore = 1 in
3486 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
3487 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
3488 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
3491 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
3492 EVEX_CD8<32, CD8VH>;
3493 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
3494 EVEX_CD8<32, CD8VH>;
3496 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
3497 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
3498 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
3500 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
3501 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
3502 (VCVTPH2PSZrr VR256X:$src)>;
3504 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
3505 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
3506 "ucomiss">, PS, EVEX, VEX_LIG,
3507 EVEX_CD8<32, CD8VT1>;
3508 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
3509 "ucomisd">, PD, EVEX,
3510 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3511 let Pattern = []<dag> in {
3512 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
3513 "comiss">, PS, EVEX, VEX_LIG,
3514 EVEX_CD8<32, CD8VT1>;
3515 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
3516 "comisd">, PD, EVEX,
3517 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3519 let isCodeGenOnly = 1 in {
3520 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
3521 load, "ucomiss">, PS, EVEX, VEX_LIG,
3522 EVEX_CD8<32, CD8VT1>;
3523 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
3524 load, "ucomisd">, PD, EVEX,
3525 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3527 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
3528 load, "comiss">, PS, EVEX, VEX_LIG,
3529 EVEX_CD8<32, CD8VT1>;
3530 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
3531 load, "comisd">, PD, EVEX,
3532 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3536 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
3537 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3538 X86MemOperand x86memop> {
3539 let hasSideEffects = 0 in {
3540 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3541 (ins RC:$src1, RC:$src2),
3542 !strconcat(OpcodeStr,
3543 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3544 let mayLoad = 1 in {
3545 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3546 (ins RC:$src1, x86memop:$src2),
3547 !strconcat(OpcodeStr,
3548 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3553 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
3554 EVEX_CD8<32, CD8VT1>;
3555 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
3556 VEX_W, EVEX_CD8<64, CD8VT1>;
3557 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
3558 EVEX_CD8<32, CD8VT1>;
3559 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
3560 VEX_W, EVEX_CD8<64, CD8VT1>;
3562 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
3563 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3564 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3565 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3567 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
3568 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3569 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3570 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3572 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
3573 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3574 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3575 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3577 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
3578 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3579 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3580 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3582 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
3583 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3584 RegisterClass RC, X86MemOperand x86memop,
3585 PatFrag mem_frag, ValueType OpVt> {
3586 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3587 !strconcat(OpcodeStr,
3588 " \t{$src, $dst|$dst, $src}"),
3589 [(set RC:$dst, (OpVt (OpNode RC:$src)))]>,
3591 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3592 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3593 [(set RC:$dst, (OpVt (OpNode (mem_frag addr:$src))))]>,
3596 defm VRSQRT14PSZ : avx512_fp14_p<0x4E, "vrsqrt14ps", X86frsqrt, VR512, f512mem,
3597 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3598 defm VRSQRT14PDZ : avx512_fp14_p<0x4E, "vrsqrt14pd", X86frsqrt, VR512, f512mem,
3599 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3600 defm VRCP14PSZ : avx512_fp14_p<0x4C, "vrcp14ps", X86frcp, VR512, f512mem,
3601 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3602 defm VRCP14PDZ : avx512_fp14_p<0x4C, "vrcp14pd", X86frcp, VR512, f512mem,
3603 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3605 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
3606 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3607 (VRSQRT14PSZr VR512:$src)>;
3608 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
3609 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3610 (VRSQRT14PDZr VR512:$src)>;
3612 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
3613 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3614 (VRCP14PSZr VR512:$src)>;
3615 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
3616 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3617 (VRCP14PDZr VR512:$src)>;
3619 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
3620 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3621 X86MemOperand x86memop> {
3622 let hasSideEffects = 0, Predicates = [HasERI] in {
3623 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3624 (ins RC:$src1, RC:$src2),
3625 !strconcat(OpcodeStr,
3626 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3627 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3628 (ins RC:$src1, RC:$src2),
3629 !strconcat(OpcodeStr,
3630 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
3631 []>, EVEX_4V, EVEX_B;
3632 let mayLoad = 1 in {
3633 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3634 (ins RC:$src1, x86memop:$src2),
3635 !strconcat(OpcodeStr,
3636 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3641 defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
3642 EVEX_CD8<32, CD8VT1>;
3643 defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
3644 VEX_W, EVEX_CD8<64, CD8VT1>;
3645 defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
3646 EVEX_CD8<32, CD8VT1>;
3647 defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
3648 VEX_W, EVEX_CD8<64, CD8VT1>;
3650 def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
3651 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3653 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3654 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3656 def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
3657 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3659 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3660 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3662 def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
3663 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3665 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3666 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3668 def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
3669 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3671 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3672 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3674 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
3675 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr,
3676 RegisterClass RC, X86MemOperand x86memop> {
3677 let hasSideEffects = 0, Predicates = [HasERI] in {
3678 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3679 !strconcat(OpcodeStr,
3680 " \t{$src, $dst|$dst, $src}"),
3682 def rb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3683 !strconcat(OpcodeStr,
3684 " \t{{sae}, $src, $dst|$dst, $src, {sae}}"),
3686 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3687 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3691 defm VRSQRT28PSZ : avx512_fp28_p<0xCC, "vrsqrt28ps", VR512, f512mem>,
3692 EVEX_V512, EVEX_CD8<32, CD8VF>;
3693 defm VRSQRT28PDZ : avx512_fp28_p<0xCC, "vrsqrt28pd", VR512, f512mem>,
3694 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3695 defm VRCP28PSZ : avx512_fp28_p<0xCA, "vrcp28ps", VR512, f512mem>,
3696 EVEX_V512, EVEX_CD8<32, CD8VF>;
3697 defm VRCP28PDZ : avx512_fp28_p<0xCA, "vrcp28pd", VR512, f512mem>,
3698 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3700 def : Pat <(v16f32 (int_x86_avx512_rsqrt28_ps (v16f32 VR512:$src),
3701 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3702 (VRSQRT28PSZrb VR512:$src)>;
3703 def : Pat <(v8f64 (int_x86_avx512_rsqrt28_pd (v8f64 VR512:$src),
3704 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3705 (VRSQRT28PDZrb VR512:$src)>;
3707 def : Pat <(v16f32 (int_x86_avx512_rcp28_ps (v16f32 VR512:$src),
3708 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3709 (VRCP28PSZrb VR512:$src)>;
3710 def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src),
3711 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3712 (VRCP28PDZrb VR512:$src)>;
3714 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3715 OpndItins itins_s, OpndItins itins_d> {
3716 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3717 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3718 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
3722 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3723 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3725 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
3726 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
3728 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3729 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3730 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
3734 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3735 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3736 [(set VR512:$dst, (OpNode
3737 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
3738 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
3742 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
3743 Intrinsic F32Int, Intrinsic F64Int,
3744 OpndItins itins_s, OpndItins itins_d> {
3745 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
3746 (ins FR32X:$src1, FR32X:$src2),
3747 !strconcat(OpcodeStr,
3748 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3749 [], itins_s.rr>, XS, EVEX_4V;
3750 let isCodeGenOnly = 1 in
3751 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3752 (ins VR128X:$src1, VR128X:$src2),
3753 !strconcat(OpcodeStr,
3754 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3756 (F32Int VR128X:$src1, VR128X:$src2))],
3757 itins_s.rr>, XS, EVEX_4V;
3758 let mayLoad = 1 in {
3759 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
3760 (ins FR32X:$src1, f32mem:$src2),
3761 !strconcat(OpcodeStr,
3762 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3763 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3764 let isCodeGenOnly = 1 in
3765 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3766 (ins VR128X:$src1, ssmem:$src2),
3767 !strconcat(OpcodeStr,
3768 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3770 (F32Int VR128X:$src1, sse_load_f32:$src2))],
3771 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3773 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
3774 (ins FR64X:$src1, FR64X:$src2),
3775 !strconcat(OpcodeStr,
3776 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3778 let isCodeGenOnly = 1 in
3779 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3780 (ins VR128X:$src1, VR128X:$src2),
3781 !strconcat(OpcodeStr,
3782 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3784 (F64Int VR128X:$src1, VR128X:$src2))],
3785 itins_s.rr>, XD, EVEX_4V, VEX_W;
3786 let mayLoad = 1 in {
3787 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
3788 (ins FR64X:$src1, f64mem:$src2),
3789 !strconcat(OpcodeStr,
3790 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3791 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3792 let isCodeGenOnly = 1 in
3793 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3794 (ins VR128X:$src1, sdmem:$src2),
3795 !strconcat(OpcodeStr,
3796 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3798 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
3799 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3804 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
3805 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
3806 SSE_SQRTSS, SSE_SQRTSD>,
3807 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
3808 SSE_SQRTPS, SSE_SQRTPD>;
3810 let Predicates = [HasAVX512] in {
3811 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
3812 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
3813 (VSQRTPSZrr VR512:$src1)>;
3814 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
3815 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
3816 (VSQRTPDZrr VR512:$src1)>;
3818 def : Pat<(f32 (fsqrt FR32X:$src)),
3819 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3820 def : Pat<(f32 (fsqrt (load addr:$src))),
3821 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3822 Requires<[OptForSize]>;
3823 def : Pat<(f64 (fsqrt FR64X:$src)),
3824 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
3825 def : Pat<(f64 (fsqrt (load addr:$src))),
3826 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
3827 Requires<[OptForSize]>;
3829 def : Pat<(f32 (X86frsqrt FR32X:$src)),
3830 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3831 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3832 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3833 Requires<[OptForSize]>;
3835 def : Pat<(f32 (X86frcp FR32X:$src)),
3836 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3837 def : Pat<(f32 (X86frcp (load addr:$src))),
3838 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3839 Requires<[OptForSize]>;
3841 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
3842 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
3843 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3845 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3846 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3848 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
3849 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
3850 (COPY_TO_REGCLASS VR128X:$src, FR64)),
3852 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3853 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3857 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
3858 X86MemOperand x86memop, RegisterClass RC,
3859 PatFrag mem_frag32, PatFrag mem_frag64,
3860 Intrinsic V4F32Int, Intrinsic V2F64Int,
3862 let ExeDomain = SSEPackedSingle in {
3863 // Intrinsic operation, reg.
3864 // Vector intrinsic operation, reg
3865 def PSr : AVX512AIi8<opcps, MRMSrcReg,
3866 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3867 !strconcat(OpcodeStr,
3868 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3869 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
3871 // Vector intrinsic operation, mem
3872 def PSm : AVX512AIi8<opcps, MRMSrcMem,
3873 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3874 !strconcat(OpcodeStr,
3875 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3877 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
3878 EVEX_CD8<32, VForm>;
3879 } // ExeDomain = SSEPackedSingle
3881 let ExeDomain = SSEPackedDouble in {
3882 // Vector intrinsic operation, reg
3883 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
3884 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3885 !strconcat(OpcodeStr,
3886 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3887 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
3889 // Vector intrinsic operation, mem
3890 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
3891 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3892 !strconcat(OpcodeStr,
3893 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3895 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
3896 EVEX_CD8<64, VForm>;
3897 } // ExeDomain = SSEPackedDouble
3900 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3904 let ExeDomain = GenericDomain in {
3906 let hasSideEffects = 0 in
3907 def SSr : AVX512AIi8<opcss, MRMSrcReg,
3908 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
3909 !strconcat(OpcodeStr,
3910 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3913 // Intrinsic operation, reg.
3914 let isCodeGenOnly = 1 in
3915 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
3916 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3917 !strconcat(OpcodeStr,
3918 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3919 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
3921 // Intrinsic operation, mem.
3922 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
3923 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
3924 !strconcat(OpcodeStr,
3925 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3926 [(set VR128X:$dst, (F32Int VR128X:$src1,
3927 sse_load_f32:$src2, imm:$src3))]>,
3928 EVEX_CD8<32, CD8VT1>;
3931 let hasSideEffects = 0 in
3932 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
3933 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
3934 !strconcat(OpcodeStr,
3935 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3938 // Intrinsic operation, reg.
3939 let isCodeGenOnly = 1 in
3940 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
3941 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3942 !strconcat(OpcodeStr,
3943 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3944 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
3947 // Intrinsic operation, mem.
3948 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
3949 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
3950 !strconcat(OpcodeStr,
3951 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3953 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
3954 VEX_W, EVEX_CD8<64, CD8VT1>;
3955 } // ExeDomain = GenericDomain
3958 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
3959 X86MemOperand x86memop, RegisterClass RC,
3960 PatFrag mem_frag, Domain d> {
3961 let ExeDomain = d in {
3962 // Intrinsic operation, reg.
3963 // Vector intrinsic operation, reg
3964 def r : AVX512AIi8<opc, MRMSrcReg,
3965 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3966 !strconcat(OpcodeStr,
3967 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3970 // Vector intrinsic operation, mem
3971 def m : AVX512AIi8<opc, MRMSrcMem,
3972 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3973 !strconcat(OpcodeStr,
3974 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3980 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
3981 memopv16f32, SSEPackedSingle>, EVEX_V512,
3982 EVEX_CD8<32, CD8VF>;
3984 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
3985 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
3987 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
3990 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
3991 memopv8f64, SSEPackedDouble>, EVEX_V512,
3992 VEX_W, EVEX_CD8<64, CD8VF>;
3994 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
3995 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
3997 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
3999 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
4000 Operand x86memop, RegisterClass RC, Domain d> {
4001 let ExeDomain = d in {
4002 def r : AVX512AIi8<opc, MRMSrcReg,
4003 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4004 !strconcat(OpcodeStr,
4005 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4008 def m : AVX512AIi8<opc, MRMSrcMem,
4009 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4010 !strconcat(OpcodeStr,
4011 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4016 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
4017 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
4019 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
4020 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
4022 def : Pat<(ffloor FR32X:$src),
4023 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
4024 def : Pat<(f64 (ffloor FR64X:$src)),
4025 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
4026 def : Pat<(f32 (fnearbyint FR32X:$src)),
4027 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
4028 def : Pat<(f64 (fnearbyint FR64X:$src)),
4029 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
4030 def : Pat<(f32 (fceil FR32X:$src)),
4031 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
4032 def : Pat<(f64 (fceil FR64X:$src)),
4033 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
4034 def : Pat<(f32 (frint FR32X:$src)),
4035 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
4036 def : Pat<(f64 (frint FR64X:$src)),
4037 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
4038 def : Pat<(f32 (ftrunc FR32X:$src)),
4039 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
4040 def : Pat<(f64 (ftrunc FR64X:$src)),
4041 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
4043 def : Pat<(v16f32 (ffloor VR512:$src)),
4044 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
4045 def : Pat<(v16f32 (fnearbyint VR512:$src)),
4046 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
4047 def : Pat<(v16f32 (fceil VR512:$src)),
4048 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
4049 def : Pat<(v16f32 (frint VR512:$src)),
4050 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
4051 def : Pat<(v16f32 (ftrunc VR512:$src)),
4052 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
4054 def : Pat<(v8f64 (ffloor VR512:$src)),
4055 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
4056 def : Pat<(v8f64 (fnearbyint VR512:$src)),
4057 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
4058 def : Pat<(v8f64 (fceil VR512:$src)),
4059 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
4060 def : Pat<(v8f64 (frint VR512:$src)),
4061 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
4062 def : Pat<(v8f64 (ftrunc VR512:$src)),
4063 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
4065 //-------------------------------------------------
4066 // Integer truncate and extend operations
4067 //-------------------------------------------------
4069 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
4070 RegisterClass dstRC, RegisterClass srcRC,
4071 RegisterClass KRC, X86MemOperand x86memop> {
4072 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4074 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
4077 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4078 (ins KRC:$mask, srcRC:$src),
4079 !strconcat(OpcodeStr,
4080 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
4083 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4084 (ins KRC:$mask, srcRC:$src),
4085 !strconcat(OpcodeStr,
4086 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4089 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
4090 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4093 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4094 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4095 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4099 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4100 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4101 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4102 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4103 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4104 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4105 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4106 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4107 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4108 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4109 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4110 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4111 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4112 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4113 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4114 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4115 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4116 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4117 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4118 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4119 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4120 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4121 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4122 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4123 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4124 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4125 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4126 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4127 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4128 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4130 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4131 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4132 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4133 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4134 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4136 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4137 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
4138 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4139 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
4140 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4141 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
4142 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4143 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
4146 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4147 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4148 PatFrag mem_frag, X86MemOperand x86memop,
4149 ValueType OpVT, ValueType InVT> {
4151 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4153 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4154 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
4156 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4157 (ins KRC:$mask, SrcRC:$src),
4158 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4161 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4162 (ins KRC:$mask, SrcRC:$src),
4163 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4166 let mayLoad = 1 in {
4167 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4168 (ins x86memop:$src),
4169 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
4171 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4174 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4175 (ins KRC:$mask, x86memop:$src),
4176 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4180 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4181 (ins KRC:$mask, x86memop:$src),
4182 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4188 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
4189 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4191 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
4192 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4194 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
4195 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4196 EVEX_CD8<16, CD8VH>;
4197 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
4198 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4199 EVEX_CD8<16, CD8VQ>;
4200 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
4201 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4202 EVEX_CD8<32, CD8VH>;
4204 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
4205 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4207 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
4208 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4210 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
4211 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4212 EVEX_CD8<16, CD8VH>;
4213 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
4214 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4215 EVEX_CD8<16, CD8VQ>;
4216 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
4217 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4218 EVEX_CD8<32, CD8VH>;
4220 //===----------------------------------------------------------------------===//
4221 // GATHER - SCATTER Operations
4223 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4224 RegisterClass RC, X86MemOperand memop> {
4226 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4227 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4228 (ins RC:$src1, KRC:$mask, memop:$src2),
4229 !strconcat(OpcodeStr,
4230 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4234 let ExeDomain = SSEPackedDouble in {
4235 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4236 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4237 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4238 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4241 let ExeDomain = SSEPackedSingle in {
4242 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4243 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4244 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4245 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4248 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4249 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4250 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4251 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4253 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4254 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4255 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4256 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4258 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4259 RegisterClass RC, X86MemOperand memop> {
4260 let mayStore = 1, Constraints = "$mask = $mask_wb" in
4261 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4262 (ins memop:$dst, KRC:$mask, RC:$src2),
4263 !strconcat(OpcodeStr,
4264 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4268 let ExeDomain = SSEPackedDouble in {
4269 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4270 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4271 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4272 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4275 let ExeDomain = SSEPackedSingle in {
4276 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4277 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4278 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4279 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4282 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4283 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4284 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4285 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4287 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4288 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4289 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4290 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4293 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4294 RegisterClass KRC, X86MemOperand memop> {
4295 let Predicates = [HasPFI], hasSideEffects = 1 in
4296 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4297 !strconcat(OpcodeStr, " \t{$src {${mask}}|{${mask}}, $src}"),
4301 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4302 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4304 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4305 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4307 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4308 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4310 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4311 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4313 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4314 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4316 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4317 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4319 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4320 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4322 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4323 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4325 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4326 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4328 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
4329 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4331 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
4332 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4334 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
4335 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4337 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
4338 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4340 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
4341 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4343 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
4344 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4346 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
4347 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4348 //===----------------------------------------------------------------------===//
4349 // VSHUFPS - VSHUFPD Operations
4351 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
4352 ValueType vt, string OpcodeStr, PatFrag mem_frag,
4354 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
4355 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4356 !strconcat(OpcodeStr,
4357 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4358 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
4359 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4360 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
4361 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
4362 (ins RC:$src1, RC:$src2, i8imm:$src3),
4363 !strconcat(OpcodeStr,
4364 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4365 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
4366 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4367 EVEX_4V, Sched<[WriteShuffle]>;
4370 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
4371 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4372 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
4373 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4375 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4376 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4377 def : Pat<(v16i32 (X86Shufp VR512:$src1,
4378 (memopv16i32 addr:$src2), (i8 imm:$imm))),
4379 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4381 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4382 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4383 def : Pat<(v8i64 (X86Shufp VR512:$src1,
4384 (memopv8i64 addr:$src2), (i8 imm:$imm))),
4385 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4387 multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
4388 X86MemOperand x86memop> {
4389 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
4390 (ins RC:$src1, RC:$src2, i8imm:$src3),
4391 !strconcat(OpcodeStr,
4392 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4395 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
4396 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4397 !strconcat(OpcodeStr,
4398 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4401 defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
4402 EVEX_V512, EVEX_CD8<32, CD8VF>;
4403 defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
4404 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4406 def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4407 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
4408 def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4409 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
4410 def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4411 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
4412 def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4413 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
4415 // Helper fragments to match sext vXi1 to vXiY.
4416 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
4417 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
4419 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
4420 RegisterClass KRC, RegisterClass RC,
4421 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
4423 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4424 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4426 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4427 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4429 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4430 !strconcat(OpcodeStr,
4431 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4433 let mayLoad = 1 in {
4434 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4435 (ins x86memop:$src),
4436 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4438 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4439 (ins KRC:$mask, x86memop:$src),
4440 !strconcat(OpcodeStr,
4441 " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4443 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4444 (ins KRC:$mask, x86memop:$src),
4445 !strconcat(OpcodeStr,
4446 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4448 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4449 (ins x86scalar_mop:$src),
4450 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4451 ", $dst|$dst, ${src}", BrdcstStr, "}"),
4453 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4454 (ins KRC:$mask, x86scalar_mop:$src),
4455 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4456 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
4457 []>, EVEX, EVEX_B, EVEX_K;
4458 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4459 (ins KRC:$mask, x86scalar_mop:$src),
4460 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4461 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
4463 []>, EVEX, EVEX_B, EVEX_KZ;
4467 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
4468 i512mem, i32mem, "{1to16}">, EVEX_V512,
4469 EVEX_CD8<32, CD8VF>;
4470 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
4471 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
4472 EVEX_CD8<64, CD8VF>;
4475 (bc_v16i32 (v16i1sextv16i32)),
4476 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
4477 (VPABSDZrr VR512:$src)>;
4479 (bc_v8i64 (v8i1sextv8i64)),
4480 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
4481 (VPABSQZrr VR512:$src)>;
4483 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
4484 (v16i32 immAllZerosV), (i16 -1))),
4485 (VPABSDZrr VR512:$src)>;
4486 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
4487 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
4488 (VPABSQZrr VR512:$src)>;
4490 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
4491 RegisterClass RC, RegisterClass KRC,
4492 X86MemOperand x86memop,
4493 X86MemOperand x86scalar_mop, string BrdcstStr> {
4494 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4496 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"),
4498 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4499 (ins x86memop:$src),
4500 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"),
4502 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4503 (ins x86scalar_mop:$src),
4504 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4505 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
4507 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4508 (ins KRC:$mask, RC:$src),
4509 !strconcat(OpcodeStr,
4510 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4512 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4513 (ins KRC:$mask, x86memop:$src),
4514 !strconcat(OpcodeStr,
4515 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4517 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4518 (ins KRC:$mask, x86scalar_mop:$src),
4519 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4520 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
4522 []>, EVEX, EVEX_KZ, EVEX_B;
4524 let Constraints = "$src1 = $dst" in {
4525 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4526 (ins RC:$src1, KRC:$mask, RC:$src2),
4527 !strconcat(OpcodeStr,
4528 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4530 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4531 (ins RC:$src1, KRC:$mask, x86memop:$src2),
4532 !strconcat(OpcodeStr,
4533 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4535 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4536 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
4537 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
4538 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
4539 []>, EVEX, EVEX_K, EVEX_B;
4543 let Predicates = [HasCDI] in {
4544 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
4545 i512mem, i32mem, "{1to16}">,
4546 EVEX_V512, EVEX_CD8<32, CD8VF>;
4549 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
4550 i512mem, i64mem, "{1to8}">,
4551 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4555 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
4557 (VPCONFLICTDrrk VR512:$src1,
4558 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4560 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
4562 (VPCONFLICTQrrk VR512:$src1,
4563 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
4565 let Predicates = [HasCDI] in {
4566 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
4567 i512mem, i32mem, "{1to16}">,
4568 EVEX_V512, EVEX_CD8<32, CD8VF>;
4571 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
4572 i512mem, i64mem, "{1to8}">,
4573 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4577 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
4579 (VPLZCNTDrrk VR512:$src1,
4580 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4582 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
4584 (VPLZCNTQrrk VR512:$src1,
4585 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
4587 def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))),
4588 (VPLZCNTDrm addr:$src)>;
4589 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
4590 (VPLZCNTDrr VR512:$src)>;
4591 def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))),
4592 (VPLZCNTQrm addr:$src)>;
4593 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
4594 (VPLZCNTQrr VR512:$src)>;
4596 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4597 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4598 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
4600 def : Pat<(store VK1:$src, addr:$dst),
4601 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
4603 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
4604 (truncstore node:$val, node:$ptr), [{
4605 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
4608 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
4609 (MOV8mr addr:$dst, GR8:$src)>;