1 // Bitcasts between 512-bit vector types. Return the original type since
2 // no instruction is needed for the conversion
3 let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
49 // Bitcasts between 256-bit vector types. Return the original type since
50 // no instruction is needed for the conversion
51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
84 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
87 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
88 isPseudo = 1, Predicates = [HasAVX512] in {
89 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
90 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
93 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
94 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
95 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
96 def : Pat<(v16f32 immAllZerosV), (AVX512_512_SET0)>;
98 //===----------------------------------------------------------------------===//
99 // AVX-512 - VECTOR INSERT
102 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
103 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
104 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
105 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
106 []>, EVEX_4V, EVEX_V512;
108 def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
109 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
110 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
111 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
114 // -- 64x4 fp form --
115 let neverHasSideEffects = 1, ExeDomain = SSEPackedDouble in {
116 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
117 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
118 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
119 []>, EVEX_4V, EVEX_V512, VEX_W;
121 def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
122 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
123 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
124 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
126 // -- 32x4 integer form --
127 let neverHasSideEffects = 1 in {
128 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
129 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
130 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
131 []>, EVEX_4V, EVEX_V512;
133 def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
134 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
135 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
136 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
140 let neverHasSideEffects = 1 in {
142 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
143 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
144 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
145 []>, EVEX_4V, EVEX_V512, VEX_W;
147 def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
148 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
149 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
150 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
153 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
154 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
155 (INSERT_get_vinsert128_imm VR512:$ins))>;
156 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
157 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
158 (INSERT_get_vinsert128_imm VR512:$ins))>;
159 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
160 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
161 (INSERT_get_vinsert128_imm VR512:$ins))>;
162 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
163 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
164 (INSERT_get_vinsert128_imm VR512:$ins))>;
166 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
167 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
168 (INSERT_get_vinsert128_imm VR512:$ins))>;
169 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
170 (bc_v4i32 (loadv2i64 addr:$src2)),
171 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
172 (INSERT_get_vinsert128_imm VR512:$ins))>;
173 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
174 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
175 (INSERT_get_vinsert128_imm VR512:$ins))>;
176 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
177 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
178 (INSERT_get_vinsert128_imm VR512:$ins))>;
180 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
181 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
182 (INSERT_get_vinsert256_imm VR512:$ins))>;
183 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
184 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
185 (INSERT_get_vinsert256_imm VR512:$ins))>;
186 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
187 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
188 (INSERT_get_vinsert256_imm VR512:$ins))>;
189 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
190 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
191 (INSERT_get_vinsert256_imm VR512:$ins))>;
193 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
194 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
195 (INSERT_get_vinsert256_imm VR512:$ins))>;
196 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
197 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
198 (INSERT_get_vinsert256_imm VR512:$ins))>;
199 def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
200 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
201 (INSERT_get_vinsert256_imm VR512:$ins))>;
202 def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
203 (bc_v8i32 (loadv4i64 addr:$src2)),
204 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
205 (INSERT_get_vinsert256_imm VR512:$ins))>;
207 // vinsertps - insert f32 to XMM
208 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
209 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
210 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
211 [(set VR128X:$dst, (X86insrtps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
213 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
214 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
215 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
216 [(set VR128X:$dst, (X86insrtps VR128X:$src1,
217 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
218 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
220 //===----------------------------------------------------------------------===//
221 // AVX-512 VECTOR EXTRACT
223 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
225 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
226 (ins VR512:$src1, i8imm:$src2),
227 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
228 []>, EVEX, EVEX_V512;
229 def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
230 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
231 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
232 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
235 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
236 (ins VR512:$src1, i8imm:$src2),
237 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
238 []>, EVEX, EVEX_V512, VEX_W;
240 def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
241 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
242 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
243 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
246 let neverHasSideEffects = 1 in {
248 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
249 (ins VR512:$src1, i8imm:$src2),
250 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
251 []>, EVEX, EVEX_V512;
252 def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
253 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
254 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
255 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
258 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
259 (ins VR512:$src1, i8imm:$src2),
260 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
261 []>, EVEX, EVEX_V512, VEX_W;
263 def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
264 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
265 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
266 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
269 def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
270 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
271 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
273 def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
274 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
275 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
277 def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
278 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
279 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
281 def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
282 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
283 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
286 def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
287 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
288 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
290 def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
291 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
292 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
294 def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
295 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
296 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
298 def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
299 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
300 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
302 // A 256-bit subvector extract from the first 512-bit vector position
303 // is a subregister copy that needs no instruction.
304 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
305 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
306 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
307 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
308 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
309 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
310 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
311 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
314 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
315 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
316 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
317 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
318 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
319 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
320 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
321 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
324 // A 128-bit subvector insert to the first 512-bit vector position
325 // is a subregister copy that needs no instruction.
326 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
327 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
328 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
330 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
331 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
332 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
334 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
335 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
336 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
338 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
339 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
340 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
343 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
344 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
345 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
346 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
347 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
348 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
349 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
350 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
352 // vextractps - extract 32 bits from XMM
353 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
354 (ins VR128X:$src1, u32u8imm:$src2),
355 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
356 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
359 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
360 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
361 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
362 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
365 //===---------------------------------------------------------------------===//
368 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
369 RegisterClass DestRC,
370 RegisterClass SrcRC, X86MemOperand x86memop> {
371 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
372 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
374 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
375 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),[]>, EVEX;
377 let ExeDomain = SSEPackedSingle in {
378 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
380 EVEX_V512, EVEX_CD8<32, CD8VT1>;
383 let ExeDomain = SSEPackedDouble in {
384 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
386 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
389 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
390 (VBROADCASTSSZrm addr:$src)>;
391 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
392 (VBROADCASTSDZrm addr:$src)>;
394 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
395 (VBROADCASTSSZrm addr:$src)>;
396 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
397 (VBROADCASTSDZrm addr:$src)>;
399 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
400 RegisterClass SrcRC, RegisterClass KRC> {
401 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
402 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
403 []>, EVEX, EVEX_V512;
404 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
405 (ins KRC:$mask, SrcRC:$src),
406 !strconcat(OpcodeStr,
407 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
408 []>, EVEX, EVEX_V512, EVEX_KZ;
411 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
412 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
415 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
416 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
418 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
419 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
421 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
422 (VPBROADCASTDrZrr GR32:$src)>;
423 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
424 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
425 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
426 (VPBROADCASTQrZrr GR64:$src)>;
427 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
428 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
430 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
431 (VPBROADCASTDrZrr GR32:$src)>;
432 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
433 (VPBROADCASTQrZrr GR64:$src)>;
435 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
436 X86MemOperand x86memop, PatFrag ld_frag,
437 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
439 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
440 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
442 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
443 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
445 !strconcat(OpcodeStr,
446 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
448 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
451 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
452 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
454 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
455 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
457 !strconcat(OpcodeStr,
458 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
459 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
460 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
464 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
465 loadi32, VR512, v16i32, v4i32, VK16WM>,
466 EVEX_V512, EVEX_CD8<32, CD8VT1>;
467 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
468 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
469 EVEX_CD8<64, CD8VT1>;
471 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
472 (VPBROADCASTDZrr VR128X:$src)>;
473 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
474 (VPBROADCASTQZrr VR128X:$src)>;
476 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
477 (VBROADCASTSSZrr VR128X:$src)>;
478 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
479 (VBROADCASTSDZrr VR128X:$src)>;
481 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
482 (VBROADCASTSSZrr VR128X:$src)>;
483 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
484 (VBROADCASTSDZrr VR128X:$src)>;
486 // Provide fallback in case the load node that is used in the patterns above
487 // is used by additional users, which prevents the pattern selection.
488 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
489 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
490 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
491 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
494 let Predicates = [HasAVX512] in {
495 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
497 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
498 addr:$src)), sub_ymm)>;
500 //===----------------------------------------------------------------------===//
501 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
504 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
505 RegisterClass DstRC, RegisterClass KRC,
506 ValueType OpVT, ValueType SrcVT> {
507 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
508 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
512 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
513 VK16, v16i32, v16i1>, EVEX_V512;
514 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
515 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
517 //===----------------------------------------------------------------------===//
520 // -- immediate form --
521 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
522 SDNode OpNode, PatFrag mem_frag,
523 X86MemOperand x86memop, ValueType OpVT> {
524 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
525 (ins RC:$src1, i8imm:$src2),
526 !strconcat(OpcodeStr,
527 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
529 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
531 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
532 (ins x86memop:$src1, i8imm:$src2),
533 !strconcat(OpcodeStr,
534 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
536 (OpVT (OpNode (mem_frag addr:$src1),
537 (i8 imm:$src2))))]>, EVEX;
540 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
541 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
542 let ExeDomain = SSEPackedDouble in
543 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
544 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
546 // -- VPERM - register form --
547 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
548 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
550 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
551 (ins RC:$src1, RC:$src2),
552 !strconcat(OpcodeStr,
553 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
555 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
557 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
558 (ins RC:$src1, x86memop:$src2),
559 !strconcat(OpcodeStr,
560 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
562 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
566 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
567 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
568 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
569 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
570 let ExeDomain = SSEPackedSingle in
571 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
572 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
573 let ExeDomain = SSEPackedDouble in
574 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
575 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
577 // -- VPERM2I - 3 source operands form --
578 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
579 PatFrag mem_frag, X86MemOperand x86memop,
581 let Constraints = "$src1 = $dst" in {
582 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
583 (ins RC:$src1, RC:$src2, RC:$src3),
584 !strconcat(OpcodeStr,
585 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
587 (OpVT (X86VPermv3 RC:$src1, RC:$src2, RC:$src3)))]>,
590 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
591 (ins RC:$src1, RC:$src2, x86memop:$src3),
592 !strconcat(OpcodeStr,
593 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
595 (OpVT (X86VPermv3 RC:$src1, RC:$src2,
596 (mem_frag addr:$src3))))]>, EVEX_4V;
599 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem,
600 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
601 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem,
602 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
603 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem,
604 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
605 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
606 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
608 //===----------------------------------------------------------------------===//
609 // AVX-512 - BLEND using mask
611 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, Intrinsic Int,
612 RegisterClass KRC, RegisterClass RC,
613 X86MemOperand x86memop, PatFrag mem_frag,
614 SDNode OpNode, ValueType vt> {
615 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
616 (ins KRC:$mask, RC:$src1, RC:$src2),
617 !strconcat(OpcodeStr,
618 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
619 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
620 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
621 def rr_Int : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
622 (ins KRC:$mask, RC:$src1, RC:$src2),
623 !strconcat(OpcodeStr,
624 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
625 [(set RC:$dst, (Int KRC:$mask, (vt RC:$src2),
626 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
629 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
630 (ins KRC:$mask, RC:$src1, x86memop:$src2),
631 !strconcat(OpcodeStr,
632 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
636 def rm_Int : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
637 (ins KRC:$mask, RC:$src1, x86memop:$src2),
638 !strconcat(OpcodeStr,
639 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
640 [(set RC:$dst, (Int KRC:$mask, (vt RC:$src1),
641 (mem_frag addr:$src2)))]>,
646 let ExeDomain = SSEPackedSingle in
647 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
648 int_x86_avx512_mask_blend_ps_512,
649 VK16WM, VR512, f512mem,
650 memopv16f32, vselect, v16f32>,
651 EVEX_CD8<32, CD8VF>, EVEX_V512;
652 let ExeDomain = SSEPackedDouble in
653 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
654 int_x86_avx512_mask_blend_pd_512,
655 VK8WM, VR512, f512mem,
656 memopv8f64, vselect, v8f64>,
657 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
659 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
660 int_x86_avx512_mask_blend_d_512,
661 VK16WM, VR512, f512mem,
662 memopv16i32, vselect, v16i32>,
663 EVEX_CD8<32, CD8VF>, EVEX_V512;
665 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
666 int_x86_avx512_mask_blend_q_512,
667 VK8WM, VR512, f512mem,
668 memopv8i64, vselect, v8i64>,
669 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
671 let Predicates = [HasAVX512] in {
672 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
673 (v8f32 VR256X:$src2))),
675 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
676 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
677 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
679 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
680 (v8i32 VR256X:$src2))),
682 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
683 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
684 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
686 //===----------------------------------------------------------------------===//
687 // Compare Instructions
688 //===----------------------------------------------------------------------===//
690 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
691 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
692 Operand CC, SDNode OpNode, ValueType VT,
693 PatFrag ld_frag, string asm, string asm_alt> {
694 def rr : AVX512Ii8<0xC2, MRMSrcReg,
695 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
696 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
697 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
698 def rm : AVX512Ii8<0xC2, MRMSrcMem,
699 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
700 [(set VK1:$dst, (OpNode (VT RC:$src1),
701 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
702 let neverHasSideEffects = 1 in {
703 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
704 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
705 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
706 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
707 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
708 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
712 let Predicates = [HasAVX512] in {
713 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
714 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
715 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
717 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
718 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
719 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
723 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
724 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
725 SDNode OpNode, ValueType vt> {
726 def rr : AVX512BI<opc, MRMSrcReg,
727 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
728 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
729 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
730 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
731 def rm : AVX512BI<opc, MRMSrcMem,
732 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
733 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
734 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
735 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
738 defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
739 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512;
740 defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
741 memopv8i64, X86pcmpeqm, v8i64>, T8, EVEX_V512, VEX_W;
743 defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
744 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512;
745 defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
746 memopv8i64, X86pcmpgtm, v8i64>, T8, EVEX_V512, VEX_W;
748 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
749 (COPY_TO_REGCLASS (VPCMPGTDZrr
750 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
751 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
753 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
754 (COPY_TO_REGCLASS (VPCMPEQDZrr
755 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
756 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
758 multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
759 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
760 SDNode OpNode, ValueType vt, Operand CC, string asm,
762 def rri : AVX512AIi8<opc, MRMSrcReg,
763 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
764 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
765 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
766 def rmi : AVX512AIi8<opc, MRMSrcMem,
767 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
768 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
769 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
770 // Accept explicit immediate argument form instead of comparison code.
771 let neverHasSideEffects = 1 in {
772 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
773 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
774 asm_alt, [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
775 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
776 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
777 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
781 defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv16i32,
782 X86cmpm, v16i32, AVXCC,
783 "vpcmp${cc}d\t{$src2, $src1, $dst|$dst, $src1, $src2}",
784 "vpcmpd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
785 EVEX_V512, EVEX_CD8<32, CD8VF>;
786 defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv16i32,
787 X86cmpmu, v16i32, AVXCC,
788 "vpcmp${cc}ud\t{$src2, $src1, $dst|$dst, $src1, $src2}",
789 "vpcmpud\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
790 EVEX_V512, EVEX_CD8<32, CD8VF>;
792 defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64,
793 X86cmpm, v8i64, AVXCC,
794 "vpcmp${cc}q\t{$src2, $src1, $dst|$dst, $src1, $src2}",
795 "vpcmpq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
796 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
797 defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64,
798 X86cmpmu, v8i64, AVXCC,
799 "vpcmp${cc}uq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
800 "vpcmpuq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
801 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
803 // avx512_cmp_packed - sse 1 & 2 compare packed instructions
804 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
805 X86MemOperand x86memop, Operand CC,
806 SDNode OpNode, ValueType vt, string asm,
807 string asm_alt, Domain d> {
808 def rri : AVX512PIi8<0xC2, MRMSrcReg,
809 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
810 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
811 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
812 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
814 (OpNode (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
816 // Accept explicit immediate argument form instead of comparison code.
817 let neverHasSideEffects = 1 in {
818 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
819 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
821 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
822 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
827 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, AVXCC, X86cmpm, v16f32,
828 "vcmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
829 "vcmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
830 SSEPackedSingle>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VF>;
831 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, AVXCC, X86cmpm, v8f64,
832 "vcmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
833 "vcmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
834 SSEPackedDouble>, OpSize, EVEX_4V, VEX_W, EVEX_V512,
837 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
838 (COPY_TO_REGCLASS (VCMPPSZrri
839 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
840 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
842 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
843 (COPY_TO_REGCLASS (VPCMPDZrri
844 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
845 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
847 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
848 (COPY_TO_REGCLASS (VPCMPUDZrri
849 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
850 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
853 // Mask register copy, including
854 // - copy between mask registers
855 // - load/store mask registers
856 // - copy from GPR to mask register and vice versa
858 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
859 string OpcodeStr, RegisterClass KRC,
860 ValueType vt, X86MemOperand x86memop> {
861 let neverHasSideEffects = 1 in {
862 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
863 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
865 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
866 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
867 [(set KRC:$dst, (vt (load addr:$src)))]>;
869 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
870 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
874 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
876 RegisterClass KRC, RegisterClass GRC> {
877 let neverHasSideEffects = 1 in {
878 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
879 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
880 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
881 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
885 let Predicates = [HasAVX512] in {
886 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
888 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
892 let Predicates = [HasAVX512] in {
893 // GR16 from/to 16-bit mask
894 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
895 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
896 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
897 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
899 // Store kreg in memory
900 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
901 (KMOVWmk addr:$dst, VK16:$src)>;
903 def : Pat<(store VK8:$src, addr:$dst),
904 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
906 def : Pat<(i1 (load addr:$src)),
907 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
909 def : Pat<(v8i1 (load addr:$src)),
910 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
912 def : Pat<(i1 (trunc (i32 GR32:$src))),
913 (COPY_TO_REGCLASS (KMOVWkr $src), VK1)>;
915 def : Pat<(i1 (trunc (i8 GR8:$src))),
917 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)), VK1)>;
919 def : Pat<(i32 (zext VK1:$src)), (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16))>;
920 def : Pat<(i8 (zext VK1:$src)),
922 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_8bit)>;
924 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
925 let Predicates = [HasAVX512] in {
926 // GR from/to 8-bit mask without native support
927 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
929 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
931 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
933 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
936 def : Pat<(i1 (extractelt VK16:$src, (iPTR 0))),
937 (COPY_TO_REGCLASS VK16:$src, VK1)>;
938 def : Pat<(i1 (extractelt VK8:$src, (iPTR 0))),
939 (COPY_TO_REGCLASS VK8:$src, VK1)>;
943 // Mask unary operation
945 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
946 RegisterClass KRC, SDPatternOperator OpNode> {
947 let Predicates = [HasAVX512] in
948 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
949 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
950 [(set KRC:$dst, (OpNode KRC:$src))]>;
953 multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
954 SDPatternOperator OpNode> {
955 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
959 defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
961 multiclass avx512_mask_unop_int<string IntName, string InstName> {
962 let Predicates = [HasAVX512] in
963 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
965 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
966 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
968 defm : avx512_mask_unop_int<"knot", "KNOT">;
970 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
971 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
972 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
974 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
975 def : Pat<(not VK8:$src),
977 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
979 // Mask binary operation
980 // - KAND, KANDN, KOR, KXNOR, KXOR
981 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
982 RegisterClass KRC, SDPatternOperator OpNode> {
983 let Predicates = [HasAVX512] in
984 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
985 !strconcat(OpcodeStr,
986 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
987 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
990 multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
991 SDPatternOperator OpNode> {
992 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
996 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
997 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
999 let isCommutable = 1 in {
1000 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
1001 let isCommutable = 0 in
1002 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
1003 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
1004 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
1005 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
1008 def : Pat<(xor VK1:$src1, VK1:$src2),
1009 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1010 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1012 def : Pat<(or VK1:$src1, VK1:$src2),
1013 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1014 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1016 def : Pat<(not VK1:$src),
1017 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src, VK16),
1018 (COPY_TO_REGCLASS (VCMPSSZrr (f32 (IMPLICIT_DEF)),
1019 (f32 (IMPLICIT_DEF)), (i8 0)), VK16)), VK1)>;
1021 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1022 let Predicates = [HasAVX512] in
1023 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1024 (i16 GR16:$src1), (i16 GR16:$src2)),
1025 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1026 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1027 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1030 defm : avx512_mask_binop_int<"kand", "KAND">;
1031 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1032 defm : avx512_mask_binop_int<"kor", "KOR">;
1033 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1034 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1036 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1037 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1038 let Predicates = [HasAVX512] in
1039 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1041 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1042 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1045 defm : avx512_binop_pat<and, KANDWrr>;
1046 defm : avx512_binop_pat<andn, KANDNWrr>;
1047 defm : avx512_binop_pat<or, KORWrr>;
1048 defm : avx512_binop_pat<xnor, KXNORWrr>;
1049 defm : avx512_binop_pat<xor, KXORWrr>;
1052 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1053 RegisterClass KRC> {
1054 let Predicates = [HasAVX512] in
1055 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1056 !strconcat(OpcodeStr,
1057 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1060 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1061 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1062 VEX_4V, VEX_L, OpSize, TB;
1065 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1066 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1067 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1068 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1071 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1072 let Predicates = [HasAVX512] in
1073 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1074 (i16 GR16:$src1), (i16 GR16:$src2)),
1075 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1076 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1077 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1079 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1082 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1084 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1085 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1086 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1087 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1090 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1091 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1095 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1097 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1098 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1099 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1102 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1104 let Predicates = [HasAVX512] in
1105 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1106 !strconcat(OpcodeStr,
1107 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
1108 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1111 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1113 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1114 VEX, OpSize, TA, VEX_W;
1117 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1118 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1120 // Mask setting all 0s or 1s
1121 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1122 let Predicates = [HasAVX512] in
1123 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1124 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1125 [(set KRC:$dst, (VT Val))]>;
1128 multiclass avx512_mask_setop_w<PatFrag Val> {
1129 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1130 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1133 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1134 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1136 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1137 let Predicates = [HasAVX512] in {
1138 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1139 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1141 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1142 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1144 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1145 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1147 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1148 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1150 //===----------------------------------------------------------------------===//
1151 // AVX-512 - Aligned and unaligned load and store
1154 multiclass avx512_mov_packed<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1155 X86MemOperand x86memop, PatFrag ld_frag,
1156 string asm, Domain d> {
1157 let neverHasSideEffects = 1 in
1158 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1159 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>,
1161 let canFoldAsLoad = 1 in
1162 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1163 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1164 [(set RC:$dst, (ld_frag addr:$src))], d>, EVEX;
1165 let Constraints = "$src1 = $dst" in {
1166 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1167 (ins RC:$src1, KRC:$mask, RC:$src2),
1169 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1171 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1172 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1174 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1175 [], d>, EVEX, EVEX_K;
1179 defm VMOVAPSZ : avx512_mov_packed<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1180 "vmovaps", SSEPackedSingle>,
1181 EVEX_V512, EVEX_CD8<32, CD8VF>;
1182 defm VMOVAPDZ : avx512_mov_packed<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1183 "vmovapd", SSEPackedDouble>,
1184 OpSize, EVEX_V512, VEX_W,
1185 EVEX_CD8<64, CD8VF>;
1186 defm VMOVUPSZ : avx512_mov_packed<0x10, VR512, VK16WM, f512mem, loadv16f32,
1187 "vmovups", SSEPackedSingle>,
1188 EVEX_V512, EVEX_CD8<32, CD8VF>;
1189 defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64,
1190 "vmovupd", SSEPackedDouble>,
1191 OpSize, EVEX_V512, VEX_W,
1192 EVEX_CD8<64, CD8VF>;
1193 def VMOVAPSZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1194 "vmovaps\t{$src, $dst|$dst, $src}",
1195 [(alignedstore512 (v16f32 VR512:$src), addr:$dst)],
1196 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1197 def VMOVAPDZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1198 "vmovapd\t{$src, $dst|$dst, $src}",
1199 [(alignedstore512 (v8f64 VR512:$src), addr:$dst)],
1200 SSEPackedDouble>, EVEX, EVEX_V512,
1201 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1202 def VMOVUPSZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1203 "vmovups\t{$src, $dst|$dst, $src}",
1204 [(store (v16f32 VR512:$src), addr:$dst)],
1205 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1206 def VMOVUPDZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1207 "vmovupd\t{$src, $dst|$dst, $src}",
1208 [(store (v8f64 VR512:$src), addr:$dst)],
1209 SSEPackedDouble>, EVEX, EVEX_V512,
1210 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1212 let neverHasSideEffects = 1 in {
1213 def VMOVDQA32rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1215 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1217 def VMOVDQA64rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1219 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1220 EVEX, EVEX_V512, VEX_W;
1221 let mayStore = 1 in {
1222 def VMOVDQA32mr : AVX512BI<0x7F, MRMDestMem, (outs),
1223 (ins i512mem:$dst, VR512:$src),
1224 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1225 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1226 def VMOVDQA64mr : AVX512BI<0x7F, MRMDestMem, (outs),
1227 (ins i512mem:$dst, VR512:$src),
1228 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1229 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1231 let mayLoad = 1 in {
1232 def VMOVDQA32rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1234 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1235 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1236 def VMOVDQA64rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1238 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1239 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1243 // 512-bit aligned load/store
1244 def : Pat<(alignedloadv8i64 addr:$src), (VMOVDQA64rm addr:$src)>;
1245 def : Pat<(alignedloadv16i32 addr:$src), (VMOVDQA32rm addr:$src)>;
1247 def : Pat<(alignedstore512 (v8i64 VR512:$src), addr:$dst),
1248 (VMOVDQA64mr addr:$dst, VR512:$src)>;
1249 def : Pat<(alignedstore512 (v16i32 VR512:$src), addr:$dst),
1250 (VMOVDQA32mr addr:$dst, VR512:$src)>;
1252 multiclass avx512_mov_int<bits<8> load_opc, bits<8> store_opc, string asm,
1253 RegisterClass RC, RegisterClass KRC,
1254 PatFrag ld_frag, X86MemOperand x86memop> {
1255 let neverHasSideEffects = 1 in
1256 def rr : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1257 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>, EVEX;
1258 let canFoldAsLoad = 1 in
1259 def rm : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1260 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1261 [(set RC:$dst, (ld_frag addr:$src))]>, EVEX;
1263 def mr : AVX512XSI<store_opc, MRMDestMem, (outs),
1264 (ins x86memop:$dst, VR512:$src),
1265 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>, EVEX;
1266 let Constraints = "$src1 = $dst" in {
1267 def rrk : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst),
1268 (ins RC:$src1, KRC:$mask, RC:$src2),
1270 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), []>,
1272 def rmk : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst),
1273 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1275 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1280 defm VMOVDQU32 : avx512_mov_int<0x6F, 0x7F, "vmovdqu32", VR512, VK16WM,
1281 memopv16i32, i512mem>,
1282 EVEX_V512, EVEX_CD8<32, CD8VF>;
1283 defm VMOVDQU64 : avx512_mov_int<0x6F, 0x7F, "vmovdqu64", VR512, VK8WM,
1284 memopv8i64, i512mem>,
1285 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1287 // 512-bit unaligned load/store
1288 def : Pat<(loadv8i64 addr:$src), (VMOVDQU64rm addr:$src)>;
1289 def : Pat<(loadv16i32 addr:$src), (VMOVDQU32rm addr:$src)>;
1291 def : Pat<(store (v8i64 VR512:$src), addr:$dst),
1292 (VMOVDQU64mr addr:$dst, VR512:$src)>;
1293 def : Pat<(store (v16i32 VR512:$src), addr:$dst),
1294 (VMOVDQU32mr addr:$dst, VR512:$src)>;
1296 let AddedComplexity = 20 in {
1297 def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1298 (v16f32 VR512:$src2))),
1299 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1300 def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1301 (v8f64 VR512:$src2))),
1302 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1303 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1304 (v16i32 VR512:$src2))),
1305 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1306 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1307 (v8i64 VR512:$src2))),
1308 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1310 // Move Int Doubleword to Packed Double Int
1312 def VMOVDI2PDIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1313 "vmovd\t{$src, $dst|$dst, $src}",
1315 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1317 def VMOVDI2PDIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1318 "vmovd\t{$src, $dst|$dst, $src}",
1320 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1321 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1322 def VMOV64toPQIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1323 "vmovq\t{$src, $dst|$dst, $src}",
1325 (v2i64 (scalar_to_vector GR64:$src)))],
1326 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
1327 let isCodeGenOnly = 1 in {
1328 def VMOV64toSDZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1329 "vmovq\t{$src, $dst|$dst, $src}",
1330 [(set FR64:$dst, (bitconvert GR64:$src))],
1331 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1332 def VMOVSDto64Zrr : AVX512SI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1333 "vmovq\t{$src, $dst|$dst, $src}",
1334 [(set GR64:$dst, (bitconvert FR64:$src))],
1335 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1337 def VMOVSDto64Zmr : AVX512SI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1338 "vmovq\t{$src, $dst|$dst, $src}",
1339 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1340 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1341 EVEX_CD8<64, CD8VT1>;
1343 // Move Int Doubleword to Single Scalar
1345 let isCodeGenOnly = 1 in {
1346 def VMOVDI2SSZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1347 "vmovd\t{$src, $dst|$dst, $src}",
1348 [(set FR32X:$dst, (bitconvert GR32:$src))],
1349 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1351 def VMOVDI2SSZrm : AVX512SI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1352 "vmovd\t{$src, $dst|$dst, $src}",
1353 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1354 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1357 // Move Packed Doubleword Int to Packed Double Int
1359 def VMOVPDI2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1360 "vmovd\t{$src, $dst|$dst, $src}",
1361 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1362 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1364 def VMOVPDI2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1365 (ins i32mem:$dst, VR128X:$src),
1366 "vmovd\t{$src, $dst|$dst, $src}",
1367 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1368 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1369 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1371 // Move Packed Doubleword Int first element to Doubleword Int
1373 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1374 "vmovq\t{$src, $dst|$dst, $src}",
1375 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1377 IIC_SSE_MOVD_ToGP>, TB, OpSize, EVEX, VEX_LIG, VEX_W,
1378 Requires<[HasAVX512, In64BitMode]>;
1380 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
1381 (ins i64mem:$dst, VR128X:$src),
1382 "vmovq\t{$src, $dst|$dst, $src}",
1383 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1384 addr:$dst)], IIC_SSE_MOVDQ>,
1385 EVEX, OpSize, VEX_LIG, VEX_W, TB, EVEX_CD8<64, CD8VT1>,
1386 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1388 // Move Scalar Single to Double Int
1390 let isCodeGenOnly = 1 in {
1391 def VMOVSS2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst),
1393 "vmovd\t{$src, $dst|$dst, $src}",
1394 [(set GR32:$dst, (bitconvert FR32X:$src))],
1395 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1396 def VMOVSS2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1397 (ins i32mem:$dst, FR32X:$src),
1398 "vmovd\t{$src, $dst|$dst, $src}",
1399 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1400 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1403 // Move Quadword Int to Packed Quadword Int
1405 def VMOVQI2PQIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst),
1407 "vmovq\t{$src, $dst|$dst, $src}",
1409 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1410 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1412 //===----------------------------------------------------------------------===//
1413 // AVX-512 MOVSS, MOVSD
1414 //===----------------------------------------------------------------------===//
1416 multiclass avx512_move_scalar <string asm, RegisterClass RC,
1417 SDNode OpNode, ValueType vt,
1418 X86MemOperand x86memop, PatFrag mem_pat> {
1419 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1420 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1421 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1422 (scalar_to_vector RC:$src2))))],
1423 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1424 let Constraints = "$src1 = $dst" in
1425 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
1426 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
1428 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
1429 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
1430 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1431 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1432 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1434 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1435 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1436 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1440 let ExeDomain = SSEPackedSingle in
1441 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
1442 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1444 let ExeDomain = SSEPackedDouble in
1445 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
1446 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1448 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
1449 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
1450 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
1452 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
1453 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
1454 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
1456 // For the disassembler
1457 let isCodeGenOnly = 1 in {
1458 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1459 (ins VR128X:$src1, FR32X:$src2),
1460 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1462 XS, EVEX_4V, VEX_LIG;
1463 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1464 (ins VR128X:$src1, FR64X:$src2),
1465 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1467 XD, EVEX_4V, VEX_LIG, VEX_W;
1470 let Predicates = [HasAVX512] in {
1471 let AddedComplexity = 15 in {
1472 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1473 // MOVS{S,D} to the lower bits.
1474 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1475 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1476 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1477 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1478 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1479 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1480 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1481 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1483 // Move low f32 and clear high bits.
1484 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1485 (SUBREG_TO_REG (i32 0),
1486 (VMOVSSZrr (v4f32 (V_SET0)),
1487 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1488 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1489 (SUBREG_TO_REG (i32 0),
1490 (VMOVSSZrr (v4i32 (V_SET0)),
1491 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1494 let AddedComplexity = 20 in {
1495 // MOVSSrm zeros the high parts of the register; represent this
1496 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1497 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1498 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1499 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1500 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1501 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1502 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1504 // MOVSDrm zeros the high parts of the register; represent this
1505 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1506 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1507 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1508 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1509 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1510 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1511 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1512 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1513 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1514 def : Pat<(v2f64 (X86vzload addr:$src)),
1515 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1517 // Represent the same patterns above but in the form they appear for
1519 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1520 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
1521 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
1522 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1523 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1524 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1525 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1526 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1527 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1529 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1530 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1531 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1532 FR32X:$src)), sub_xmm)>;
1533 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1534 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1535 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1536 FR64X:$src)), sub_xmm)>;
1537 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1538 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
1539 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
1541 // Move low f64 and clear high bits.
1542 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1543 (SUBREG_TO_REG (i32 0),
1544 (VMOVSDZrr (v2f64 (V_SET0)),
1545 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1547 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1548 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1549 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1551 // Extract and store.
1552 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1554 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1555 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1557 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1559 // Shuffle with VMOVSS
1560 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1561 (VMOVSSZrr (v4i32 VR128X:$src1),
1562 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1563 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1564 (VMOVSSZrr (v4f32 VR128X:$src1),
1565 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1568 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1569 (SUBREG_TO_REG (i32 0),
1570 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1571 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1573 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1574 (SUBREG_TO_REG (i32 0),
1575 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1576 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1579 // Shuffle with VMOVSD
1580 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1581 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1582 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1583 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1584 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1585 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1586 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1587 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1590 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1591 (SUBREG_TO_REG (i32 0),
1592 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1593 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1595 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1596 (SUBREG_TO_REG (i32 0),
1597 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1598 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1601 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1602 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1603 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1604 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1605 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1606 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1607 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1608 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1611 let AddedComplexity = 15 in
1612 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1614 "vmovq\t{$src, $dst|$dst, $src}",
1615 [(set VR128X:$dst, (v2i64 (X86vzmovl
1616 (v2i64 VR128X:$src))))],
1617 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1619 let AddedComplexity = 20 in
1620 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1622 "vmovq\t{$src, $dst|$dst, $src}",
1623 [(set VR128X:$dst, (v2i64 (X86vzmovl
1624 (loadv2i64 addr:$src))))],
1625 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1626 EVEX_CD8<8, CD8VT8>;
1628 let Predicates = [HasAVX512] in {
1629 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1630 let AddedComplexity = 20 in {
1631 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1632 (VMOVDI2PDIZrm addr:$src)>;
1633 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
1634 (VMOV64toPQIZrr GR64:$src)>;
1635 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
1636 (VMOVDI2PDIZrr GR32:$src)>;
1638 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1639 (VMOVDI2PDIZrm addr:$src)>;
1640 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1641 (VMOVDI2PDIZrm addr:$src)>;
1642 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1643 (VMOVZPQILo2PQIZrm addr:$src)>;
1644 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1645 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1646 def : Pat<(v2i64 (X86vzload addr:$src)),
1647 (VMOVZPQILo2PQIZrm addr:$src)>;
1650 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1651 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1652 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1653 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1654 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1655 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1656 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1659 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
1660 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1662 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
1663 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1665 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
1666 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1668 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
1669 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1671 //===----------------------------------------------------------------------===//
1672 // AVX-512 - Integer arithmetic
1674 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1675 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1676 X86MemOperand x86memop, PatFrag scalar_mfrag,
1677 X86MemOperand x86scalar_mop, string BrdcstStr,
1678 OpndItins itins, bit IsCommutable = 0> {
1679 let isCommutable = IsCommutable in
1680 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1681 (ins RC:$src1, RC:$src2),
1682 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1683 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1685 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1686 (ins RC:$src1, x86memop:$src2),
1687 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1688 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
1690 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1691 (ins RC:$src1, x86scalar_mop:$src2),
1692 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1693 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1694 [(set RC:$dst, (OpNode RC:$src1,
1695 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1696 itins.rm>, EVEX_4V, EVEX_B;
1698 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr,
1699 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
1700 PatFrag memop_frag, X86MemOperand x86memop,
1702 bit IsCommutable = 0> {
1703 let isCommutable = IsCommutable in
1704 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1705 (ins RC:$src1, RC:$src2),
1706 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1707 []>, EVEX_4V, VEX_W;
1708 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1709 (ins RC:$src1, x86memop:$src2),
1710 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1711 []>, EVEX_4V, VEX_W;
1714 defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VR512, memopv16i32,
1715 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1716 EVEX_V512, EVEX_CD8<32, CD8VF>;
1718 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VR512, memopv16i32,
1719 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 0>,
1720 EVEX_V512, EVEX_CD8<32, CD8VF>;
1722 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VR512, memopv16i32,
1723 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1724 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1726 defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VR512, memopv8i64,
1727 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 1>,
1728 EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
1730 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VR512, memopv8i64,
1731 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1732 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1734 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32,
1735 VR512, memopv8i64, i512mem, SSE_INTALU_ITINS_P, 1>, T8,
1736 EVEX_V512, EVEX_CD8<64, CD8VF>;
1738 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32,
1739 VR512, memopv8i64, i512mem, SSE_INTMUL_ITINS_P, 1>, EVEX_V512,
1740 EVEX_CD8<64, CD8VF>;
1742 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
1743 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1745 defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VR512, memopv16i32,
1746 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1747 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1748 defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VR512, memopv8i64,
1749 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1750 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1752 defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VR512, memopv16i32,
1753 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1754 EVEX_V512, EVEX_CD8<32, CD8VF>;
1755 defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VR512, memopv8i64,
1756 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1757 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1759 defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VR512, memopv16i32,
1760 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1761 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1762 defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VR512, memopv8i64,
1763 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1764 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1766 defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VR512, memopv16i32,
1767 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1768 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1769 defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VR512, memopv8i64,
1770 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1771 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1773 //===----------------------------------------------------------------------===//
1774 // AVX-512 - Unpack Instructions
1775 //===----------------------------------------------------------------------===//
1777 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
1778 PatFrag mem_frag, RegisterClass RC,
1779 X86MemOperand x86memop, string asm,
1781 def rr : AVX512PI<opc, MRMSrcReg,
1782 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1784 (vt (OpNode RC:$src1, RC:$src2)))],
1786 def rm : AVX512PI<opc, MRMSrcMem,
1787 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1789 (vt (OpNode RC:$src1,
1790 (bitconvert (mem_frag addr:$src2)))))],
1794 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
1795 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1796 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1797 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
1798 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1799 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1800 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
1801 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1802 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1803 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
1804 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1805 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1807 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
1808 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1809 X86MemOperand x86memop> {
1810 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1811 (ins RC:$src1, RC:$src2),
1812 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1813 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1814 IIC_SSE_UNPCK>, EVEX_4V;
1815 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1816 (ins RC:$src1, x86memop:$src2),
1817 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1818 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
1819 (bitconvert (memop_frag addr:$src2)))))],
1820 IIC_SSE_UNPCK>, EVEX_4V;
1822 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
1823 VR512, memopv16i32, i512mem>, EVEX_V512,
1824 EVEX_CD8<32, CD8VF>;
1825 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
1826 VR512, memopv8i64, i512mem>, EVEX_V512,
1827 VEX_W, EVEX_CD8<64, CD8VF>;
1828 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
1829 VR512, memopv16i32, i512mem>, EVEX_V512,
1830 EVEX_CD8<32, CD8VF>;
1831 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
1832 VR512, memopv8i64, i512mem>, EVEX_V512,
1833 VEX_W, EVEX_CD8<64, CD8VF>;
1834 //===----------------------------------------------------------------------===//
1838 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
1839 SDNode OpNode, PatFrag mem_frag,
1840 X86MemOperand x86memop, ValueType OpVT> {
1841 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
1842 (ins RC:$src1, i8imm:$src2),
1843 !strconcat(OpcodeStr,
1844 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1846 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
1848 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
1849 (ins x86memop:$src1, i8imm:$src2),
1850 !strconcat(OpcodeStr,
1851 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1853 (OpVT (OpNode (mem_frag addr:$src1),
1854 (i8 imm:$src2))))]>, EVEX;
1857 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
1858 i512mem, v16i32>, OpSize, EVEX_V512, EVEX_CD8<32, CD8VF>;
1860 let ExeDomain = SSEPackedSingle in
1861 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
1862 memopv16f32, i512mem, v16f32>, OpSize, TA, EVEX_V512,
1863 EVEX_CD8<32, CD8VF>;
1864 let ExeDomain = SSEPackedDouble in
1865 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
1866 memopv8f64, i512mem, v8f64>, OpSize, TA, EVEX_V512,
1867 VEX_W, EVEX_CD8<32, CD8VF>;
1869 def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1870 (VPERMILPSZri VR512:$src1, imm:$imm)>;
1871 def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1872 (VPERMILPDZri VR512:$src1, imm:$imm)>;
1874 //===----------------------------------------------------------------------===//
1875 // AVX-512 Logical Instructions
1876 //===----------------------------------------------------------------------===//
1878 defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VR512, memopv16i32,
1879 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1880 EVEX_V512, EVEX_CD8<32, CD8VF>;
1881 defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VR512, memopv8i64,
1882 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1883 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1884 defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VR512, memopv16i32,
1885 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1886 EVEX_V512, EVEX_CD8<32, CD8VF>;
1887 defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VR512, memopv8i64,
1888 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1889 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1890 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VR512, memopv16i32,
1891 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1892 EVEX_V512, EVEX_CD8<32, CD8VF>;
1893 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VR512, memopv8i64,
1894 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1895 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1896 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VR512,
1897 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1898 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1899 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VR512, memopv8i64,
1900 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 0>,
1901 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1903 //===----------------------------------------------------------------------===//
1904 // AVX-512 FP arithmetic
1905 //===----------------------------------------------------------------------===//
1907 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1909 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
1910 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
1911 EVEX_CD8<32, CD8VT1>;
1912 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
1913 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
1914 EVEX_CD8<64, CD8VT1>;
1917 let isCommutable = 1 in {
1918 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
1919 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
1920 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
1921 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
1923 let isCommutable = 0 in {
1924 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
1925 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
1928 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1929 RegisterClass RC, ValueType vt,
1930 X86MemOperand x86memop, PatFrag mem_frag,
1931 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
1933 Domain d, OpndItins itins, bit commutable> {
1934 let isCommutable = commutable in
1935 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1936 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1937 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
1939 let mayLoad = 1 in {
1940 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1941 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1942 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
1943 itins.rm, d>, EVEX_4V, TB;
1944 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
1945 (ins RC:$src1, x86scalar_mop:$src2),
1946 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1947 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1948 [(set RC:$dst, (OpNode RC:$src1,
1949 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1950 itins.rm, d>, EVEX_4V, EVEX_B, TB;
1954 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VR512, v16f32, f512mem,
1955 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1956 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1958 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VR512, v8f64, f512mem,
1959 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1960 SSE_ALU_ITINS_P.d, 1>,
1961 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1963 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VR512, v16f32, f512mem,
1964 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1965 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1966 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VR512, v8f64, f512mem,
1967 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1968 SSE_ALU_ITINS_P.d, 1>,
1969 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1971 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VR512, v16f32, f512mem,
1972 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1973 SSE_ALU_ITINS_P.s, 1>,
1974 EVEX_V512, EVEX_CD8<32, CD8VF>;
1975 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VR512, v16f32, f512mem,
1976 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1977 SSE_ALU_ITINS_P.s, 1>,
1978 EVEX_V512, EVEX_CD8<32, CD8VF>;
1980 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VR512, v8f64, f512mem,
1981 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1982 SSE_ALU_ITINS_P.d, 1>,
1983 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1984 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VR512, v8f64, f512mem,
1985 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1986 SSE_ALU_ITINS_P.d, 1>,
1987 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1989 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VR512, v16f32, f512mem,
1990 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1991 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1992 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VR512, v16f32, f512mem,
1993 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1994 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1996 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VR512, v8f64, f512mem,
1997 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1998 SSE_ALU_ITINS_P.d, 0>,
1999 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
2000 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VR512, v8f64, f512mem,
2001 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2002 SSE_ALU_ITINS_P.d, 0>,
2003 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
2005 //===----------------------------------------------------------------------===//
2006 // AVX-512 VPTESTM instructions
2007 //===----------------------------------------------------------------------===//
2009 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2010 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
2011 SDNode OpNode, ValueType vt> {
2012 def rr : AVX5128I<opc, MRMSrcReg,
2013 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
2014 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2015 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))]>, EVEX_4V;
2016 def rm : AVX5128I<opc, MRMSrcMem,
2017 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
2018 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2019 [(set KRC:$dst, (OpNode (vt RC:$src1),
2020 (bitconvert (memop_frag addr:$src2))))]>, EVEX_4V;
2023 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
2024 memopv16i32, X86testm, v16i32>, EVEX_V512,
2025 EVEX_CD8<32, CD8VF>;
2026 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
2027 memopv8i64, X86testm, v8i64>, EVEX_V512, VEX_W,
2028 EVEX_CD8<64, CD8VF>;
2030 //===----------------------------------------------------------------------===//
2031 // AVX-512 Shift instructions
2032 //===----------------------------------------------------------------------===//
2033 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
2034 string OpcodeStr, SDNode OpNode, RegisterClass RC,
2035 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
2036 RegisterClass KRC> {
2037 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2038 (ins RC:$src1, i8imm:$src2),
2039 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2040 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
2041 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2042 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2043 (ins KRC:$mask, RC:$src1, i8imm:$src2),
2044 !strconcat(OpcodeStr,
2045 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2046 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2047 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2048 (ins x86memop:$src1, i8imm:$src2),
2049 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2050 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
2051 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2052 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2053 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
2054 !strconcat(OpcodeStr,
2055 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2056 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2059 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2060 RegisterClass RC, ValueType vt, ValueType SrcVT,
2061 PatFrag bc_frag, RegisterClass KRC> {
2062 // src2 is always 128-bit
2063 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2064 (ins RC:$src1, VR128X:$src2),
2065 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2066 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
2067 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2068 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2069 (ins KRC:$mask, RC:$src1, VR128X:$src2),
2070 !strconcat(OpcodeStr,
2071 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2072 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2073 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2074 (ins RC:$src1, i128mem:$src2),
2075 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2076 [(set RC:$dst, (vt (OpNode RC:$src1,
2077 (bc_frag (memopv2i64 addr:$src2)))))],
2078 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2079 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2080 (ins KRC:$mask, RC:$src1, i128mem:$src2),
2081 !strconcat(OpcodeStr,
2082 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2083 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2086 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
2087 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2088 EVEX_V512, EVEX_CD8<32, CD8VF>;
2089 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
2090 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2091 EVEX_CD8<32, CD8VQ>;
2093 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
2094 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2095 EVEX_CD8<64, CD8VF>, VEX_W;
2096 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
2097 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2098 EVEX_CD8<64, CD8VQ>, VEX_W;
2100 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
2101 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
2102 EVEX_CD8<32, CD8VF>;
2103 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
2104 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2105 EVEX_CD8<32, CD8VQ>;
2107 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
2108 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2109 EVEX_CD8<64, CD8VF>, VEX_W;
2110 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
2111 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2112 EVEX_CD8<64, CD8VQ>, VEX_W;
2114 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
2115 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2116 EVEX_V512, EVEX_CD8<32, CD8VF>;
2117 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
2118 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2119 EVEX_CD8<32, CD8VQ>;
2121 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
2122 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2123 EVEX_CD8<64, CD8VF>, VEX_W;
2124 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
2125 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2126 EVEX_CD8<64, CD8VQ>, VEX_W;
2128 //===-------------------------------------------------------------------===//
2129 // Variable Bit Shifts
2130 //===-------------------------------------------------------------------===//
2131 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
2132 RegisterClass RC, ValueType vt,
2133 X86MemOperand x86memop, PatFrag mem_frag> {
2134 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
2135 (ins RC:$src1, RC:$src2),
2136 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2138 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
2140 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
2141 (ins RC:$src1, x86memop:$src2),
2142 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2144 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
2148 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
2149 i512mem, memopv16i32>, EVEX_V512,
2150 EVEX_CD8<32, CD8VF>;
2151 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
2152 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2153 EVEX_CD8<64, CD8VF>;
2154 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
2155 i512mem, memopv16i32>, EVEX_V512,
2156 EVEX_CD8<32, CD8VF>;
2157 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
2158 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2159 EVEX_CD8<64, CD8VF>;
2160 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
2161 i512mem, memopv16i32>, EVEX_V512,
2162 EVEX_CD8<32, CD8VF>;
2163 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
2164 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2165 EVEX_CD8<64, CD8VF>;
2167 //===----------------------------------------------------------------------===//
2168 // AVX-512 - MOVDDUP
2169 //===----------------------------------------------------------------------===//
2171 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
2172 X86MemOperand x86memop, PatFrag memop_frag> {
2173 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2174 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2175 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
2176 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2177 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2179 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
2182 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
2183 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
2184 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
2185 (VMOVDDUPZrm addr:$src)>;
2187 //===---------------------------------------------------------------------===//
2188 // Replicate Single FP - MOVSHDUP and MOVSLDUP
2189 //===---------------------------------------------------------------------===//
2190 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
2191 ValueType vt, RegisterClass RC, PatFrag mem_frag,
2192 X86MemOperand x86memop> {
2193 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2194 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2195 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
2197 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2198 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2199 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
2202 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
2203 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2204 EVEX_CD8<32, CD8VF>;
2205 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
2206 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2207 EVEX_CD8<32, CD8VF>;
2209 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
2210 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
2211 (VMOVSHDUPZrm addr:$src)>;
2212 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
2213 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
2214 (VMOVSLDUPZrm addr:$src)>;
2216 //===----------------------------------------------------------------------===//
2217 // Move Low to High and High to Low packed FP Instructions
2218 //===----------------------------------------------------------------------===//
2219 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
2220 (ins VR128X:$src1, VR128X:$src2),
2221 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2222 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2223 IIC_SSE_MOV_LH>, EVEX_4V;
2224 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2225 (ins VR128X:$src1, VR128X:$src2),
2226 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2227 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2228 IIC_SSE_MOV_LH>, EVEX_4V;
2230 let Predicates = [HasAVX512] in {
2232 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2233 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2234 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2235 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
2238 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2239 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2242 //===----------------------------------------------------------------------===//
2243 // FMA - Fused Multiply Operations
2245 let Constraints = "$src1 = $dst" in {
2246 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2247 RegisterClass RC, X86MemOperand x86memop,
2248 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2249 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2250 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2251 (ins RC:$src1, RC:$src2, RC:$src3),
2252 !strconcat(OpcodeStr,"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2253 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2256 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2257 (ins RC:$src1, RC:$src2, x86memop:$src3),
2258 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2259 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2260 (mem_frag addr:$src3))))]>;
2261 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2262 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2263 !strconcat(OpcodeStr, "\t{${src3}", BrdcstStr,
2264 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2265 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2266 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2268 } // Constraints = "$src1 = $dst"
2270 let ExeDomain = SSEPackedSingle in {
2271 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2272 memopv16f32, f32mem, loadf32, "{1to16}",
2273 X86Fmadd, v16f32>, EVEX_V512,
2274 EVEX_CD8<32, CD8VF>;
2275 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2276 memopv16f32, f32mem, loadf32, "{1to16}",
2277 X86Fmsub, v16f32>, EVEX_V512,
2278 EVEX_CD8<32, CD8VF>;
2279 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2280 memopv16f32, f32mem, loadf32, "{1to16}",
2281 X86Fmaddsub, v16f32>,
2282 EVEX_V512, EVEX_CD8<32, CD8VF>;
2283 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2284 memopv16f32, f32mem, loadf32, "{1to16}",
2285 X86Fmsubadd, v16f32>,
2286 EVEX_V512, EVEX_CD8<32, CD8VF>;
2287 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2288 memopv16f32, f32mem, loadf32, "{1to16}",
2289 X86Fnmadd, v16f32>, EVEX_V512,
2290 EVEX_CD8<32, CD8VF>;
2291 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2292 memopv16f32, f32mem, loadf32, "{1to16}",
2293 X86Fnmsub, v16f32>, EVEX_V512,
2294 EVEX_CD8<32, CD8VF>;
2296 let ExeDomain = SSEPackedDouble in {
2297 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2298 memopv8f64, f64mem, loadf64, "{1to8}",
2299 X86Fmadd, v8f64>, EVEX_V512,
2300 VEX_W, EVEX_CD8<64, CD8VF>;
2301 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2302 memopv8f64, f64mem, loadf64, "{1to8}",
2303 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2304 EVEX_CD8<64, CD8VF>;
2305 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2306 memopv8f64, f64mem, loadf64, "{1to8}",
2307 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2308 EVEX_CD8<64, CD8VF>;
2309 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2310 memopv8f64, f64mem, loadf64, "{1to8}",
2311 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2312 EVEX_CD8<64, CD8VF>;
2313 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2314 memopv8f64, f64mem, loadf64, "{1to8}",
2315 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2316 EVEX_CD8<64, CD8VF>;
2317 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2318 memopv8f64, f64mem, loadf64, "{1to8}",
2319 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2320 EVEX_CD8<64, CD8VF>;
2323 let Constraints = "$src1 = $dst" in {
2324 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2325 RegisterClass RC, X86MemOperand x86memop,
2326 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2327 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2329 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2330 (ins RC:$src1, RC:$src3, x86memop:$src2),
2331 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2332 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2333 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2334 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2335 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2336 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2337 [(set RC:$dst, (OpNode RC:$src1,
2338 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2340 } // Constraints = "$src1 = $dst"
2343 let ExeDomain = SSEPackedSingle in {
2344 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2345 memopv16f32, f32mem, loadf32, "{1to16}",
2346 X86Fmadd, v16f32>, EVEX_V512,
2347 EVEX_CD8<32, CD8VF>;
2348 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2349 memopv16f32, f32mem, loadf32, "{1to16}",
2350 X86Fmsub, v16f32>, EVEX_V512,
2351 EVEX_CD8<32, CD8VF>;
2352 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
2353 memopv16f32, f32mem, loadf32, "{1to16}",
2354 X86Fmaddsub, v16f32>,
2355 EVEX_V512, EVEX_CD8<32, CD8VF>;
2356 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
2357 memopv16f32, f32mem, loadf32, "{1to16}",
2358 X86Fmsubadd, v16f32>,
2359 EVEX_V512, EVEX_CD8<32, CD8VF>;
2360 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
2361 memopv16f32, f32mem, loadf32, "{1to16}",
2362 X86Fnmadd, v16f32>, EVEX_V512,
2363 EVEX_CD8<32, CD8VF>;
2364 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
2365 memopv16f32, f32mem, loadf32, "{1to16}",
2366 X86Fnmsub, v16f32>, EVEX_V512,
2367 EVEX_CD8<32, CD8VF>;
2369 let ExeDomain = SSEPackedDouble in {
2370 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
2371 memopv8f64, f64mem, loadf64, "{1to8}",
2372 X86Fmadd, v8f64>, EVEX_V512,
2373 VEX_W, EVEX_CD8<64, CD8VF>;
2374 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
2375 memopv8f64, f64mem, loadf64, "{1to8}",
2376 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2377 EVEX_CD8<64, CD8VF>;
2378 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
2379 memopv8f64, f64mem, loadf64, "{1to8}",
2380 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2381 EVEX_CD8<64, CD8VF>;
2382 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
2383 memopv8f64, f64mem, loadf64, "{1to8}",
2384 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2385 EVEX_CD8<64, CD8VF>;
2386 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
2387 memopv8f64, f64mem, loadf64, "{1to8}",
2388 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2389 EVEX_CD8<64, CD8VF>;
2390 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
2391 memopv8f64, f64mem, loadf64, "{1to8}",
2392 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2393 EVEX_CD8<64, CD8VF>;
2397 let Constraints = "$src1 = $dst" in {
2398 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2399 RegisterClass RC, ValueType OpVT,
2400 X86MemOperand x86memop, Operand memop,
2402 let isCommutable = 1 in
2403 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2404 (ins RC:$src1, RC:$src2, RC:$src3),
2405 !strconcat(OpcodeStr,
2406 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2408 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
2410 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2411 (ins RC:$src1, RC:$src2, f128mem:$src3),
2412 !strconcat(OpcodeStr,
2413 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2415 (OpVT (OpNode RC:$src2, RC:$src1,
2416 (mem_frag addr:$src3))))]>;
2419 } // Constraints = "$src1 = $dst"
2421 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
2422 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2423 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
2424 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2425 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
2426 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2427 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
2428 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2429 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
2430 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2431 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
2432 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2433 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
2434 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2435 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
2436 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2438 //===----------------------------------------------------------------------===//
2439 // AVX-512 Scalar convert from sign integer to float/double
2440 //===----------------------------------------------------------------------===//
2442 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2443 X86MemOperand x86memop, string asm> {
2444 let neverHasSideEffects = 1 in {
2445 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
2446 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2449 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
2450 (ins DstRC:$src1, x86memop:$src),
2451 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2453 } // neverHasSideEffects = 1
2455 let Predicates = [HasAVX512] in {
2456 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
2457 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2458 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
2459 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2460 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
2461 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2462 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
2463 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2465 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
2466 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2467 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
2468 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2469 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
2470 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2471 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
2472 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2474 def : Pat<(f32 (sint_to_fp GR32:$src)),
2475 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2476 def : Pat<(f32 (sint_to_fp GR64:$src)),
2477 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2478 def : Pat<(f64 (sint_to_fp GR32:$src)),
2479 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2480 def : Pat<(f64 (sint_to_fp GR64:$src)),
2481 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2483 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
2484 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2485 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
2486 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2487 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
2488 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2489 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
2490 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2492 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
2493 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2494 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
2495 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2496 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
2497 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2498 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
2499 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2501 def : Pat<(f32 (uint_to_fp GR32:$src)),
2502 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2503 def : Pat<(f32 (uint_to_fp GR64:$src)),
2504 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2505 def : Pat<(f64 (uint_to_fp GR32:$src)),
2506 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2507 def : Pat<(f64 (uint_to_fp GR64:$src)),
2508 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2511 //===----------------------------------------------------------------------===//
2512 // AVX-512 Scalar convert from float/double to integer
2513 //===----------------------------------------------------------------------===//
2514 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2515 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
2517 let neverHasSideEffects = 1 in {
2518 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2519 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2520 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
2521 Requires<[HasAVX512]>;
2523 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
2524 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
2525 Requires<[HasAVX512]>;
2526 } // neverHasSideEffects = 1
2528 let Predicates = [HasAVX512] in {
2529 // Convert float/double to signed/unsigned int 32/64
2530 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
2531 ssmem, sse_load_f32, "cvtss2si">,
2532 XS, EVEX_CD8<32, CD8VT1>;
2533 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
2534 ssmem, sse_load_f32, "cvtss2si">,
2535 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
2536 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
2537 ssmem, sse_load_f32, "cvtss2usi">,
2538 XS, EVEX_CD8<32, CD8VT1>;
2539 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2540 int_x86_avx512_cvtss2usi64, ssmem,
2541 sse_load_f32, "cvtss2usi">, XS, VEX_W,
2542 EVEX_CD8<32, CD8VT1>;
2543 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
2544 sdmem, sse_load_f64, "cvtsd2si">,
2545 XD, EVEX_CD8<64, CD8VT1>;
2546 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
2547 sdmem, sse_load_f64, "cvtsd2si">,
2548 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2549 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
2550 sdmem, sse_load_f64, "cvtsd2usi">,
2551 XD, EVEX_CD8<64, CD8VT1>;
2552 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2553 int_x86_avx512_cvtsd2usi64, sdmem,
2554 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
2555 EVEX_CD8<64, CD8VT1>;
2557 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2558 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
2559 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2560 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2561 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
2562 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2563 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2564 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
2565 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2566 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2567 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
2568 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2570 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2571 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
2572 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2573 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2574 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
2575 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2576 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2577 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
2578 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2579 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2580 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
2581 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2583 // Convert float/double to signed/unsigned int 32/64 with truncation
2584 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
2585 ssmem, sse_load_f32, "cvttss2si">,
2586 XS, EVEX_CD8<32, CD8VT1>;
2587 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2588 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
2589 "cvttss2si">, XS, VEX_W,
2590 EVEX_CD8<32, CD8VT1>;
2591 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
2592 sdmem, sse_load_f64, "cvttsd2si">, XD,
2593 EVEX_CD8<64, CD8VT1>;
2594 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2595 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
2596 "cvttsd2si">, XD, VEX_W,
2597 EVEX_CD8<64, CD8VT1>;
2598 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2599 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
2600 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
2601 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2602 int_x86_avx512_cvttss2usi64, ssmem,
2603 sse_load_f32, "cvttss2usi">, XS, VEX_W,
2604 EVEX_CD8<32, CD8VT1>;
2605 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2606 int_x86_avx512_cvttsd2usi,
2607 sdmem, sse_load_f64, "cvttsd2usi">, XD,
2608 EVEX_CD8<64, CD8VT1>;
2609 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2610 int_x86_avx512_cvttsd2usi64, sdmem,
2611 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
2612 EVEX_CD8<64, CD8VT1>;
2614 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2615 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
2617 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2618 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2619 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
2620 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2621 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2622 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
2625 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
2626 loadf32, "cvttss2si">, XS,
2627 EVEX_CD8<32, CD8VT1>;
2628 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
2629 loadf32, "cvttss2usi">, XS,
2630 EVEX_CD8<32, CD8VT1>;
2631 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
2632 loadf32, "cvttss2si">, XS, VEX_W,
2633 EVEX_CD8<32, CD8VT1>;
2634 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
2635 loadf32, "cvttss2usi">, XS, VEX_W,
2636 EVEX_CD8<32, CD8VT1>;
2637 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
2638 loadf64, "cvttsd2si">, XD,
2639 EVEX_CD8<64, CD8VT1>;
2640 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
2641 loadf64, "cvttsd2usi">, XD,
2642 EVEX_CD8<64, CD8VT1>;
2643 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
2644 loadf64, "cvttsd2si">, XD, VEX_W,
2645 EVEX_CD8<64, CD8VT1>;
2646 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
2647 loadf64, "cvttsd2usi">, XD, VEX_W,
2648 EVEX_CD8<64, CD8VT1>;
2650 //===----------------------------------------------------------------------===//
2651 // AVX-512 Convert form float to double and back
2652 //===----------------------------------------------------------------------===//
2653 let neverHasSideEffects = 1 in {
2654 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
2655 (ins FR32X:$src1, FR32X:$src2),
2656 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2657 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
2659 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
2660 (ins FR32X:$src1, f32mem:$src2),
2661 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2662 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
2663 EVEX_CD8<32, CD8VT1>;
2665 // Convert scalar double to scalar single
2666 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
2667 (ins FR64X:$src1, FR64X:$src2),
2668 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2669 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
2671 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
2672 (ins FR64X:$src1, f64mem:$src2),
2673 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2674 []>, EVEX_4V, VEX_LIG, VEX_W,
2675 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
2678 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
2679 Requires<[HasAVX512]>;
2680 def : Pat<(fextend (loadf32 addr:$src)),
2681 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
2683 def : Pat<(extloadf32 addr:$src),
2684 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
2685 Requires<[HasAVX512, OptForSize]>;
2687 def : Pat<(extloadf32 addr:$src),
2688 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
2689 Requires<[HasAVX512, OptForSpeed]>;
2691 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
2692 Requires<[HasAVX512]>;
2694 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
2695 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2696 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2698 let neverHasSideEffects = 1 in {
2699 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2700 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2702 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2704 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2705 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2707 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2708 } // neverHasSideEffects = 1
2711 defm VCVTPD2PSZ : avx512_vcvt_fp<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
2712 memopv8f64, f512mem, v8f32, v8f64,
2713 SSEPackedSingle>, EVEX_V512, VEX_W, OpSize,
2714 EVEX_CD8<64, CD8VF>;
2716 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
2717 memopv4f64, f256mem, v8f64, v8f32,
2718 SSEPackedDouble>, EVEX_V512, EVEX_CD8<32, CD8VH>;
2719 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2720 (VCVTPS2PDZrm addr:$src)>;
2722 //===----------------------------------------------------------------------===//
2723 // AVX-512 Vector convert from sign integer to float/double
2724 //===----------------------------------------------------------------------===//
2726 defm VCVTDQ2PSZ : avx512_vcvt_fp<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
2727 memopv8i64, i512mem, v16f32, v16i32,
2728 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2730 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
2731 memopv4i64, i256mem, v8f64, v8i32,
2732 SSEPackedDouble>, EVEX_V512, XS,
2733 EVEX_CD8<32, CD8VH>;
2735 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
2736 memopv16f32, f512mem, v16i32, v16f32,
2737 SSEPackedSingle>, EVEX_V512, XS,
2738 EVEX_CD8<32, CD8VF>;
2740 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
2741 memopv8f64, f512mem, v8i32, v8f64,
2742 SSEPackedDouble>, EVEX_V512, OpSize, VEX_W,
2743 EVEX_CD8<64, CD8VF>;
2745 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
2746 memopv16f32, f512mem, v16i32, v16f32,
2747 SSEPackedSingle>, EVEX_V512,
2748 EVEX_CD8<32, CD8VF>;
2750 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
2751 memopv8f64, f512mem, v8i32, v8f64,
2752 SSEPackedDouble>, EVEX_V512, VEX_W,
2753 EVEX_CD8<64, CD8VF>;
2755 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
2756 memopv4i64, f256mem, v8f64, v8i32,
2757 SSEPackedDouble>, EVEX_V512, XS,
2758 EVEX_CD8<32, CD8VH>;
2760 defm VCVTUDQ2PSZ : avx512_vcvt_fp<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
2761 memopv16i32, f512mem, v16f32, v16i32,
2762 SSEPackedSingle>, EVEX_V512, XD,
2763 EVEX_CD8<32, CD8VF>;
2765 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
2766 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
2767 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
2770 def : Pat<(int_x86_avx512_cvtdq2_ps_512 VR512:$src),
2771 (VCVTDQ2PSZrr VR512:$src)>;
2772 def : Pat<(int_x86_avx512_cvtdq2_ps_512 (bitconvert (memopv8i64 addr:$src))),
2773 (VCVTDQ2PSZrm addr:$src)>;
2775 def VCVTPS2DQZrr : AVX512BI<0x5B, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2776 "vcvtps2dq\t{$src, $dst|$dst, $src}",
2778 (int_x86_avx512_cvt_ps2dq_512 VR512:$src))],
2779 IIC_SSE_CVT_PS_RR>, EVEX, EVEX_V512;
2780 def VCVTPS2DQZrm : AVX512BI<0x5B, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2781 "vcvtps2dq\t{$src, $dst|$dst, $src}",
2783 (int_x86_avx512_cvt_ps2dq_512 (memopv16f32 addr:$src)))],
2784 IIC_SSE_CVT_PS_RM>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2787 let Predicates = [HasAVX512] in {
2788 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
2789 (VCVTPD2PSZrm addr:$src)>;
2790 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2791 (VCVTPS2PDZrm addr:$src)>;
2794 //===----------------------------------------------------------------------===//
2795 // Half precision conversion instructions
2796 //===----------------------------------------------------------------------===//
2797 multiclass avx512_f16c_ph2ps<RegisterClass destRC, RegisterClass srcRC,
2798 X86MemOperand x86memop, Intrinsic Int> {
2799 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
2800 "vcvtph2ps\t{$src, $dst|$dst, $src}",
2801 [(set destRC:$dst, (Int srcRC:$src))]>, EVEX;
2802 let neverHasSideEffects = 1, mayLoad = 1 in
2803 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
2804 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
2807 multiclass avx512_f16c_ps2ph<RegisterClass destRC, RegisterClass srcRC,
2808 X86MemOperand x86memop, Intrinsic Int> {
2809 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
2810 (ins srcRC:$src1, i32i8imm:$src2),
2811 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2812 [(set destRC:$dst, (Int srcRC:$src1, imm:$src2))]>, EVEX;
2813 let neverHasSideEffects = 1, mayStore = 1 in
2814 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
2815 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
2816 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
2819 defm VCVTPH2PSZ : avx512_f16c_ph2ps<VR512, VR256X, f256mem,
2820 int_x86_avx512_vcvtph2ps_512>, EVEX_V512,
2821 EVEX_CD8<32, CD8VH>;
2822 defm VCVTPS2PHZ : avx512_f16c_ps2ph<VR256X, VR512, f256mem,
2823 int_x86_avx512_vcvtps2ph_512>, EVEX_V512,
2824 EVEX_CD8<32, CD8VH>;
2826 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
2827 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
2828 "ucomiss">, TB, EVEX, VEX_LIG,
2829 EVEX_CD8<32, CD8VT1>;
2830 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
2831 "ucomisd">, TB, OpSize, EVEX,
2832 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2833 let Pattern = []<dag> in {
2834 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
2835 "comiss">, TB, EVEX, VEX_LIG,
2836 EVEX_CD8<32, CD8VT1>;
2837 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
2838 "comisd">, TB, OpSize, EVEX,
2839 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2841 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
2842 load, "ucomiss">, TB, EVEX, VEX_LIG,
2843 EVEX_CD8<32, CD8VT1>;
2844 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
2845 load, "ucomisd">, TB, OpSize, EVEX,
2846 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2848 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
2849 load, "comiss">, TB, EVEX, VEX_LIG,
2850 EVEX_CD8<32, CD8VT1>;
2851 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
2852 load, "comisd">, TB, OpSize, EVEX,
2853 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2856 /// avx512_unop_p - AVX-512 unops in packed form.
2857 multiclass avx512_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2858 def PSZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2859 !strconcat(OpcodeStr,
2860 "ps\t{$src, $dst|$dst, $src}"),
2861 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))]>,
2863 def PSZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f256mem:$src),
2864 !strconcat(OpcodeStr,
2865 "ps\t{$src, $dst|$dst, $src}"),
2866 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
2867 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2868 def PDZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2869 !strconcat(OpcodeStr,
2870 "pd\t{$src, $dst|$dst, $src}"),
2871 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))]>,
2872 EVEX, EVEX_V512, VEX_W;
2873 def PDZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2874 !strconcat(OpcodeStr,
2875 "pd\t{$src, $dst|$dst, $src}"),
2876 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
2877 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2880 /// avx512_fp_unop_p_int - AVX-512 intrinsics unops in packed forms.
2881 multiclass avx512_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2882 Intrinsic V16F32Int, Intrinsic V8F64Int> {
2883 def PSZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2884 !strconcat(OpcodeStr,
2885 "ps\t{$src, $dst|$dst, $src}"),
2886 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
2888 def PSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2889 !strconcat(OpcodeStr,
2890 "ps\t{$src, $dst|$dst, $src}"),
2892 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
2893 EVEX_V512, EVEX_CD8<32, CD8VF>;
2894 def PDZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2895 !strconcat(OpcodeStr,
2896 "pd\t{$src, $dst|$dst, $src}"),
2897 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
2898 EVEX, EVEX_V512, VEX_W;
2899 def PDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2900 !strconcat(OpcodeStr,
2901 "pd\t{$src, $dst|$dst, $src}"),
2903 (V8F64Int (memopv8f64 addr:$src)))]>,
2904 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2907 /// avx512_fp_unop_s - AVX-512 unops in scalar form.
2908 multiclass avx512_fp_unop_s<bits<8> opc, string OpcodeStr> {
2909 let hasSideEffects = 0 in {
2910 def SSZr : AVX5128I<opc, MRMSrcReg, (outs FR32X:$dst),
2911 (ins FR32X:$src1, FR32X:$src2),
2912 !strconcat(OpcodeStr,
2913 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2915 let mayLoad = 1 in {
2916 def SSZm : AVX5128I<opc, MRMSrcMem, (outs FR32X:$dst),
2917 (ins FR32X:$src1, f32mem:$src2),
2918 !strconcat(OpcodeStr,
2919 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2920 []>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2921 def SSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
2922 (ins VR128X:$src1, ssmem:$src2),
2923 !strconcat(OpcodeStr,
2924 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2925 []>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2927 def SDZr : AVX5128I<opc, MRMSrcReg, (outs FR64X:$dst),
2928 (ins FR64X:$src1, FR64X:$src2),
2929 !strconcat(OpcodeStr,
2930 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2932 let mayLoad = 1 in {
2933 def SDZm : AVX5128I<opc, MRMSrcMem, (outs FR64X:$dst),
2934 (ins FR64X:$src1, f64mem:$src2),
2935 !strconcat(OpcodeStr,
2936 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2937 EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
2938 def SDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
2939 (ins VR128X:$src1, sdmem:$src2),
2940 !strconcat(OpcodeStr,
2941 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2942 []>, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
2947 defm VRCP14 : avx512_fp_unop_s<0x4D, "vrcp14">,
2948 avx512_fp_unop_p<0x4C, "vrcp14", X86frcp>,
2949 avx512_fp_unop_p_int<0x4C, "vrcp14",
2950 int_x86_avx512_rcp14_ps_512, int_x86_avx512_rcp14_pd_512>;
2952 defm VRSQRT14 : avx512_fp_unop_s<0x4F, "vrsqrt14">,
2953 avx512_fp_unop_p<0x4E, "vrsqrt14", X86frsqrt>,
2954 avx512_fp_unop_p_int<0x4E, "vrsqrt14",
2955 int_x86_avx512_rsqrt14_ps_512, int_x86_avx512_rsqrt14_pd_512>;
2957 def : Pat<(int_x86_avx512_rsqrt14_ss VR128X:$src),
2958 (COPY_TO_REGCLASS (VRSQRT14SSZr (f32 (IMPLICIT_DEF)),
2959 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2961 def : Pat<(int_x86_avx512_rsqrt14_ss sse_load_f32:$src),
2962 (VRSQRT14SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2964 def : Pat<(int_x86_avx512_rcp14_ss VR128X:$src),
2965 (COPY_TO_REGCLASS (VRCP14SSZr (f32 (IMPLICIT_DEF)),
2966 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2968 def : Pat<(int_x86_avx512_rcp14_ss sse_load_f32:$src),
2969 (VRCP14SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2971 let AddedComplexity = 20, Predicates = [HasERI] in {
2972 defm VRCP28 : avx512_fp_unop_s<0xCB, "vrcp28">,
2973 avx512_fp_unop_p<0xCA, "vrcp28", X86frcp>,
2974 avx512_fp_unop_p_int<0xCA, "vrcp28",
2975 int_x86_avx512_rcp28_ps_512, int_x86_avx512_rcp28_pd_512>;
2977 defm VRSQRT28 : avx512_fp_unop_s<0xCD, "vrsqrt28">,
2978 avx512_fp_unop_p<0xCC, "vrsqrt28", X86frsqrt>,
2979 avx512_fp_unop_p_int<0xCC, "vrsqrt28",
2980 int_x86_avx512_rsqrt28_ps_512, int_x86_avx512_rsqrt28_pd_512>;
2983 let Predicates = [HasERI] in {
2984 def : Pat<(int_x86_avx512_rsqrt28_ss VR128X:$src),
2985 (COPY_TO_REGCLASS (VRSQRT28SSZr (f32 (IMPLICIT_DEF)),
2986 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2988 def : Pat<(int_x86_avx512_rsqrt28_ss sse_load_f32:$src),
2989 (VRSQRT28SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2991 def : Pat<(int_x86_avx512_rcp28_ss VR128X:$src),
2992 (COPY_TO_REGCLASS (VRCP28SSZr (f32 (IMPLICIT_DEF)),
2993 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2995 def : Pat<(int_x86_avx512_rcp28_ss sse_load_f32:$src),
2996 (VRCP28SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2998 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2999 Intrinsic V16F32Int, Intrinsic V8F64Int,
3000 OpndItins itins_s, OpndItins itins_d> {
3001 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3002 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3003 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
3007 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3008 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3010 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
3011 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
3013 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3014 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3015 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
3019 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3020 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3021 [(set VR512:$dst, (OpNode
3022 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
3023 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
3025 def PSZr_Int : AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3026 !strconcat(OpcodeStr,
3027 "ps\t{$src, $dst|$dst, $src}"),
3028 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
3030 def PSZm_Int : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3031 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3033 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
3034 EVEX_V512, EVEX_CD8<32, CD8VF>;
3035 def PDZr_Int : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3036 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3037 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
3038 EVEX, EVEX_V512, VEX_W;
3039 def PDZm_Int : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3040 !strconcat(OpcodeStr,
3041 "pd\t{$src, $dst|$dst, $src}"),
3042 [(set VR512:$dst, (V8F64Int (memopv8f64 addr:$src)))]>,
3043 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3046 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
3047 Intrinsic F32Int, Intrinsic F64Int,
3048 OpndItins itins_s, OpndItins itins_d> {
3049 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
3050 (ins FR32X:$src1, FR32X:$src2),
3051 !strconcat(OpcodeStr,
3052 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3053 [], itins_s.rr>, XS, EVEX_4V;
3054 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3055 (ins VR128X:$src1, VR128X:$src2),
3056 !strconcat(OpcodeStr,
3057 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3059 (F32Int VR128X:$src1, VR128X:$src2))],
3060 itins_s.rr>, XS, EVEX_4V;
3061 let mayLoad = 1 in {
3062 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
3063 (ins FR32X:$src1, f32mem:$src2),
3064 !strconcat(OpcodeStr,
3065 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3066 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3067 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3068 (ins VR128X:$src1, ssmem:$src2),
3069 !strconcat(OpcodeStr,
3070 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3072 (F32Int VR128X:$src1, sse_load_f32:$src2))],
3073 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3075 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
3076 (ins FR64X:$src1, FR64X:$src2),
3077 !strconcat(OpcodeStr,
3078 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3080 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3081 (ins VR128X:$src1, VR128X:$src2),
3082 !strconcat(OpcodeStr,
3083 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3085 (F64Int VR128X:$src1, VR128X:$src2))],
3086 itins_s.rr>, XD, EVEX_4V, VEX_W;
3087 let mayLoad = 1 in {
3088 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
3089 (ins FR64X:$src1, f64mem:$src2),
3090 !strconcat(OpcodeStr,
3091 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3092 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3093 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3094 (ins VR128X:$src1, sdmem:$src2),
3095 !strconcat(OpcodeStr,
3096 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3098 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
3099 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3104 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
3105 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
3106 SSE_SQRTSS, SSE_SQRTSD>,
3107 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
3108 int_x86_avx512_sqrt_ps_512, int_x86_avx512_sqrt_pd_512,
3109 SSE_SQRTPS, SSE_SQRTPD>;
3111 let Predicates = [HasAVX512] in {
3112 def : Pat<(f32 (fsqrt FR32X:$src)),
3113 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3114 def : Pat<(f32 (fsqrt (load addr:$src))),
3115 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3116 Requires<[OptForSize]>;
3117 def : Pat<(f64 (fsqrt FR64X:$src)),
3118 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
3119 def : Pat<(f64 (fsqrt (load addr:$src))),
3120 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
3121 Requires<[OptForSize]>;
3123 def : Pat<(f32 (X86frsqrt FR32X:$src)),
3124 (VRSQRT14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3125 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3126 (VRSQRT14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3127 Requires<[OptForSize]>;
3129 def : Pat<(f32 (X86frcp FR32X:$src)),
3130 (VRCP14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3131 def : Pat<(f32 (X86frcp (load addr:$src))),
3132 (VRCP14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3133 Requires<[OptForSize]>;
3135 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
3136 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
3137 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3139 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3140 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3142 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
3143 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
3144 (COPY_TO_REGCLASS VR128X:$src, FR64)),
3146 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3147 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3151 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
3152 X86MemOperand x86memop, RegisterClass RC,
3153 PatFrag mem_frag32, PatFrag mem_frag64,
3154 Intrinsic V4F32Int, Intrinsic V2F64Int,
3156 let ExeDomain = SSEPackedSingle in {
3157 // Intrinsic operation, reg.
3158 // Vector intrinsic operation, reg
3159 def PSr : AVX512AIi8<opcps, MRMSrcReg,
3160 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3161 !strconcat(OpcodeStr,
3162 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3163 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
3165 // Vector intrinsic operation, mem
3166 def PSm : AVX512AIi8<opcps, MRMSrcMem,
3167 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3168 !strconcat(OpcodeStr,
3169 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3171 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
3172 EVEX_CD8<32, VForm>;
3173 } // ExeDomain = SSEPackedSingle
3175 let ExeDomain = SSEPackedDouble in {
3176 // Vector intrinsic operation, reg
3177 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
3178 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3179 !strconcat(OpcodeStr,
3180 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3181 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
3183 // Vector intrinsic operation, mem
3184 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
3185 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3186 !strconcat(OpcodeStr,
3187 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3189 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
3190 EVEX_CD8<64, VForm>;
3191 } // ExeDomain = SSEPackedDouble
3194 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3198 let ExeDomain = GenericDomain in {
3200 let hasSideEffects = 0 in
3201 def SSr : AVX512AIi8<opcss, MRMSrcReg,
3202 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
3203 !strconcat(OpcodeStr,
3204 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3207 // Intrinsic operation, reg.
3208 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
3209 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3210 !strconcat(OpcodeStr,
3211 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3212 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
3214 // Intrinsic operation, mem.
3215 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
3216 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
3217 !strconcat(OpcodeStr,
3218 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3219 [(set VR128X:$dst, (F32Int VR128X:$src1,
3220 sse_load_f32:$src2, imm:$src3))]>,
3221 EVEX_CD8<32, CD8VT1>;
3224 let hasSideEffects = 0 in
3225 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
3226 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
3227 !strconcat(OpcodeStr,
3228 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3231 // Intrinsic operation, reg.
3232 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
3233 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3234 !strconcat(OpcodeStr,
3235 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3236 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
3239 // Intrinsic operation, mem.
3240 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
3241 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
3242 !strconcat(OpcodeStr,
3243 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3245 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
3246 VEX_W, EVEX_CD8<64, CD8VT1>;
3247 } // ExeDomain = GenericDomain
3250 let Predicates = [HasAVX512] in {
3251 defm VRNDSCALE : avx512_fp_binop_rm<0x0A, 0x0B, "vrndscale",
3252 int_x86_avx512_rndscale_ss,
3253 int_x86_avx512_rndscale_sd>, EVEX_4V;
3255 defm VRNDSCALEZ : avx512_fp_unop_rm<0x08, 0x09, "vrndscale", f256mem, VR512,
3256 memopv16f32, memopv8f64,
3257 int_x86_avx512_rndscale_ps_512,
3258 int_x86_avx512_rndscale_pd_512, CD8VF>,
3262 def : Pat<(ffloor FR32X:$src),
3263 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
3264 def : Pat<(f64 (ffloor FR64X:$src)),
3265 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
3266 def : Pat<(f32 (fnearbyint FR32X:$src)),
3267 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
3268 def : Pat<(f64 (fnearbyint FR64X:$src)),
3269 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
3270 def : Pat<(f32 (fceil FR32X:$src)),
3271 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
3272 def : Pat<(f64 (fceil FR64X:$src)),
3273 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
3274 def : Pat<(f32 (frint FR32X:$src)),
3275 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
3276 def : Pat<(f64 (frint FR64X:$src)),
3277 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
3278 def : Pat<(f32 (ftrunc FR32X:$src)),
3279 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
3280 def : Pat<(f64 (ftrunc FR64X:$src)),
3281 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
3283 def : Pat<(v16f32 (ffloor VR512:$src)),
3284 (VRNDSCALEZPSr VR512:$src, (i32 0x1))>;
3285 def : Pat<(v16f32 (fnearbyint VR512:$src)),
3286 (VRNDSCALEZPSr VR512:$src, (i32 0xC))>;
3287 def : Pat<(v16f32 (fceil VR512:$src)),
3288 (VRNDSCALEZPSr VR512:$src, (i32 0x2))>;
3289 def : Pat<(v16f32 (frint VR512:$src)),
3290 (VRNDSCALEZPSr VR512:$src, (i32 0x4))>;
3291 def : Pat<(v16f32 (ftrunc VR512:$src)),
3292 (VRNDSCALEZPSr VR512:$src, (i32 0x3))>;
3294 def : Pat<(v8f64 (ffloor VR512:$src)),
3295 (VRNDSCALEZPDr VR512:$src, (i32 0x1))>;
3296 def : Pat<(v8f64 (fnearbyint VR512:$src)),
3297 (VRNDSCALEZPDr VR512:$src, (i32 0xC))>;
3298 def : Pat<(v8f64 (fceil VR512:$src)),
3299 (VRNDSCALEZPDr VR512:$src, (i32 0x2))>;
3300 def : Pat<(v8f64 (frint VR512:$src)),
3301 (VRNDSCALEZPDr VR512:$src, (i32 0x4))>;
3302 def : Pat<(v8f64 (ftrunc VR512:$src)),
3303 (VRNDSCALEZPDr VR512:$src, (i32 0x3))>;
3305 //-------------------------------------------------
3306 // Integer truncate and extend operations
3307 //-------------------------------------------------
3309 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
3310 RegisterClass dstRC, RegisterClass srcRC,
3311 RegisterClass KRC, X86MemOperand x86memop> {
3312 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3314 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
3317 def krr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3318 (ins KRC:$mask, srcRC:$src),
3319 !strconcat(OpcodeStr,
3320 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3323 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
3324 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3327 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
3328 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3329 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
3330 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3331 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
3332 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3333 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
3334 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3335 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
3336 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3337 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
3338 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3339 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
3340 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3341 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
3342 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3343 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
3344 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3345 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
3346 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3347 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
3348 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3349 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
3350 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3351 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
3352 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3353 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
3354 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3355 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
3356 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3358 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
3359 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
3360 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
3361 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
3362 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
3364 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3365 (VPMOVDBkrr VK16WM:$mask, VR512:$src)>;
3366 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3367 (VPMOVDWkrr VK16WM:$mask, VR512:$src)>;
3368 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3369 (VPMOVQWkrr VK8WM:$mask, VR512:$src)>;
3370 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3371 (VPMOVQDkrr VK8WM:$mask, VR512:$src)>;
3374 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass DstRC,
3375 RegisterClass SrcRC, SDNode OpNode, PatFrag mem_frag,
3376 X86MemOperand x86memop, ValueType OpVT, ValueType InVT> {
3378 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
3380 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3381 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
3382 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
3383 (ins x86memop:$src),
3384 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
3386 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
3390 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VR512, VR128X, X86vzext,
3391 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3393 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VR512, VR128X, X86vzext,
3394 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3396 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VR512, VR256X, X86vzext,
3397 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3398 EVEX_CD8<16, CD8VH>;
3399 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VR512, VR128X, X86vzext,
3400 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3401 EVEX_CD8<16, CD8VQ>;
3402 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VR512, VR256X, X86vzext,
3403 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3404 EVEX_CD8<32, CD8VH>;
3406 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VR512, VR128X, X86vsext,
3407 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3409 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VR512, VR128X, X86vsext,
3410 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3412 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VR512, VR256X, X86vsext,
3413 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3414 EVEX_CD8<16, CD8VH>;
3415 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VR512, VR128X, X86vsext,
3416 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3417 EVEX_CD8<16, CD8VQ>;
3418 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VR512, VR256X, X86vsext,
3419 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3420 EVEX_CD8<32, CD8VH>;
3422 //===----------------------------------------------------------------------===//
3423 // GATHER - SCATTER Operations
3425 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3426 RegisterClass RC, X86MemOperand memop> {
3428 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
3429 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
3430 (ins RC:$src1, KRC:$mask, memop:$src2),
3431 !strconcat(OpcodeStr,
3432 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3435 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
3436 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3437 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
3438 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3440 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
3441 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3442 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
3443 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3445 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
3446 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3447 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
3448 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3450 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
3451 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3452 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
3453 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3455 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3456 RegisterClass RC, X86MemOperand memop> {
3457 let mayStore = 1, Constraints = "$mask = $mask_wb" in
3458 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
3459 (ins memop:$dst, KRC:$mask, RC:$src2),
3460 !strconcat(OpcodeStr,
3461 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3465 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
3466 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3467 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
3468 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3470 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
3471 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3472 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
3473 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3475 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
3476 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3477 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
3478 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3480 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
3481 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3482 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
3483 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3485 //===----------------------------------------------------------------------===//
3486 // VSHUFPS - VSHUFPD Operations
3488 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
3489 ValueType vt, string OpcodeStr, PatFrag mem_frag,
3491 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
3492 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3493 !strconcat(OpcodeStr,
3494 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3495 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
3496 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3497 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
3498 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
3499 (ins RC:$src1, RC:$src2, i8imm:$src3),
3500 !strconcat(OpcodeStr,
3501 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3502 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
3503 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3504 EVEX_4V, Sched<[WriteShuffle]>;
3507 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
3508 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3509 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
3510 SSEPackedDouble>, OpSize, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3512 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3513 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3514 def : Pat<(v16i32 (X86Shufp VR512:$src1,
3515 (memopv16i32 addr:$src2), (i8 imm:$imm))),
3516 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3518 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3519 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3520 def : Pat<(v8i64 (X86Shufp VR512:$src1,
3521 (memopv8i64 addr:$src2), (i8 imm:$imm))),
3522 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3524 multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
3525 X86MemOperand x86memop> {
3526 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
3527 (ins RC:$src1, RC:$src2, i8imm:$src3),
3528 !strconcat(OpcodeStr,
3529 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3532 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
3533 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3534 !strconcat(OpcodeStr,
3535 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3538 defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
3539 EVEX_V512, EVEX_CD8<32, CD8VF>;
3540 defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
3541 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3543 def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3544 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3545 def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3546 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3547 def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3548 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3549 def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3550 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3552 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, RegisterClass RC,
3553 X86MemOperand x86memop> {
3554 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3555 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3557 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
3558 (ins x86memop:$src),
3559 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3563 defm VPABSD : avx512_vpabs<0x1E, "vpabsd", VR512, i512mem>, EVEX_V512,
3564 EVEX_CD8<32, CD8VF>;
3565 defm VPABSQ : avx512_vpabs<0x1F, "vpabsq", VR512, i512mem>, EVEX_V512, VEX_W,
3566 EVEX_CD8<64, CD8VF>;
3568 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
3569 RegisterClass RC, RegisterClass KRC,
3570 X86MemOperand x86memop,
3571 X86MemOperand x86scalar_mop, string BrdcstStr> {
3572 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3574 !strconcat(OpcodeStr, "\t{$src, ${dst} |${dst}, $src}"),
3576 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3577 (ins x86memop:$src),
3578 !strconcat(OpcodeStr, "\t{$src, ${dst}|${dst}, $src}"),
3580 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3581 (ins x86scalar_mop:$src),
3582 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
3583 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
3585 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3586 (ins KRC:$mask, RC:$src),
3587 !strconcat(OpcodeStr,
3588 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3590 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3591 (ins KRC:$mask, x86memop:$src),
3592 !strconcat(OpcodeStr,
3593 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3595 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3596 (ins KRC:$mask, x86scalar_mop:$src),
3597 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
3598 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
3600 []>, EVEX, EVEX_KZ, EVEX_B;
3602 let Constraints = "$src1 = $dst" in {
3603 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3604 (ins RC:$src1, KRC:$mask, RC:$src2),
3605 !strconcat(OpcodeStr,
3606 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3608 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3609 (ins RC:$src1, KRC:$mask, x86memop:$src2),
3610 !strconcat(OpcodeStr,
3611 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3613 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3614 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
3615 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
3616 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
3617 []>, EVEX, EVEX_K, EVEX_B;
3621 let Predicates = [HasCDI] in {
3622 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
3623 i512mem, i32mem, "{1to16}">,
3624 EVEX_V512, EVEX_CD8<32, CD8VF>;
3627 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
3628 i512mem, i64mem, "{1to8}">,
3629 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3633 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
3635 (VPCONFLICTDrrk VR512:$src1,
3636 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
3638 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
3640 (VPCONFLICTQrrk VR512:$src1,
3641 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;