1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
16 #define LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
18 #include "llvm/CodeGen/CallingConvLower.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/Target/TargetOptions.h"
25 class X86TargetMachine;
28 // X86 Specific DAG Nodes
29 enum NodeType : unsigned {
30 // Start the numbering where the builtin ops leave off.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
38 /// Double shift instructions. These correspond to
39 /// X86::SHLDxx and X86::SHRDxx instructions.
43 /// Bitwise logical AND of floating point values. This corresponds
44 /// to X86::ANDPS or X86::ANDPD.
47 /// Bitwise logical OR of floating point values. This corresponds
48 /// to X86::ORPS or X86::ORPD.
51 /// Bitwise logical XOR of floating point values. This corresponds
52 /// to X86::XORPS or X86::XORPD.
55 /// Bitwise logical ANDNOT of floating point values. This
56 /// corresponds to X86::ANDNPS or X86::ANDNPD.
59 /// These operations represent an abstract X86 call
60 /// instruction, which includes a bunch of information. In particular the
61 /// operands of these node are:
63 /// #0 - The incoming token chain
65 /// #2 - The number of arg bytes the caller pushes on the stack.
66 /// #3 - The number of arg bytes the callee pops off the stack.
67 /// #4 - The value to pass in AL/AX/EAX (optional)
68 /// #5 - The value to pass in DL/DX/EDX (optional)
70 /// The result values of these nodes are:
72 /// #0 - The outgoing token chain
73 /// #1 - The first register result value (optional)
74 /// #2 - The second register result value (optional)
78 /// This operation implements the lowering for readcyclecounter
81 /// X86 Read Time-Stamp Counter and Processor ID.
84 /// X86 Read Performance Monitoring Counters.
87 /// X86 compare and logical compare instructions.
90 /// X86 bit-test instructions.
93 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
94 /// operand, usually produced by a CMP instruction.
100 // Same as SETCC except it's materialized with a sbb and the value is all
101 // one's or all zero's.
102 SETCC_CARRY, // R = carry_bit ? ~0 : 0
104 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
105 /// Operands are two FP values to compare; result is a mask of
106 /// 0s or 1s. Generally DTRT for C/C++ with NaNs.
109 /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values,
110 /// result in an integer GPR. Needs masking for scalar result.
113 /// X86 conditional moves. Operand 0 and operand 1 are the two values
114 /// to select from. Operand 2 is the condition code, and operand 3 is the
115 /// flag operand produced by a CMP or TEST instruction. It also writes a
119 /// X86 conditional branches. Operand 0 is the chain operand, operand 1
120 /// is the block to branch if condition is true, operand 2 is the
121 /// condition code, and operand 3 is the flag operand produced by a CMP
122 /// or TEST instruction.
125 /// Return with a flag operand. Operand 0 is the chain operand, operand
126 /// 1 is the number of bytes of stack to pop.
129 /// Repeat fill, corresponds to X86::REP_STOSx.
132 /// Repeat move, corresponds to X86::REP_MOVSx.
135 /// On Darwin, this node represents the result of the popl
136 /// at function entry, used for PIC code.
139 /// A wrapper node for TargetConstantPool,
140 /// TargetExternalSymbol, and TargetGlobalAddress.
143 /// Special wrapper used under X86-64 PIC mode for RIP
144 /// relative displacements.
147 /// Copies a 64-bit value from the low word of an XMM vector
148 /// to an MMX vector. If you think this is too close to the previous
149 /// mnemonic, so do I; blame Intel.
152 /// Copies a 32-bit value from the low word of a MMX
156 /// Copies a GPR into the low 32-bit word of a MMX vector
157 /// and zero out the high word.
160 /// Extract an 8-bit value from a vector and zero extend it to
161 /// i32, corresponds to X86::PEXTRB.
164 /// Extract a 16-bit value from a vector and zero extend it to
165 /// i32, corresponds to X86::PEXTRW.
168 /// Insert any element of a 4 x float vector into any element
169 /// of a destination 4 x floatvector.
172 /// Insert the lower 8-bits of a 32-bit value to a vector,
173 /// corresponds to X86::PINSRB.
176 /// Insert the lower 16-bits of a 32-bit value to a vector,
177 /// corresponds to X86::PINSRW.
180 /// Shuffle 16 8-bit values within a vector.
183 /// Compute Sum of Absolute Differences.
186 /// Bitwise Logical AND NOT of Packed FP values.
189 /// Copy integer sign.
192 /// Blend where the selector is an immediate.
195 /// Blend where the condition has been shrunk.
196 /// This is used to emphasize that the condition mask is
197 /// no more valid for generic VSELECT optimizations.
200 /// Combined add and sub on an FP vector.
203 // FP vector ops with rounding mode.
212 // FP vector get exponent
216 // Integer add/sub with unsigned saturation.
219 // Integer add/sub with signed saturation.
222 // Unsigned Integer average
224 /// Integer horizontal add.
227 /// Integer horizontal sub.
230 /// Floating point horizontal add.
233 /// Floating point horizontal sub.
236 // Integer absolute value
239 /// Floating point max and min.
242 /// Commutative FMIN and FMAX.
245 /// Floating point reciprocal-sqrt and reciprocal approximation.
246 /// Note that these typically require refinement
247 /// in order to obtain suitable precision.
250 // Thread Local Storage.
253 // Thread Local Storage. A call to get the start address
254 // of the TLS block for the current module.
257 // Thread Local Storage. When calling to an OS provided
258 // thunk at the address from an earlier relocation.
261 // Exception Handling helpers.
264 // SjLj exception handling setjmp.
267 // SjLj exception handling longjmp.
270 /// Tail call return. See X86TargetLowering::LowerCall for
271 /// the list of operands.
274 // Vector move to low scalar and zero higher vector elements.
277 // Vector integer zero-extend.
280 // Vector integer signed-extend.
283 // Vector integer truncate.
286 // Vector integer truncate with mask.
295 // Vector signed/unsigned integer to double.
298 // 128-bit vector logical left / right shift
301 // Vector shift elements
304 // Vector shift elements by immediate
307 // Vector packed double/float comparison.
310 // Vector integer comparisons.
312 // Vector integer comparisons, the result is in a mask vector.
315 /// Vector comparison generating mask bits for fp and
316 /// integer signed and unsigned data types.
319 // Vector comparison with rounding mode for FP values
322 // Arithmetic operations with FLAGS results.
323 ADD, SUB, ADC, SBB, SMUL,
324 INC, DEC, OR, XOR, AND,
326 BEXTR, // Bit field extract
328 UMUL, // LOW, HI, FLAGS = umul LHS, RHS
330 // 8-bit SMUL/UMUL - AX, FLAGS = smul8/umul8 AL, RHS
333 // 8-bit divrem that zero-extend the high result (AH).
337 // X86-specific multiply by immediate.
340 // Vector bitwise comparisons.
343 // Vector packed fp sign bitwise comparisons.
346 // Vector "test" in AVX-512, the result is in a mask vector.
350 // OR/AND test for masks
353 // Several flavors of instructions with vector shuffle behaviors.
358 // AVX512 inter-lane alignr
364 //Shuffle Packed Values at 128-bit granularity
385 //Fix Up Special Packed Float32/64 values
387 //Range Restriction Calculation For Packed Pairs of Float32/64 values
389 // Reduce - Perform Reduction Transformation on scalar\packed FP
391 // RndScale - Round FP Values To Include A Given Number Of Fraction Bits
393 // Broadcast scalar to vector
395 // Broadcast subvector to vector
397 // Insert/Extract vector element
401 /// SSE4A Extraction and Insertion.
404 // Vector multiply packed unsigned doubleword integers
406 // Vector multiply packed signed doubleword integers
408 // Vector Multiply Packed UnsignedIntegers with Round and Scale
410 // Multiply and Add Packed Integers
411 VPMADDUBSW, VPMADDWD,
419 // FMA with rounding mode
427 // Compress and expand
431 //Convert Unsigned/Integer to Scalar Floating-Point Value
436 // Vector float/double to signed/unsigned integer.
437 FP_TO_SINT_RND, FP_TO_UINT_RND,
438 // Save xmm argument registers to the stack, according to %al. An operator
439 // is needed so that this can be expanded with control flow.
440 VASTART_SAVE_XMM_REGS,
442 // Windows's _chkstk call to do stack probing.
445 // For allocating variable amounts of stack space when using
446 // segmented stacks. Check if the current stacklet has enough space, and
447 // falls back to heap allocation if not.
450 // Windows's _ftol2 runtime routine to do fptoui.
459 // Store FP status word into i16 register.
462 // Store contents of %ah into %eflags.
465 // Get a random integer and indicate whether it is valid in CF.
468 // Get a NIST SP800-90B & C compliant random integer and
469 // indicate whether it is valid in CF.
475 // Test if in transactional execution.
479 RSQRT28, RCP28, EXP2,
482 LCMPXCHG_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
486 // Load, scalar_to_vector, and zero extend.
489 // Store FP control world into i16 memory.
492 /// This instruction implements FP_TO_SINT with the
493 /// integer destination in memory and a FP reg source. This corresponds
494 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
495 /// has two inputs (token chain and address) and two outputs (int value
496 /// and token chain).
501 /// This instruction implements SINT_TO_FP with the
502 /// integer source in memory and FP reg result. This corresponds to the
503 /// X86::FILD*m instructions. It has three inputs (token chain, address,
504 /// and source type) and two outputs (FP value and token chain). FILD_FLAG
505 /// also produces a flag).
509 /// This instruction implements an extending load to FP stack slots.
510 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
511 /// operand, ptr to load from, and a ValueType node indicating the type
515 /// This instruction implements a truncating store to FP stack
516 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
517 /// chain operand, value to store, address, and a ValueType to store it
521 /// This instruction grabs the address of the next argument
522 /// from a va_list. (reads and modifies the va_list in memory)
525 // WARNING: Do not add anything in the end unless you want the node to
526 // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be
527 // thought as target memory ops!
531 /// Define some predicates that are used for node matching.
533 /// Return true if the specified
534 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
535 /// suitable for input to VEXTRACTF128, VEXTRACTI128 instructions.
536 bool isVEXTRACT128Index(SDNode *N);
538 /// Return true if the specified
539 /// INSERT_SUBVECTOR operand specifies a subvector insert that is
540 /// suitable for input to VINSERTF128, VINSERTI128 instructions.
541 bool isVINSERT128Index(SDNode *N);
543 /// Return true if the specified
544 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
545 /// suitable for input to VEXTRACTF64X4, VEXTRACTI64X4 instructions.
546 bool isVEXTRACT256Index(SDNode *N);
548 /// Return true if the specified
549 /// INSERT_SUBVECTOR operand specifies a subvector insert that is
550 /// suitable for input to VINSERTF64X4, VINSERTI64X4 instructions.
551 bool isVINSERT256Index(SDNode *N);
553 /// Return the appropriate
554 /// immediate to extract the specified EXTRACT_SUBVECTOR index
555 /// with VEXTRACTF128, VEXTRACTI128 instructions.
556 unsigned getExtractVEXTRACT128Immediate(SDNode *N);
558 /// Return the appropriate
559 /// immediate to insert at the specified INSERT_SUBVECTOR index
560 /// with VINSERTF128, VINSERT128 instructions.
561 unsigned getInsertVINSERT128Immediate(SDNode *N);
563 /// Return the appropriate
564 /// immediate to extract the specified EXTRACT_SUBVECTOR index
565 /// with VEXTRACTF64X4, VEXTRACTI64x4 instructions.
566 unsigned getExtractVEXTRACT256Immediate(SDNode *N);
568 /// Return the appropriate
569 /// immediate to insert at the specified INSERT_SUBVECTOR index
570 /// with VINSERTF64x4, VINSERTI64x4 instructions.
571 unsigned getInsertVINSERT256Immediate(SDNode *N);
573 /// Returns true if Elt is a constant zero or floating point constant +0.0.
574 bool isZeroNode(SDValue Elt);
576 /// Returns true of the given offset can be
577 /// fit into displacement field of the instruction.
578 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
579 bool hasSymbolicDisplacement = true);
582 /// Determines whether the callee is required to pop its
583 /// own arguments. Callee pop is necessary to support tail calls.
584 bool isCalleePop(CallingConv::ID CallingConv,
585 bool is64Bit, bool IsVarArg, bool TailCallOpt);
587 /// AVX512 static rounding constants. These need to match the values in
589 enum STATIC_ROUNDING {
598 //===--------------------------------------------------------------------===//
599 // X86 Implementation of the TargetLowering interface
600 class X86TargetLowering final : public TargetLowering {
602 explicit X86TargetLowering(const X86TargetMachine &TM,
603 const X86Subtarget &STI);
605 unsigned getJumpTableEncoding() const override;
606 bool useSoftFloat() const override;
608 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
613 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
614 const MachineBasicBlock *MBB, unsigned uid,
615 MCContext &Ctx) const override;
617 /// Returns relocation base for the given PIC jumptable.
618 SDValue getPICJumpTableRelocBase(SDValue Table,
619 SelectionDAG &DAG) const override;
621 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
622 unsigned JTI, MCContext &Ctx) const override;
624 /// Return the desired alignment for ByVal aggregate
625 /// function arguments in the caller parameter area. For X86, aggregates
626 /// that contains are placed at 16-byte boundaries while the rest are at
627 /// 4-byte boundaries.
628 unsigned getByValTypeAlignment(Type *Ty,
629 const DataLayout &DL) const override;
631 /// Returns the target specific optimal type for load
632 /// and store operations as a result of memset, memcpy, and memmove
633 /// lowering. If DstAlign is zero that means it's safe to destination
634 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
635 /// means there isn't a need to check it against alignment requirement,
636 /// probably because the source does not need to be loaded. If 'IsMemset' is
637 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
638 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
639 /// source is constant so it does not need to be loaded.
640 /// It returns EVT::Other if the type should be determined using generic
641 /// target-independent logic.
642 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
643 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
644 MachineFunction &MF) const override;
646 /// Returns true if it's safe to use load / store of the
647 /// specified type to expand memcpy / memset inline. This is mostly true
648 /// for all types except for some special cases. For example, on X86
649 /// targets without SSE2 f64 load / store are done with fldl / fstpl which
650 /// also does type conversion. Note the specified type doesn't have to be
651 /// legal as the hook is used before type legalization.
652 bool isSafeMemOpType(MVT VT) const override;
654 /// Returns true if the target allows unaligned memory accesses of the
655 /// specified type. Returns whether it is "fast" in the last argument.
656 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align,
657 bool *Fast) const override;
659 /// Provide custom lowering hooks for some operations.
661 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
663 /// Replace the results of node with an illegal result
664 /// type with new values built out of custom code.
666 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
667 SelectionDAG &DAG) const override;
670 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
672 /// Return true if the target has native support for
673 /// the specified value type and it is 'desirable' to use the type for the
674 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
675 /// instruction encodings are longer and some i16 instructions are slow.
676 bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override;
678 /// Return true if the target has native support for the
679 /// specified value type and it is 'desirable' to use the type. e.g. On x86
680 /// i16 is legal, but undesirable since i16 instruction encodings are longer
681 /// and some i16 instructions are slow.
682 bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override;
685 EmitInstrWithCustomInserter(MachineInstr *MI,
686 MachineBasicBlock *MBB) const override;
689 /// This method returns the name of a target specific DAG node.
690 const char *getTargetNodeName(unsigned Opcode) const override;
692 bool isCheapToSpeculateCttz() const override;
694 bool isCheapToSpeculateCtlz() const override;
696 /// Return the value type to use for ISD::SETCC.
697 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
698 EVT VT) const override;
700 /// Determine which of the bits specified in Mask are known to be either
701 /// zero or one and return them in the KnownZero/KnownOne bitsets.
702 void computeKnownBitsForTargetNode(const SDValue Op,
705 const SelectionDAG &DAG,
706 unsigned Depth = 0) const override;
708 /// Determine the number of bits in the operation that are sign bits.
709 unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
710 const SelectionDAG &DAG,
711 unsigned Depth) const override;
713 bool isGAPlusOffset(SDNode *N, const GlobalValue* &GA,
714 int64_t &Offset) const override;
716 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
718 bool ExpandInlineAsm(CallInst *CI) const override;
720 ConstraintType getConstraintType(StringRef Constraint) const override;
722 /// Examine constraint string and operand type and determine a weight value.
723 /// The operand object must already have been set up with the operand type.
725 getSingleConstraintMatchWeight(AsmOperandInfo &info,
726 const char *constraint) const override;
728 const char *LowerXConstraint(EVT ConstraintVT) const override;
730 /// Lower the specified operand into the Ops vector. If it is invalid, don't
731 /// add anything to Ops. If hasMemory is true it means one of the asm
732 /// constraint of the inline asm instruction being processed is 'm'.
733 void LowerAsmOperandForConstraint(SDValue Op,
734 std::string &Constraint,
735 std::vector<SDValue> &Ops,
736 SelectionDAG &DAG) const override;
739 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
740 if (ConstraintCode == "i")
741 return InlineAsm::Constraint_i;
742 else if (ConstraintCode == "o")
743 return InlineAsm::Constraint_o;
744 else if (ConstraintCode == "v")
745 return InlineAsm::Constraint_v;
746 else if (ConstraintCode == "X")
747 return InlineAsm::Constraint_X;
748 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
751 /// Given a physical register constraint
752 /// (e.g. {edx}), return the register number and the register class for the
753 /// register. This should only be used for C_Register constraints. On
754 /// error, this returns a register number of 0.
755 std::pair<unsigned, const TargetRegisterClass *>
756 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
757 StringRef Constraint, MVT VT) const override;
759 /// Return true if the addressing mode represented
760 /// by AM is legal for this target, for a load/store of the specified type.
761 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
762 Type *Ty, unsigned AS) const override;
764 /// Return true if the specified immediate is legal
765 /// icmp immediate, that is the target has icmp instructions which can
766 /// compare a register against the immediate without having to materialize
767 /// the immediate into a register.
768 bool isLegalICmpImmediate(int64_t Imm) const override;
770 /// Return true if the specified immediate is legal
771 /// add immediate, that is the target has add instructions which can
772 /// add a register and the immediate without having to materialize
773 /// the immediate into a register.
774 bool isLegalAddImmediate(int64_t Imm) const override;
776 /// \brief Return the cost of the scaling factor used in the addressing
777 /// mode represented by AM for this target, for a load/store
778 /// of the specified type.
779 /// If the AM is supported, the return value must be >= 0.
780 /// If the AM is not supported, it returns a negative value.
781 int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,
782 unsigned AS) const override;
784 bool isVectorShiftByScalarCheap(Type *Ty) const override;
786 /// Return true if it's free to truncate a value of
787 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
788 /// register EAX to i16 by referencing its sub-register AX.
789 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
790 bool isTruncateFree(EVT VT1, EVT VT2) const override;
792 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
794 /// Return true if any actual instruction that defines a
795 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
796 /// register. This does not necessarily include registers defined in
797 /// unknown ways, such as incoming arguments, or copies from unknown
798 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
799 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
800 /// all instructions that define 32-bit values implicit zero-extend the
801 /// result out to 64 bits.
802 bool isZExtFree(Type *Ty1, Type *Ty2) const override;
803 bool isZExtFree(EVT VT1, EVT VT2) const override;
804 bool isZExtFree(SDValue Val, EVT VT2) const override;
806 /// Return true if folding a vector load into ExtVal (a sign, zero, or any
807 /// extend node) is profitable.
808 bool isVectorLoadExtDesirable(SDValue) const override;
810 /// Return true if an FMA operation is faster than a pair of fmul and fadd
811 /// instructions. fmuladd intrinsics will be expanded to FMAs when this
812 /// method returns true, otherwise fmuladd is expanded to fmul + fadd.
813 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
815 /// Return true if it's profitable to narrow
816 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
817 /// from i32 to i8 but not from i32 to i16.
818 bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
820 /// Returns true if the target can instruction select the
821 /// specified FP immediate natively. If false, the legalizer will
822 /// materialize the FP immediate as a load from a constant pool.
823 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
825 /// Targets can use this to indicate that they only support *some*
826 /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
827 /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to
829 bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
830 EVT VT) const override;
832 /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
833 /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to
834 /// replace a VAND with a constant pool entry.
835 bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
836 EVT VT) const override;
838 /// If true, then instruction selection should
839 /// seek to shrink the FP constant of the specified type to a smaller type
840 /// in order to save space and / or reduce runtime.
841 bool ShouldShrinkFPConstant(EVT VT) const override {
842 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
843 // expensive than a straight movsd. On the other hand, it's important to
844 // shrink long double fp constant since fldt is very slow.
845 return !X86ScalarSSEf64 || VT == MVT::f80;
848 /// Return true if we believe it is correct and profitable to reduce the
849 /// load node to a smaller type.
850 bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
851 EVT NewVT) const override;
853 /// Return true if the specified scalar FP type is computed in an SSE
854 /// register, not on the X87 floating point stack.
855 bool isScalarFPTypeInSSEReg(EVT VT) const {
856 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
857 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
860 /// Return true if the target uses the MSVC _ftol2 routine for fptoui.
861 bool isTargetFTOL() const;
863 /// Return true if the MSVC _ftol2 routine should be used for fptoui to the
865 bool isIntegerTypeFTOL(EVT VT) const {
866 return isTargetFTOL() && VT == MVT::i64;
869 /// \brief Returns true if it is beneficial to convert a load of a constant
870 /// to just the constant itself.
871 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
872 Type *Ty) const override;
874 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
876 bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const override;
878 /// Intel processors have a unified instruction and data cache
879 const char * getClearCacheBuiltinName() const override {
880 return nullptr; // nothing to do, move along.
883 unsigned getRegisterByName(const char* RegName, EVT VT,
884 SelectionDAG &DAG) const override;
886 /// This method returns a target specific FastISel object,
887 /// or null if the target does not support "fast" ISel.
888 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
889 const TargetLibraryInfo *libInfo) const override;
891 /// Return true if the target stores stack protector cookies at a fixed
892 /// offset in some non-standard address space, and populates the address
893 /// space and offset as appropriate.
894 bool getStackCookieLocation(unsigned &AddressSpace,
895 unsigned &Offset) const override;
897 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
898 SelectionDAG &DAG) const;
900 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
902 bool useLoadStackGuardNode() const override;
903 /// \brief Customize the preferred legalization strategy for certain types.
904 LegalizeTypeAction getPreferredVectorAction(EVT VT) const override;
907 std::pair<const TargetRegisterClass *, uint8_t>
908 findRepresentativeClass(const TargetRegisterInfo *TRI,
909 MVT VT) const override;
912 /// Keep a pointer to the X86Subtarget around so that we can
913 /// make the right decision when generating code for different targets.
914 const X86Subtarget *Subtarget;
915 const DataLayout *TD;
917 /// Select between SSE or x87 floating point ops.
918 /// When SSE is available, use it for f32 operations.
919 /// When SSE2 is available, use it for f64 operations.
920 bool X86ScalarSSEf32;
921 bool X86ScalarSSEf64;
923 /// A list of legal FP immediates.
924 std::vector<APFloat> LegalFPImmediates;
926 /// Indicate that this x86 target can instruction
927 /// select the specified FP immediate natively.
928 void addLegalFPImmediate(const APFloat& Imm) {
929 LegalFPImmediates.push_back(Imm);
932 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
933 CallingConv::ID CallConv, bool isVarArg,
934 const SmallVectorImpl<ISD::InputArg> &Ins,
935 SDLoc dl, SelectionDAG &DAG,
936 SmallVectorImpl<SDValue> &InVals) const;
937 SDValue LowerMemArgument(SDValue Chain,
938 CallingConv::ID CallConv,
939 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
940 SDLoc dl, SelectionDAG &DAG,
941 const CCValAssign &VA, MachineFrameInfo *MFI,
943 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
944 SDLoc dl, SelectionDAG &DAG,
945 const CCValAssign &VA,
946 ISD::ArgFlagsTy Flags) const;
948 // Call lowering helpers.
950 /// Check whether the call is eligible for tail call optimization. Targets
951 /// that want to do tail call optimization should implement this function.
952 bool IsEligibleForTailCallOptimization(SDValue Callee,
953 CallingConv::ID CalleeCC,
955 bool isCalleeStructRet,
956 bool isCallerStructRet,
958 const SmallVectorImpl<ISD::OutputArg> &Outs,
959 const SmallVectorImpl<SDValue> &OutVals,
960 const SmallVectorImpl<ISD::InputArg> &Ins,
961 SelectionDAG& DAG) const;
962 bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const;
963 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
964 SDValue Chain, bool IsTailCall, bool Is64Bit,
965 int FPDiff, SDLoc dl) const;
967 unsigned GetAlignedArgumentStackSize(unsigned StackSize,
968 SelectionDAG &DAG) const;
970 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
972 bool isReplace) const;
974 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
975 SDValue LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const;
976 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
977 SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
978 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
979 SDValue ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const;
980 SDValue InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const;
982 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
983 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
984 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
985 SDValue LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
986 int64_t Offset, SelectionDAG &DAG) const;
987 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
988 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
989 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
990 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
991 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
992 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const;
993 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const;
994 SDValue lowerUINT_TO_FP_vec(SDValue Op, SelectionDAG &DAG) const;
995 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
996 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
997 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
998 SDValue LowerToBT(SDValue And, ISD::CondCode CC,
999 SDLoc dl, SelectionDAG &DAG) const;
1000 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
1001 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
1002 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
1003 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
1004 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
1005 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
1006 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
1007 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
1008 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
1009 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
1010 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
1011 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
1012 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
1013 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
1014 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
1015 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
1016 SDValue LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const;
1017 SDValue LowerGC_TRANSITION_START(SDValue Op, SelectionDAG &DAG) const;
1018 SDValue LowerGC_TRANSITION_END(SDValue Op, SelectionDAG &DAG) const;
1021 LowerFormalArguments(SDValue Chain,
1022 CallingConv::ID CallConv, bool isVarArg,
1023 const SmallVectorImpl<ISD::InputArg> &Ins,
1024 SDLoc dl, SelectionDAG &DAG,
1025 SmallVectorImpl<SDValue> &InVals) const override;
1026 SDValue LowerCall(CallLoweringInfo &CLI,
1027 SmallVectorImpl<SDValue> &InVals) const override;
1029 SDValue LowerReturn(SDValue Chain,
1030 CallingConv::ID CallConv, bool isVarArg,
1031 const SmallVectorImpl<ISD::OutputArg> &Outs,
1032 const SmallVectorImpl<SDValue> &OutVals,
1033 SDLoc dl, SelectionDAG &DAG) const override;
1035 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
1037 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
1039 EVT getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1040 ISD::NodeType ExtendKind) const override;
1042 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
1044 const SmallVectorImpl<ISD::OutputArg> &Outs,
1045 LLVMContext &Context) const override;
1047 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
1049 bool shouldExpandAtomicLoadInIR(LoadInst *SI) const override;
1050 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
1051 TargetLoweringBase::AtomicRMWExpansionKind
1052 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
1055 lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const override;
1057 bool needsCmpXchgNb(const Type *MemType) const;
1059 /// Utility function to emit atomic-load-arith operations (and, or, xor,
1060 /// nand, max, min, umax, umin). It takes the corresponding instruction to
1061 /// expand, the associated machine basic block, and the associated X86
1062 /// opcodes for reg/reg.
1063 MachineBasicBlock *EmitAtomicLoadArith(MachineInstr *MI,
1064 MachineBasicBlock *MBB) const;
1066 /// Utility function to emit atomic-load-arith operations (and, or, xor,
1067 /// nand, add, sub, swap) for 64-bit operands on 32-bit target.
1068 MachineBasicBlock *EmitAtomicLoadArith6432(MachineInstr *MI,
1069 MachineBasicBlock *MBB) const;
1071 // Utility function to emit the low-level va_arg code for X86-64.
1072 MachineBasicBlock *EmitVAARG64WithCustomInserter(
1074 MachineBasicBlock *MBB) const;
1076 /// Utility function to emit the xmm reg save portion of va_start.
1077 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
1078 MachineInstr *BInstr,
1079 MachineBasicBlock *BB) const;
1081 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
1082 MachineBasicBlock *BB) const;
1084 MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI,
1085 MachineBasicBlock *BB) const;
1087 MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI,
1088 MachineBasicBlock *BB) const;
1090 MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI,
1091 MachineBasicBlock *BB) const;
1093 MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *MI,
1094 MachineBasicBlock *BB) const;
1096 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
1097 MachineBasicBlock *MBB) const;
1099 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
1100 MachineBasicBlock *MBB) const;
1102 MachineBasicBlock *emitFMA3Instr(MachineInstr *MI,
1103 MachineBasicBlock *MBB) const;
1105 /// Emit nodes that will be selected as "test Op0,Op0", or something
1106 /// equivalent, for use with the given x86 condition code.
1107 SDValue EmitTest(SDValue Op0, unsigned X86CC, SDLoc dl,
1108 SelectionDAG &DAG) const;
1110 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
1111 /// equivalent, for use with the given x86 condition code.
1112 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, SDLoc dl,
1113 SelectionDAG &DAG) const;
1115 /// Convert a comparison if required by the subtarget.
1116 SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG) const;
1118 /// Use rsqrt* to speed up sqrt calculations.
1119 SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI,
1120 unsigned &RefinementSteps,
1121 bool &UseOneConstNR) const override;
1123 /// Use rcp* to speed up fdiv calculations.
1124 SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI,
1125 unsigned &RefinementSteps) const override;
1127 /// Reassociate floating point divisions into multiply by reciprocal.
1128 bool combineRepeatedFPDivisors(unsigned NumUsers) const override;
1132 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
1133 const TargetLibraryInfo *libInfo);
1137 #endif // X86ISELLOWERING_H